mirror of
https://github.com/apache/nuttx.git
synced 2026-10-10 07:40:27 +00:00
2fde85162c
Add the PIC32MZ-W1 family, used in Microchip's WFI32E01 Wi-Fi modules. W1 shares the MIPS32 M-Class core and much of the peripheral IP with PIC32MZ EC/EF, but its SFR map, IRQ vectors, PPS registers and configuration words are laid out differently, so these are new files selected by CONFIG_ARCH_CHIP_PIC32MZW1: - hardware/pic32mzw1_*.h, irq_pic32mzw1.h: memory map, PPS, IRQ vectors and configuration words, from the PIC32MZ-W_DFP (Apache-2.0). - pic32mz_wfi32_pwrclk.c: W1 does not set up its PLLs from the configuration words. Software starts the 40 MHz crystal oscillator, runs SYSCLK at 200 MHz from the system PLL, starts the Ethernet/Wi-Fi PLL and switches the regulator from MLDO to buck mode using the factory trim values (on B0 silicon). Facts not found in the data sheet or DFP are marked [EX] in comments; they come from Microchip's WFI32 Ethernet/Wi-Fi bridge example firmware. - pic32mz_head.S, pic32mz_config.h: emit the W1 configuration words (DEVCFG0/1/2/4, FBCFG0, FCPN0, FSIGN0). - W1 differences in shared code: PREFEN only accepts 0/1, PB6DIV clocks the CPU and is left alone, UART1/2, SPI1/2 and I2C2 are clocked from PBCLK3 and the timers from PBCLK1 (data sheet Table 11-1), I2C1 and I2C2 are not contiguous in the SFR map, UART1 and SPI1 can use their dedicated (non-PPS) pins. New Kconfig options: PIC32MZ_W1_PMU_MLDO (keep the regulator in its power-on MLDO mode), PIC32MZ_W1_FLASH_WAITSTATES (default 5, the value used by Microchip's example at 200 MHz) and PIC32MZ_W1_BOOTTRACE (polled early boot trace on UART1, a bring-up aid). Assisted-by: Claude Code:claude-opus-5-5 Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com> |
||
|---|---|---|
| .. | ||
| arm | ||
| arm64 | ||
| avr | ||
| ceva | ||
| dummy | ||
| hc | ||
| mips | ||
| misoc | ||
| or1k | ||
| renesas | ||
| risc-v | ||
| sim | ||
| sparc | ||
| tricore | ||
| x86 | ||
| x86_64 | ||
| xtensa | ||
| z16 | ||
| z80 | ||
| CMakeLists.txt | ||
| Kconfig | ||