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Most of the peripheral support matches litex vexriscv-smp. * arch/risc-v/Kconfig: Defer RV32 selection to core as litex board can do RV64. * arch/risc-v/src/litex/Make.defs arch/risc-v/src/litex/hardware/litex_clint.h arch/risc-v/src/litex/hardware/litex_memorymap.h arch/risc-v/src/litex/hardware/litex_plic.h arch/risc-v/src/litex/litex_irq.c arch/risc-v/src/litex/litex_irq_dispatch.c: Add CONFIG_LITEX_CORE_VEXIIRISCV conditional where vexriscv_smp conditionals are. * boards/risc-v/litex/arty_a7/configs/nsh-vexii/defconfig: New config. * boards/risc-v/litex/arty_a7/include/vexii_irq.h: vexiiriscv irq defintion. * boards/risc-v/litex/arty_a7/include/vexii_memorymap.h: vexiiriscv memory map. * boards/risc-v/litex/arty_a7/scripts/ld.script: Define __global_pointer for toolchain happiness matching other RISC-V linker scripts. (This commit was written with assistance from Claude Code.) Signed-off-by: Justin Erenkrantz <justin@erenkrantz.com> |
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| arm | ||
| arm64 | ||
| avr | ||
| ceva | ||
| dummy | ||
| hc | ||
| mips | ||
| misoc | ||
| or1k | ||
| renesas | ||
| risc-v | ||
| sim | ||
| sparc | ||
| tricore | ||
| x86 | ||
| x86_64 | ||
| xtensa | ||
| z16 | ||
| z80 | ||
| CMakeLists.txt | ||
| Kconfig | ||