Most of the peripheral support matches litex vexriscv-smp.
* arch/risc-v/Kconfig: Defer RV32 selection to core as litex board can do RV64.
* arch/risc-v/src/litex/Make.defs
arch/risc-v/src/litex/hardware/litex_clint.h
arch/risc-v/src/litex/hardware/litex_memorymap.h
arch/risc-v/src/litex/hardware/litex_plic.h
arch/risc-v/src/litex/litex_irq.c
arch/risc-v/src/litex/litex_irq_dispatch.c: Add CONFIG_LITEX_CORE_VEXIIRISCV
conditional where vexriscv_smp conditionals are.
* boards/risc-v/litex/arty_a7/configs/nsh-vexii/defconfig: New config.
* boards/risc-v/litex/arty_a7/include/vexii_irq.h: vexiiriscv irq defintion.
* boards/risc-v/litex/arty_a7/include/vexii_memorymap.h: vexiiriscv memory map.
* boards/risc-v/litex/arty_a7/scripts/ld.script: Define __global_pointer for
toolchain happiness matching other RISC-V linker scripts.
(This commit was written with assistance from Claude Code.)
Signed-off-by: Justin Erenkrantz <justin@erenkrantz.com>
When compiling with O2 optimization, the compiler optimizes the code
in a way that causes irq variable to be corrupted. The getipsr()
function reads IPSR into r0, but the subsequent inline assembly that
sets FPSCR also uses r0 without declaring it as clobbered. This causes
the compiler to reuse r0 for the immediate value (0x40000), overwriting
the IRQ number read from IPSR.
The issue manifests as:
- getipsr() correctly reads IPSR (e.g., 0xf for IRQ 15)
- Compiler optimizes and reuses r0 for ARM_FPSCR_LTPSIZE_NONE (0x40000)
- irq variable gets the wrong value 0x40000 instead of actual IRQ number
- This leads to assertion failures in irq_dispatch due to invalid IRQ
Root cause analysis from disassembly:
mrs r0, IPSR ; Read IPSR to r0
mov.w r0, #262144 ; Compiler overwrites r0 with 0x40000!
vmsr fpscr, r0 ; Set FPSCR
str r0, [sp, #4] ; Store corrupted 0x40000 as irq
...
ldr r0, [sp, #4] ; Load corrupted value
bl irq_dispatch ; Call with wrong IRQ number 0x40000
Fix by adding r0 to the clobber list in the inline assembly, which
forces the compiler to save irq value before using r0 for FPSCR setup.
This issue only occurs at O2 optimization level and affects ARMv8-M
architecture with FPU enabled.
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
This duplicates the up_invalidate_dcache_all as vexriscv's DBUS cache
does not distinguish between flushing and invalidation.
Signed-off-by: Justin Erenkrantz <justin@erenkrantz.com>
armv8m:use ip save pc
armv7m:use ip save pc, r11 save sp
nsh_main backtrace before:
```
0 nxsem_wait_slow (sem=0x10001e0 <g_uart0port+32>) at semaphore/sem_wait.c:202
1 0x0000882c in nxsem_wait (sem=0x10001e0 <g_uart0port+32>) at semaphore/sem_wait.c:270
2 0x0000e7e2 in uart_read (filep=0x608037d4, buffer=0x60c013eb " h\024\300`", buflen=1)
at serial/serial.c:1203
3 0x0001aad4 in file_readv_compat (filep=0x608037d4, uio=0x60c01344) at vfs/fs_read.c:81
4 0x0001abae in file_readv (filep=0x608037d4, uio=0x60c01344) at vfs/fs_read.c:165
5 0x0001ac2e in nx_readv (fd=0, iov=0x60c01388, iovcnt=1) at vfs/fs_read.c:256
6 0x0001ac84 in readv (fd=0, iov=0x60c01388, iovcnt=1) at vfs/fs_read.c:318
7 0x0001acca in read (fd=0, buf=0x60c013eb, nbytes=1) at vfs/fs_read.c:352
8 0x000100ea in STUB_read (nbr=56, parm1=0, parm2=1623200747, parm3=1) at stubs/STUB_read.c:9
9 0x000014d2 in dispatch_syscall () at armv8-m/arm_svcall.c:82
```
nsh_main backtrace after:
```
0 nxsem_wait_slow (sem=0x10001f0 <g_uart0port+32>) at semaphore/sem_wait.c:202
1 0x000088c0 in nxsem_wait (sem=0x10001f0 <g_uart0port+32>) at semaphore/sem_wait.c:270
2 0x0000e882 in uart_read (filep=0x6080380c, buffer=0x60c013eb " h\024\300`", buflen=1)
at serial/serial.c:1203
3 0x0001ab74 in file_readv_compat (filep=0x6080380c, uio=0x60c01344) at vfs/fs_read.c:81
4 0x0001ac4e in file_readv (filep=0x6080380c, uio=0x60c01344) at vfs/fs_read.c:165
5 0x0001acce in nx_readv (fd=0, iov=0x60c01388, iovcnt=1) at vfs/fs_read.c:256
6 0x0001ad24 in readv (fd=0, iov=0x60c01388, iovcnt=1) at vfs/fs_read.c:318
7 0x0001ad6a in read (fd=0, buf=0x60c013eb, nbytes=1) at vfs/fs_read.c:352
8 0x0001018a in STUB_read (nbr=56, parm1=0, parm2=1623200747, parm3=1) at stubs/STUB_read.c:9
9 0x00001ece in dispatch_syscall () at armv8-m/arm_dispatch_syscall.S:111
10 0x2000a874 in read (parm1=0, parm2=0x60c013eb, parm3=1) at proxies/PROXY_read.c:9
11 0x20001152 in readline_getc (vtbl=0x60c01468) at readline_fd.c:73
12 0x20003994 in readline_common (vtbl=0x60c01468, buf=0x60c017f8 "\n", buflen=80)
at readline_common.c:513
13 0x200012ec in readline_fd (buf=0x60c017f8 "\n", buflen=80, infd=0, outfd=1) at readline_fd.c:236
14 0x200010a8 in nsh_session (pstate=0x60c01540, login=1, argc=1, argv=0x60c00548)
at nsh_session.c:229
15 0x20000eb0 in nsh_consolemain (argc=1, argv=0x60c00548) at nsh_consolemain.c:75
16 0x20000e4c in nsh_main (argc=1, argv=0x60c00548) at nsh_main.c:74
17 0x20000062 in nxtask_startup (entrypt=0x20000e11 <nsh_main>, argc=1, argv=0x60c00548)
at sched/task_startup.c:72
18 0x00009ac4 in nxtask_start () at task/task_start.c:106
19 0x60c00548 in ?? ()
Backtrace stopped: previous frame identical to this frame (corrupt stack?)
```
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
This commit add the option that was missing in the esp32_start.c
to ignore the chip version for boards with old ESP32 silicon tape out.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
* Explicit registration of ttys0 when no console defined
* Fixes overwriting registration of lpuart1 on ttys1 when no console on ttys0
* Change regstration logic to check for console assignment
* See issue 17116
Signed-off-by: dirksavage88 <dirksavage88@gmail.com>
The -D_FILE_OFFSET_BITS=64 parameter is missing
during the CMake compilation of the sim (simulator) build,
which causes incorrect version invocations of interfaces
such as hostfs_stat.
Signed-off-by: guohao15 <guohao15@xiaomi.com>
/home/ajh/work/vela_system/nuttx/include/arch/syscall.h:181: Error: operand type mismatch for `movq'
`rax`: Used in 64-bit mode, suitable for storing 64 bits of data.
`eax`: In 64-bit mode, typically used for operating on 32-bit data. When writing to `eax`, the high 32 bits of `rax` are automatically cleared to zero.
`nbr` is an unsigned int, is 32-bit.
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Previously only up to 31 PIO instructions were accepted.
But the hardware allowed 32 instructions.
Now we accept 32 instructions.
See the corresponding commit in the pico-sdk repository:
6f7dc67791
Signed-off-by: Lars Kruse <devel@sumpfralle.de>
Upperhalf supports multiple working modes at the same time,
which is specified by NIC when register
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
After processing a packet of data, do not exit interrupt, but continues
to check whether there is data to be processed. If there is, continue
processing.
Signed-off-by: yangsong8 <yangsong8@xiaomi.com>
when start multiple sim, the host refuses to recognize multiple USB
devices, and the prompt message is as follows:
[365652.175289] UDC core: USB Raw Gadget: couldn't find an available UDC or it's busy
[365652.175304] misc raw-gadget: fail, usb_gadget_probe_driver returned -16
Signed-off-by: yangsong8 <yangsong8@xiaomi.com>
Modifies Kconfig and build tools to support flash encryption
and E-Fuse burning when flash encryption is enabled.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
The efuse initialization requires critical section to avoid a very
hidden corner case when flash encryption is enabled.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Moves the clearing of global variables to the very start
of the chip start up process. This avoids clearing some
globals that are initialized between the new location and
previous location.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
