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ccdc7a3a28
BREAKING CHANGE: Part of splitting the legacy stm32 super-directory; relocates the stm32f0 sources, headers and boards into arch/arm/src/stm32f0, arch/arm/include/stm32f0 and boards/arm/stm32f0. Signed-off-by: raiden00pl <raiden00@railab.me>
238 lines
12 KiB
C
238 lines
12 KiB
C
/****************************************************************************
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* arch/arm/include/stm32f0/chip.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_STM32F0_CHIP_H
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#define __ARCH_ARM_INCLUDE_STM32F0_CHIP_H
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#define ARMV6M_PERIPHERAL_INTERRUPTS 32
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* Get customizations for each supported chip */
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#if defined(CONFIG_ARCH_CHIP_STM32F030RC) || defined(CONFIG_ARCH_CHIP_STM32F030CC)
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# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */
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# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */
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# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
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# define STM32_NI2S 0 /* No I2S modules */
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# define STM32_NI2C 2 /* Two I2C modules */
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# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
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# define STM32_NUSART 6 /* Six USARTs modules */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_NUSBDEV 0 /* One USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 0 /* One DAC channel */
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# define STM32_NCOMP 0 /* Two Analog Comparators */
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# define STM32_NCAP 0 /* Capacitive sensing channels (14 on UFQFPN32)) */
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# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */
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#elif defined(CONFIG_ARCH_CHIP_STM32F051R8)
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# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */
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# define STM32_SRAM_SIZE (8 * 1024) /* 8Kb */
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# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
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# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
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# define STM32_NI2C 2 /* Two I2C modules */
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# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
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# define STM32_NUSART 2 /* Two USARTs modules */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_NUSBDEV 1 /* One USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 1 /* One DAC channel */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCAP 13 /* Capacitive sensing channels (14 on UFQFPN32)) */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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#elif defined(CONFIG_ARCH_CHIP_STM32F072C8) || defined(CONFIG_ARCH_CHIP_STM32F072CB)
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# ifdef CONFIG_ARCH_CHIP_STM32F072C8
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# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */
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# else
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# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */
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# endif
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# define STM32_SRAM_SIZE (16 * 1024) /* 16Kb */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
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# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
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# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
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# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
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# define STM32_NI2C 2 /* Two I2C modules */
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# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
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# define STM32_NUSART 4 /* Four USARTs module */
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# define STM32_NCAN 1 /* One CAN controller */
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# define STM32_NUSBDEV 1 /* One USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 1 /* One HDMI-CEC controller */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 2 /* Two DAC channel */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCAP 17 /* Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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#elif defined(CONFIG_ARCH_CHIP_STM32F072R8) || defined(CONFIG_ARCH_CHIP_STM32F072RB)
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# ifdef CONFIG_ARCH_CHIP_STM32F072R8
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# define STM32_FLASH_SIZE (64*1024) /* 64Kb */
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# else
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# define STM32_FLASH_SIZE (128*1024) /* 128Kb */
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# endif
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# define STM32_SRAM_SIZE (16*1024) /* 16Kb */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
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# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
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# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
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# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
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# define STM32_NI2C 2 /* Two I2C modules */
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# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
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# define STM32_NUSART 4 /* Four USARTs module */
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# define STM32_NCAN 1 /* One CAN controller */
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# define STM32_NUSBDEV 1 /* One USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 1 /* One HDMI-CEC controller */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 2 /* Two DAC channel */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCAP 18 /* Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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#elif defined(CONFIG_ARCH_CHIP_STM32F072V8) || defined(CONFIG_ARCH_CHIP_STM32F072VB)
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# ifdef CONFIG_ARCH_CHIP_STM32F072V8
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# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */
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# else
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# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */
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# endif
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# define STM32_SRAM_SIZE (16 * 1024) /* 16Kb */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
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# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
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# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
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# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
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# define STM32_NI2C 2 /* Two I2C modules */
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# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
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# define STM32_NUSART 4 /* Four USARTs module */
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# define STM32_NCAN 1 /* One CAN controller */
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# define STM32_NUSBDEV 1 /* One USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 1 /* One HDMI-CEC controller */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 2 /* Two DAC channel */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCAP 24 /* Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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#elif defined(CONFIG_ARCH_CHIP_STM32F091CB) || defined(CONFIG_ARCH_CHIP_STM32F091CC)
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# ifdef CONFIG_ARCH_CHIP_STM32F091CB
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# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */
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# else
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# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */
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# endif
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# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
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# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
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# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
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# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
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# define STM32_NI2C 2 /* Two I2C modules */
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# define STM32_NDMA 2 /* DMA1, DMA2 */
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# define STM32_NUSART 6 /* Six USARTs modules */
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# define STM32_NCAN 1 /* One CAN controller */
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# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 1 /* One HDMI-CEC controller */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 2 /* Two DAC channel */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCAP 17 /* Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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#elif defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091RC) || \
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defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC)
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# if defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091VB)
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# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */
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# else
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# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */
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# endif
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# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
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# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
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# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
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# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
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# define STM32_NI2C 2 /* Two I2C modules */
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# define STM32_NDMA 2 /* DMA1, DMA2 */
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# define STM32_NUSART 8 /* Eight USARTs modules */
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# define STM32_NCAN 1 /* One CAN controller */
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# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 1 /* One HDMI-CEC controller */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 2 /* Two DAC channel */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# if defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC)
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# define STM32_NCAP 24 /* Capacitive sensing channels */
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# else
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# define STM32_NCAP 18 /* Capacitive sensing channels */
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# endif
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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#endif
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/* NVIC priority levels *****************************************************/
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/* Each priority field holds a priority value, 0-31. The lower the value,
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* the greater the priority of the corresponding interrupt. The processor
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* implements only bits[7:6] of each field, bits[5:0] read as zero and
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* ignore writes.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */
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#endif /* __ARCH_ARM_INCLUDE_STM32F0_CHIP_H */
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