mirror of
https://github.com/apache/nuttx.git
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79e3c2e59f
Move the stm32c0 sources, headers and boards into arch/arm/src/stm32c0, arch/arm/include/stm32c0 and boards/arm/stm32c0, then finalize the split: source each split family directly in arch/arm/Kconfig and boards/Kconfig and remove the now-empty combined arch/arm/src/stm32f0l0g0 and boards/arm/stm32f0l0g0 trees. BREAKING CHANGE: The combined STM32F0/L0/G0/C0 architecture and board paths were split into stm32f0, stm32l0, stm32g0, and stm32c0 directories. Out-of-tree boards, include paths, source paths, and defconfigs must move from stm32f0l0g0 to the matching split family. Signed-off-by: raiden00pl <raiden00@railab.me>
157 lines
8.5 KiB
C
157 lines
8.5 KiB
C
/****************************************************************************
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* arch/arm/include/stm32c0/chip.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_STM32C0_CHIP_H
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#define __ARCH_ARM_INCLUDE_STM32C0_CHIP_H
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#define ARMV6M_PERIPHERAL_INTERRUPTS 32
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* Get customizations for each supported chip */
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#if defined(CONFIG_ARCH_CHIP_STM32C051XX)
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# define STM32_NATIM 1 /* One advanced timers TIM1 */
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# define STM32_NGTIM16 4 /* Four 16-bit general up/down timers TIM3, TIM14,
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* TIM16 and TIM17 */
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# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */
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# define STM32_NBTIM 0 /* No basic timers */
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/* One LPTIMER */
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# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
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# define STM32_NI2S 0 /* No I2S module */
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# define STM32_NI2C 2 /* Two I2C */
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# define STM32_NDMA 1 /* One DMA1, 5-channels */
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# define STM32_NUSART 2 /* Two USART modules, USART1-2 */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_FDCAN 0 /* No FD CAN */
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# define STM32_NLCD 0 /* No LCD controller */
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# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 0 /* No HDMI-CEC controller */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 0 /* No DAC channels */
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# define STM32_NCOMP 0 /* No Analog Comparators */
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# define STM32_NCRC 1 /* One CRC module */
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# define STM32_NRNG 0 /* No Random number generator (RNG) */
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# define STM32_NCAP 0 /* No Capacitive sensing channels */
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# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */
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#elif defined(CONFIG_ARCH_CHIP_STM32C071XX)
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# define STM32_NATIM 1 /* One advanced timers TIM1 */
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# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM3, TIM14,
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* TIM16 and TIM17 */
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# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */
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# define STM32_NBTIM 0 /* No basic timers */
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/* One LPTIMER */
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# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
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# define STM32_NI2S 0 /* No I2S module */
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# define STM32_NI2C 2 /* Two I2C */
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# define STM32_NDMA 1 /* One DMA1, 5-channels */
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# define STM32_NUSART 2 /* Two USART modules, USART1-2 */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_FDCAN 0 /* No FD CAN */
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# define STM32_NLCD 0 /* No LCD controller */
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# define STM32_NUSBDEV 1 /* USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 0 /* No HDMI-CEC controller */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 0 /* No DAC channels */
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# define STM32_NCOMP 0 /* No Analog Comparators */
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# define STM32_NCRC 1 /* One CRC module */
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# define STM32_NRNG 0 /* No Random number generator (RNG) */
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# define STM32_NCAP 0 /* No Capacitive sensing channels */
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# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */
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#elif defined(CONFIG_ARCH_CHIP_STM32C091XX)
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# define STM32_NATIM 1 /* One advanced timers TIM1 */
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# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14,
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* TIM15, TIM16 and TIM17 */
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# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */
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# define STM32_NBTIM 0 /* No basic timers */
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/* One LPTIMER */
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# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
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# define STM32_NI2S 0 /* No I2S module */
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# define STM32_NI2C 2 /* Two I2C */
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# define STM32_NDMA 1 /* One DMA1, 5-channels */
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# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_FDCAN 0 /* No FD CAN */
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# define STM32_NLCD 0 /* No LCD controller */
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# define STM32_NUSBDEV 1 /* USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 0 /* No HDMI-CEC controller */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 0 /* No DAC channels */
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# define STM32_NCOMP 0 /* No Analog Comparators */
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# define STM32_NCRC 1 /* One CRC module */
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# define STM32_NRNG 0 /* No Random number generator (RNG) */
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# define STM32_NCAP 0 /* No Capacitive sensing channels */
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# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */
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#elif defined(CONFIG_ARCH_CHIP_STM32C092XX)
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# define STM32_NATIM 1 /* One advanced timers TIM1 */
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# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14,
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* TIM15, TIM16 and TIM17 */
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# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */
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# define STM32_NBTIM 0 /* No basic timers */
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/* One LPTIMER */
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# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
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# define STM32_NI2S 0 /* No I2S module */
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# define STM32_NI2C 2 /* Two I2C */
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# define STM32_NDMA 1 /* One DMA1, 5-channels */
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# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_FDCAN 1 /* One FD CAN */
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# define STM32_NLCD 0 /* No LCD controller */
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# define STM32_NUSBDEV 1 /* USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 0 /* No HDMI-CEC controller */
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 0 /* No DAC channels */
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# define STM32_NCOMP 0 /* No Analog Comparators */
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# define STM32_NCRC 1 /* One CRC module */
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# define STM32_NRNG 0 /* No Random number generator (RNG) */
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# define STM32_NCAP 0 /* No Capacitive sensing channels */
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# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */
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#else
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# error "Unsupported STM32 Cortex M0 chip"
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#endif
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/* NVIC priority levels *****************************************************/
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/* Each priority field holds a priority value, 0-31. The lower the value,
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* the greater the priority of the corresponding interrupt. The processor
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* implements only bits[7:6] of each field, bits[5:0] read as zero and
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* ignore writes.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */
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#endif /* __ARCH_ARM_INCLUDE_STM32C0_CHIP_H */
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