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!arch/stm32f0l0g0: move stm32c0 and finalize the directory split
Move the stm32c0 sources, headers and boards into arch/arm/src/stm32c0, arch/arm/include/stm32c0 and boards/arm/stm32c0, then finalize the split: source each split family directly in arch/arm/Kconfig and boards/Kconfig and remove the now-empty combined arch/arm/src/stm32f0l0g0 and boards/arm/stm32f0l0g0 trees. BREAKING CHANGE: The combined STM32F0/L0/G0/C0 architecture and board paths were split into stm32f0, stm32l0, stm32g0, and stm32c0 directories. Out-of-tree boards, include paths, source paths, and defconfigs must move from stm32f0l0g0 to the matching split family. Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl
Alan C. Assis
parent
6d6bcbfcba
commit
79e3c2e59f
81 changed files with 865 additions and 3262 deletions
559
.github/CODEOWNERS
vendored
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@ -905,9 +905,7 @@ arch/arm/include/mps/irq.h anjiahao@xiaomi.com alin.jerpelea@sony.com
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arch/arm/include/mx8mp/chip.h philippe.leduc@wandercraft.eu alin.jerpelea@sony.com
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arch/arm/include/mx8mp/irq.h philippe.leduc@wandercraft.eu alin.jerpelea@sony.com
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arch/arm/include/mx8mp/mx8mp_irq.h philippe.leduc@wandercraft.eu devel@sumpfralle.de alin.jerpelea@sony.com
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arch/arm/include/nrf* raiden00@railab.me alin.jerpelea@sony.com
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arch/arm/include/nuc1xx/chip.h alin.jerpelea@sony.com loketep@yahoo.com xiaoxiang@xiaomi.com
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arch/arm/include/nuc1xx/irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com xiaoxiang@xiaomi.com
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arch/arm/include/nuc1xx/nuc120_irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com xiaoxiang@xiaomi.com
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@ -974,17 +972,17 @@ arch/arm/include/stm32/stm32f37xxx_irq.h 59230071+hartmannathan@users.noreply.gi
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arch/arm/include/stm32/stm32f40xxx_irq.h gwenj@trabucayre.com paul-a.patience@polymtl.ca david_s5@usa.net alin.jerpelea@sony.com
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arch/arm/include/stm32/stm32g4xxxx_irq.h raiden00@railab.me alin.jerpelea@sony.com devel@sumpfralle.de gustavo.nihei@espressif.com
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arch/arm/include/stm32/stm32l15xxx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com xiaoxiang@xiaomi.com
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arch/arm/include/stm32f0l0g0/chip.h raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com tbennett@2g-eng.com
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arch/arm/include/stm32f0l0g0/irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me gustavo.nihei@espressif.com
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arch/arm/include/stm32f0l0g0/stm32c0_irq.h raiden00@railab.me
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arch/arm/include/stm32f0l0g0/stm32f0_irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com
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arch/arm/include/stm32f0l0g0/stm32g0_irq.h dpo@certi.org.br 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com kwilson@2g-eng.com
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arch/arm/include/stm32f0l0g0/stm32l0_irq.h alin.jerpelea@sony.com raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com xiaoxiang@xiaomi.com
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arch/arm/include/stm32c0/chip.h raiden00@railab.me
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arch/arm/include/stm32c0/irq.h raiden00pl@gmail.com dpo@certi.org.br raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com
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arch/arm/include/stm32f0/chip.h raiden00@railab.me juha.niskanen@haltian.com dave@marples.net acassis@gmail.com
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arch/arm/include/stm32f0/irq.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com peter.barada@gmail.com
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arch/arm/include/stm32f7/chip.h david_s5@usa.net alin.jerpelea@sony.com bob.feretich@rafresearch.com dave@marples.net
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arch/arm/include/stm32f7/irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com bob.feretich@rafresearch.com david_s5@usa.net
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arch/arm/include/stm32f7/stm32f72xx73xx_irq.h bob.feretich@rafresearch.com alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com gustavo.nihei@espressif.com
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arch/arm/include/stm32f7/stm32f74xx75xx_irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com gustavo.nihei@espressif.com titus@elbe-informatik.de
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arch/arm/include/stm32f7/stm32f76xx77xx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com gustavo.nihei@espressif.com
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arch/arm/include/stm32g0/chip.h raiden00@railab.me
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arch/arm/include/stm32g0/irq.h raiden00pl@gmail.com dpo@certi.org.br raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com
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arch/arm/include/stm32h5/chip.h kwilson@2g-eng.com tbennett@2g-eng.com alin.jerpelea@sony.com
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arch/arm/include/stm32h5/irq.h kwilson@2g-eng.com alin.jerpelea@sony.com
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arch/arm/include/stm32h5/stm32h5xx_irq.h kwilson@2g-eng.com alin.jerpelea@sony.com
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@ -994,6 +992,8 @@ arch/arm/include/stm32h7/stm32h7x3xx_irq.h simon@leitwert.ch David.Sidrane@NscDg
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arch/arm/include/stm32h7/stm32h7x5xx_cpu2_irq.h raiden00@railab.me alin.jerpelea@sony.com
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arch/arm/include/stm32h7/stm32h7x5xx_irq.h raiden00@railab.me alin.jerpelea@sony.com
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arch/arm/include/stm32h7/stm32h7x7xx_irq.h 59230071+hartmannathan@users.noreply.github.com lwazeh@gmail.com alin.jerpelea@sony.com gustavo.nihei@espressif.com
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arch/arm/include/stm32l0/chip.h raiden00@railab.me
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arch/arm/include/stm32l0/irq.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com peter.barada@gmail.com 59230071+hartmannathan@users.noreply.github.com
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arch/arm/include/stm32l4/chip.h juha.niskanen@haltian.com sebastien@lorquet.fr dave@marples.net alin.jerpelea@sony.com
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arch/arm/include/stm32l4/irq.h sebastien@lorquet.fr 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com juha.niskanen@haltian.com
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arch/arm/include/stm32l4/stm32l4x3xx_irq.h juha.niskanen@haltian.com 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com daniel.carvalho@ufu.br
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@ -3431,7 +3431,6 @@ arch/arm/src/rp2040/rp2040_ws2812.h 58759586+curuvar@users.noreply.github.com xi
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arch/arm/src/rp2040/rp2040_ws2812.pio 58759586+curuvar@users.noreply.github.com alin.jerpelea@sony.com xiaoxiang@xiaomi.com devel@sumpfralle.de
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arch/arm/src/rp2040/rp2040_xosc.c y.512.nakamura@gmail.com ian@iandouglasscott.com xiaoxiang@xiaomi.com yinshengkai@xiaomi.com
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arch/arm/src/rp2040/rp2040_xosc.h y.512.nakamura@gmail.com alin.jerpelea@sony.com
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arch/arm/src/rp23xx/* marco.casaroli@gmail.com alin.jerpelea@sony.com bijunda@dreame.tech
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arch/arm/src/rtl8720c/* jerry_tang@realsil.com.cn petro.karashchenko@gmail.com alin.jerpelea@sony.com
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arch/arm/src/s32k1xx/* jari.vanewijk@nxp.com peter.vanderperk@nxp.com David.Sidrane@NscDg.com alin.jerpelea@sony.com gustavo.nihei@espressif.com
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@ -3440,7 +3439,6 @@ arch/arm/src/sama5/* alin.jerpelea@sony.com adam@adamfeuer.com 56726697+TimJTi@u
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arch/arm/src/samd2l2/* alin.jerpelea@sony.com
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arch/arm/src/samd5e5/* alin.jerpelea@sony.com xiaoxiang@xiaomi.com leomar@falker.com.br
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arch/arm/src/samv7/* michallenc@seznam.cz petro.karashchenko@gmail.com pressste@fel.cvut.cz alin.jerpelea@sony.com xiaoxiang@xiaomi.com
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arch/arm/src/stm32/Kconfig raiden00pl@gmail.com raiden00@railab.me danieloak@gmail.com
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arch/arm/src/stm32/chip.h raiden00pl@gmail.com alin.jerpelea@sony.com paul-a.patience@polymtl.ca
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arch/arm/src/stm32/hardware/stm32_adc.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com
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@ -3746,142 +3744,38 @@ arch/arm/src/stm32/stm32l15xx_flash.c alin.jerpelea@sony.com abdelatif.guettouch
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arch/arm/src/stm32/stm32l15xxx_alarm.h juha.niskanen@haltian.com alin.jerpelea@sony.com xiaoxiang@xiaomi.com 59230071+hartmannathan@users.noreply.github.com
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arch/arm/src/stm32/stm32l15xxx_rcc.c 59230071+hartmannathan@users.noreply.github.com juha.niskanen@haltian.com alin.jerpelea@sony.com raiden00pl@gmail.com
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arch/arm/src/stm32/stm32l15xxx_rtcc.c juha.niskanen@haltian.com xiaoxiang@xiaomi.com 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/Kconfig dpo@certi.org.br raiden00@railab.me kwilson@2g-eng.com tbennett@2g-eng.com
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arch/arm/src/stm32f0l0g0/chip.h alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h tbennett@2g-eng.com alin.jerpelea@sony.com raiden00@railab.me kwilson@2g-eng.com
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arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32_can.h alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h raiden00@railab.me alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h alin.jerpelea@sony.com devel@sumpfralle.de
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arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com devel@sumpfralle.de
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arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h raiden00@railab.me
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arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h alin.jerpelea@sony.com raiden00@railab.me
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arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h alin.jerpelea@sony.com raiden00@railab.me
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arch/arm/src/stm32f0l0g0/hardware/stm32_fdcan.h raiden00@railab.me
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arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h alin.jerpelea@sony.com raiden00@railab.me
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arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h alin.jerpelea@sony.com raiden00@railab.me hartman.nathan@gmail.com
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arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h alin.jerpelea@sony.com acassis@gmail.com raiden00@railab.me
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arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h alin.jerpelea@sony.com David.Sidrane@NscDg.com acassis@gmail.com raiden00@railab.me
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arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
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arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h alin.jerpelea@sony.com raiden00@railab.me
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arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h alin.jerpelea@sony.com gustavo.nihei@espressif.com
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arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h alin.jerpelea@sony.com raiden00@railab.me
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arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h dpo@certi.org.br alin.jerpelea@sony.com raiden00@railab.me gvr@certi.org.br
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arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h alin.jerpelea@sony.com petro.karashchenko@gmail.com
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arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com petro.karashchenko@gmail.com
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arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h raiden00@railab.me
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arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32c0_dmamux.h raiden00@railab.me
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arch/arm/src/stm32f0l0g0/hardware/stm32c0_exti.h raiden00@railab.me
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arch/arm/src/stm32f0l0g0/hardware/stm32c0_flash.h raiden00@railab.me
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arch/arm/src/stm32f0l0g0/hardware/stm32c0_memorymap.h raiden00@railab.me
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arch/arm/src/stm32f0l0g0/hardware/stm32c0_pinmap.h raiden00@railab.me
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arch/arm/src/stm32f0l0g0/hardware/stm32c0_pwr.h raiden00@railab.me
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arch/arm/src/stm32f0l0g0/hardware/stm32c0_rcc.h raiden00@railab.me
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arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h acassis@gmail.com alin.jerpelea@sony.com raiden00@railab.me petro.karashchenko@gmail.com gustavo.nihei@espressif.com
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arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h acassis@gmail.com David.Sidrane@NscDg.com alin.jerpelea@sony.com xiaoxiang@xiaomi.com
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arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap_legacy.h David.Sidrane@NscDg.com alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h David.Sidrane@NscDg.com alin.jerpelea@sony.com xiaoxiang@xiaomi.com
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arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap_legacy.h David.Sidrane@NscDg.com alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h alin.jerpelea@sony.com raiden00@railab.me petro.karashchenko@gmail.com
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arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h David.Sidrane@NscDg.com alin.jerpelea@sony.com xiaoxiang@xiaomi.com
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arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap_legacy.h David.Sidrane@NscDg.com alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h David.Sidrane@NscDg.com alin.jerpelea@sony.com xiaoxiang@xiaomi.com
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arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap_legacy.h David.Sidrane@NscDg.com alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h alin.jerpelea@sony.com gustavo.nihei@espressif.com
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arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h alin.jerpelea@sony.com raiden00@railab.me
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arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com
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arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h kwilson@2g-eng.com raiden00@railab.me alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h raiden00@railab.me alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h tbennett@2g-eng.com alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h raiden00@railab.me alin.jerpelea@sony.com raiden00pl@gmail.com petro.karashchenko@gmail.com
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arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h dpo@certi.org.br David.Sidrane@NscDg.com raiden00@railab.me gvr@certi.org.br
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arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap_legacy.h David.Sidrane@NscDg.com tbennett@2g-eng.com alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h alin.jerpelea@sony.com raiden00@railab.me
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arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h raiden00@railab.me alin.jerpelea@sony.com raiden00pl@gmail.com kwilson@2g-eng.com
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arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h raiden00@railab.me alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32l0_exti.h alin.jerpelea@sony.com gustavo.nihei@espressif.com
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arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h raiden00@railab.me alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h David.Sidrane@NscDg.com raiden00@railab.me alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap_legacy.h David.Sidrane@NscDg.com alin.jerpelea@sony.com
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arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h alin.jerpelea@sony.com raiden00@railab.me
|
||||
arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h raiden00@railab.me alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h raiden00@railab.me alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32f0l0g0/stm32.h alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_adc.c raiden00@railab.me xiaoxiang@xiaomi.com tbennett@2g-eng.com kwilson@2g-eng.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_adc.h raiden00@railab.me xiaoxiang@xiaomi.com kwilson@2g-eng.com alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_aes.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com anjiahao@xiaomi.com wangbowen6@xiaomi.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_aes.h alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_crypto.c anjiahao@xiaomi.com devel@sumpfralle.de alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_dma.c raiden00@railab.me
|
||||
arch/arm/src/stm32f0l0g0/stm32_dma.h 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_dma_v1.c alin.jerpelea@sony.com anjiahao@xiaomi.com xiaoxiang@xiaomi.com abdelatif.guettouche@gmail.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c raiden00@railab.me kwilson@2g-eng.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_exti.h alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_fdcan.c raiden00@railab.me
|
||||
arch/arm/src/stm32f0l0g0/stm32_fdcan.h raiden00@railab.me
|
||||
arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c raiden00@railab.me carlossanchez@geotab.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_flash.c tbennett@2g-eng.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_flash.h tbennett@2g-eng.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_gpio.c alin.jerpelea@sony.com hujun5@xiaomi.com xiaoxiang@xiaomi.com David.Sidrane@NscDg.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_gpio.h alin.jerpelea@sony.com t-ando@advaly.co.jp 59230071+hartmannathan@users.noreply.github.com xiaoxiang@xiaomi.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_hsi48.c alin.jerpelea@sony.com kwilson@2g-eng.com devel@sumpfralle.de xiaoxiang@xiaomi.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_hsi48.h alin.jerpelea@sony.com devel@sumpfralle.de
|
||||
arch/arm/src/stm32f0l0g0/stm32_i2c.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com anjiahao@xiaomi.com yamamoto@midokura.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_i2c.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com juha.niskanen@haltian.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_idle.c alin.jerpelea@sony.com gustavo.nihei@espressif.com abdelatif.guettouche@gmail.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_irq.c xiaoxiang@xiaomi.com alin.jerpelea@sony.com wangzhi16@xiaomi.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_iwdg.c raiden00@railab.me
|
||||
arch/arm/src/stm32f0l0g0/stm32_lowputc.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_lowputc.h alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com hartman.nathan@gmail.com raiden00pl@gmail.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c alin.jerpelea@sony.com raiden00pl@gmail.com xiaoxiang@xiaomi.com hartman.nathan@gmail.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_lse.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com gustavo.nihei@espressif.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_lsi.c raiden00@railab.me
|
||||
arch/arm/src/stm32f0l0g0/stm32_pwm.c dpo@certi.org.br gvr@certi.org.br anthony@vergeaero.com xiaoxiang@xiaomi.com 59230071+hartmannathan@users.noreply.github.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_pwm.h dpo@certi.org.br alin.jerpelea@sony.com gvr@certi.org.br anchao@xiaomi.com xiaoxiang@xiaomi.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_pwr.c dpo@certi.org.br alin.jerpelea@sony.com huangqi3@xiaomi.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_pwr.h alin.jerpelea@sony.com dpo@certi.org.br
|
||||
arch/arm/src/stm32f0l0g0/stm32_rcc.c alin.jerpelea@sony.com raiden00@railab.me 85544393+oreh-a@users.noreply.github.com alexander.oryshchenko@ge.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_rcc.h alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_rng.c alin.jerpelea@sony.com anjiahao@xiaomi.com xiaoxiang@xiaomi.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_serial.c alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_serial.h alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_serial_v1.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com David.Sidrane@NscDg.com yangsong8@xiaomi.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_serial_v2.c alin.jerpelea@sony.com David.Sidrane@NscDg.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_spi.c raiden00@railab.me petro.karashchenko@gmail.com xiaoxiang@xiaomi.com anjiahao@xiaomi.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_spi.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com raiden00@railab.me petro.karashchenko@gmail.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_start.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com raiden00@railab.me yinshengkai@xiaomi.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_start.h alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_tim.c dpo@certi.org.br xiaoxiang@xiaomi.com yamamoto@midokura.com anthony@vergeaero.com raiden00@railab.me
|
||||
arch/arm/src/stm32f0l0g0/stm32_tim.h dpo@certi.org.br xiaoxiang@xiaomi.com alin.jerpelea@sony.com danieloak@gmail.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c dpo@certi.org.br xiaoxiang@xiaomi.com yamamoto@midokura.com alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_timerisr.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_uart.h alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_uid.c kwilson@2g-eng.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_uid.h kwilson@2g-eng.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_usbdev.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com wangzhi16@xiaomi.com gustavo.nihei@espressif.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_usbdev.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
arch/arm/src/stm32f0l0g0/stm32_wdg.h raiden00@railab.me
|
||||
arch/arm/src/stm32f0l0g0/stm32_wwdg.c raiden00@railab.me
|
||||
arch/arm/src/stm32f0l0g0/stm32c0_rcc.c raiden00@railab.me
|
||||
arch/arm/src/stm32f0l0g0/stm32f0_rcc.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com alexander.oryshchenko@ge.com
|
||||
arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
arch/arm/src/stm32f0l0g0/stm32g0_flash.c tbennett@2g-eng.com simbit18@gmail.com
|
||||
arch/arm/src/stm32f0l0g0/stm32g0_pwr.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
arch/arm/src/stm32f0l0g0/stm32g0_rcc.c alin.jerpelea@sony.com dpo@certi.org.br raiden00@railab.me raiden00pl@gmail.com
|
||||
arch/arm/src/stm32f0l0g0/stm32l0_rcc.c raiden00@railab.me xiaoxiang@xiaomi.com alin.jerpelea@sony.com alexander.oryshchenko@ge.com
|
||||
arch/arm/src/stm32c0/Kconfig raiden00@railab.me
|
||||
arch/arm/src/stm32c0/chip.h alin.jerpelea@sony.com acassis@gmail.com raiden00@railab.me raiden00pl@gmail.com
|
||||
arch/arm/src/stm32c0/hardware/stm32_memorymap.h raiden00@railab.me
|
||||
arch/arm/src/stm32c0/hardware/stm32_pinmap.h raiden00@railab.me
|
||||
arch/arm/src/stm32c0/hardware/stm32c0_dmamux.h raiden00pl@gmail.com raiden00@railab.me pettitkd@gmail.com alin.jerpelea@sony.com acassis@gmail.com
|
||||
arch/arm/src/stm32c0/hardware/stm32c0_exti.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32c0/hardware/stm32c0_flash.h raiden00@railab.me raiden00pl@gmail.com alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32c0/hardware/stm32c0_memorymap.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com petro.karashchenko@gmail.com t-ando@advaly.co.jp
|
||||
arch/arm/src/stm32c0/hardware/stm32c0_pinmap.h raiden00@railab.me
|
||||
arch/arm/src/stm32c0/hardware/stm32c0_pwr.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32c0/hardware/stm32c0_rcc.h raiden00@railab.me
|
||||
arch/arm/src/stm32c0/stm32.h alin.jerpelea@sony.com raiden00pl@gmail.com pettitkd@gmail.com raiden00@railab.me acassis@gmail.com
|
||||
arch/arm/src/stm32c0/stm32_rcc.c raiden00@railab.me alin.jerpelea@sony.com raiden00pl@gmail.com 85544393+oreh-a@users.noreply.github.com alexander.oryshchenko@ge.com
|
||||
arch/arm/src/stm32c0/stm32c0_rcc.c raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com dpo@certi.org.br juha.niskanen@haltian.com
|
||||
arch/arm/src/stm32f0/Kconfig acassis@gmail.com raiden00@railab.me jussi.kivilinna@haltian.com raiden00pl@gmail.com david_s5@nscdg.com
|
||||
arch/arm/src/stm32f0/chip.h alin.jerpelea@sony.com acassis@gmail.com raiden00@railab.me raiden00pl@gmail.com
|
||||
arch/arm/src/stm32f0/hardware/stm32_memorymap.h raiden00@railab.me
|
||||
arch/arm/src/stm32f0/hardware/stm32_pinmap.h raiden00@railab.me
|
||||
arch/arm/src/stm32f0/hardware/stm32f03x_memorymap.h alin.jerpelea@sony.com acassis@gmail.com raiden00pl@gmail.com raiden00@railab.me petro.karashchenko@gmail.com
|
||||
arch/arm/src/stm32f0/hardware/stm32f03x_pinmap.h acassis@gmail.com David.Sidrane@NscDg.com alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
arch/arm/src/stm32f0/hardware/stm32f05x_pinmap.h acassis@gmail.com David.Sidrane@NscDg.com alin.jerpelea@sony.com raiden00pl@gmail.com raiden00@railab.me
|
||||
arch/arm/src/stm32f0/hardware/stm32f05xf07xf09x_memorymap.h alin.jerpelea@sony.com raiden00pl@gmail.com raiden00@railab.me petro.karashchenko@gmail.com david_s5@nscdg.com
|
||||
arch/arm/src/stm32f0/hardware/stm32f07x_pinmap.h David.Sidrane@NscDg.com raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
arch/arm/src/stm32f0/hardware/stm32f09x_pinmap.h David.Sidrane@NscDg.com alin.jerpelea@sony.com raiden00pl@gmail.com juha.niskanen@haltian.com raiden00@railab.me
|
||||
arch/arm/src/stm32f0/hardware/stm32f0_exti.h alin.jerpelea@sony.com raiden00@railab.me raiden00pl@gmail.com david_s5@usa.net bob.feretich@rafresearch.com
|
||||
arch/arm/src/stm32f0/hardware/stm32f0_flash.h alin.jerpelea@sony.com raiden00pl@gmail.com raiden00@railab.me
|
||||
arch/arm/src/stm32f0/hardware/stm32f0_pwr.h acassis@gmail.com alin.jerpelea@sony.com raiden00pl@gmail.com raiden00@railab.me
|
||||
arch/arm/src/stm32f0/hardware/stm32f0_rcc.h acassis@gmail.com raiden00pl@gmail.com alin.jerpelea@sony.com mrechte2@yahoo.com raiden00@railab.me
|
||||
arch/arm/src/stm32f0/hardware/stm32f0_syscfg.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com raiden00pl@gmail.com raiden00@railab.me
|
||||
arch/arm/src/stm32f0/stm32.h alin.jerpelea@sony.com raiden00pl@gmail.com pettitkd@gmail.com raiden00@railab.me acassis@gmail.com
|
||||
arch/arm/src/stm32f0/stm32_rcc.c raiden00@railab.me alin.jerpelea@sony.com raiden00pl@gmail.com 85544393+oreh-a@users.noreply.github.com alexander.oryshchenko@ge.com
|
||||
arch/arm/src/stm32f0/stm32f0_rcc.c raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com xiaoxiang@xiaomi.com piyushpatle228@gmail.com
|
||||
arch/arm/src/stm32f7/Kconfig david_s5@nscdg.com raiden00@railab.me david_s5@usa.net titus@elbe-informatik.de
|
||||
arch/arm/src/stm32f7/chip.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com Lok Tep 1 file changed, 1 insertion(+)
|
||||
arch/arm/src/stm32f7/hardware/stm32_adc.h alin.jerpelea@sony.com
|
||||
|
|
@ -4046,6 +3940,21 @@ arch/arm/src/stm32f7/stm32_waste.h ville.juven@unikie.com 101105604+simbit18@use
|
|||
arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c bob.feretich@rafresearch.com alin.jerpelea@sony.com b.brandt@messwerk-gmbh.de ramtin@lambdaconcept.com
|
||||
arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c david_s5@nscdg.com jussi.kivilinna@haltian.com alin.jerpelea@sony.com b.brandt@messwerk-gmbh.de
|
||||
arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c david_s5@usa.net david_s5@nscdg.com titus@elbe-informatik.de jussi.kivilinna@haltian.com alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32g0/Kconfig raiden00@railab.me
|
||||
arch/arm/src/stm32g0/chip.h alin.jerpelea@sony.com acassis@gmail.com raiden00@railab.me raiden00pl@gmail.com
|
||||
arch/arm/src/stm32g0/hardware/stm32_memorymap.h raiden00@railab.me
|
||||
arch/arm/src/stm32g0/hardware/stm32_pinmap.h raiden00@railab.me
|
||||
arch/arm/src/stm32g0/hardware/stm32g0_dmamux.h kwilson@2g-eng.com raiden00pl@gmail.com raiden00@railab.me pettitkd@gmail.com alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32g0/hardware/stm32g0_exti.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32g0/hardware/stm32g0_flash.h tbennett@2g-eng.com raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me
|
||||
arch/arm/src/stm32g0/hardware/stm32g0_memorymap.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com petro.karashchenko@gmail.com kwilson@2g-eng.com
|
||||
arch/arm/src/stm32g0/hardware/stm32g0_pinmap.h raiden00pl@gmail.com dpo@certi.org.br raiden00@railab.me David.Sidrane@NscDg.com gvr@certi.org.br
|
||||
arch/arm/src/stm32g0/hardware/stm32g0_pwr.h raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me
|
||||
arch/arm/src/stm32g0/hardware/stm32g0_rcc.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com kwilson@2g-eng.com tbennett@2g-eng.com
|
||||
arch/arm/src/stm32g0/hardware/stm32g0_syscfg.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32g0/stm32.h alin.jerpelea@sony.com raiden00pl@gmail.com pettitkd@gmail.com raiden00@railab.me acassis@gmail.com
|
||||
arch/arm/src/stm32g0/stm32_rcc.c raiden00@railab.me alin.jerpelea@sony.com raiden00pl@gmail.com 85544393+oreh-a@users.noreply.github.com alexander.oryshchenko@ge.com
|
||||
arch/arm/src/stm32g0/stm32g0_rcc.c raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me dpo@certi.org.br juha.niskanen@haltian.com
|
||||
arch/arm/src/stm32h5/Kconfig kwilson@2g-eng.com tbennett@2g-eng.com 101105604+simbit18@users.noreply.github.com raiden00@railab.me jlange@2g-eng.com
|
||||
arch/arm/src/stm32h5/chip.h kwilson@2g-eng.com tbennett@2g-eng.com alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32h5/hardware/stm32_adc.h tbennett@2g-eng.com 101105604+simbit18@users.noreply.github.com
|
||||
|
|
@ -4276,6 +4185,20 @@ arch/arm/src/stm32h7/stm32h743xx_flash.c javiercasas@geotab.com petro.karashchen
|
|||
arch/arm/src/stm32h7/stm32h7b3xx_flash.c javiercasas@geotab.com petro.karashchenko@gmail.com alin.jerpelea@sony.com lipengfei28@xiaomi.com
|
||||
arch/arm/src/stm32h7/stm32h7x3xx_rcc.c simon@leitwert.ch raiden00pl@gmail.com david.sidrane@nscdg.com raiden00@railab.me anthony@vergeaero.com
|
||||
arch/arm/src/stm32h7/stm32h7x7xx_rcc.c lwazeh@gmail.com anthony@vergeaero.com raiden00@railab.me alin.jerpelea@sony.com jfbblue0922@gmail.com
|
||||
arch/arm/src/stm32l0/Kconfig raiden00@railab.me
|
||||
arch/arm/src/stm32l0/chip.h alin.jerpelea@sony.com acassis@gmail.com raiden00@railab.me raiden00pl@gmail.com
|
||||
arch/arm/src/stm32l0/hardware/stm32_memorymap.h raiden00@railab.me
|
||||
arch/arm/src/stm32l0/hardware/stm32_pinmap.h raiden00@railab.me
|
||||
arch/arm/src/stm32l0/hardware/stm32l0_exti.h alin.jerpelea@sony.com raiden00pl@gmail.com raiden00@railab.me david_s5@usa.net bob.feretich@rafresearch.com
|
||||
arch/arm/src/stm32l0/hardware/stm32l0_flash.h raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me
|
||||
arch/arm/src/stm32l0/hardware/stm32l0_memorymap.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com juha.niskanen@haltian.com
|
||||
arch/arm/src/stm32l0/hardware/stm32l0_pinmap.h David.Sidrane@NscDg.com raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32l0/hardware/stm32l0_pwr.h raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me
|
||||
arch/arm/src/stm32l0/hardware/stm32l0_rcc.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32l0/hardware/stm32l0_syscfg.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com acassis@gmail.com
|
||||
arch/arm/src/stm32l0/stm32.h alin.jerpelea@sony.com raiden00pl@gmail.com pettitkd@gmail.com raiden00@railab.me acassis@gmail.com
|
||||
arch/arm/src/stm32l0/stm32_rcc.c raiden00@railab.me alin.jerpelea@sony.com raiden00pl@gmail.com 85544393+oreh-a@users.noreply.github.com alexander.oryshchenko@ge.com
|
||||
arch/arm/src/stm32l0/stm32l0_rcc.c raiden00pl@gmail.com raiden00@railab.me juha.niskanen@haltian.com matteo.golin@gmail.com xiaoxiang@xiaomi.com
|
||||
arch/arm/src/stm32l4/Kconfig dev@ziggurat29.com danieloak@gmail.com juha.niskanen@haltian.com sebastien@lorquet.fr
|
||||
arch/arm/src/stm32l4/chip.h sebastien@lorquet.fr alin.jerpelea@sony.com juha.niskanen@haltian.com
|
||||
arch/arm/src/stm32l4/hardware/stm32l4_adc.h danieloak@gmail.com alin.jerpelea@sony.com anchao@xiaomi.com acassis@gmail.com
|
||||
|
|
@ -4698,12 +4621,10 @@ arch/arm/src/stm32wl5/stm32wl5_userspace.c michal.lyszczek@bofc.pl alin.jerpelea
|
|||
arch/arm/src/stm32wl5/stm32wl5_userspace.h michal.lyszczek@bofc.pl alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32wl5/stm32wl5_waste.c michal.lyszczek@bofc.pl alin.jerpelea@sony.com
|
||||
arch/arm/src/stm32wl5/stm32wl5_waste.h michal.lyszczek@bofc.pl alin.jerpelea@sony.com
|
||||
|
||||
arch/arm/src/str71x/* alin.jerpelea@sony.com
|
||||
arch/arm/src/tiva/* alin.jerpelea@sony.com xiaoxiang@xiaomi.com hartman.nathan@gmail.com
|
||||
arch/arm/src/tlsr82/* wangbowen6@xiaomi.com devel@sumpfralle.de alin.jerpelea@sony.com
|
||||
arch/arm/src/tms570/* xiaoxiang@xiaomi.com alin.jerpelea@sony.com
|
||||
|
||||
arch/arm/src/xmc4/Kconfig 101105604+simbit18@users.noreply.github.com adrien.desproges@gmail.com nicolas.lemble@gmail.com acassis@gmail.com
|
||||
arch/arm/src/xmc4/chip.h alin.jerpelea@sony.com raiden00pl@gmail.com
|
||||
arch/arm/src/xmc4/hardware/xmc4_ccu4.h thomas.narayana-swamy@wandercraft.eu nicolas.lemble@gmail.com alin.jerpelea@sony.com adrien.desproges@gmail.com
|
||||
|
|
@ -10399,179 +10320,175 @@ boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c alin.jerpelea@sony.com x
|
|||
boards/arm/stm32/viewtool-stm32f107/src/stm32_usbdev.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32/viewtool-stm32f107/src/stm32_usbmsc.c alin.jerpelea@sony.com
|
||||
boards/arm/stm32/viewtool-stm32f107/src/viewtool_stm32f107.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com petro.karashchenko@gmail.com thomas.narayana-swamy@wandercraft.eu raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/b-l072z-lrwan1/Kconfig alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h alin.jerpelea@sony.com raiden00@railab.me devel@sumpfralle.de anthony@vergeaero.com
|
||||
boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/ld.script alin.jerpelea@sony.com acassis@gmail.com cuiziwei@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_adc.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_appinit.c alin.jerpelea@sony.com raiden00@railab.me gustavo.nihei@espressif.com 59230071+hartmannathan@users.noreply.github.com hartman.nathan@gmail.com
|
||||
boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_autoleds.c alin.jerpelea@sony.com raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_sx127x.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com gustavo.nihei@espressif.com
|
||||
boards/arm/stm32f0l0g0/common/Kconfig raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/common/Makefile raiden00@railab.me alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/common/include/stm32_ssd1306.h raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/common/src/stm32_ssd1306.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/nucleo-c071rb/Kconfig raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c071rb/include/board.h raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/flash.ld raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c071rb/src/nucleo-c071rb.h raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_adc.c raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_appinit.c raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_autoleds.c raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_buttons.c raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_userleds.c raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c092rc/Kconfig raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c092rc/include/board.h raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/flash.ld raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_adc.c raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_appinit.c raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_autoleds.c raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_buttons.c raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_can.c raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_cansock.c raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_userleds.c raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-f072rb/Kconfig alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com devel@sumpfralle.de anthony@vergeaero.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/flash.ld alin.jerpelea@sony.com raiden00@railab.me cuiziwei@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f072rb/src/nucleo-f072rb.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_appinit.c alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com hartman.nathan@gmail.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_autoleds.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_boot.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com devel@sumpfralle.de
|
||||
boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_buttons.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_userleds.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f091rc/Kconfig alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com devel@sumpfralle.de anthony@vergeaero.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/flash.ld alin.jerpelea@sony.com raiden00@railab.me cuiziwei@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f091rc/src/nucleo-f091rc.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_appinit.c alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com hartman.nathan@gmail.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_autoleds.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_bringup.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_buttons.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_sx127x.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_userleds.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g070rb/Kconfig dpo@certi.org.br
|
||||
boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig dpo@certi.org.br gvr@certi.org.br xiaoxiang@xiaomi.com liguiding1@xiaomi.com gustavo.nihei@espressif.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g070rb/include/board.h dpo@certi.org.br alin.jerpelea@sony.com raiden00@railab.me gvr@certi.org.br anthony@vergeaero.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/ld.script dpo@certi.org.br alin.jerpelea@sony.com cuiziwei@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g070rb/src/nucleo-g070rb.h dpo@certi.org.br alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_appinit.c dpo@certi.org.br alin.jerpelea@sony.com xiaoxiang@xiaomi.com 59230071+hartmannathan@users.noreply.github.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_autoleds.c dpo@certi.org.br alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c dpo@certi.org.br alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c dpo@certi.org.br gvr@certi.org.br alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_buttons.c dpo@certi.org.br alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c dpo@certi.org.br xiaoxiang@xiaomi.com alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c dpo@certi.org.br alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_timer.c dpo@certi.org.br alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g071rb/Kconfig alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g071rb/include/board.h alin.jerpelea@sony.com raiden00@railab.me anthony@vergeaero.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/ld.script alin.jerpelea@sony.com dpo@certi.org.br acassis@gmail.com cuiziwei@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g071rb/src/nucleo-g071rb.h alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_appinit.c alin.jerpelea@sony.com raiden00@railab.me gustavo.nihei@espressif.com 59230071+hartmannathan@users.noreply.github.com hartman.nathan@gmail.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_autoleds.c alin.jerpelea@sony.com raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_bringup.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_buttons.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g0b1re/Kconfig tbennett@2g-eng.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig tbennett@2g-eng.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig kwilson@2g-eng.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig tbennett@2g-eng.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g0b1re/include/board.h tbennett@2g-eng.com kwilson@2g-eng.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/ld.script tbennett@2g-eng.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g0b1re/src/nucleo-g0b1re.h tbennett@2g-eng.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c tbennett@2g-eng.com kwilson@2g-eng.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_appinit.c tbennett@2g-eng.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_autoleds.c tbennett@2g-eng.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_boot.c tbennett@2g-eng.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_bringup.c tbennett@2g-eng.com
|
||||
boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_buttons.c tbennett@2g-eng.com
|
||||
boards/arm/stm32f0l0g0/nucleo-l073rz/Kconfig alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h alin.jerpelea@sony.com raiden00@railab.me devel@sumpfralle.de anthony@vergeaero.com
|
||||
boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/ld.script alin.jerpelea@sony.com acassis@gmail.com cuiziwei@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_appinit.c alin.jerpelea@sony.com raiden00@railab.me gustavo.nihei@espressif.com 59230071+hartmannathan@users.noreply.github.com hartman.nathan@gmail.com
|
||||
boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_autoleds.c alin.jerpelea@sony.com raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_bringup.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_buttons.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_mfrc522.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_nrf24l01.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_sx127x.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/stm32f051-discovery/Kconfig alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com devel@sumpfralle.de anthony@vergeaero.com
|
||||
boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/flash.ld alin.jerpelea@sony.com raiden00@railab.me cuiziwei@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_appinit.c alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com hartman.nathan@gmail.com
|
||||
boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_autoleds.c alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_boot.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_bringup.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_buttons.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com
|
||||
boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_userleds.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32f051-discovery.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/stm32f072-discovery/Kconfig alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com devel@sumpfralle.de anthony@vergeaero.com
|
||||
boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/flash.ld alin.jerpelea@sony.com raiden00@railab.me cuiziwei@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_appinit.c alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com hartman.nathan@gmail.com
|
||||
boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_autoleds.c alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_boot.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com
|
||||
boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_bringup.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_buttons.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com
|
||||
boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_userleds.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32f072-discovery.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/stm32g071b-disco/Kconfig raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig raiden00@railab.me xiaoxiang@xiaomi.com wangjianyu3@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig raiden00@railab.me xiaoxiang@xiaomi.com wangjianyu3@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/stm32g071b-disco/include/board.h raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/ld.script raiden00@railab.me cuiziwei@xiaomi.com alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_appinit.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_boot.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_bringup.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_djoystick.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_gpio.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_ina226.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_spi.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_userleds.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32g071b-disco.h raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32l0538-disco/Kconfig raiden00@railab.me
|
||||
boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig raiden00@railab.me xiaoxiang@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h raiden00@railab.me devel@sumpfralle.de alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/ld.script raiden00@railab.me cuiziwei@xiaomi.com alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_appinit.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_autoleds.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_boot.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_bringup.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_buttons.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32l0538-disco.h raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32l0/b-l072z-lrwan1/Kconfig alin.jerpelea@sony.com
|
||||
boards/arm/stm32l0/b-l072z-lrwan1/configs/adc/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32l0/b-l072z-lrwan1/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32l0/b-l072z-lrwan1/configs/nxlines_oled/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32l0/b-l072z-lrwan1/configs/sx127x/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32l0/b-l072z-lrwan1/include/board.h alin.jerpelea@sony.com raiden00@railab.me devel@sumpfralle.de anthony@vergeaero.com
|
||||
boards/arm/stm32l0/b-l072z-lrwan1/scripts/ld.script alin.jerpelea@sony.com acassis@gmail.com cuiziwei@xiaomi.com
|
||||
boards/arm/stm32l0/b-l072z-lrwan1/src/b-l072z-lrwan1.h alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_adc.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_appinit.c alin.jerpelea@sony.com raiden00@railab.me gustavo.nihei@espressif.com 59230071+hartmannathan@users.noreply.github.com hartman.nathan@gmail.com
|
||||
boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_autoleds.c alin.jerpelea@sony.com raiden00@railab.me
|
||||
boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_boot.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_bringup.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_spi.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_sx127x.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com gustavo.nihei@espressif.com
|
||||
boards/arm/stm32c0/nucleo-c071rb/Kconfig raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c071rb/configs/jumbo/defconfig raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c071rb/configs/nsh/defconfig raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c071rb/include/board.h raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c071rb/scripts/flash.ld raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c071rb/src/nucleo-c071rb.h raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c071rb/src/stm32_adc.c raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c071rb/src/stm32_appinit.c raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c071rb/src/stm32_autoleds.c raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c071rb/src/stm32_boot.c raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c071rb/src/stm32_bringup.c raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c071rb/src/stm32_buttons.c raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c071rb/src/stm32_userleds.c raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c092rc/Kconfig raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c092rc/configs/can/defconfig raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c092rc/configs/cansock/defconfig raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c092rc/configs/jumbo/defconfig raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c092rc/configs/nsh/defconfig raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c092rc/include/board.h raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c092rc/scripts/flash.ld raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c092rc/src/nucleo-c092rc.h raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c092rc/src/stm32_adc.c raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c092rc/src/stm32_appinit.c raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c092rc/src/stm32_autoleds.c raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c092rc/src/stm32_boot.c raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c092rc/src/stm32_bringup.c raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c092rc/src/stm32_buttons.c raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c092rc/src/stm32_can.c raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c092rc/src/stm32_cansock.c raiden00@railab.me
|
||||
boards/arm/stm32c0/nucleo-c092rc/src/stm32_userleds.c raiden00@railab.me
|
||||
boards/arm/stm32f0/nucleo-f072rb/Kconfig alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0/nucleo-f072rb/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32f0/nucleo-f072rb/include/board.h alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com devel@sumpfralle.de anthony@vergeaero.com
|
||||
boards/arm/stm32f0/nucleo-f072rb/scripts/flash.ld alin.jerpelea@sony.com raiden00@railab.me cuiziwei@xiaomi.com
|
||||
boards/arm/stm32f0/nucleo-f072rb/src/nucleo-f072rb.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0/nucleo-f072rb/src/stm32_appinit.c alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com hartman.nathan@gmail.com
|
||||
boards/arm/stm32f0/nucleo-f072rb/src/stm32_autoleds.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0/nucleo-f072rb/src/stm32_boot.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com
|
||||
boards/arm/stm32f0/nucleo-f072rb/src/stm32_bringup.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com devel@sumpfralle.de
|
||||
boards/arm/stm32f0/nucleo-f072rb/src/stm32_buttons.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0/nucleo-f072rb/src/stm32_userleds.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0/nucleo-f091rc/Kconfig alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0/nucleo-f091rc/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32f0/nucleo-f091rc/configs/sx127x/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32f0/nucleo-f091rc/include/board.h alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com devel@sumpfralle.de anthony@vergeaero.com
|
||||
boards/arm/stm32f0/nucleo-f091rc/scripts/flash.ld alin.jerpelea@sony.com raiden00@railab.me cuiziwei@xiaomi.com
|
||||
boards/arm/stm32f0/nucleo-f091rc/src/nucleo-f091rc.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0/nucleo-f091rc/src/stm32_appinit.c alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com hartman.nathan@gmail.com
|
||||
boards/arm/stm32f0/nucleo-f091rc/src/stm32_autoleds.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0/nucleo-f091rc/src/stm32_boot.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0/nucleo-f091rc/src/stm32_bringup.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0/nucleo-f091rc/src/stm32_buttons.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0/nucleo-f091rc/src/stm32_spi.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0/nucleo-f091rc/src/stm32_sx127x.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0/nucleo-f091rc/src/stm32_userleds.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32g0/nucleo-g070rb/Kconfig dpo@certi.org.br
|
||||
boards/arm/stm32g0/nucleo-g070rb/configs/nsh/defconfig dpo@certi.org.br gvr@certi.org.br xiaoxiang@xiaomi.com liguiding1@xiaomi.com gustavo.nihei@espressif.com
|
||||
boards/arm/stm32g0/nucleo-g070rb/include/board.h dpo@certi.org.br alin.jerpelea@sony.com raiden00@railab.me gvr@certi.org.br anthony@vergeaero.com
|
||||
boards/arm/stm32g0/nucleo-g070rb/scripts/ld.script dpo@certi.org.br alin.jerpelea@sony.com cuiziwei@xiaomi.com
|
||||
boards/arm/stm32g0/nucleo-g070rb/src/nucleo-g070rb.h dpo@certi.org.br alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32g0/nucleo-g070rb/src/stm32_appinit.c dpo@certi.org.br alin.jerpelea@sony.com xiaoxiang@xiaomi.com 59230071+hartmannathan@users.noreply.github.com
|
||||
boards/arm/stm32g0/nucleo-g070rb/src/stm32_autoleds.c dpo@certi.org.br alin.jerpelea@sony.com
|
||||
boards/arm/stm32g0/nucleo-g070rb/src/stm32_boot.c dpo@certi.org.br alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32g0/nucleo-g070rb/src/stm32_bringup.c dpo@certi.org.br gvr@certi.org.br alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com
|
||||
boards/arm/stm32g0/nucleo-g070rb/src/stm32_buttons.c dpo@certi.org.br alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32g0/nucleo-g070rb/src/stm32_gpio.c dpo@certi.org.br xiaoxiang@xiaomi.com alin.jerpelea@sony.com
|
||||
boards/arm/stm32g0/nucleo-g070rb/src/stm32_pwm.c dpo@certi.org.br alin.jerpelea@sony.com
|
||||
boards/arm/stm32g0/nucleo-g070rb/src/stm32_timer.c dpo@certi.org.br alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com
|
||||
boards/arm/stm32g0/nucleo-g071rb/Kconfig alin.jerpelea@sony.com
|
||||
boards/arm/stm32g0/nucleo-g071rb/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32g0/nucleo-g071rb/include/board.h alin.jerpelea@sony.com raiden00@railab.me anthony@vergeaero.com
|
||||
boards/arm/stm32g0/nucleo-g071rb/scripts/ld.script alin.jerpelea@sony.com dpo@certi.org.br acassis@gmail.com cuiziwei@xiaomi.com
|
||||
boards/arm/stm32g0/nucleo-g071rb/src/nucleo-g071rb.h alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32g0/nucleo-g071rb/src/stm32_appinit.c alin.jerpelea@sony.com raiden00@railab.me gustavo.nihei@espressif.com 59230071+hartmannathan@users.noreply.github.com hartman.nathan@gmail.com
|
||||
boards/arm/stm32g0/nucleo-g071rb/src/stm32_autoleds.c alin.jerpelea@sony.com raiden00@railab.me
|
||||
boards/arm/stm32g0/nucleo-g071rb/src/stm32_boot.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32g0/nucleo-g071rb/src/stm32_bringup.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32g0/nucleo-g071rb/src/stm32_buttons.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32g0/nucleo-g0b1re/Kconfig tbennett@2g-eng.com
|
||||
boards/arm/stm32g0/nucleo-g0b1re/configs/adc/defconfig tbennett@2g-eng.com
|
||||
boards/arm/stm32g0/nucleo-g0b1re/configs/adc_dma/defconfig kwilson@2g-eng.com
|
||||
boards/arm/stm32g0/nucleo-g0b1re/configs/nsh/defconfig tbennett@2g-eng.com
|
||||
boards/arm/stm32g0/nucleo-g0b1re/include/board.h tbennett@2g-eng.com kwilson@2g-eng.com
|
||||
boards/arm/stm32g0/nucleo-g0b1re/scripts/ld.script tbennett@2g-eng.com
|
||||
boards/arm/stm32g0/nucleo-g0b1re/src/nucleo-g0b1re.h tbennett@2g-eng.com
|
||||
boards/arm/stm32g0/nucleo-g0b1re/src/stm32_adc.c tbennett@2g-eng.com kwilson@2g-eng.com
|
||||
boards/arm/stm32g0/nucleo-g0b1re/src/stm32_appinit.c tbennett@2g-eng.com
|
||||
boards/arm/stm32g0/nucleo-g0b1re/src/stm32_autoleds.c tbennett@2g-eng.com
|
||||
boards/arm/stm32g0/nucleo-g0b1re/src/stm32_boot.c tbennett@2g-eng.com
|
||||
boards/arm/stm32g0/nucleo-g0b1re/src/stm32_bringup.c tbennett@2g-eng.com
|
||||
boards/arm/stm32g0/nucleo-g0b1re/src/stm32_buttons.c tbennett@2g-eng.com
|
||||
boards/arm/stm32l0/nucleo-l073rz/Kconfig alin.jerpelea@sony.com
|
||||
boards/arm/stm32l0/nucleo-l073rz/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32l0/nucleo-l073rz/configs/sx127x/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32l0/nucleo-l073rz/include/board.h alin.jerpelea@sony.com raiden00@railab.me devel@sumpfralle.de anthony@vergeaero.com
|
||||
boards/arm/stm32l0/nucleo-l073rz/scripts/ld.script alin.jerpelea@sony.com acassis@gmail.com cuiziwei@xiaomi.com
|
||||
boards/arm/stm32l0/nucleo-l073rz/src/nucleo-l073rz.h alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32l0/nucleo-l073rz/src/stm32_appinit.c alin.jerpelea@sony.com raiden00@railab.me gustavo.nihei@espressif.com 59230071+hartmannathan@users.noreply.github.com hartman.nathan@gmail.com
|
||||
boards/arm/stm32l0/nucleo-l073rz/src/stm32_autoleds.c alin.jerpelea@sony.com raiden00@railab.me
|
||||
boards/arm/stm32l0/nucleo-l073rz/src/stm32_boot.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32l0/nucleo-l073rz/src/stm32_bringup.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32l0/nucleo-l073rz/src/stm32_buttons.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32l0/nucleo-l073rz/src/stm32_mfrc522.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32l0/nucleo-l073rz/src/stm32_nrf24l01.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32l0/nucleo-l073rz/src/stm32_spi.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32l0/nucleo-l073rz/src/stm32_sx127x.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0/stm32f051-discovery/Kconfig alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0/stm32f051-discovery/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32f0/stm32f051-discovery/include/board.h alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com devel@sumpfralle.de anthony@vergeaero.com
|
||||
boards/arm/stm32f0/stm32f051-discovery/scripts/flash.ld alin.jerpelea@sony.com raiden00@railab.me cuiziwei@xiaomi.com
|
||||
boards/arm/stm32f0/stm32f051-discovery/src/stm32_appinit.c alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com hartman.nathan@gmail.com
|
||||
boards/arm/stm32f0/stm32f051-discovery/src/stm32_autoleds.c alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0/stm32f051-discovery/src/stm32_boot.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0/stm32f051-discovery/src/stm32_bringup.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0/stm32f051-discovery/src/stm32_buttons.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com
|
||||
boards/arm/stm32f0/stm32f051-discovery/src/stm32_userleds.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0/stm32f051-discovery/src/stm32f051-discovery.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0/stm32f072-discovery/Kconfig alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0/stm32f072-discovery/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32f0/stm32f072-discovery/include/board.h alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com devel@sumpfralle.de anthony@vergeaero.com
|
||||
boards/arm/stm32f0/stm32f072-discovery/scripts/flash.ld alin.jerpelea@sony.com raiden00@railab.me cuiziwei@xiaomi.com
|
||||
boards/arm/stm32f0/stm32f072-discovery/src/stm32_appinit.c alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com hartman.nathan@gmail.com
|
||||
boards/arm/stm32f0/stm32f072-discovery/src/stm32_autoleds.c alin.jerpelea@sony.com
|
||||
boards/arm/stm32f0/stm32f072-discovery/src/stm32_boot.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com
|
||||
boards/arm/stm32f0/stm32f072-discovery/src/stm32_bringup.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0/stm32f072-discovery/src/stm32_buttons.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com
|
||||
boards/arm/stm32f0/stm32f072-discovery/src/stm32_userleds.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32f0/stm32f072-discovery/src/stm32f072-discovery.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com
|
||||
boards/arm/stm32g0/stm32g071b-disco/Kconfig raiden00@railab.me
|
||||
boards/arm/stm32g0/stm32g071b-disco/configs/nsh/defconfig raiden00@railab.me xiaoxiang@xiaomi.com wangjianyu3@xiaomi.com
|
||||
boards/arm/stm32g0/stm32g071b-disco/configs/oled/defconfig raiden00@railab.me xiaoxiang@xiaomi.com wangjianyu3@xiaomi.com
|
||||
boards/arm/stm32g0/stm32g071b-disco/include/board.h raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32g0/stm32g071b-disco/scripts/ld.script raiden00@railab.me cuiziwei@xiaomi.com alin.jerpelea@sony.com
|
||||
boards/arm/stm32g0/stm32g071b-disco/src/stm32_appinit.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32g0/stm32g071b-disco/src/stm32_boot.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32g0/stm32g071b-disco/src/stm32_bringup.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32g0/stm32g071b-disco/src/stm32_djoystick.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32g0/stm32g071b-disco/src/stm32_gpio.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32g0/stm32g071b-disco/src/stm32_ina226.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32g0/stm32g071b-disco/src/stm32_spi.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32g0/stm32g071b-disco/src/stm32_userleds.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32g0/stm32g071b-disco/src/stm32g071b-disco.h raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32l0/stm32l0538-disco/Kconfig raiden00@railab.me
|
||||
boards/arm/stm32l0/stm32l0538-disco/configs/nsh/defconfig raiden00@railab.me xiaoxiang@xiaomi.com dongjiuzhu1@xiaomi.com
|
||||
boards/arm/stm32l0/stm32l0538-disco/include/board.h raiden00@railab.me devel@sumpfralle.de alin.jerpelea@sony.com
|
||||
boards/arm/stm32l0/stm32l0538-disco/scripts/ld.script raiden00@railab.me cuiziwei@xiaomi.com alin.jerpelea@sony.com
|
||||
boards/arm/stm32l0/stm32l0538-disco/src/stm32_appinit.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32l0/stm32l0538-disco/src/stm32_autoleds.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32l0/stm32l0538-disco/src/stm32_boot.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32l0/stm32l0538-disco/src/stm32_bringup.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32l0/stm32l0538-disco/src/stm32_buttons.c raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32l0/stm32l0538-disco/src/stm32l0538-disco.h raiden00@railab.me alin.jerpelea@sony.com
|
||||
boards/arm/stm32f7/common/Kconfig raiden00@railab.me acassis@gmail.com
|
||||
boards/arm/stm32f7/common/Makefile acassis@gmail.com alin.jerpelea@sony.com
|
||||
boards/arm/stm32f7/common/include/stm32_bh1750.h acassis@gmail.com alin.jerpelea@sony.com
|
||||
|
|
|
|||
20
LICENSE
20
LICENSE
|
|
@ -3386,9 +3386,9 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|||
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c
|
||||
boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c
|
||||
boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_timer.c
|
||||
boards/arm/stm32g0/nucleo-g070rb/src/stm32_gpio.c
|
||||
boards/arm/stm32g0/nucleo-g070rb/src/stm32_pwm.c
|
||||
boards/arm/stm32g0/nucleo-g070rb/src/stm32_timer.c
|
||||
=====================================================
|
||||
Copyright (C) 2019 Fundação CERTI. All rights reserved.
|
||||
|
||||
|
|
@ -4243,7 +4243,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|||
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h
|
||||
arch/arm/src/stm32g0/hardware/stm32g0_pinmap.h
|
||||
=====================================================
|
||||
|
||||
Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
|
|
@ -4276,7 +4276,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|||
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
arch/arm/src/stm32f0l0g0/stm32_i2c.c
|
||||
arch/arm/src/common/stm32/stm32_i2c_m0_v1.c
|
||||
===========================================
|
||||
|
||||
Copyright (C) 2011 Uros Platise. All rights reserved.
|
||||
|
|
@ -4309,7 +4309,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|||
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
arch/arm/src/stm32f0l0g0/stm32_pwm.c
|
||||
arch/arm/src/common/stm32/stm32_pwm_m0_v1.c
|
||||
=======================================
|
||||
|
||||
Copyright (C) 2019 Fundação CERTI. All rights reserved.
|
||||
|
|
@ -4341,9 +4341,9 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|||
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
arch/arm/src/stm32f0l0g0/stm32_pwm.h
|
||||
arch/arm/src/stm32f0l0g0/stm32_tim.c
|
||||
arch/arm/src/stm32f0l0g0/stm32_tim.h
|
||||
arch/arm/src/common/stm32/stm32_pwm_m0_v1.h
|
||||
arch/arm/src/common/stm32/stm32_tim_m0_v1.c
|
||||
arch/arm/src/common/stm32/stm32_tim_m0_v1.h
|
||||
=======================================
|
||||
|
||||
Copyright (C) 2019 Fundação CERTI. All rights reserved.
|
||||
|
|
@ -4375,7 +4375,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|||
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c
|
||||
arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c
|
||||
=================================================
|
||||
|
||||
Copyright (C) 2019 Fundação CERTI. All rights reserved.
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@
|
|||
* memory in the IRQ to handle mapping tables.
|
||||
*
|
||||
* Processor Exceptions (vectors 0-15). These common definitions can be
|
||||
* found in nuttx/arch/arm/include/stm32f0l0g0/irq.h
|
||||
* found in nuttx/arch/arm/include/phy62xx/irq.h
|
||||
*/
|
||||
|
||||
#define PHY62XX_IRQ_BB_IRQn (PHY62XX_IRQ_EXTINT + 4) /* 4: RCC and CRS */
|
||||
|
|
|
|||
157
arch/arm/include/stm32c0/chip.h
Normal file
157
arch/arm/include/stm32c0/chip.h
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/include/stm32c0/chip.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_STM32C0_CHIP_H
|
||||
#define __ARCH_ARM_INCLUDE_STM32C0_CHIP_H
|
||||
|
||||
#define ARMV6M_PERIPHERAL_INTERRUPTS 32
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/* Get customizations for each supported chip */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32C051XX)
|
||||
# define STM32_NATIM 1 /* One advanced timers TIM1 */
|
||||
# define STM32_NGTIM16 4 /* Four 16-bit general up/down timers TIM3, TIM14,
|
||||
* TIM16 and TIM17 */
|
||||
# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */
|
||||
# define STM32_NBTIM 0 /* No basic timers */
|
||||
/* One LPTIMER */
|
||||
# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
|
||||
# define STM32_NI2S 0 /* No I2S module */
|
||||
# define STM32_NI2C 2 /* Two I2C */
|
||||
# define STM32_NDMA 1 /* One DMA1, 5-channels */
|
||||
# define STM32_NUSART 2 /* Two USART modules, USART1-2 */
|
||||
# define STM32_NCAN 0 /* No CAN controllers */
|
||||
# define STM32_FDCAN 0 /* No FD CAN */
|
||||
# define STM32_NLCD 0 /* No LCD controller */
|
||||
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 0 /* No HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 0 /* No DAC channels */
|
||||
# define STM32_NCOMP 0 /* No Analog Comparators */
|
||||
# define STM32_NCRC 1 /* One CRC module */
|
||||
# define STM32_NRNG 0 /* No Random number generator (RNG) */
|
||||
# define STM32_NCAP 0 /* No Capacitive sensing channels */
|
||||
# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32C071XX)
|
||||
# define STM32_NATIM 1 /* One advanced timers TIM1 */
|
||||
# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM3, TIM14,
|
||||
* TIM16 and TIM17 */
|
||||
# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */
|
||||
# define STM32_NBTIM 0 /* No basic timers */
|
||||
/* One LPTIMER */
|
||||
# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
|
||||
# define STM32_NI2S 0 /* No I2S module */
|
||||
# define STM32_NI2C 2 /* Two I2C */
|
||||
# define STM32_NDMA 1 /* One DMA1, 5-channels */
|
||||
# define STM32_NUSART 2 /* Two USART modules, USART1-2 */
|
||||
# define STM32_NCAN 0 /* No CAN controllers */
|
||||
# define STM32_FDCAN 0 /* No FD CAN */
|
||||
# define STM32_NLCD 0 /* No LCD controller */
|
||||
# define STM32_NUSBDEV 1 /* USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 0 /* No HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 0 /* No DAC channels */
|
||||
# define STM32_NCOMP 0 /* No Analog Comparators */
|
||||
# define STM32_NCRC 1 /* One CRC module */
|
||||
# define STM32_NRNG 0 /* No Random number generator (RNG) */
|
||||
# define STM32_NCAP 0 /* No Capacitive sensing channels */
|
||||
# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32C091XX)
|
||||
# define STM32_NATIM 1 /* One advanced timers TIM1 */
|
||||
# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14,
|
||||
* TIM15, TIM16 and TIM17 */
|
||||
# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */
|
||||
# define STM32_NBTIM 0 /* No basic timers */
|
||||
/* One LPTIMER */
|
||||
# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
|
||||
# define STM32_NI2S 0 /* No I2S module */
|
||||
# define STM32_NI2C 2 /* Two I2C */
|
||||
# define STM32_NDMA 1 /* One DMA1, 5-channels */
|
||||
# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
|
||||
# define STM32_NCAN 0 /* No CAN controllers */
|
||||
# define STM32_FDCAN 0 /* No FD CAN */
|
||||
# define STM32_NLCD 0 /* No LCD controller */
|
||||
# define STM32_NUSBDEV 1 /* USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 0 /* No HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 0 /* No DAC channels */
|
||||
# define STM32_NCOMP 0 /* No Analog Comparators */
|
||||
# define STM32_NCRC 1 /* One CRC module */
|
||||
# define STM32_NRNG 0 /* No Random number generator (RNG) */
|
||||
# define STM32_NCAP 0 /* No Capacitive sensing channels */
|
||||
# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32C092XX)
|
||||
# define STM32_NATIM 1 /* One advanced timers TIM1 */
|
||||
# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14,
|
||||
* TIM15, TIM16 and TIM17 */
|
||||
# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */
|
||||
# define STM32_NBTIM 0 /* No basic timers */
|
||||
/* One LPTIMER */
|
||||
# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
|
||||
# define STM32_NI2S 0 /* No I2S module */
|
||||
# define STM32_NI2C 2 /* Two I2C */
|
||||
# define STM32_NDMA 1 /* One DMA1, 5-channels */
|
||||
# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
|
||||
# define STM32_NCAN 0 /* No CAN controllers */
|
||||
# define STM32_FDCAN 1 /* One FD CAN */
|
||||
# define STM32_NLCD 0 /* No LCD controller */
|
||||
# define STM32_NUSBDEV 1 /* USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 0 /* No HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 0 /* No DAC channels */
|
||||
# define STM32_NCOMP 0 /* No Analog Comparators */
|
||||
# define STM32_NCRC 1 /* One CRC module */
|
||||
# define STM32_NRNG 0 /* No Random number generator (RNG) */
|
||||
# define STM32_NCAP 0 /* No Capacitive sensing channels */
|
||||
# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */
|
||||
#else
|
||||
# error "Unsupported STM32 Cortex M0 chip"
|
||||
#endif
|
||||
|
||||
/* NVIC priority levels *****************************************************/
|
||||
|
||||
/* Each priority field holds a priority value, 0-31. The lower the value,
|
||||
* the greater the priority of the corresponding interrupt. The processor
|
||||
* implements only bits[7:6] of each field, bits[5:0] read as zero and
|
||||
* ignore writes.
|
||||
*/
|
||||
|
||||
#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
|
||||
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
|
||||
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
|
||||
#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_STM32C0_CHIP_H */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/include/stm32f0l0g0/stm32c0_irq.h
|
||||
* arch/arm/include/stm32c0/irq.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -24,16 +24,17 @@
|
|||
* through nuttx/irq.h
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H
|
||||
#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H
|
||||
#ifndef __ARCH_ARM_INCLUDE_STM32C0_IRQ_H
|
||||
#define __ARCH_ARM_INCLUDE_STM32C0_IRQ_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/irq.h>
|
||||
#include <arch/stm32f0l0g0/chip.h>
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
#endif
|
||||
#include <arch/stm32c0/chip.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Prototypes
|
||||
|
|
@ -42,11 +43,31 @@
|
|||
/* IRQ numbers. The IRQ number corresponds vector number and hence map
|
||||
* directly to bits in the NVIC. This does, however, waste several words of
|
||||
* memory in the IRQ to handle mapping tables.
|
||||
*
|
||||
* Processor Exceptions (vectors 0-15). These common definitions can be
|
||||
* found in nuttx/arch/arm/include/stm32f0l0g0/irq.h
|
||||
*/
|
||||
|
||||
/* Common Processor Exceptions (vectors 0-15) */
|
||||
|
||||
#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
|
||||
/* Vector 0: Reset stack pointer value */
|
||||
/* Vector 1: Reset (not handler as an IRQ) */
|
||||
#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
|
||||
#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
|
||||
/* Vectors 4-10: Reserved */
|
||||
#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */
|
||||
/* Vector 12-13: Reserved */
|
||||
#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
|
||||
#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */
|
||||
|
||||
/* External interrupts (vectors >= 16) */
|
||||
|
||||
#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
/* External interrupt vectors */
|
||||
|
||||
#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */
|
||||
#define STM32_IRQ_PVM (STM32_IRQ_EXTINT + 1) /* 1: VDDIO2 monitor interrupt */
|
||||
#define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC */
|
||||
|
|
@ -87,31 +108,6 @@
|
|||
|
||||
#define STM32_IRQ_NEXTINTS (32)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINTS)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H */
|
||||
#endif /* __ARCH_ARM_INCLUDE_STM32C0_IRQ_H */
|
||||
|
|
@ -1,776 +0,0 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/include/stm32f0l0g0/chip.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H
|
||||
#define __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/* Get customizations for each supported chip */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32F030RC) || defined(CONFIG_ARCH_CHIP_STM32F030CC)
|
||||
|
||||
# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */
|
||||
# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */
|
||||
|
||||
# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
|
||||
# define STM32_NI2S 0 /* No I2S modules */
|
||||
# define STM32_NI2C 2 /* Two I2C modules */
|
||||
# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
|
||||
# define STM32_NUSART 6 /* Six USARTs modules */
|
||||
# define STM32_NCAN 0 /* No CAN controllers */
|
||||
# define STM32_NUSBDEV 0 /* One USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 0 /* One DAC channel */
|
||||
# define STM32_NCOMP 0 /* Two Analog Comparators */
|
||||
# define STM32_NCAP 0 /* Capacitive sensing channels (14 on UFQFPN32)) */
|
||||
# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F051R8)
|
||||
|
||||
# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */
|
||||
# define STM32_SRAM_SIZE (8 * 1024) /* 8Kb */
|
||||
|
||||
# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
|
||||
# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
|
||||
# define STM32_NI2C 2 /* Two I2C modules */
|
||||
# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
|
||||
# define STM32_NUSART 2 /* Two USARTs modules */
|
||||
# define STM32_NCAN 0 /* No CAN controllers */
|
||||
# define STM32_NUSBDEV 1 /* One USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 1 /* One DAC channel */
|
||||
# define STM32_NCOMP 2 /* Two Analog Comparators */
|
||||
# define STM32_NCAP 13 /* Capacitive sensing channels (14 on UFQFPN32)) */
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F072C8) || defined(CONFIG_ARCH_CHIP_STM32F072CB)
|
||||
|
||||
# ifdef CONFIG_ARCH_CHIP_STM32F072C8
|
||||
# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */
|
||||
# else
|
||||
# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */
|
||||
# endif
|
||||
# define STM32_SRAM_SIZE (16 * 1024) /* 16Kb */
|
||||
|
||||
# define STM32_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
|
||||
# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
|
||||
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
|
||||
# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
|
||||
# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
|
||||
# define STM32_NI2C 2 /* Two I2C modules */
|
||||
# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
|
||||
# define STM32_NUSART 4 /* Four USARTs module */
|
||||
# define STM32_NCAN 1 /* One CAN controller */
|
||||
# define STM32_NUSBDEV 1 /* One USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 1 /* One HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 2 /* Two DAC channel */
|
||||
# define STM32_NCOMP 2 /* Two Analog Comparators */
|
||||
# define STM32_NCAP 17 /* Capacitive sensing channels */
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F072R8) || defined(CONFIG_ARCH_CHIP_STM32F072RB)
|
||||
|
||||
# ifdef CONFIG_ARCH_CHIP_STM32F072R8
|
||||
# define STM32_FLASH_SIZE (64*1024) /* 64Kb */
|
||||
# else
|
||||
# define STM32_FLASH_SIZE (128*1024) /* 128Kb */
|
||||
# endif
|
||||
# define STM32_SRAM_SIZE (16*1024) /* 16Kb */
|
||||
|
||||
# define STM32_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
|
||||
# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
|
||||
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
|
||||
# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
|
||||
# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
|
||||
# define STM32_NI2C 2 /* Two I2C modules */
|
||||
# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
|
||||
# define STM32_NUSART 4 /* Four USARTs module */
|
||||
# define STM32_NCAN 1 /* One CAN controller */
|
||||
# define STM32_NUSBDEV 1 /* One USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 1 /* One HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 2 /* Two DAC channel */
|
||||
# define STM32_NCOMP 2 /* Two Analog Comparators */
|
||||
# define STM32_NCAP 18 /* Capacitive sensing channels */
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F072V8) || defined(CONFIG_ARCH_CHIP_STM32F072VB)
|
||||
|
||||
# ifdef CONFIG_ARCH_CHIP_STM32F072V8
|
||||
# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */
|
||||
# else
|
||||
# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */
|
||||
# endif
|
||||
# define STM32_SRAM_SIZE (16 * 1024) /* 16Kb */
|
||||
|
||||
# define STM32_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
|
||||
# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
|
||||
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
|
||||
# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
|
||||
# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
|
||||
# define STM32_NI2C 2 /* Two I2C modules */
|
||||
# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
|
||||
# define STM32_NUSART 4 /* Four USARTs module */
|
||||
# define STM32_NCAN 1 /* One CAN controller */
|
||||
# define STM32_NUSBDEV 1 /* One USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 1 /* One HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 2 /* Two DAC channel */
|
||||
# define STM32_NCOMP 2 /* Two Analog Comparators */
|
||||
# define STM32_NCAP 24 /* Capacitive sensing channels */
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F091CB) || defined(CONFIG_ARCH_CHIP_STM32F091CC)
|
||||
|
||||
# ifdef CONFIG_ARCH_CHIP_STM32F091CB
|
||||
# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */
|
||||
# else
|
||||
# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */
|
||||
# endif
|
||||
# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */
|
||||
|
||||
# define STM32_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
|
||||
# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
|
||||
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
|
||||
# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
|
||||
# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
|
||||
# define STM32_NI2C 2 /* Two I2C modules */
|
||||
# define STM32_NDMA 2 /* DMA1, DMA2 */
|
||||
# define STM32_NUSART 6 /* Six USARTs modules */
|
||||
# define STM32_NCAN 1 /* One CAN controller */
|
||||
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 1 /* One HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 2 /* Two DAC channel */
|
||||
# define STM32_NCOMP 2 /* Two Analog Comparators */
|
||||
# define STM32_NCAP 17 /* Capacitive sensing channels */
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091RC) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC)
|
||||
|
||||
# if defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091VB)
|
||||
# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */
|
||||
# else
|
||||
# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */
|
||||
# endif
|
||||
# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */
|
||||
|
||||
# define STM32_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
|
||||
# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
|
||||
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
|
||||
# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
|
||||
# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
|
||||
# define STM32_NI2C 2 /* Two I2C modules */
|
||||
# define STM32_NDMA 2 /* DMA1, DMA2 */
|
||||
# define STM32_NUSART 8 /* Eight USARTs modules */
|
||||
# define STM32_NCAN 1 /* One CAN controller */
|
||||
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 1 /* One HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 2 /* Two DAC channel */
|
||||
# define STM32_NCOMP 2 /* Two Analog Comparators */
|
||||
# if defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC)
|
||||
# define STM32_NCAP 24 /* Capacitive sensing channels */
|
||||
# else
|
||||
# define STM32_NCAP 18 /* Capacitive sensing channels */
|
||||
# endif
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32G070RB)
|
||||
|
||||
# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */
|
||||
# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */
|
||||
|
||||
# define STM32_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3,
|
||||
* TIM14-17 */
|
||||
# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
|
||||
# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 */
|
||||
# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
|
||||
# define STM32_NI2S 1 /* One I2S module (SPI or I2S) */
|
||||
# define STM32_NI2C 2 /* Two I2C (1 with SMBus/PMBus) */
|
||||
# define STM32_NDMA 1 /* One DMA1, 7-channels */
|
||||
# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
|
||||
# define STM32_NCAN 0 /* No CAN controllers */
|
||||
# define STM32_NLCD 0 /* No LCD */
|
||||
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG */
|
||||
# define STM32_NCEC 0 /* One HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* (1) ADC1, 16-channels */
|
||||
|
||||
# define STM32_NDAC 0 /* No DAC */
|
||||
# define STM32_NCOMP 0 /* No Analog Comparators */
|
||||
# define STM32_NCRC 1 /* No CRC module */
|
||||
# define STM32_NRNG 0 /* No Random number generator (RNG) */
|
||||
# define STM32_NCAP 0 /* No Capacitive sensing channels */
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32G071EB) || defined(CONFIG_ARCH_CHIP_STM32G071G8) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32G071GB) || defined(CONFIG_ARCH_CHIP_STM32G071G8XN) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32G071GBXN) || defined(CONFIG_ARCH_CHIP_STM32G071K8) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32G071KB) || defined(CONFIG_ARCH_CHIP_STM32G071K8XN) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32G071KBXN) || defined(CONFIG_ARCH_CHIP_STM32G071C8) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32G071CB) || defined(CONFIG_ARCH_CHIP_STM32G071R8) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32G071RB)
|
||||
|
||||
# define STM32_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
|
||||
* (with DMA) and TIM21-22 without DMA */
|
||||
# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
|
||||
# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
|
||||
/* Two LPTIMER */
|
||||
# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
|
||||
# define STM32_NI2C 2 /* Two I2C (2 with SMBus/PMBus) */
|
||||
# define STM32_NDMA 1 /* One DMA1, 7-channels */
|
||||
# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
|
||||
/* One LPUART */
|
||||
# define STM32_NCAN 0 /* No CAN controllers */
|
||||
# define STM32_NLCD 0 /* No LCD */
|
||||
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG */
|
||||
# define STM32_NCEC 1 /* One HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* (1) ADC1, 12-channels */
|
||||
|
||||
# define STM32_NDAC 2 /* Two DAC channels */
|
||||
# define STM32_NCOMP 2 /* Two Analog Comparators */
|
||||
# define STM32_NCRC 0 /* No CRC module */
|
||||
# define STM32_NRNG 0 /* No Random number generator (RNG) */
|
||||
# define STM32_NCAP 0 /* No Capacitive sensing channels */
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32G0B1KB) || defined(CONFIG_ARCH_CHIP_STM32G0B1CB) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32G0B1RB) || defined(CONFIG_ARCH_CHIP_STM32G0B1MB) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32G0B1VB) || defined(CONFIG_ARCH_CHIP_STM32G0B1KC) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32G0B1CC) || defined(CONFIG_ARCH_CHIP_STM32G0B1RC) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32G0B1MC) || defined(CONFIG_ARCH_CHIP_STM32G0B1VC) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32G0B1KE) || defined(CONFIG_ARCH_CHIP_STM32G0B1CE) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32G0B1RE) || defined(CONFIG_ARCH_CHIP_STM32G0B1NE) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32G0B1ME) || defined(CONFIG_ARCH_CHIP_STM32G0B1VE)
|
||||
|
||||
# define STM32_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32_NGTIM16 6 /* 16-bit general purpose timers */
|
||||
# define STM32_NGTIM32 1 /* TIM2 */
|
||||
# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
|
||||
/* One LPTIMER */
|
||||
# define STM32_NSPI 3 /* Two SPI modules SPI1-2 */
|
||||
# define STM32_NI2C 3 /* Two I2C (2 with SMBus/PMBus) */
|
||||
# define STM32_NDMA 2 /* DMA1 7-channels, DMA2 5-channels DMA1 */
|
||||
# define STM32_NUSART 6 /* Six USART modules, USART1-6 */
|
||||
/* Two LPUART */
|
||||
# define STM32_NCAN 1 /* One FDCAN controller */
|
||||
# define STM32_NLCD 0 /* No LCD */
|
||||
# define STM32_NUSBDEV 1 /* One USB full-speed controller */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG */
|
||||
# define STM32_NCEC 1 /* One HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* (1) ADC1, 12-channels */
|
||||
|
||||
# define STM32_NDAC 2 /* Two DAC channels */
|
||||
# define STM32_NCOMP 3 /* Three Analog Comparators */
|
||||
# define STM32_NCRC 0 /* No CRC module */
|
||||
# define STM32_NRNG 1 /* One Random number generator (RNG) */
|
||||
# define STM32_NCAP 0 /* No Capacitive sensing channels */
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
|
||||
|
||||
/* STM32L EnergyLite Line ***************************************************/
|
||||
|
||||
/* STM32L073XX - With LCD
|
||||
* STM32L072XX - No LCD
|
||||
* STM32L071XX - Access line, no LCD
|
||||
*
|
||||
* STM32L0XXX8 - 64KB FLASH, 20KB SRAM, 3KB EEPROM
|
||||
* STM32L0XXXB - 128KB FLASH, 20KB SRAM, 6KB EEPROM
|
||||
* STM32L0XXXZ - 192KB FLASH, 20KB SRAM, 3KB EEPROM
|
||||
*
|
||||
* STM32L0XXCX - 48-pins
|
||||
* STM32L0XXRX - 64-pins
|
||||
* STM32L0XXVX - 100-pins
|
||||
*/
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L071K8)
|
||||
# define STM32_NATIM 0 /* No advanced timers */
|
||||
# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
|
||||
* (with DMA) and TIM21-22 without DMA */
|
||||
# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
|
||||
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
|
||||
/* 1 LPTIMER */
|
||||
# define STM32_NSPI 1 /* 1 SPI modules SPI1 */
|
||||
# define STM32_NI2S 0 /* 0 I2S module */
|
||||
# define STM32_NI2C 2 /* 2 I2C */
|
||||
# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
|
||||
# define STM32_NUSART 3 /* 3 USART modules, USART1-3 */
|
||||
/* 1 LPUART */
|
||||
# define STM32_NCAN 0 /* 0 CAN controllers */
|
||||
# define STM32_NLCD 0 /* 0 LCD */
|
||||
# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 0 /* 0 HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 0 /* 0 DAC channel */
|
||||
# define STM32_NCOMP 2 /* 2 Analog Comparators */
|
||||
# define STM32_NCRC 0 /* 0 CRC module */
|
||||
# define STM32_NRNG 0 /* 0 Random number generator (RNG) */
|
||||
# define STM32_NCAP 0 /* 0 Capacitive sensing channels */
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L053C8)
|
||||
# define STM32_NATIM 0 /* No advanced timers */
|
||||
# define STM32_NGTIM16 3 /* 16-bit general up/down timers TIM2-3
|
||||
* (with DMA) and TIM22 without DMA */
|
||||
# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
|
||||
# define STM32_NBTIM 1 /* 1 basic timers: TIM6 with DMA */
|
||||
/* 1 LPTIMER */
|
||||
# define STM32_NSPI 2 /* 2 SPI modules SPI1 */
|
||||
# define STM32_NI2S 1 /* 1 I2S module */
|
||||
# define STM32_NI2C 2 /* 2 I2C */
|
||||
# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
|
||||
# define STM32_NUSART 2 /* 2 USART modules, USART1-1 */
|
||||
/* 1 LPUART */
|
||||
# define STM32_NCAN 0 /* 0 CAN controllers */
|
||||
# define STM32_NLCD 1 /* 1 LCD */
|
||||
# define STM32_NUSBDEV 1 /* 1 USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 0 /* 0 HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 0 /* 0 DAC channel */
|
||||
# define STM32_NCOMP 2 /* 2 Analog Comparators */
|
||||
# define STM32_NCRC 0 /* 0 CRC module */
|
||||
# define STM32_NRNG 0 /* 0 Random number generator (RNG) */
|
||||
# define STM32_NCAP 24 /* 24 Capacitive sensing channels */
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L053R8)
|
||||
# define STM32_NATIM 0 /* No advanced timers */
|
||||
# define STM32_NGTIM16 3 /* 16-bit general up/down timers TIM2-3
|
||||
* (with DMA) and TIM22 without DMA */
|
||||
# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
|
||||
# define STM32_NBTIM 1 /* 1 basic timers: TIM6 with DMA */
|
||||
/* 1 LPTIMER */
|
||||
# define STM32_NSPI 2 /* 2 SPI modules SPI1 */
|
||||
# define STM32_NI2S 1 /* 1 I2S module */
|
||||
# define STM32_NI2C 2 /* 2 I2C */
|
||||
# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
|
||||
# define STM32_NUSART 2 /* 2 USART modules, USART1-1 */
|
||||
/* 1 LPUART */
|
||||
# define STM32_NCAN 0 /* 0 CAN controllers */
|
||||
# define STM32_NLCD 1 /* 1 LCD */
|
||||
# define STM32_NUSBDEV 1 /* 1 USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 0 /* 0 HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 0 /* 0 DAC channel */
|
||||
# define STM32_NCOMP 2 /* 2 Analog Comparators */
|
||||
# define STM32_NCRC 0 /* 0 CRC module */
|
||||
# define STM32_NRNG 0 /* 0 Random number generator (RNG) */
|
||||
# define STM32_NCAP 24 /* 24 Capacitive sensing channels */
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L071C8) || defined(CONFIG_ARCH_CHIP_STM32L071V8) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32L071CB) || defined(CONFIG_ARCH_CHIP_STM32L071VB) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32L071RB) || defined(CONFIG_ARCH_CHIP_STM32L071CZ) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32L071VZ) || defined(CONFIG_ARCH_CHIP_STM32L071RZ)
|
||||
# define STM32_NATIM 0 /* 0 advanced timers */
|
||||
# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
|
||||
* (with DMA) and TIM21-22 without DMA */
|
||||
# define STM32_NGTIM32 0 /* 0 32-bit general up/down timers */
|
||||
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
|
||||
/* 1 LPTIMER */
|
||||
# define STM32_NSPI 2 /* 2 SPI modules SPI1-2 */
|
||||
# define STM32_NI2S 1 /* 1 I2S module */
|
||||
# define STM32_NI2C 3 /* 3 I2C */
|
||||
# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
|
||||
# define STM32_NUSART 4 /* 4 USART modules, USART1-4 */
|
||||
/* 1 LPUART */
|
||||
# define STM32_NCAN 0 /* 0 CAN controllers */
|
||||
# define STM32_NLCD 0 /* 0 LCD */
|
||||
# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 0 /* 0 HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 0 /* 0 DAC channel */
|
||||
# define STM32_NCOMP 2 /* 2 Analog Comparators */
|
||||
# define STM32_NCRC 0 /* 0 CRC module */
|
||||
# define STM32_NRNG 0 /* 0 Random number generator (RNG) */
|
||||
# define STM32_NCAP 0 /* 0 Capacitive sensing channels */
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L071KB) || defined(CONFIG_ARCH_CHIP_STM32L071KZ)
|
||||
# define STM32_NATIM 0 /* 0 advanced timers */
|
||||
# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
|
||||
* (with DMA) and TIM21-22 without DMA */
|
||||
# define STM32_NGTIM32 0 /* 0 32-bit general up/down timers */
|
||||
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
|
||||
/* 1 LPTIMER */
|
||||
# define STM32_NSPI 1 /* 1 SPI modules SPI1 */
|
||||
# define STM32_NI2S 0 /* 0 I2S module */
|
||||
# define STM32_NI2C 3 /* 3 I2C */
|
||||
# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
|
||||
# define STM32_NUSART 4 /* 4 USART modules, USART1-4 */
|
||||
/* 1 LPUART */
|
||||
# define STM32_NCAN 0 /* 0 CAN controllers */
|
||||
# define STM32_NLCD 0 /* 0 LCD */
|
||||
# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 0 /* 0 HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 0 /* 0 DAC channel */
|
||||
# define STM32_NCOMP 2 /* 2 Analog Comparators */
|
||||
# define STM32_NCRC 0 /* 0 CRC module */
|
||||
# define STM32_NRNG 0 /* 0 Random number generator (RNG) */
|
||||
# define STM32_NCAP 0 /* 0 Capacitive sensing channels */
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L072V8) || defined(CONFIG_ARCH_CHIP_STM32L072VB) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32L072VZ)
|
||||
# define STM32_NATIM 0 /* No advanced timers */
|
||||
# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
|
||||
* (with DMA) and TIM21-22 without DMA */
|
||||
# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
|
||||
# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
|
||||
/* One LPTIMER */
|
||||
# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
|
||||
# define STM32_NI2S 1 /* One I2S module */
|
||||
# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */
|
||||
# define STM32_NDMA 1 /* One DMA1, 7-channels */
|
||||
# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
|
||||
/* One LPUART */
|
||||
# define STM32_NCAN 0 /* No CAN controllers */
|
||||
# define STM32_NLCD 0 /* No LCD */
|
||||
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 0 /* No HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 2 /* Two DAC channels */
|
||||
# define STM32_NCOMP 2 /* Two Analog Comparators */
|
||||
# define STM32_NCRC 1 /* One CRC module */
|
||||
# define STM32_NRNG 1 /* One Random number generator (RNG) */
|
||||
# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L072KB) || defined(CONFIG_ARCH_CHIP_STM32L072KZ)
|
||||
# define STM32_NATIM 0 /* No advanced timers */
|
||||
# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
|
||||
* (with DMA) and TIM21-22 without DMA */
|
||||
# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
|
||||
# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
|
||||
/* One LPTIMER */
|
||||
# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
|
||||
# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */
|
||||
# define STM32_NDMA 1 /* One DMA1, 7-channels */
|
||||
# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
|
||||
/* One LPUART */
|
||||
# define STM32_NCAN 0 /* No CAN controllers */
|
||||
# define STM32_NLCD 0 /* No LCD */
|
||||
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 0 /* No HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 2 /* Two DAC channels */
|
||||
# define STM32_NCOMP 2 /* Two Analog Comparators */
|
||||
# define STM32_NCRC 1 /* One CRC module */
|
||||
# define STM32_NRNG 1 /* One Random number generator (RNG) */
|
||||
# define STM32_NCAP 13 /* Thirteen Capacitive sensing channels */
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L072CB) || defined(CONFIG_ARCH_CHIP_STM32L072CZ)
|
||||
# define STM32_NATIM 0 /* No advanced timers */
|
||||
# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
|
||||
* (with DMA) and TIM21-22 without DMA */
|
||||
# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
|
||||
# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
|
||||
/* One LPTIMER */
|
||||
# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
|
||||
# define STM32_NI2S 1 /* One I2S module */
|
||||
# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */
|
||||
# define STM32_NDMA 1 /* One DMA1, 7-channels */
|
||||
# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
|
||||
/* One LPUART */
|
||||
# define STM32_NCAN 0 /* No CAN controllers */
|
||||
# define STM32_NLCD 0 /* No LCD */
|
||||
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 0 /* No HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 2 /* Two DAC channels */
|
||||
# define STM32_NCOMP 2 /* Two Analog Comparators */
|
||||
# define STM32_NCRC 1 /* One CRC module */
|
||||
# define STM32_NRNG 1 /* One Random number generator (RNG) */
|
||||
# define STM32_NCAP 18 /* Nineteen Capacitive sensing channels */
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L072RB) || defined(CONFIG_ARCH_CHIP_STM32L072RZ)
|
||||
# define STM32_NATIM 0 /* No advanced timers */
|
||||
# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
|
||||
* (with DMA) and TIM21-22 without DMA */
|
||||
# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
|
||||
# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
|
||||
/* One LPTIMER */
|
||||
# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
|
||||
# define STM32_NI2S 1 /* One I2S module */
|
||||
# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */
|
||||
# define STM32_NDMA 1 /* One DMA1, 7-channels */
|
||||
# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
|
||||
/* One LPUART */
|
||||
# define STM32_NCAN 0 /* No CAN controllers */
|
||||
# define STM32_NLCD 0 /* No LCD */
|
||||
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 0 /* No HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 2 /* Two DAC channels */
|
||||
# define STM32_NCOMP 2 /* Two Analog Comparators */
|
||||
# define STM32_NCRC 1 /* One CRC module */
|
||||
# define STM32_NRNG 1 /* One Random number generator (RNG) */
|
||||
# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L073V8) || defined(CONFIG_ARCH_CHIP_STM32L073VB) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32L073VZ)
|
||||
# define STM32_NATIM 0 /* No advanced timers */
|
||||
# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
|
||||
* (with DMA) and TIM21-22 without DMA */
|
||||
# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
|
||||
# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
|
||||
/* One LPTIMER */
|
||||
# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
|
||||
# define STM32_NI2S 1 /* One I2S module */
|
||||
# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */
|
||||
# define STM32_NDMA 1 /* One DMA1, 7-channels */
|
||||
# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
|
||||
/* One LPUART */
|
||||
# define STM32_NCAN 0 /* No CAN controllers */
|
||||
# define STM32_NLCD 1 /* One LCD controller */
|
||||
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 0 /* No HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 2 /* Two DAC channels */
|
||||
# define STM32_NCOMP 2 /* Two Analog Comparators */
|
||||
# define STM32_NCRC 1 /* One CRC module */
|
||||
# define STM32_NRNG 1 /* One Random number generator (RNG) */
|
||||
# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L073CB) || defined(CONFIG_ARCH_CHIP_STM32L073CZ)
|
||||
# define STM32_NATIM 0 /* No advanced timers */
|
||||
# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
|
||||
* (with DMA) and TIM21-22 without DMA */
|
||||
# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
|
||||
# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
|
||||
/* One LPTIMER */
|
||||
# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
|
||||
# define STM32_NI2S 1 /* One I2S module */
|
||||
# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */
|
||||
# define STM32_NDMA 1 /* One DMA1, 7-channels */
|
||||
# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
|
||||
/* One LPUART */
|
||||
# define STM32_NCAN 0 /* No CAN controllers */
|
||||
# define STM32_NLCD 1 /* One LCD controller */
|
||||
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 0 /* No HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 2 /* Two DAC channels */
|
||||
# define STM32_NCOMP 2 /* Two Analog Comparators */
|
||||
# define STM32_NCRC 1 /* One CRC module */
|
||||
# define STM32_NRNG 1 /* One Random number generator (RNG) */
|
||||
# define STM32_NCAP 17 /* Seventeen Capacitive sensing channels */
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L073RB) || defined(CONFIG_ARCH_CHIP_STM32L073RZ)
|
||||
# define STM32_NATIM 0 /* No advanced timers */
|
||||
# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
|
||||
* (with DMA) and TIM21-22 without DMA */
|
||||
# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
|
||||
# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
|
||||
/* One LPTIMER */
|
||||
# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
|
||||
# define STM32_NI2S 1 /* One I2S module */
|
||||
# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */
|
||||
# define STM32_NDMA 1 /* One DMA1, 7-channels */
|
||||
# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
|
||||
/* One LPUART */
|
||||
# define STM32_NCAN 0 /* No CAN controllers */
|
||||
# define STM32_NLCD 1 /* One LCD controller */
|
||||
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 0 /* No HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 2 /* Two DAC channels */
|
||||
# define STM32_NCOMP 2 /* Two Analog Comparators */
|
||||
# define STM32_NCRC 1 /* One CRC module */
|
||||
# define STM32_NRNG 1 /* One Random number generator (RNG) */
|
||||
# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32C051XX)
|
||||
# define STM32_NATIM 1 /* One advanced timers TIM1 */
|
||||
# define STM32_NGTIM16 4 /* Four 16-bit general up/down timers TIM3, TIM14,
|
||||
* TIM16 and TIM17 */
|
||||
# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */
|
||||
# define STM32_NBTIM 0 /* No basic timers */
|
||||
/* One LPTIMER */
|
||||
# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
|
||||
# define STM32_NI2S 0 /* No I2S module */
|
||||
# define STM32_NI2C 2 /* Two I2C */
|
||||
# define STM32_NDMA 1 /* One DMA1, 5-channels */
|
||||
# define STM32_NUSART 2 /* Two USART modules, USART1-2 */
|
||||
# define STM32_NCAN 0 /* No CAN controllers */
|
||||
# define STM32_FDCAN 0 /* No FD CAN */
|
||||
# define STM32_NLCD 0 /* No LCD controller */
|
||||
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 0 /* No HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 0 /* No DAC channels */
|
||||
# define STM32_NCOMP 0 /* No Analog Comparators */
|
||||
# define STM32_NCRC 1 /* One CRC module */
|
||||
# define STM32_NRNG 0 /* No Random number generator (RNG) */
|
||||
# define STM32_NCAP 0 /* No Capacitive sensing channels */
|
||||
# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32C071XX)
|
||||
# define STM32_NATIM 1 /* One advanced timers TIM1 */
|
||||
# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM3, TIM14,
|
||||
* TIM16 and TIM17 */
|
||||
# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */
|
||||
# define STM32_NBTIM 0 /* No basic timers */
|
||||
/* One LPTIMER */
|
||||
# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
|
||||
# define STM32_NI2S 0 /* No I2S module */
|
||||
# define STM32_NI2C 2 /* Two I2C */
|
||||
# define STM32_NDMA 1 /* One DMA1, 5-channels */
|
||||
# define STM32_NUSART 2 /* Two USART modules, USART1-2 */
|
||||
# define STM32_NCAN 0 /* No CAN controllers */
|
||||
# define STM32_FDCAN 0 /* No FD CAN */
|
||||
# define STM32_NLCD 0 /* No LCD controller */
|
||||
# define STM32_NUSBDEV 1 /* USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 0 /* No HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 0 /* No DAC channels */
|
||||
# define STM32_NCOMP 0 /* No Analog Comparators */
|
||||
# define STM32_NCRC 1 /* One CRC module */
|
||||
# define STM32_NRNG 0 /* No Random number generator (RNG) */
|
||||
# define STM32_NCAP 0 /* No Capacitive sensing channels */
|
||||
# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32C091XX)
|
||||
# define STM32_NATIM 1 /* One advanced timers TIM1 */
|
||||
# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14,
|
||||
* TIM15, TIM16 and TIM17 */
|
||||
# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */
|
||||
# define STM32_NBTIM 0 /* No basic timers */
|
||||
/* One LPTIMER */
|
||||
# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
|
||||
# define STM32_NI2S 0 /* No I2S module */
|
||||
# define STM32_NI2C 2 /* Two I2C */
|
||||
# define STM32_NDMA 1 /* One DMA1, 5-channels */
|
||||
# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
|
||||
# define STM32_NCAN 0 /* No CAN controllers */
|
||||
# define STM32_FDCAN 0 /* No FD CAN */
|
||||
# define STM32_NLCD 0 /* No LCD controller */
|
||||
# define STM32_NUSBDEV 1 /* USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 0 /* No HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 0 /* No DAC channels */
|
||||
# define STM32_NCOMP 0 /* No Analog Comparators */
|
||||
# define STM32_NCRC 1 /* One CRC module */
|
||||
# define STM32_NRNG 0 /* No Random number generator (RNG) */
|
||||
# define STM32_NCAP 0 /* No Capacitive sensing channels */
|
||||
# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32C092XX)
|
||||
# define STM32_NATIM 1 /* One advanced timers TIM1 */
|
||||
# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14,
|
||||
* TIM15, TIM16 and TIM17 */
|
||||
# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */
|
||||
# define STM32_NBTIM 0 /* No basic timers */
|
||||
/* One LPTIMER */
|
||||
# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
|
||||
# define STM32_NI2S 0 /* No I2S module */
|
||||
# define STM32_NI2C 2 /* Two I2C */
|
||||
# define STM32_NDMA 1 /* One DMA1, 5-channels */
|
||||
# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
|
||||
# define STM32_NCAN 0 /* No CAN controllers */
|
||||
# define STM32_FDCAN 1 /* One FD CAN */
|
||||
# define STM32_NLCD 0 /* No LCD controller */
|
||||
# define STM32_NUSBDEV 1 /* USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 0 /* No HDMI-CEC controller */
|
||||
# define STM32_NADC 1 /* One 12-bit module */
|
||||
# define STM32_NDAC 0 /* No DAC channels */
|
||||
# define STM32_NCOMP 0 /* No Analog Comparators */
|
||||
# define STM32_NCRC 1 /* One CRC module */
|
||||
# define STM32_NRNG 0 /* No Random number generator (RNG) */
|
||||
# define STM32_NCAP 0 /* No Capacitive sensing channels */
|
||||
# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */
|
||||
#else
|
||||
# error "Unsupported STM32 Cortex M0 chip"
|
||||
#endif
|
||||
|
||||
/* NVIC priority levels *****************************************************/
|
||||
|
||||
/* Each priority field holds a priority value, 0-31. The lower the value,
|
||||
* the greater the priority of the corresponding interrupt. The processor
|
||||
* implements only bits[7:6] of each field, bits[5:0] read as zero and
|
||||
* ignore writes.
|
||||
*/
|
||||
|
||||
#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
|
||||
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
|
||||
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
|
||||
#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H */
|
||||
|
|
@ -1,114 +0,0 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/include/stm32f0l0g0/irq.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* This file should never be included directly but, rather, only indirectly
|
||||
* through nuttx/irq.h
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H
|
||||
#define __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
#endif
|
||||
#include <arch/stm32f0l0g0/chip.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/* IRQ numbers. The IRQ number corresponds vector number and hence map
|
||||
* directly to bits in the NVIC. This does, however, waste several words of
|
||||
* memory in the IRQ to handle mapping tables.
|
||||
*/
|
||||
|
||||
/* Common Processor Exceptions (vectors 0-15) */
|
||||
|
||||
#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
|
||||
/* Vector 0: Reset stack pointer value */
|
||||
/* Vector 1: Reset (not handler as an IRQ) */
|
||||
#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
|
||||
#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
|
||||
/* Vectors 4-10: Reserved */
|
||||
#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */
|
||||
/* Vector 12-13: Reserved */
|
||||
#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
|
||||
#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */
|
||||
|
||||
/* External interrupts (vectors >= 16) */
|
||||
|
||||
#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
/* Include MCU-specific external interrupt definitions */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32F0)
|
||||
# include <arch/stm32f0l0g0/stm32f0_irq.h>
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# include <arch/stm32f0l0g0/stm32l0_irq.h>
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32G0)
|
||||
# include <arch/stm32f0l0g0/stm32g0_irq.h>
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32C0)
|
||||
# include <arch/stm32f0l0g0/stm32c0_irq.h>
|
||||
#else
|
||||
# error Unrecognized STM32 Cortex M0 family
|
||||
#endif
|
||||
|
||||
#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINTS)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef void (*vic_vector_t)(uint32_t *regs);
|
||||
|
||||
/****************************************************************************
|
||||
* Inline functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H */
|
||||
|
|
@ -467,6 +467,12 @@ if(CONFIG_ARCH_CORTEXM0)
|
|||
list(APPEND SRCS stm32_aes_m0_v1.c)
|
||||
endif()
|
||||
|
||||
if(CONFIG_CRYPTO_CRYPTODEV_HARDWARE
|
||||
AND CONFIG_STM32_AES
|
||||
AND CONFIG_STM32_HAVE_IP_AES_M0_V1)
|
||||
list(APPEND SRCS stm32_crypto_m0_v1.c)
|
||||
endif()
|
||||
|
||||
if(CONFIG_STM32_RNG AND CONFIG_STM32_HAVE_IP_RNG_M0_V1)
|
||||
list(APPEND SRCS stm32_rng_m0_v1.c)
|
||||
endif()
|
||||
|
|
|
|||
|
|
@ -511,6 +511,10 @@ ifeq ($(CONFIG_STM32_AES)$(CONFIG_STM32_HAVE_IP_AES_M0_V1),yy)
|
|||
CHIP_CSRCS += stm32_aes_m0_v1.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE)$(CONFIG_STM32_AES)$(CONFIG_STM32_HAVE_IP_AES_M0_V1),yyy)
|
||||
CHIP_CSRCS += stm32_crypto_m0_v1.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_STM32_RNG)$(CONFIG_STM32_HAVE_IP_RNG_M0_V1),yy)
|
||||
CHIP_CSRCS += stm32_rng_m0_v1.c
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32f0l0g0/stm32_crypto.c
|
||||
* arch/arm/src/common/stm32/stm32_crypto_m0_v1.c
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -26,6 +26,8 @@
|
|||
|
||||
#include <errno.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <assert.h>
|
||||
|
||||
#include <crypto/cryptodev.h>
|
||||
#include <crypto/xform.h>
|
||||
|
|
@ -134,6 +136,8 @@ static int stm32_process(struct cryptop *crp)
|
|||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
# ##############################################################################
|
||||
# boards/arm/stm32f0l0g0/nucleo-g070rb/CMakeLists.txt
|
||||
# arch/arm/src/stm32c0/CMakeLists.txt
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
|
@ -20,4 +20,13 @@
|
|||
#
|
||||
# ##############################################################################
|
||||
|
||||
add_subdirectory(src)
|
||||
set(SRCS)
|
||||
|
||||
list(APPEND SRCS stm32_rcc.c)
|
||||
|
||||
if(CONFIG_BUILD_PROTECTED)
|
||||
list(APPEND SRCS stm32_userspace.c)
|
||||
endif()
|
||||
|
||||
target_sources(arch PRIVATE ${SRCS})
|
||||
add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common)
|
||||
286
arch/arm/src/stm32c0/Kconfig
Normal file
286
arch/arm/src/stm32c0/Kconfig
Normal file
|
|
@ -0,0 +1,286 @@
|
|||
#
|
||||
# For a description of the syntax of this configuration file,
|
||||
# see the file kconfig-language.txt in the NuttX tools repository.
|
||||
#
|
||||
comment "STM32 C0 configuration"
|
||||
|
||||
if ARCH_CHIP_STM32C0
|
||||
|
||||
choice
|
||||
prompt "ST STM32C0 Chip Selection"
|
||||
default ARCH_CHIP_STM32C071RB
|
||||
depends on ARCH_CHIP_STM32C0
|
||||
|
||||
config ARCH_CHIP_STM32C051D8
|
||||
bool "STM32C051D8"
|
||||
select ARCH_CHIP_STM32C051XX
|
||||
select STM32_FLASH_CONFIG_8
|
||||
|
||||
config ARCH_CHIP_STM32C051F6
|
||||
bool "STM32C051F6"
|
||||
select ARCH_CHIP_STM32C051XX
|
||||
select STM32_FLASH_CONFIG_6
|
||||
|
||||
config ARCH_CHIP_STM32C051F8
|
||||
bool "STM32C051F8"
|
||||
select ARCH_CHIP_STM32C051XX
|
||||
select STM32_FLASH_CONFIG_8
|
||||
|
||||
config ARCH_CHIP_STM32C051G6
|
||||
bool "STM32C051G6"
|
||||
select ARCH_CHIP_STM32C051XX
|
||||
select STM32_FLASH_CONFIG_6
|
||||
|
||||
config ARCH_CHIP_STM32C051G8
|
||||
bool "STM32C051G8"
|
||||
select ARCH_CHIP_STM32C051XX
|
||||
select STM32_FLASH_CONFIG_8
|
||||
|
||||
config ARCH_CHIP_STM32C051K6
|
||||
bool "STM32C051K6"
|
||||
select ARCH_CHIP_STM32C051XX
|
||||
select STM32_FLASH_CONFIG_6
|
||||
|
||||
config ARCH_CHIP_STM32C051K8
|
||||
bool "STM32C051K8"
|
||||
select ARCH_CHIP_STM32C051XX
|
||||
select STM32_FLASH_CONFIG_8
|
||||
|
||||
config ARCH_CHIP_STM32C051C6
|
||||
bool "STM32C051C6"
|
||||
select ARCH_CHIP_STM32C051XX
|
||||
select STM32_FLASH_CONFIG_6
|
||||
|
||||
config ARCH_CHIP_STM32C051C8
|
||||
bool "STM32C051C8"
|
||||
select ARCH_CHIP_STM32C051XX
|
||||
select STM32_FLASH_CONFIG_8
|
||||
|
||||
config ARCH_CHIP_STM32C071F8
|
||||
bool "STM32C071F8"
|
||||
select ARCH_CHIP_STM32C071XX
|
||||
select STM32_FLASH_CONFIG_8
|
||||
|
||||
config ARCH_CHIP_STM32C071FB
|
||||
bool "STM32C071FB"
|
||||
select ARCH_CHIP_STM32C071XX
|
||||
select STM32_FLASH_CONFIG_B
|
||||
|
||||
config ARCH_CHIP_STM32C071G8
|
||||
bool "STM32C071G8"
|
||||
select ARCH_CHIP_STM32C071XX
|
||||
select STM32_FLASH_CONFIG_8
|
||||
|
||||
config ARCH_CHIP_STM32C071GB
|
||||
bool "STM32C071GB"
|
||||
select ARCH_CHIP_STM32C071XX
|
||||
select STM32_FLASH_CONFIG_B
|
||||
|
||||
config ARCH_CHIP_STM32C071K8
|
||||
bool "STM32C071K8"
|
||||
select ARCH_CHIP_STM32C071XX
|
||||
select STM32_FLASH_CONFIG_8
|
||||
|
||||
config ARCH_CHIP_STM32C071KB
|
||||
bool "STM32C071KB"
|
||||
select ARCH_CHIP_STM32C071XX
|
||||
select STM32_FLASH_CONFIG_B
|
||||
|
||||
config ARCH_CHIP_STM32C071C8
|
||||
bool "STM32C071C8"
|
||||
select ARCH_CHIP_STM32C071XX
|
||||
select STM32_FLASH_CONFIG_8
|
||||
|
||||
config ARCH_CHIP_STM32C071CB
|
||||
bool "STM32C071CB"
|
||||
select ARCH_CHIP_STM32C071XX
|
||||
select STM32_FLASH_CONFIG_B
|
||||
|
||||
config ARCH_CHIP_STM32C071R8
|
||||
bool "STM32C071R8"
|
||||
select ARCH_CHIP_STM32C071XX
|
||||
select STM32_FLASH_CONFIG_8
|
||||
|
||||
config ARCH_CHIP_STM32C071RB
|
||||
bool "STM32C071RB"
|
||||
select ARCH_CHIP_STM32C071XX
|
||||
select STM32_FLASH_CONFIG_B
|
||||
|
||||
config ARCH_CHIP_STM32C091FB
|
||||
bool "STM32C091FB"
|
||||
select ARCH_CHIP_STM32C091XX
|
||||
select STM32_FLASH_CONFIG_B
|
||||
|
||||
config ARCH_CHIP_STM32C091FC
|
||||
bool "STM32C091FC"
|
||||
select ARCH_CHIP_STM32C091XX
|
||||
select STM32_FLASH_CONFIG_C
|
||||
|
||||
config ARCH_CHIP_STM32C091EC
|
||||
bool "STM32C091EC"
|
||||
select ARCH_CHIP_STM32C091XX
|
||||
select STM32_FLASH_CONFIG_C
|
||||
|
||||
config ARCH_CHIP_STM32C091GB
|
||||
bool "STM32C091GB"
|
||||
select ARCH_CHIP_STM32C091XX
|
||||
select STM32_FLASH_CONFIG_B
|
||||
|
||||
config ARCH_CHIP_STM32C091GC
|
||||
bool "STM32C091GC"
|
||||
select ARCH_CHIP_STM32C091XX
|
||||
select STM32_FLASH_CONFIG_C
|
||||
|
||||
config ARCH_CHIP_STM32C091KB
|
||||
bool "STM32C091KB"
|
||||
select ARCH_CHIP_STM32C091XX
|
||||
select STM32_FLASH_CONFIG_B
|
||||
|
||||
config ARCH_CHIP_STM32C091KC
|
||||
bool "STM32C091KC"
|
||||
select ARCH_CHIP_STM32C091XX
|
||||
select STM32_FLASH_CONFIG_C
|
||||
|
||||
config ARCH_CHIP_STM32C091CB
|
||||
bool "STM32C091CB"
|
||||
select ARCH_CHIP_STM32C091XX
|
||||
select STM32_FLASH_CONFIG_B
|
||||
|
||||
config ARCH_CHIP_STM32C091CC
|
||||
bool "STM32C091CC"
|
||||
select ARCH_CHIP_STM32C091XX
|
||||
select STM32_FLASH_CONFIG_C
|
||||
|
||||
config ARCH_CHIP_STM32C091RB
|
||||
bool "STM32C091RB"
|
||||
select ARCH_CHIP_STM32C091XX
|
||||
select STM32_FLASH_CONFIG_B
|
||||
|
||||
config ARCH_CHIP_STM32C091RC
|
||||
bool "STM32C091RC"
|
||||
select ARCH_CHIP_STM32C091XX
|
||||
select STM32_FLASH_CONFIG_C
|
||||
|
||||
config ARCH_CHIP_STM32C092FB
|
||||
bool "STM32C092FB"
|
||||
select ARCH_CHIP_STM32C092XX
|
||||
select STM32_FLASH_CONFIG_B
|
||||
|
||||
config ARCH_CHIP_STM32C092FC
|
||||
bool "STM32C092FC"
|
||||
select ARCH_CHIP_STM32C092XX
|
||||
select STM32_FLASH_CONFIG_C
|
||||
|
||||
config ARCH_CHIP_STM32C092EC
|
||||
bool "STM32C092EC"
|
||||
select ARCH_CHIP_STM32C092XX
|
||||
select STM32_FLASH_CONFIG_C
|
||||
|
||||
config ARCH_CHIP_STM32C092GB
|
||||
bool "STM32C092GB"
|
||||
select ARCH_CHIP_STM32C092XX
|
||||
select STM32_FLASH_CONFIG_B
|
||||
|
||||
config ARCH_CHIP_STM32C092GC
|
||||
bool "STM32C092GC"
|
||||
select ARCH_CHIP_STM32C092XX
|
||||
select STM32_FLASH_CONFIG_C
|
||||
|
||||
config ARCH_CHIP_STM32C092KB
|
||||
bool "STM32C092KB"
|
||||
select ARCH_CHIP_STM32C092XX
|
||||
select STM32_FLASH_CONFIG_B
|
||||
|
||||
config ARCH_CHIP_STM32C092KC
|
||||
bool "STM32C092KC"
|
||||
select ARCH_CHIP_STM32C092XX
|
||||
select STM32_FLASH_CONFIG_C
|
||||
|
||||
config ARCH_CHIP_STM32C092CB
|
||||
bool "STM32C092CB"
|
||||
select ARCH_CHIP_STM32C092XX
|
||||
select STM32_FLASH_CONFIG_B
|
||||
|
||||
config ARCH_CHIP_STM32C092CC
|
||||
bool "STM32C092CC"
|
||||
select ARCH_CHIP_STM32C092XX
|
||||
select STM32_FLASH_CONFIG_C
|
||||
|
||||
config ARCH_CHIP_STM32C092RB
|
||||
bool "STM32C092RB"
|
||||
select ARCH_CHIP_STM32C092XX
|
||||
select STM32_FLASH_CONFIG_B
|
||||
|
||||
config ARCH_CHIP_STM32C092RC
|
||||
bool "STM32C092RC"
|
||||
select ARCH_CHIP_STM32C092XX
|
||||
select STM32_FLASH_CONFIG_C
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
config STM32_STM32C0
|
||||
bool
|
||||
default n
|
||||
select STM32_HAVE_DMA1
|
||||
select STM32_HAVE_USART1
|
||||
select STM32_HAVE_USART2
|
||||
select STM32_HAVE_SPI2
|
||||
select STM32_HAVE_I2C2
|
||||
select STM32_HAVE_DMAMUX
|
||||
select STM32_HAVE_IP_ADC_M0_V1
|
||||
select STM32_HAVE_CRC
|
||||
select STM32_HAVE_BKP
|
||||
select STM32_HAVE_BKPSRAM
|
||||
select STM32_HAVE_IP_AES_M0_V1 if STM32_HAVE_AES
|
||||
select STM32_HAVE_IP_COMP_M0_V1 if STM32_HAVE_COMP
|
||||
select STM32_HAVE_IP_DAC_M0_V1 if STM32_HAVE_DAC1
|
||||
select STM32_HAVE_IP_DBGMCU_M0_V1
|
||||
select STM32_HAVE_IP_DMA_V1
|
||||
select STM32_HAVE_IP_FDCAN_MCAN_M0_V1
|
||||
select STM32_HAVE_IP_DMA_V1_7CH_DMAMUX
|
||||
select STM32_HAVE_IP_EXTI_V2
|
||||
select STM32_HAVE_IP_FLASH_M0_V1
|
||||
select STM32_HAVE_IP_FLASH_M0_G0C0
|
||||
select STM32_HAVE_IP_GPIO_M0_V1
|
||||
select STM32_HAVE_IP_I2C_M0_V1
|
||||
select STM32_HAVE_IP_PWR_G0
|
||||
select STM32_HAVE_IP_RNG_M0_V1 if STM32_HAVE_RNG
|
||||
select STM32_HAVE_IP_RTCC_M0_V1
|
||||
select STM32_HAVE_IP_SPI_V2
|
||||
select STM32_HAVE_IP_TIMERS_M0_V1
|
||||
select STM32_HAVE_IP_USART_V4
|
||||
select STM32_HAVE_IP_WDG_M0_V1
|
||||
select STM32_HAVE_IP_UID_M0_V1
|
||||
select STM32_HAVE_IP_USBDEV_M0_V1 if STM32_HAVE_USBDEV
|
||||
select STM32_HAVE_TIM1
|
||||
select STM32_HAVE_TIM2
|
||||
select STM32_HAVE_TIM3
|
||||
select STM32_HAVE_TIM14
|
||||
select STM32_HAVE_TIM16
|
||||
select STM32_HAVE_TIM17
|
||||
select ARCH_HAVE_PROGMEM
|
||||
|
||||
config ARCH_CHIP_STM32C051XX
|
||||
bool
|
||||
select STM32_STM32C0
|
||||
|
||||
config ARCH_CHIP_STM32C071XX
|
||||
bool
|
||||
select STM32_STM32C0
|
||||
select STM32_HAVE_USBDEV
|
||||
|
||||
config ARCH_CHIP_STM32C091XX
|
||||
bool
|
||||
select STM32_STM32C0
|
||||
select STM32_HAVE_USART3
|
||||
select STM32_HAVE_USART4
|
||||
select STM32_HAVE_TIM15
|
||||
|
||||
config ARCH_CHIP_STM32C092XX
|
||||
bool
|
||||
select STM32_STM32C0
|
||||
select STM32_HAVE_USART3
|
||||
select STM32_HAVE_USART4
|
||||
select STM32_HAVE_FDCAN1
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
############################################################################
|
||||
# arch/arm/src/stm32f0l0g0/Make.defs
|
||||
# arch/arm/src/stm32c0/Make.defs
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
|
@ -22,24 +22,7 @@
|
|||
|
||||
include armv6-m/Make.defs
|
||||
|
||||
CHIP_CSRCS = stm32_start.c stm32_irq.c stm32_lowputc.c
|
||||
CHIP_CSRCS += stm32_rcc.c stm32_lsi.c
|
||||
|
||||
ifneq ($(CONFIG_STM32_RTC_LSECLOCK)$(CONFIG_STM32_LCD_LSECLOCK),)
|
||||
CHIP_CSRCS += stm32_lse.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_STM32_PWR),y)
|
||||
CHIP_CSRCS += stm32_pwr.c
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
|
||||
CHIP_CSRCS += stm32_idle.c
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_SCHED_TICKLESS),y)
|
||||
CHIP_CSRCS += stm32_timerisr.c
|
||||
endif
|
||||
CHIP_CSRCS = stm32_rcc.c
|
||||
|
||||
ifeq ($(CONFIG_BUILD_PROTECTED),y)
|
||||
CHIP_CSRCS += stm32_userspace.c
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32f0l0g0/chip.h
|
||||
* arch/arm/src/stm32c0/chip.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -20,8 +20,8 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_CHIP_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0G0_CHIP_H
|
||||
#ifndef __ARCH_ARM_SRC_STM32C0_CHIP_H
|
||||
#define __ARCH_ARM_SRC_STM32C0_CHIP_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
|
|
@ -32,9 +32,7 @@
|
|||
|
||||
/* Include the chip capabilities file */
|
||||
|
||||
#include <arch/stm32f0l0g0/chip.h>
|
||||
|
||||
#define ARMV6M_PERIPHERAL_INTERRUPTS 32
|
||||
#include <arch/stm32c0/chip.h>
|
||||
|
||||
/* Include the memory map file.
|
||||
* Other chip hardware files should then include this file for the proper
|
||||
|
|
@ -43,4 +41,4 @@
|
|||
|
||||
#include "hardware/stm32_memorymap.h"
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_CHIP_H */
|
||||
#endif /* __ARCH_ARM_SRC_STM32C0_CHIP_H */
|
||||
17
arch/arm/src/stm32c0/hardware/stm32_memorymap.h
Normal file
17
arch/arm/src/stm32c0/hardware/stm32_memorymap.h
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32c0/hardware/stm32_memorymap.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_MEMORYMAP_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "hardware/stm32c0_memorymap.h"
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_MEMORYMAP_H */
|
||||
17
arch/arm/src/stm32c0/hardware/stm32_pinmap.h
Normal file
17
arch/arm/src/stm32c0/hardware/stm32_pinmap.h
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32c0/hardware/stm32_pinmap.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_PINMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_PINMAP_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "hardware/stm32c0_pinmap.h"
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_PINMAP_H */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32f0l0g0/hardware/stm32c0_dmamux.h
|
||||
* arch/arm/src/stm32c0/hardware/stm32c0_dmamux.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -20,8 +20,8 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_DMAMUX_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_DMAMUX_H
|
||||
#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_DMAMUX_H
|
||||
#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_DMAMUX_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
|
|
@ -54,4 +54,4 @@
|
|||
#define DMAMAP_DMA1_REQGEN3 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN3)
|
||||
#define DMAMAP_DMA1_ADC1 DMAMAP_MAP(DMA1, DMAMUX1_ADC1)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_DMAMUX_H */
|
||||
#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_DMAMUX_H */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32f0l0g0/hardware/stm32c0_exti.h
|
||||
* arch/arm/src/stm32c0/hardware/stm32c0_exti.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -20,8 +20,8 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_EXTI_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_EXTI_H
|
||||
#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_EXTI_H
|
||||
#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_EXTI_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
|
|
@ -87,4 +87,4 @@
|
|||
|
||||
/* TODO */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_EXTI_H */
|
||||
#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_EXTI_H */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32f0l0g0/hardware/stm32c0_flash.h
|
||||
* arch/arm/src/stm32c0/hardware/stm32c0_flash.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -20,8 +20,8 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_FLASH_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_FLASH_H
|
||||
#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_FLASH_H
|
||||
#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_FLASH_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
|
|
@ -202,4 +202,4 @@
|
|||
#define FLASH_SECR_BOOT_LOCK (1 << 16) /* Bit 16: Used to force boot from user area */
|
||||
/* Bits 20-31: Reserved */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_FLASH_H */
|
||||
#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_FLASH_H */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32f0l0g0/hardware/stm32c0_memorymap.h
|
||||
* arch/arm/src/stm32c0/hardware/stm32c0_memorymap.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -20,8 +20,8 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_MEMORYMAP_H
|
||||
#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_MEMORYMAP_H
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
|
@ -115,4 +115,4 @@
|
|||
|
||||
#define STM32_SYSMEM_UID 0x1fff7550 /* The 96-bit unique device identifier */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_MEMORYMAP_H */
|
||||
#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_MEMORYMAP_H */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32f0l0g0/hardware/stm32c0_pinmap.h
|
||||
* arch/arm/src/stm32c0/hardware/stm32c0_pinmap.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -32,8 +32,8 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PINMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PINMAP_H
|
||||
#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PINMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PINMAP_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
|
|
@ -351,4 +351,4 @@
|
|||
#define GPIO_TIM17_CH1NOUT_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN4)
|
||||
#define GPIO_TIM17_CH1NOUT_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN7)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PINMAP_H */
|
||||
#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PINMAP_H */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32f0l0g0/hardware/stm32c0_pwr.h
|
||||
* arch/arm/src/stm32c0/hardware/stm32c0_pwr.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -20,8 +20,8 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PWR_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PWR_H
|
||||
#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PWR_H
|
||||
#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PWR_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
|
|
@ -150,4 +150,4 @@
|
|||
|
||||
#define PWR_BKPR_MASK (0xffff) /* Bits 0-16: Backup bitfield */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PWR_H */
|
||||
#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PWR_H */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32f0l0g0/hardware/stm32c0_rcc.h
|
||||
* arch/arm/src/stm32c0/hardware/stm32c0_rcc.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -20,8 +20,8 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_RCC_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_RCC_H
|
||||
#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_RCC_H
|
||||
#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_RCC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
|
@ -394,4 +394,4 @@
|
|||
#define RCC_CSR2_WWDGRSTF (1 << 30) /* Bit 30: WWDG reset flag */
|
||||
#define RCC_CSR2_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_RCC_H */
|
||||
#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_RCC_H */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32f0l0g0/stm32.h
|
||||
* arch/arm/src/stm32c0/stm32.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -20,8 +20,8 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_H
|
||||
#ifndef __ARCH_ARM_SRC_STM32C0_STM32_H
|
||||
#define __ARCH_ARM_SRC_STM32C0_STM32_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
|
|
@ -51,4 +51,4 @@
|
|||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_H */
|
||||
#endif /* __ARCH_ARM_SRC_STM32C0_STM32_H */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32f0l0g0/stm32_rcc.c
|
||||
* arch/arm/src/stm32c0/stm32_rcc.c
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -36,7 +36,7 @@
|
|||
#include "arm_internal.h"
|
||||
#include "hardware/stm32_flash.h"
|
||||
#include "stm32_rcc.h"
|
||||
#include "stm32_hsi48.h"
|
||||
#include "stm32_hsi48_m0_v1.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
|
@ -70,17 +70,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
|
|||
|
||||
/* Include chip-specific clocking initialization logic */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32F0)
|
||||
# include "stm32f0_rcc.c"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# include "stm32l0_rcc.c"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32G0)
|
||||
# include "stm32g0_rcc.c"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32C0)
|
||||
# include "stm32c0_rcc.c"
|
||||
#else
|
||||
# error "Unsupported STM32F0/L0 RCC"
|
||||
#endif
|
||||
#include "stm32c0_rcc.c"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32f0l0g0/stm32c0_rcc.c
|
||||
* arch/arm/src/stm32c0/stm32c0_rcc.c
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
# ##############################################################################
|
||||
# arch/arm/src/stm32f0l0g0/CMakeLists.txt
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
|
||||
# license agreements. See the NOTICE file distributed with this work for
|
||||
# additional information regarding copyright ownership. The ASF licenses this
|
||||
# file to you under the Apache License, Version 2.0 (the "License"); you may not
|
||||
# use this file except in compliance with the License. You may obtain a copy of
|
||||
# the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations under
|
||||
# the License.
|
||||
#
|
||||
# ##############################################################################
|
||||
|
||||
set(SRCS)
|
||||
|
||||
list(
|
||||
APPEND
|
||||
SRCS
|
||||
stm32_start.c
|
||||
stm32_irq.c
|
||||
stm32_lowputc.c
|
||||
stm32_lsi.c
|
||||
stm32_rcc.c)
|
||||
|
||||
if(CONFIG_STM32_RTC_LSECLOCK OR CONFIG_LCD_LSECLOCK)
|
||||
list(APPEND SRCS stm32_lse.c)
|
||||
endif()
|
||||
|
||||
if(CONFIG_STM32_PWR)
|
||||
list(APPEND SRCS stm32_pwr.c)
|
||||
endif()
|
||||
|
||||
if(NOT CONFIG_ARCH_IDLE_CUSTOM)
|
||||
list(APPEND SRCS stm32_idle.c)
|
||||
endif()
|
||||
|
||||
if(NOT CONFIG_SCHED_TICKLESS)
|
||||
list(APPEND SRCS stm32_timerisr.c)
|
||||
endif()
|
||||
|
||||
if(CONFIG_BUILD_PROTECTED)
|
||||
list(APPEND SRCS stm32_userspace.c)
|
||||
endif()
|
||||
|
||||
target_sources(arch PRIVATE ${SRCS})
|
||||
add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../common/stm32 stm32_common)
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,90 +0,0 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32f0l0g0/stm32_rcc.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "arm_internal.h"
|
||||
#include "chip.h"
|
||||
|
||||
#include "hardware/stm32_rcc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_clockconfig
|
||||
*
|
||||
* Description:
|
||||
* Called to initialize the STM32F0XX.
|
||||
* This does whatever setup is needed to put the MCU in a usable state.
|
||||
* This includes the initialization of clocking using the settings
|
||||
* in board.h.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_clockconfig(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_rcc_enablelse
|
||||
*
|
||||
* Description:
|
||||
* Enable the External Low-Speed (LSE) Oscillator.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_rcc_enablelse(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_rcc_enablelsi
|
||||
*
|
||||
* Description:
|
||||
* Enable the Internal Low-Speed (LSI) RC Oscillator.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_rcc_enablelsi(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_rcc_disablelsi
|
||||
*
|
||||
* Description:
|
||||
* Disable the Internal Low-Speed (LSI) RC Oscillator.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_rcc_disablelsi(void);
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H */
|
||||
|
|
@ -5207,13 +5207,10 @@ endif
|
|||
if ARCH_CHIP_SAMV7
|
||||
source "boards/arm/samv7/common/Kconfig"
|
||||
endif
|
||||
if ARCH_CHIP_STM32
|
||||
source "boards/arm/common/stm32/Kconfig"
|
||||
endif
|
||||
if ARCH_CHIP_STM32F7
|
||||
source "boards/arm/stm32f7/common/Kconfig"
|
||||
endif
|
||||
if ARCH_CHIP_STM32F0L0G0
|
||||
if ARCH_CHIP_STM32C0 || ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32L1
|
||||
source "boards/arm/common/stm32/Kconfig"
|
||||
endif
|
||||
if ARCH_CHIP_RP2040
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
# ##############################################################################
|
||||
# boards/arm/stm32f0l0g0/common/CMakeLists.txt
|
||||
# boards/arm/stm32c0/common/CMakeLists.txt
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
#############################################################################
|
||||
# boards/arm/stm32f0l0g0/common/Makefile
|
||||
# boards/arm/stm32c0/common/Makefile
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
# ##############################################################################
|
||||
# boards/arm/stm32f0l0g0/nucleo-c092rc/CMakeLists.txt
|
||||
# boards/arm/stm32c0/nucleo-c071rb/CMakeLists.txt
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
|
@ -13,7 +13,7 @@ CONFIG_ARCH="arm"
|
|||
CONFIG_ARCH_BOARD="nucleo-c071rb"
|
||||
CONFIG_ARCH_BOARD_NUCLEO_C071RB=y
|
||||
CONFIG_ARCH_BUTTONS=y
|
||||
CONFIG_ARCH_CHIP="stm32f0l0g0"
|
||||
CONFIG_ARCH_CHIP="stm32c0"
|
||||
CONFIG_ARCH_CHIP_STM32=y
|
||||
CONFIG_ARCH_CHIP_STM32C071RB=y
|
||||
CONFIG_ARCH_CHIP_STM32C071XX=y
|
||||
|
|
@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-c071rb"
|
|||
CONFIG_ARCH_BOARD_COMMON=y
|
||||
CONFIG_ARCH_BOARD_NUCLEO_C071RB=y
|
||||
CONFIG_ARCH_BUTTONS=y
|
||||
CONFIG_ARCH_CHIP="stm32f0l0g0"
|
||||
CONFIG_ARCH_CHIP="stm32c0"
|
||||
CONFIG_ARCH_CHIP_STM32=y
|
||||
CONFIG_ARCH_CHIP_STM32C071RB=y
|
||||
CONFIG_ARCH_CHIP_STM32C071XX=y
|
||||
|
|
@ -9,7 +9,7 @@ CONFIG_ARCH="arm"
|
|||
CONFIG_ARCH_BOARD="nucleo-c071rb"
|
||||
CONFIG_ARCH_BOARD_NUCLEO_C071RB=y
|
||||
CONFIG_ARCH_BUTTONS=y
|
||||
CONFIG_ARCH_CHIP="stm32f0l0g0"
|
||||
CONFIG_ARCH_CHIP="stm32c0"
|
||||
CONFIG_ARCH_CHIP_STM32=y
|
||||
CONFIG_ARCH_CHIP_STM32C071RB=y
|
||||
CONFIG_ARCH_CHIP_STM32C071XX=y
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/stm32f0l0g0/nucleo-c071rb/include/board.h
|
||||
* boards/arm/stm32c0/nucleo-c071rb/include/board.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
############################################################################
|
||||
# boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/Make.defs
|
||||
# boards/arm/stm32c0/nucleo-c071rb/scripts/Make.defs
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/flash.ld
|
||||
* boards/arm/stm32c0/nucleo-c071rb/scripts/flash.ld
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
# ##############################################################################
|
||||
# boards/arm/stm32f0l0g0/nucleo-c071rb/src/CMakeLists.txt
|
||||
# boards/arm/stm32c0/nucleo-c071rb/src/CMakeLists.txt
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
############################################################################
|
||||
# boards/arm/stm32f0l0g0/nucleo-c071rb/src/Make.defs
|
||||
# boards/arm/stm32c0/nucleo-c071rb/src/Make.defs
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/stm32f0l0g0/nucleo-c071rb/src/nucleo-c071rb.h
|
||||
* boards/arm/stm32c0/nucleo-c071rb/src/nucleo-c071rb.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_adc.c
|
||||
* boards/arm/stm32c0/nucleo-c071rb/src/stm32_adc.c
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_autoleds.c
|
||||
* boards/arm/stm32c0/nucleo-c071rb/src/stm32_autoleds.c
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c
|
||||
* boards/arm/stm32c0/nucleo-c071rb/src/stm32_boot.c
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c
|
||||
* boards/arm/stm32c0/nucleo-c071rb/src/stm32_bringup.c
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_buttons.c
|
||||
* boards/arm/stm32c0/nucleo-c071rb/src/stm32_buttons.c
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_userleds.c
|
||||
* boards/arm/stm32c0/nucleo-c071rb/src/stm32_userleds.c
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
# ##############################################################################
|
||||
# boards/arm/stm32f0l0g0/nucleo-g071rb/CMakeLists.txt
|
||||
# boards/arm/stm32c0/nucleo-c092rc/CMakeLists.txt
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
|
@ -9,7 +9,7 @@ CONFIG_ARCH="arm"
|
|||
CONFIG_ARCH_BOARD="nucleo-c092rc"
|
||||
CONFIG_ARCH_BOARD_NUCLEO_C092RC=y
|
||||
CONFIG_ARCH_BUTTONS=y
|
||||
CONFIG_ARCH_CHIP="stm32f0l0g0"
|
||||
CONFIG_ARCH_CHIP="stm32c0"
|
||||
CONFIG_ARCH_CHIP_STM32=y
|
||||
CONFIG_ARCH_CHIP_STM32C092RC=y
|
||||
CONFIG_ARCH_CHIP_STM32C092XX=y
|
||||
|
|
@ -12,7 +12,7 @@ CONFIG_ARCH="arm"
|
|||
CONFIG_ARCH_BOARD="nucleo-c092rc"
|
||||
CONFIG_ARCH_BOARD_NUCLEO_C092RC=y
|
||||
CONFIG_ARCH_BUTTONS=y
|
||||
CONFIG_ARCH_CHIP="stm32f0l0g0"
|
||||
CONFIG_ARCH_CHIP="stm32c0"
|
||||
CONFIG_ARCH_CHIP_STM32=y
|
||||
CONFIG_ARCH_CHIP_STM32C092RC=y
|
||||
CONFIG_ARCH_CHIP_STM32C092XX=y
|
||||
|
|
@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-c092rc"
|
|||
CONFIG_ARCH_BOARD_COMMON=y
|
||||
CONFIG_ARCH_BOARD_NUCLEO_C092RC=y
|
||||
CONFIG_ARCH_BUTTONS=y
|
||||
CONFIG_ARCH_CHIP="stm32f0l0g0"
|
||||
CONFIG_ARCH_CHIP="stm32c0"
|
||||
CONFIG_ARCH_CHIP_STM32=y
|
||||
CONFIG_ARCH_CHIP_STM32C092RC=y
|
||||
CONFIG_ARCH_CHIP_STM32C092XX=y
|
||||
|
|
@ -9,7 +9,7 @@ CONFIG_ARCH="arm"
|
|||
CONFIG_ARCH_BOARD="nucleo-c092rc"
|
||||
CONFIG_ARCH_BOARD_NUCLEO_C092RC=y
|
||||
CONFIG_ARCH_BUTTONS=y
|
||||
CONFIG_ARCH_CHIP="stm32f0l0g0"
|
||||
CONFIG_ARCH_CHIP="stm32c0"
|
||||
CONFIG_ARCH_CHIP_STM32=y
|
||||
CONFIG_ARCH_CHIP_STM32C092RC=y
|
||||
CONFIG_ARCH_CHIP_STM32C092XX=y
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/stm32f0l0g0/nucleo-c092rc/include/board.h
|
||||
* boards/arm/stm32c0/nucleo-c092rc/include/board.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
############################################################################
|
||||
# boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/Make.defs
|
||||
# boards/arm/stm32c0/nucleo-c092rc/scripts/Make.defs
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/flash.ld
|
||||
* boards/arm/stm32c0/nucleo-c092rc/scripts/flash.ld
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
# ##############################################################################
|
||||
# boards/arm/stm32f0l0g0/nucleo-c092rc/src/CMakeLists.txt
|
||||
# boards/arm/stm32c0/nucleo-c092rc/src/CMakeLists.txt
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
############################################################################
|
||||
# boards/arm/stm32f0l0g0/nucleo-c092rc/src/Make.defs
|
||||
# boards/arm/stm32c0/nucleo-c092rc/src/Make.defs
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h
|
||||
* boards/arm/stm32c0/nucleo-c092rc/src/nucleo-c092rc.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_adc.c
|
||||
* boards/arm/stm32c0/nucleo-c092rc/src/stm32_adc.c
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_autoleds.c
|
||||
* boards/arm/stm32c0/nucleo-c092rc/src/stm32_autoleds.c
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c
|
||||
* boards/arm/stm32c0/nucleo-c092rc/src/stm32_boot.c
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c
|
||||
* boards/arm/stm32c0/nucleo-c092rc/src/stm32_bringup.c
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_buttons.c
|
||||
* boards/arm/stm32c0/nucleo-c092rc/src/stm32_buttons.c
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_can.c
|
||||
* boards/arm/stm32c0/nucleo-c092rc/src/stm32_can.c
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_cansock.c
|
||||
* boards/arm/stm32c0/nucleo-c092rc/src/stm32_cansock.c
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_userleds.c
|
||||
* boards/arm/stm32c0/nucleo-c092rc/src/stm32_userleds.c
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
############################################################################
|
||||
# boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/Make.defs
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
# contributor license agreements. See the NOTICE file distributed with
|
||||
# this work for additional information regarding copyright ownership. The
|
||||
# ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
# "License"); you may not use this file except in compliance with the
|
||||
# License. You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations
|
||||
# under the License.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
include $(TOPDIR)/.config
|
||||
include $(TOPDIR)/tools/Config.mk
|
||||
include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs
|
||||
|
||||
LDSCRIPT = ld.script
|
||||
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
|
||||
|
||||
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
|
||||
|
||||
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
|
||||
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
|
||||
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
|
||||
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
|
||||
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
|
||||
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
|
||||
|
||||
NXFLATLDFLAGS1 = -r -d -warn-common
|
||||
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
|
||||
LDNXFLATFLAGS = -e main -s 2048
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
# ##############################################################################
|
||||
# boards/arm/stm32f0l0g0/nucleo-f072rb/CMakeLists.txt
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
|
||||
# license agreements. See the NOTICE file distributed with this work for
|
||||
# additional information regarding copyright ownership. The ASF licenses this
|
||||
# file to you under the Apache License, Version 2.0 (the "License"); you may not
|
||||
# use this file except in compliance with the License. You may obtain a copy of
|
||||
# the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations under
|
||||
# the License.
|
||||
#
|
||||
# ##############################################################################
|
||||
|
||||
add_subdirectory(src)
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
# ##############################################################################
|
||||
# boards/arm/stm32f0l0g0/nucleo-g0b1re/CMakeLists.txt
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
|
||||
# license agreements. See the NOTICE file distributed with this work for
|
||||
# additional information regarding copyright ownership. The ASF licenses this
|
||||
# file to you under the Apache License, Version 2.0 (the "License"); you may not
|
||||
# use this file except in compliance with the License. You may obtain a copy of
|
||||
# the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations under
|
||||
# the License.
|
||||
#
|
||||
# ##############################################################################
|
||||
|
||||
add_subdirectory(src)
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
# ##############################################################################
|
||||
# boards/arm/stm32f0l0g0/nucleo-l073rz/CMakeLists.txt
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
|
||||
# license agreements. See the NOTICE file distributed with this work for
|
||||
# additional information regarding copyright ownership. The ASF licenses this
|
||||
# file to you under the Apache License, Version 2.0 (the "License"); you may not
|
||||
# use this file except in compliance with the License. You may obtain a copy of
|
||||
# the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations under
|
||||
# the License.
|
||||
#
|
||||
# ##############################################################################
|
||||
|
||||
add_subdirectory(src)
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
# ##############################################################################
|
||||
# boards/arm/stm32f0l0g0/stm32f051-discovery/CMakeLists.txt
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
|
||||
# license agreements. See the NOTICE file distributed with this work for
|
||||
# additional information regarding copyright ownership. The ASF licenses this
|
||||
# file to you under the Apache License, Version 2.0 (the "License"); you may not
|
||||
# use this file except in compliance with the License. You may obtain a copy of
|
||||
# the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations under
|
||||
# the License.
|
||||
#
|
||||
# ##############################################################################
|
||||
|
||||
add_subdirectory(src)
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
############################################################################
|
||||
# boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/Make.defs
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
# contributor license agreements. See the NOTICE file distributed with
|
||||
# this work for additional information regarding copyright ownership. The
|
||||
# ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
# "License"); you may not use this file except in compliance with the
|
||||
# License. You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations
|
||||
# under the License.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
include $(TOPDIR)/.config
|
||||
include $(TOPDIR)/tools/Config.mk
|
||||
include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs
|
||||
|
||||
LDSCRIPT = flash.ld
|
||||
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
|
||||
|
||||
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
|
||||
|
||||
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
|
||||
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
|
||||
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
|
||||
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
|
||||
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
|
||||
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
|
||||
|
||||
NXFLATLDFLAGS1 = -r -d -warn-common
|
||||
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
|
||||
LDNXFLATFLAGS = -e main -s 2048
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
# ##############################################################################
|
||||
# boards/arm/stm32f0l0g0/stm32f072-discovery/CMakeLists.txt
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
|
||||
# license agreements. See the NOTICE file distributed with this work for
|
||||
# additional information regarding copyright ownership. The ASF licenses this
|
||||
# file to you under the Apache License, Version 2.0 (the "License"); you may not
|
||||
# use this file except in compliance with the License. You may obtain a copy of
|
||||
# the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations under
|
||||
# the License.
|
||||
#
|
||||
# ##############################################################################
|
||||
|
||||
add_subdirectory(src)
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
############################################################################
|
||||
# boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/Make.defs
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
# contributor license agreements. See the NOTICE file distributed with
|
||||
# this work for additional information regarding copyright ownership. The
|
||||
# ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
# "License"); you may not use this file except in compliance with the
|
||||
# License. You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations
|
||||
# under the License.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
include $(TOPDIR)/.config
|
||||
include $(TOPDIR)/tools/Config.mk
|
||||
include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs
|
||||
|
||||
LDSCRIPT = flash.ld
|
||||
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
|
||||
|
||||
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
|
||||
|
||||
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
|
||||
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
|
||||
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
|
||||
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
|
||||
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
|
||||
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
|
||||
|
||||
NXFLATLDFLAGS1 = -r -d -warn-common
|
||||
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
|
||||
LDNXFLATFLAGS = -e main -s 2048
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
# ##############################################################################
|
||||
# boards/arm/stm32f0l0g0/stm32g071b-disco/CMakeLists.txt
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
|
||||
# license agreements. See the NOTICE file distributed with this work for
|
||||
# additional information regarding copyright ownership. The ASF licenses this
|
||||
# file to you under the Apache License, Version 2.0 (the "License"); you may not
|
||||
# use this file except in compliance with the License. You may obtain a copy of
|
||||
# the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations under
|
||||
# the License.
|
||||
#
|
||||
# ##############################################################################
|
||||
|
||||
add_subdirectory(src)
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
############################################################################
|
||||
# boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/Make.defs
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
# contributor license agreements. See the NOTICE file distributed with
|
||||
# this work for additional information regarding copyright ownership. The
|
||||
# ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
# "License"); you may not use this file except in compliance with the
|
||||
# License. You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations
|
||||
# under the License.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
include $(TOPDIR)/.config
|
||||
include $(TOPDIR)/tools/Config.mk
|
||||
include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs
|
||||
|
||||
LDSCRIPT = ld.script
|
||||
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
|
||||
|
||||
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
|
||||
|
||||
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
|
||||
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
|
||||
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
|
||||
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
|
||||
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
|
||||
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
|
||||
|
||||
NXFLATLDFLAGS1 = -r -d -warn-common
|
||||
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
|
||||
LDNXFLATFLAGS = -e main -s 2048
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
# ##############################################################################
|
||||
# boards/arm/stm32f0l0g0/stm32l0538-disco/CMakeLists.txt
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
|
||||
# license agreements. See the NOTICE file distributed with this work for
|
||||
# additional information regarding copyright ownership. The ASF licenses this
|
||||
# file to you under the Apache License, Version 2.0 (the "License"); you may not
|
||||
# use this file except in compliance with the License. You may obtain a copy of
|
||||
# the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations under
|
||||
# the License.
|
||||
#
|
||||
# ##############################################################################
|
||||
|
||||
add_subdirectory(src)
|
||||
Loading…
Add table
Add a link
Reference in a new issue