Make sure interrupt stack is colored before IRQ is enabled.
Currently, after calling irq_initialize in nx_start to
enable interrupts, there is still a period of execution
path before the interrupt stack is colored.
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
The current implementation does not call
nxsched_switch_context() exactly when a
task switch occurs.
This patch fixes the issue by placing the
call at the correct location.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Remove the comment which is copy-paste from stm32/stm32_eth.c.
stm3240g-eval doesn't contain any valuable information about eth driver.
If we need to find an explanation of the configuration options, they are in
Kconfig files.
Signed-off-by: raiden00pl <raiden00@railab.me>
clock_systime_timespec() always returns 0, so there is no need to
check the return value in the caller code, let us remove the return
value directly.
Signed-off-by: chao an <anchao.archer@bytedance.com>
E51 needs to use vendor specific CSR to enable L1 cache.
This adds the relevant register setting and makes it
configurable by CONFIG_MPFS_E51_ENABLE_CACHE. With this flag set, the L2
cache on E51 depends on the cache lane configuration. Disabling this flag
disables all caches on E51.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This adds a header file, defining microchip's vendor specific
CSR registers for E51 monitor core on MPFS SoC
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Incorrect FSM status checks in the suspend path could cause
deadlocks when power management was enabled. This patch fixes
the condition to allow proper UART suspend/resume handling.
Signed-off-by: Thiago Finelon <thiago.sfinelon@gmail.com>
Updates the common source code for the LEDC peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Add FLASH support for STM32C0 based on STM32G0 FLASH driver.
FLASH support is identical for these two, except that the STM32G0 can support
dual bank, which is not available in the STM32C0.
Signed-off-by: raiden00pl <raiden00@railab.me>
Updates the common source code for the SHA accelerator used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
PWR is not supported for STM32C0 yet, fix build error when CONFIG_STM32F0L0G0_PWR=y
which is required to access backup registers (we need enable PWR clock for this).
Signed-off-by: raiden00pl <raiden00@railab.me>
Updates the common source code for the GPIO peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
update STM32C0 PWR registers:
- there is no F,G,H and I GPIOs, so we can remove some registers
- add definitions for PWR backup registers
Signed-off-by: raiden00pl <raiden00@railab.me>
Updates the common source code for the PCNT peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Updates the common source code for the MCPWM peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Fix tricore running issue introduced by PR17060.
The bug is that when irq returns, the running_task was not
updated to the current task with highest priority from
the scheduler readytorun_list
Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>
After irq_dispatch finished, the interrupt stack will be checked to
determine whether overflow occurs.
The relevant configuration reuses the configuration of stack overflow
detection during context switching.
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
Many different architectures re-implemented the exact same code for
`up_*delay` because it was originally written as architecture dependent
code. Busy-waiting can be done regardless of architecture, so this
commit moves that duplicated implementation to a common file with weak
definitions so that individual architectures (see tc32) are still able
to override the definition if needed/desired.
Default implementation is not included if ARCH_TIMER is enabled, since
it is more accurate and provides its own weak definitions to override.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
A basic implementation of mailbox API with some helpers for accessing
properties implemented. Uses busy-wait due to documentation challenges
with mailbox API.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
Updates the common source code for the I2C peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Many times, context switching does not occur when the thread stack
memory is almost exhausted, so we need to mofify up_check_tcbstack to
accurately detect it.
Co-authored-by: Chengdong Wang <wangchengdong@lixiang.com>
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
Added ioctls and functions for watchdogs 2 & 3. Modifed wdog1 functions. Needs testing.
Fixed issues with started variable.
Change to add only 3 ioctls, a config for each watchdog. Created cfg structures for watchdog1 and watchdog23. Added code to set difsel register. stop conversions before changing watchdog configs. Other logic changes.
Define AN_STM32H5_FIRST and AN_STM32H5_NCMDS in nuttx/analog/ioctl.h
Remove hardcoded AN_STM32H5_FIRST.
Style fixes.
Fix thershold for watchdog1
Got working watchdog driver with queue and signal. Needs polish.
Refined isr for watchdogs. Added value back to event. value is more accurate, but not guaranteed. It accomdates dma.
Used stm32_adc_sigcfg_s structure inside stm32_adc_sig_s structure. Used common naming for ioctls.
Added stopifstarted and startifstopped for setting watchdogs and other bits. Added adc_reset_dma, which must be run after stopping conversions in circular mode, because buffer and conversions become misaligned. Other refinements.
Added guard around adc_reset_dma, added comment blocks to new functions
NuttX style fixes.
Add return value to wdog configure functions.
Correct number of stm32h5 adc ioctls.
Minor style fix.
Reduce watchdog commit to fit NuttX standards. Remove Queue and Signal aspects. Added Kconfig to initialize watchdog.
Signed-off-by: kywwilson11 <kwilson@2g-eng.com>
Added guard around code referencing priv->circular. Added adc_watchdog config for testing watchdog1 with adc1. Added documentation about adc_watchdog config.
Adjusted documentation for adc_watchdog config. Added detailed test procedure.
Longer underline under adc_watchdog title.
Add code for differential adc calibration. Need to calibrate both single-ended and differential if a given adc has both single-ended and differential channels.
Fixed typo.
Initialize watchdog1 parameters at compile time when configured. Added comments to new elements in stm32_dev_s. Confirmed style is good.
Add proper guards around ADC WDG1 variables and functions.
Implemented feedback per raiden00. 1. Changed to use old chanlist type uint8_t. 2. Added smpr1, smpr2, and difsel variables to stm32_dev_s structure. 2. smpr1 and smpr2 are initialized to board defined values if BOARD_ADCx_SMPRx is defined, otherwise initialized to default. 3. difsel initialized to BOARD_ADCx_DIFSEL if defined, otherwise use default (0) for all single-ended.
Complete the missing scheduling information in some architectures
In these architectures (riscv, avr, tricor) context switching
can occur in both up_switch_context and xx_doirq
Co-authored-by: yinshengkai <yinshengkai@xiaomi.com>
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
The arm-m architecture svc call will trigger an interrupt,
and the actual context switch is executed after doirq is completed,
so only the scheduling information needs to be updated in doirq.
In the arm-a/r architecture, interrupts and syscalls are independent,
and scheduling information needs to be updated in both locations
Co-authored-by: yinshengkai <yinshengkai@xiaomi.com>
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
Replace all nxsched_suspend/resume_*** with nxsched_switch_context
Delete nxsched_resume_scheduler in up_exit and call it uniformly in task_exit
Co-authored-by: yinshengkai <yinshengkai@xiaomi.com>
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
Currently the mdio communication is part of the monolithic 'full netdevs'.
This commit serves as an way to add modularity for the netdevs drivers.
A new upperhalf/lowerhalf mdio device comes with this commit that manages the data transfer ofer mdio interface.
Signed-off-by: Luchian Mihai <luchiann.mihai@gmail.com>
Updates the common source code for the UART peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Updates the common source code for the RMT peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Updates the common source code for the twai peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
- Created a file rp2040_common_pico.h with function
prototype
int rp2040_dev_gpio_init(void);
to allow cmake + ninja to build without errors.
- Updated file rp2040_pico.h with
for all boards.
Signed-off-by: simbit18 <simbit18@gmail.com>
- CMake added board Raspberry Pi Pico
- Added the entry:
CMake,raspberrypi-pico:bmp280
to the file arm-06.dat.
- Moved the search for the Python 3 interpreter to the
root CMakefile to avoid unnecessary repetition.
Signed-off-by: simbit18 <simbit18@gmail.com>
