Export qemu_rv_configure_mpu() and invoke it on the secondary-hart
boot path before riscv_cpu_boot().
This keeps protected SMP builds from faulting on !CPU0 when userspace
work is first scheduled there.
Signed-off-by: Shunchao Hu <ankohuu@gmail.com>
This is necessary because new defconfig were recently added to
Xtensa-based Espressif SoCs and the build job may exceed 2 hours.
In order to avoid increasing job timeout, a specific job for each
supported SoC (ESP32, ESP32-S2 and ESP32-S3) was created instead.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
This commit updates the common-source integration for Xtensa-based
Espressif devices (ESP32, ESP32-S2, and ESP32-S3). This is part of a larger
common-source update split by architecture for better maintainability.
Major components updated:
- IRQ allocator refactoring with intr_alloc integration
- Common-source drivers (GPIO, RMT, I2C, SPI, UART, etc.)
- Espressif components upgrade to release/master.b-test
- Peripheral drivers (ADC, PWM, LEDC, MCPWM, PCNT, Temperature Sensor, etc.)
- Wireless adapters (Wi-Fi and BLE)
- esp_timer migration to the common-source path for Xtensa devices
- Common-source power management implementation (auto-sleep and wakeup paths)
- Board defconfigs for all Xtensa Espressif boards
- SMP support improvements for ESP32-S3
- Critical section handling improvements
Key architectural changes:
- IRQ Allocator: The new interrupt allocator enables multiple mapping
options from interrupt sources to CPU interrupts, providing flexibility
required by modern peripherals. Although this introduces breaking changes
to the interrupt handling API, the required ARCH_MINIMAL_VECTORTABLE
Kconfig option is explicitly checked during startup to ensure proper
configuration. This validation prevents runtime issues from configuration
mismatches.
- Xtensa-specific interrupt handling via esp_xtensa_intr.c providing
NuttX-native implementations of xt_ints_on/off and interrupt handlers,
avoiding conflicts with NuttX's core Xtensa macros.
- Timer/RTC unification: ESP32/ESP32-S2/ESP32-S3 move from chip-specific
RTC/RT-timer code to common-source Espressif integration, including
esp_timer_adapter/esp_rtc paths and the required bringup/defconfig updates.
- Power management consolidation: Xtensa PM follows the common-source
implementation, including common-source auto-sleep behavior, UART/Wi-Fi
wakeup coordination, and tickless-safe sleep flow compatibility.
Note: This is a large commit to maintain bisectability. Breaking the
changes into smaller commits would result in non-building intermediate
states across the common-source infrastructure update.
Tested configurations:
- All defconfigs were tested, including `ostest`.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
This is necessary because new defconfig were recently added to
Xtensa-based Espressif SoCs and the build job may exceed 2 hours.
In order to avoid increasing job timeout, a specific job for each
supported SoC (ESP32, ESP32-S2 and ESP32-S3) was created instead.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Fixes the following compilation error.
stm32_gpio.c: In function 'stm32gpio_interrupt':
stm32_gpio.c:150:24: error: 'tm32gpint' undeclared (first use in
this function); did you mean 'stm32gpint'?
150 | tm32gpint->stm32gpio.id);
| ^~~~~~~~~
| stm32gpint
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
The definition of ADC channels should not depend on option
CONFIG_INPUT_AJOYSTICK at all. Moreover, the include of stm32l4_adc.h
file was missing (PWM include was used instead), causing the implicit
declaration of stm32l4_adc_initialize function.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Add rst documentation for the getevent tool under
Documentation/applications/graphics/input/. Content is placed
directly in index.rst following the existing convention used by
other graphics application docs.
Signed-off-by: liuhongchao <liuhongchao@xiaomi.com>
When a developer working on BSP wants UART1 with RTS, the following
needs to be added in the BSP's include/board.h file:
#define PIN_UART1_RTS PIN_UART1_RTS_1
which says that PIN_UART1_RTS_1 -- the first alternative pin with UART1
RTS function -- should be used for the UART1's RTS.
There are no alternative pins for PIN_UART2_RTS, therefore a similar
definition is not used for PIN_UART2_RTS.
However, that is a complication when we want PIN_UART2_RTS to be defined
as GPIO, for example:
#define PIN_UART2_RTS (GPIO_OUTPUT | PIN_PORTB | PIN2)
In such a case, PIN_UART2_RTS is later redefined to the only alternative
function from hardware/kinetis_???pinmux.h file.
This patch avoids the redefinition of already defined names.
We considered renaming PIN_UART2_RTS to PIN_UART2_RTS_1 in the
hardware/kinetis_???pinmux.h file, but that is breaking change. We try
to avoid breaking change.
Signed-off-by: Jiri Vlasak <jvlasak@elektroline.cz>
Because it is not needed anymore.
The original code here is from the initial implementation in the commit
66b873ef77.
Signed-off-by: Jiri Vlasak <jvlasak@elektroline.cz>
When using CONFIG_UART?_RS485CONTROL, RTS pin is set high when sending
data and low otherwise. PIN_UART?_RTS is defined in the board.h file as
the appropriate ALT functionality of the chip's port.
However, it may happen that PIN_UART?_RTS is wired to another pin of the
chip that does not support the RTS as ALT functionality of the UART? in
question. This commit addresses such a situation.
When UART?_RS485CONTROL_RTSISGPIO is set in menuconfig for the given
UART?, it is expected that the PIN_UART?_RTS is defined as GPIO_OUTPUT,
and the PIN_UART?_RTS is set high when sending data and low otherwise.
Signed-off-by: Jiri Vlasak <jvlasak@elektroline.cz>
Rename STM32_IRQ_NEXTINT to STM32_IRQ_NEXTINTS across all stm32
variants.
In stm32_dumpnvic() dynamically print NVIC enable and priority
registers based on STM32_IRQ_NEXTINTS.
Use PRIx32 format specifier instead of 'x' (since uint32_t on arm is
actually a long unsigned int).
Simplify if/else chain in stm32_irqinfo() to determine irq reg/bit.
There's no stm32_irqinfo.c; remove mention in stm32f0l0g0/Make.defs.
Signed-off-by Peter Barada <peter.barada@gmail.com>
When using a dummy memory address in DMA LLI transfers,
do not update the memory address.
Signed-off-by: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
Ignore unsupported telnet subnegotiation payload until `IAC SE` so
option bytes do not leak into the first NSH command.
Keep existing NAWS handling intact and also treat `IAC IAC` inside
subnegotiation payload as an escaped `0xFF` data byte rather than a
subnegotiation terminator.
This makes subnegotiation parsing RFC-compliant for both unsupported
options and NAWS payload processing.
Signed-off-by: Shunchao Hu <ankohuu@gmail.com>
Fix adc_oversample() where priv->trovs (a bool, 0 or 1) was OR'd
directly into setbits instead of using ADC_CFGR2_TROVS (bit 9).
This caused triggered oversampling to never actually be enabled.
Fix ANIOC_WDOG_UPPER and ANIOC_WDOG_LOWER ioctls where the TR1
register was overwritten with only the new threshold value, zeroing
out the opposite threshold and the AWDFILT digital filter bits.
Use read-modify-write to preserve the other fields.
Signed-off-by: kywwilson11 <kwilson@2g-eng.com>
Replace GPIO driver with userled driver for Pin 12 and 13 LEDs.
The red LED on Pin 14 remains as system LED.
- Add user LED definitions in board.h (BOARD_LED1, BOARD_LED2)
- Add k210_userleds.c implementing board_userled_* functions
- Remove k210_gpio.c (GPIO driver no longer needed)
- Update CMakeLists.txt and Makefile for userled build
- Update k210_bringup.c to initialize userled instead of GPIO
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
fix compilation warning:
group/group_foreachchild.c:85:10: warning: 'ret' may be used uninitialized [-Wmaybe-uninitialized]
85 | return ret;
| ^~~
group/group_foreachchild.c:67:7: note: 'ret' was declared here
67 | int ret;
Signed-off-by: raiden00pl <raiden00@railab.me>
Add detailed steps for copying nuttx.bin to eMMC via u-boot USB Mass
Storage (ums) mode, which exposes the eMMC as a USB drive on the host
PC for easy file transfer.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Add a dedicated emmc board configuration that enables USDHC1 8-bit
eMMC access with MBR/GPT partition table parsing, instead of polluting
the base nsh defconfig. This allows users to build and test eMMC
functionality with:
cmake -DBOARD_CONFIG=imx95-a55-evk/emmc
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Parse the partition table on /dev/mmcsd0 during board bringup and
register each partition as /dev/mmcsd0pN. MBR partitions have no
name field so a custom handler is needed instead of the default
register_partition which skips unnamed entries.
Verify by i.mx95 FRDM
'mount -t vfat /dev/mmcsd0p0 /data'
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
imx9_dmapreflight() rejected unaligned buffers unconditionally, but
dmarecvsetup() has a bounce path via priv->rxbuffer for small
transfers. Add a buflen > sizeof(priv->rxbuffer) check so that
small reads (e.g. ext_csd 512-byte stack buffer) can use the
bounce buffer instead of failing with -EFAULT.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Port USDHC1 (eMMC) driver to the i.MX95 FRDM EVK board:
- Create imx95_pinmux.h with SD1/USDHC1 pin definitions
- Add USDHC1 pin macros to board.h
- Create board-level imx9_usdhc.c glue code
- Update imx9_bringup.c with DMA allocator and USDHC init
- Add SCMI clock guards in imx9_usdhc.c (imx95 clock roots
are owned by System Manager, direct CCM writes are no-ops)
- Fix CCM_CR_USDHC2 copy-paste bug to CCM_CR_USDHC1
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Add imx95 GPIO register definitions (same IP block as imx93), fill
g_gpio_base[] array for imx95, include imx95_gpio.h from the common
header, and compile imx9_gpio.c/imx9_gpiobase.c for imx95 in cmake.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Rename IMX9_IRQ_uSDHC{1,2,3} to IMX9_IRQ_USDHC{1,2,3} in both arm
and arm64 imx95_irq.h to follow the all-caps naming convention used
by imx93_irq.h and the rest of the NuttX codebase. Remove the now
unnecessary USDHC IRQ alias block from arm64 imx95_irq.h.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
The MMC CMD6 bus width switch was gated on priv->buswidth which is
derived from the SD SCR register. For MMC cards this field is never
set (unless SDIO_CAPS_4BIT_ONLY), so the CMD6 was skipped while the
host PROCTL DTW was still changed - causing a bus width mismatch and
data transfer timeouts.
Fix by checking priv->caps instead of priv->buswidth for MMC cards.
Also select EXT_CSD_BUS_WIDTH_8 when host reports SDIO_CAPS_8BIT.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
