common/arm64_mpu.c:355:13: error: format '%llX' expects argument of type 'long long unsigned int', but argument 4 has type 'long unsigned int' [-Werror=format=]
355 | _info("MPU-%d, 0x%08llX-0x%08llX SH=%llX AP=%llX XN=%llX\n", i,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
common/arm64_mpu.c:355:29: note: format string is defined here
355 | _info("MPU-%d, 0x%08llX-0x%08llX SH=%llX AP=%llX XN=%llX\n", i,
| ~~~~~^
| |
| long long unsigned int
| %08lX
common/arm64_mpu.c:355:13: error: format '%llX' expects argument of type 'long long unsigned int', but argument 5 has type 'long unsigned int' [-Werror=format=]
355 | _info("MPU-%d, 0x%08llX-0x%08llX SH=%llX AP=%llX XN=%llX\n", i,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
common/arm64_mpu.c:355:38: note: format string is defined here
355 | _info("MPU-%d, 0x%08llX-0x%08llX SH=%llX AP=%llX XN=%llX\n", i,
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
1. add IS_ALIGNED() definitions for NuttX;
2. replace all the ALIGN_UP() and ALIGN_DOWN() to use common
align implementation;
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
When using alarm_arch implementation, 64-bit time can be returned. Using unsign long will cause precision loss.
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Summary:
- GICv2 cannot be detected on the golsfish platform
- Golsfish uses version 2.12.0 of qemu with a GICC_IIDR value of 0,
read ICPIDR2 to determine the GIC version
Signed-off-by: wangming9 <wangming9@xiaomi.com>
Summary:
1、cntfrq_el0 is used to store the timer frequency, which may
be different from the CPU frequency.
2、Do not use up_perf interface for SMP.
Signed-off-by: wangming9 <wangming9@xiaomi.com>
Some app with same code runs on different cores in AMP mode,
need the physical core on which the function is called.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
reason:
To remove the "sync pause" and decouple the critical section from the dependency on enabling interrupts,
after that we need to further implement "schedlock + spinlock".
changelist
1 Modify the implementation of critical sections to no longer involve enabling interrupts or handling synchronous pause events.
2 GIC_SMP_CPUCALL attach to pause handler to remove arch interface up_cpu_paused_restore up_cpu_paused_save
3 Completely remove up_cpu_pause, up_cpu_resume, up_cpu_paused, and up_cpu_pausereq
4 change up_cpu_pause_async to up_send_cpu_sgi
Signed-off-by: hujun5 <hujun5@xiaomi.com>
reason:
In the kernel, we are planning to remove all occurrences of up_cpu_pause as one of the steps to
simplify the implementation of critical sections. The goal is to enable spin_lock_irqsave to encapsulate critical sections,
thereby facilitating the replacement of critical sections(big lock) with smaller spin_lock_irqsave(small lock)
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Since FPU is now always saved into the current process stack location
upon exception entry, there is no need to keep fpu_regs (or saved_fpu_regs)
in the TCB.
Correct some of the cache operations:
- EP0 request length was handled incorrectly
- Received data cache invalidate was exceeding the received buffer
- writedtd is also called with no data (EP0 ACK/NACK). Don't touch cache in that case.
Fix trip wire handling to conform with the IMX93 reference manual
Also add DEBUGASSERTS for future to check the validity of pointers and sizes
Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
As the handling of sp_el0 was moved from the context switch routine
to exception entry/exit, we must set sp_el0 explicitly when the user
process is first started.
