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arch/arm64/src/imx9/imx9_usbdev.c: Clean up cache operations, add DEBUGASSERTS
Correct some of the cache operations: - EP0 request length was handled incorrectly - Received data cache invalidate was exceeding the received buffer - writedtd is also called with no data (EP0 ACK/NACK). Don't touch cache in that case. Fix trip wire handling to conform with the IMX93 reference manual Also add DEBUGASSERTS for future to check the validity of pointers and sizes Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This commit is contained in:
Jouni Ukkonen
Xiang Xiao
parent
534114395e
commit
9ea098558a
1 changed files with 60 additions and 33 deletions
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@ -60,7 +60,7 @@
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#endif
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#define DCACHE_LINEMASK (ARMV8A_DCACHE_LINESIZE - 1)
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#define DCACHE_ALIGN_UP(a) (((a) + DCACHE_LINEMASK) & ~DCACHE_LINEMASK)
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#if !defined(CONFIG_ARM64_DCACHE_DISABLE)
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# define cache_aligned_alloc(s) kmm_memalign(ARMV8A_DCACHE_LINESIZE,(s))
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# define CACHE_ALIGNED_DATA aligned_data(ARMV8A_DCACHE_LINESIZE)
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@ -69,6 +69,11 @@
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# define CACHE_ALIGNED_DATA
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#endif
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/* Check that both start and length are cache-aligned */
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#define IS_CACHE_ALIGNED(x,y) (((uintptr_t)(x) & DCACHE_LINEMASK) == 0 && \
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((y) & DCACHE_LINEMASK) == 0)
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/* Configuration ************************************************************/
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#ifndef CONFIG_USBDEV_EP0_MAXSIZE
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@ -218,6 +223,10 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] =
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};
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#endif
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/* Length of allocated EP0 buffer (DCACHE aligned) */
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#define EP0_MAXBUFLEN 64
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/* Hardware interface *******************************************************/
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/* This represents a Endpoint Transfer Descriptor dQH overlay (32 bytes) */
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@ -528,20 +537,20 @@ static int imx9_pullup(struct usbdev_s *dev, bool enable);
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*/
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#ifdef CONFIG_IMX9_USBDEV_USBC1
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static uint8_t g_usb0_ep0buf[64] CACHE_ALIGNED_DATA;
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static uint8_t g_usb0_ep0buf[EP0_MAXBUFLEN] CACHE_ALIGNED_DATA;
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static struct imx9_dqh_s g_usb0_qh[IMX9_NPHYSENDPOINTS] aligned_data(2048);
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static struct imx9_dtd_s g_usb0_td[IMX9_NPHYSENDPOINTS];
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#endif
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#ifdef CONFIG_IMX9_USBDEV_USBC2
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static uint8_t g_usb1_ep0buf[64] CACHE_ALIGNED_DATA;
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static uint8_t g_usb1_ep0buf[EP0_MAXBUFLEN] CACHE_ALIGNED_DATA;
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static struct imx9_dqh_s g_usb1_qh[IMX9_NPHYSENDPOINTS] aligned_data(2048);
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static struct imx9_dtd_s g_usb1_td[IMX9_NPHYSENDPOINTS];
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#endif
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static struct imx9_usb_s g_usbdev[] =
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{
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#ifdef CONFIG_IMX9_USBDEV_USBC1
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#ifdef CONFIG_IMX9_USBDEV_USBC1
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{
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.id = 0,
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.base = IMX9_USB_OTG1_BASE,
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@ -692,10 +701,7 @@ static void imx9_putreg(struct imx9_usb_s *priv, off_t offset, uint32_t val)
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static inline void imx9_modifyreg(struct imx9_usb_s *priv, off_t offset,
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uint32_t clear, uint32_t set)
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{
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uint32_t reg = imx9_getreg(priv, offset);
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reg &= ~clear;
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reg |= set;
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imx9_putreg(priv, offset, reg);
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modifyreg32(priv->base + offset, clear, set);
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}
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/****************************************************************************
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@ -764,6 +770,8 @@ static inline void imx9_writedtd(struct imx9_dtd_s *dtd,
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const uint8_t *data,
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uint32_t nbytes)
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{
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DEBUGASSERT(IS_CACHE_ALIGNED(dtd, sizeof(*dtd)));
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dtd->nextdesc = DTD_NEXTDESC_INVALID;
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dtd->config = DTD_CONFIG_LENGTH(nbytes) | DTD_CONFIG_IOC |
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DTD_CONFIG_ACTIVE;
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@ -776,8 +784,18 @@ static inline void imx9_writedtd(struct imx9_dtd_s *dtd,
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up_clean_dcache((uintptr_t)dtd,
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(uintptr_t)dtd + sizeof(struct imx9_dtd_s));
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up_clean_dcache((uintptr_t)data,
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(uintptr_t)data + nbytes);
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/* the pointer is NULL for EP0 NAK IN/OUT */
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if (data != NULL)
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{
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DEBUGASSERT(IS_CACHE_ALIGNED(data, DCACHE_ALIGN_UP(nbytes)));
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DEBUGASSERT(nbytes <= 0x5000);
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/* Data needs to be clean before TX, clean or invalid before RX */
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up_clean_dcache((uintptr_t)data, (uintptr_t)data + nbytes);
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}
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}
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/****************************************************************************
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@ -803,7 +821,7 @@ static void imx9_queuedtd(struct imx9_usb_s *priv, uint8_t epphy,
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dqh->overlay.nextdesc = (uint32_t)(uintptr_t)dtd;
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dqh->overlay.config &= ~(DTD_CONFIG_ACTIVE | DTD_CONFIG_HALTED);
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up_flush_dcache((uintptr_t)dqh,
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up_clean_dcache((uintptr_t)dqh,
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(uintptr_t)dqh + sizeof(struct imx9_dqh_s));
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uint32_t bit = IMX9_ENDPTMASK(epphy);
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@ -845,21 +863,20 @@ static void imx9_readsetup(struct imx9_usb_s *priv, uint8_t epphy,
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struct imx9_dqh_s *dqh = &priv->qh[epphy];
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int i;
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do
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/* Set the trip wire */
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imx9_modifyreg(priv, IMX9_USBDEV_USBCMD_OFFSET, 0, USBDEV_USBCMD_SUTW);
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ARM64_DSB();
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DEBUGASSERT(IS_CACHE_ALIGNED(dqh, sizeof(struct imx9_dqh_s)));
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up_invalidate_dcache((uintptr_t)dqh,
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(uintptr_t)dqh + sizeof(struct imx9_dqh_s));
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/* Copy the request... */
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for (i = 0; i < 8; i++)
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{
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/* Set the trip wire */
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imx9_modifyreg(priv, IMX9_USBDEV_USBCMD_OFFSET, 0, USBDEV_USBCMD_SUTW);
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up_invalidate_dcache((uintptr_t)dqh,
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(uintptr_t)dqh + sizeof(struct imx9_dqh_s));
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/* Copy the request... */
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for (i = 0; i < 8; i++)
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{
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((uint8_t *) ctrl)[i] = ((uint8_t *) dqh->setup)[i];
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}
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((uint8_t *) ctrl)[i] = ((uint8_t *) dqh->setup)[i];
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}
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while (!(imx9_getreg(priv,
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@ -869,13 +886,11 @@ static void imx9_readsetup(struct imx9_usb_s *priv, uint8_t epphy,
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imx9_modifyreg(priv, IMX9_USBDEV_USBCMD_OFFSET, USBDEV_USBCMD_SUTW, 0);
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up_clean_dcache((uintptr_t)dqh,
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(uintptr_t)dqh + sizeof(struct imx9_dqh_s));
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/* Clear the Setup Interrupt */
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imx9_putreg(priv, IMX9_USBDEV_ENDPTSETUPSTAT_OFFSET,
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IMX9_ENDPTMASK(IMX9_EP0_OUT));
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ARM64_DSB();
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}
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/****************************************************************************
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@ -1120,8 +1135,9 @@ static void imx9_dispatchrequest(struct imx9_usb_s *priv,
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{
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/* Invalidate buffer data cache */
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DEBUGASSERT(IS_CACHE_ALIGNED(priv->ep0.buf, EP0_MAXBUFLEN));
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up_invalidate_dcache((uintptr_t)priv->ep0.buf,
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(uintptr_t)priv->ep0.buf + sizeof(priv->ep0.buf));
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(uintptr_t)priv->ep0.buf + EP0_MAXBUFLEN);
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/* Forward to the control request to the class driver implementation */
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@ -1162,7 +1178,7 @@ static void imx9_ep0configure(struct imx9_usb_s *priv)
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priv->qh[IMX9_EP0_IN].currdesc = DTD_NEXTDESC_INVALID;
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up_clean_dcache((uintptr_t)priv->qh,
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(uintptr_t)priv->qh + (sizeof(struct imx9_dqh_s) * 2));
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(uintptr_t)priv->qh + (sizeof(struct imx9_dqh_s)));
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/* Enable EP0 */
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@ -1303,6 +1319,8 @@ static inline void imx9_ep0state(struct imx9_usb_s *priv,
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imx9_putreg(priv, IMX9_USBDEV_ENDPTNAKEN_OFFSET, 0);
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break;
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}
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ARM64_DSB();
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}
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/****************************************************************************
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@ -1347,7 +1365,9 @@ static inline void imx9_ep0setup(struct imx9_usb_s *priv)
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index = GETUINT16(ctrl->index);
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len = GETUINT16(ctrl->len);
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priv->ep0.buf_len = len;
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/* Limit the ep0 length to maximum */
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priv->ep0.buf_len = len <= EP0_MAXBUFLEN ? len : EP0_MAXBUFLEN;
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uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
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ctrl->type, ctrl->req, value, index, len);
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@ -1868,10 +1888,9 @@ bool imx9_epcomplete(struct imx9_usb_s *priv, uint8_t epphy)
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/* Make sure we have updated data after the DMA transfer. */
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DEBUGASSERT(IS_CACHE_ALIGNED(dtd, sizeof(struct imx9_dtd_s)));
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up_invalidate_dcache((uintptr_t)dtd,
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(uintptr_t)dtd + sizeof(struct imx9_dtd_s));
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up_invalidate_dcache((uintptr_t)dtd->buffer0,
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(uintptr_t)dtd->buffer0 + dtd->xfer_len);
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int xfrd = dtd->xfer_len - (dtd->config >> 16);
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@ -1885,6 +1904,14 @@ bool imx9_epcomplete(struct imx9_usb_s *priv, uint8_t epphy)
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*/
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usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_EPIN), complete);
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/* Invalidate rx buffer cache */
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DEBUGASSERT(IS_CACHE_ALIGNED(privreq->req.buf,
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DCACHE_ALIGN_UP(privreq->req.xfrd)));
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up_invalidate_dcache((uintptr_t)privreq->req.buf,
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(uintptr_t)privreq->req.buf +
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DCACHE_ALIGN_UP(privreq->req.xfrd));
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}
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else
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{
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