The GreenHills Compiler uses Unified Assembler Language by default and
it does not recognize .syntax unified instruction. Therefore, remove
them if GHS compiler is used.
Co-authored-by: Chengdong Wang <wangchengdong@lixiang.com>
Signed-off-by: xiezhanpeng3 <xiezhanpeng3@lixiang.com>
The GreenHills Compiler uses different grammer for the .type directive
in asm, this patch adds support for the grammer for arm-v8r.
Similar change for arm-v7r was done in pull request #12883.
Co-authored-by: Chengdong Wang <wangchengdong@lixiang.com>
Signed-off-by: xiezhanpeng3 <xiezhanpeng3@lixiang.com>
We found that specific chip pin definitions were used in the generic UART source file. Since pin definitions vary across different chips, the UART pin definitions have been moved to the corresponding chip-specific directory.
Co-authored-by: Chengdong Wang <wangchengdong@lixiang.com>
Signed-off-by: Qinshuo Duan <duanqinshuo@lixiang.com>
1. up_irq_save should not mask fiq if CONFIG_ARCH_HIPRI_INTERRUPT=y
2. up_irq_save should mask fiq if CONFIG_ARCH_TRUSTZONE_SECURE=y
3. up_irq_save should mask irq if CONFIG_ARCH_TRUSTZONE_SECURE=n
4. add up_secure_irq in arm64
5. add ARCH_HAVE_TRUSTZONE support for ARCH_CORTEX_R82
Signed-off-by: hujun5 <hujun5@xiaomi.com>
MTDIOC_RESET ioctl command executes "Reset Enable" and "Reset Memory"
commands to enter a power-on reset condition.
Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
Fix a transfer issue in the Kinetis DSPI driver when operating
with transmit and receive FIFOs disabled (`MCR[DIS_TXF]=1`,
`MCR[DIS_RXF]=1`). In this mode, the DSPI module behaves as a
simple double-buffered SPI interface without TX staging.
When FIFOs are disabled, `PUSHR` acts as a single 32-bit
command/data register. Partial (16-bit) writes to its upper or
lower halves can result in incomplete or corrupted transfers.
This patch ensures the full 32-bit packet is prepared and
written in a single operation.
* Resolves broken SPI transactions with LAN9252 (EasyCAT).
* Improves reliability in non-FIFO DSPI configurations.
* No impact on DMA or FIFO-enabled modes.
Signed-off-by: trns1997 <trns1997@gmail.com>
In MSS CAN transmit function, the check of net pkt data len is not neccessary. Since there are cases that the pkt len can exceed the expected 16 bytes of can_frame but the pkt is still valid. Such a case is when CONFIG_NET_CAN_RAW_TX_DEADLINE is enabled which has pkt len to become 32 bytes due to cmsghdr overhead.
Signed-off-by: haitomatic <hai.to@unikie.com>
Introduces a very basic frame buffer driver implementation for the RPi4B
which is registered at startup and works with frame buffer graphics
examples (and LVGL). Graphics are displayed on the HDMI0 and HDMI1
output, depending which one is plugged into the display. I have not
tested using both at once, nor does the driver account for that. They
are both referred to as display 0, plane 0 since the RPi4B frame buffer
interface does not seem to have a way of distinguishing.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
Gdbstub demo::
The Qemu version must be above 9.2 to support two serial ports.
One window:
./tools/configure.sh qemu-armv8a:gdbstub; make -j25
qemu-system-aarch64 -cpu cortex-a53 -nographic -machine virt,virtualization=on,gic-version=3 -net none -kernel ./nuttx -serial mon:stdio -serial pty
char device redirected to /dev/pts/27 (label serial1)
- Ready to Boot Primary CPU
- Boot from EL2
- Boot from EL1
- Boot to C runtime for OS Initialize
Another window:
gdb-multiarch nuttx -ex "target remot /dev/pts/27"
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There is NO WARRANTY, to the extent permitted by law.
Type "show copying" and "show warranty" for details.
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Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<https://www.gnu.org/software/gdb/bugs/>.
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Reading symbols from nuttx...
Remote debugging using /dev/pts/26
gdb_get_registers (state=0x403e1590) at gdbstub/lib_gdbstub.c:1020
1020 reg = state->running_regs;
(gdb) c
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Replace the spinlock/sched_lock pair in xtensa/esp32s2 with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in xtensa/esp32 with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in renesas/rx65n with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in arm64/imx9 with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in arm/stm32 with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in arm/sam34 with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in arm/s32k3xx with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in arm/s32k1xx with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in arm/kinetis with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in arm/imx9 with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
The Nuttx MSS CAN driver has an exclusive interface to the integrated MSS CAN peripheral residing in Polarfire SoC FPGAs. There are two CAN block 0 and 1 that can be configured for use. In normal mode (non AMP), CAN0 and CAN1 block base register addresses are 0x2010C000UL and 0x2010D000UL.
Signed-off-by: Hai To <hai.to@tii.ae>
By default, the full configured DTCM region is assigned to the heap for
dynamic allocation. In scenarios requiring deterministic memory regions
for static buffers or control structures, you can reduce the heap
allocation to reserve part of DTCM for manual/static use.
This kconfig symbol allows to limit the size.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Updates the SPI Flash driver used for user storage MTD.
Moves ESP32 and ESP32S3 to use common driver.
Updates KConfig options to keep backwards compatibility.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Updates the SPI Flash driver used for user storage MTD.
Updates board linker script and bring up.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
The adc_dmaconvcallback routine was far too slow and inefficient. This was not caught until recently when I was testing faster sample rates. When in circular mode for the adc (dma and constant conversions), the adc_dmaconvcallback function would overwhelm the OS and lock it up. I looked into this and did a lot of testing. First I tried minimally improving the dma callback by removing the % operator from the algorithm, this was slow and inefficient. I also tried increasing the batch size considerably as well as the fifo size. This helped but the OS would still lockup with the fastest sample rate (5 Msps). au_receive_batch was the solution. In order to use this, I needed to change the dmabuffer to be of type uint32_t to match the data pointer in au_receive_batch. I also needed to create a channel buffer, which is initialized once in adc_setup. stm32_gpdma_cfg_s->tr1 needed to be updated for the uint32_t dmabuffer. Once I made changes to use au_receive_batch, I could reliably use the fastest sample rate without locking up the OS. Calling au_receive for every single conversion in a batch is far less efficient than calling au_receive_batch. I also snuck in some changes for the ADC watchdog defines and guards. These were fixes that were tested while testing these changes.
Signed-off-by: kywwilson11 <kwilson@2g-eng.com>
This initial implementation sets up support for the EMMC interfaces on
the BCM2711. Only EMMC2 is tested since it is the interface of interest
(connects to uSD card). MMCSD communication is functional and the boot
partition of the SD card can be mounted and interacted with.
Insertion/removal interrupts do not fire after initial boot, and
sdstress fails with any byte size larger than 1023. 32GB card works
perfectly, while 64GB card exhibits strange behaviour when interacting
with VFAT filesystem.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
This function can identify (during the runtime) whether the chip
is revB or revA. Bear in mind PIC32CZ2051CA70 is always revB.
Allows to have one binary compatible with SAMV7 and PIC32.
Thanks to Pavel Pisa and Michal Lenc for the suggested code.
Signed-off-by: Stepan Pressl <pressl.stepan@gmail.com>
Previously the function "up_cpu_pause" was used for preventing all other
CPUs from executing code from flash.
The above function was removed in d8cb7759.
Now flash operations work on rp2040 in SMP mode by blocking all but the
current CPU for the duration of the critical function (write or erase).
Closes: #16203
Signed-off-by: Lars Kruse <devel@sumpfralle.de>
Adding the stm32h5 pwm driver. This is almost an exact copy of the stm32h7 pwm driver. I confirmed the timers for the h5 are version v2 and added the preprocessor definition. This commit was tested on a stm32h5 nucleo-h563zi development board. Necessary board files and a pwm config have been added. Added pin mappings for all timer outputs.
Signed-off-by: kywwilson11 <kwilson@2g-eng.com>
Added documentation regarding nucleo-h563zi:pwm config.
Removed CONFIG_STM32H5_PWM guard at the top. Fixed IRQs for tim1 and tim8. Added H5 to list of Timer IP v2 timers.
Conditionally compile stm32_serial.c.
Add stm32_pwm.c to CMakeLists.txt
Curently, the driver code for HW accelerated AES is not usable
since it's not registered within esp32_crypto. This commit fixes
it as well as a few bugs.
Signed-off-by: Vlad Pruteanu <pruteanuvlad1611@yahoo.com>
Fix exception issue when PM and DEBUG_ASSERTIONS enabled for esp32 and esp32s3.
This error happens due to PM system workflow, when system gets into sleep-modes with
removing PM_NORMAL count, system is raising an exception for not having
enough number of PM_NORMAL state count if DEBUG_ASSERTIONS enabled.
Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
When closing a serial port an ongoing TX DMA transfer will be stopped. This can cause
one (or multiple) the following:
- dev->dmatx.length != 0
- dev->dmatx.nlength != 0
- stm32_dmaresidual returning a non-zero residual
This is caused by length/nlength not being set to 0 at startup or during closing.
In addition the DMA_SxNDTR register is not set to 0 at startup or during closing.
This commit solves the issue by setting the variables and register to 0 during closing.
Signed-off-by: Alexander Lerach <alexander@auterion.com>
arch/arm/stm32h7: Add review feedback regarding style
Removed non-needed spaces.
Aligned style of documentation.
Signed-off-by: Alexander Lerach <alexander@auterion.com>
The nxsched_switch_context() function should only be called
when a task switch actually occurs. The RISC-V architecture
already performs this call in riscv_perform_syscall(),
so this PR removed the redundant nxsched_switch_context() call in
up_switch_context().
Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>
Updates the common source code for the SPI peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
This commit refactors the I2S common driver for Espressif's RISC-V
SoCs. Previously, the peripheral was not working as expected.
Along with the new I2S character driver, this new I2S lower-half
driver can be easily tested using internal loopback between the
transmitter and receiver channels.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Adds Kconfig knobs for the ESP32-S3 RX FIFO full threshold and timeout and wires them into the UART driver.
Clears RX FIFO overflow interrupts by resetting the hardware FIFO so reception resumes cleanly.
Signed-off-by: Thiago Finelon <thiago.sfinelon@gmail.com>
Nuttx currently has 2 types of sleep interfaces:
1. Signal-scheduled sleep: nxsig_sleep() / nxsig_usleep() / nxsig_nanosleep()
Weaknesses:
a. Signal-dependent: The signal-scheduled sleep method is bound to the signal framework, while some driver sleep operations do not depend on signals.
b. Timespec conversion: Signal-scheduled sleep involves timespec conversion, which has a significant impact on performance.
2. Busy sleep: up_mdelay() / up_udelay()
Weaknesses:
a. Does not actively trigger scheduling, occupy the CPU loading.
3. New interfaces: Scheduled sleep: nxsched_sleep() / nxsched_usleep() / nxsched_msleep() / nxsched_ticksleep()
Strengths:
a. Does not depend on the signal framework.
b. Tick-based, without additional computational overhead.
Currently, the Nuttx driver framework extensively uses nxsig_* interfaces. However, the driver does not need to rely on signals or timespec conversion.
Therefore, a new set of APIs is added to reduce dependencies on other modules.
(This PR also aims to make signals optional, further reducing the code size of Nuttx.)
Signed-off-by: chao an <anchao.archer@bytedance.com>
