PIC(Position-Independent-Code) board could work on cmake:
cmake -B ap -DBOARD_CONFIG=mps3-an547:ap -GNinja
Signed-off-by: chao an <anchao.archer@bytedance.com>
What's really need is a done signal sent from the secondary
cpu to the boot cpu, so let's simplify the logic by:
1.Change the spinlock to a bool flag
2.Set the flag to true in the secondary cpu
3.Wait the flag set in the boot cpu before continue booting
This also remove all bad usage of spinlock from the code base:
1.Lock spinlock in one thread, but unlock in a different thread
2.Lock spinlock twice in one thread, but unlock only once
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
So far only USART drivers could use TX/RX DMA. This commit adds the
support for UART drivers as well (with the exception of serial console).
UART peripheral does not have timeout interrupt, so external polling
is required to flush the RX data from DMA buffers even if the buffer
is not yet full. The board layer can do this by calling
sam_serial_dma_poll function.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Progress in USB driver
Nothing is working yet. But just getting this in here so it is saved.
Minor changes with USB power enabled
Serial over USB is working now.
Removed stm32_usbdev.c, added stm32_usbfs.c. Still needs review before pull-request.
Rewrote VDDUSB valid check to use register definitions. Wait for USB33RDY before moving on. Also style updates.
Renamed stm32_usbdev files to stm32_usbfs. Renamed STM32H5 configuration options from STM32H5_USB to STM32H5_USBFS. Properly named REGDEBUG defines. Added STM32H5_USB_REGDEBUG to Kconfig and updated stm32_usbfs.c to use it. TRACE functionality still needs work.
Updated REGDEBUG for 32-bit register accesses.
More style updates.
Added usbnsh defconfig to nucleo-h563zi
Update to allow 16 buffers (max for 8 endpoints). Renamed lpinterrupt and lptransfer. Changed board.h to use SYNCSRC_USB only if USB is enabled.
Buffer size is still set to max packet size of 64 bytes, because we are using a full-speed peripheral. It is unclear to me whether having a buffer larger than the max packet size has any benefit. Double buffering is a way to increase throughput, though that still needs to be implemented.
Adapted USBFS Buffer table for 32-bit accesses.
Style updates
Build stm32_hsi48.c based on CONFIG_STM32H5_HAVE_HSI48.
Change LPMODE CNTR bit to SUSPRDY.
fix smp crash on sabre-6quad/smp, regression from:
|commit 1e49cb4828
|Author: hujun5 <hujun5@xiaomi.com>
|Date: Thu Dec 5 16:58:17 2024 +0800
|
| armv7-a/armv7-r/armv8-r: percpu reg store this_task
|
| This is continue work of https://github.com/apache/nuttx/pull/13726
|
| We can utilize percpu storage to hold information about the
| current running task. If we intend to implement this feature, we would
| need to define two macros that help us manage this percpu information
| effectively.
|
| up_this_task: This macro is designed to read the contents of the percpu
| register to retrieve information about the current
| running task.This allows us to quickly access
| task-specific data without having to disable interrupts,
| access global variables and obtain the current cpu index.
|
| up_update_task: This macro is responsible for updating the contents of
| the percpu register.It is typically called during
| initialization or when a context switch occurs to ensure
| that the percpu register reflects the information of the
| newly running task.
|
| Signed-off-by: hujun5 <hujun5@xiaomi.com>
Signed-off-by: chao an <anchao.archer@bytedance.com>
ADC peripheral can be configured also for PWM trigger, so the ifdef
should depend only on CONFIG_SAMV7_AFEC_SWTRIG. Also handle the
situation when ANIOC_TRIGGER is called and the peripheral is not
configured for SW trigger (but the other one may be, so config option
is set).
Trigger values saved to the private structure are also changed to
enums for better code clarity.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This follows the formula in the "Startup Delay" section of the
datasheets, where `BOARD_XOSC_STARTUPDELAY` is the time in milliseconds,
which is then multiplied by the clock fequency in kHz, divided by 256
cycles, and rounded up.
This differs from `pico-sdk`, which just multiplied the value of the
expression it previously used by a `PICO_XOSC_STARTUP_DELAY_MULTIPLIER`.
This seems less correct, though it should be essentially the same except
rounding. (`BOARD_XOSC_STARTUPDELAY_MULTIPLIER` also wouldn't fit nicely
the way the `#define`s are aligned.)
This sets `BOARD_XOSC_STARTUPDELAY` to `1` for all boards, so this will
produce the same output and not change behavior.
Signed-off-by: Ian Douglas Scott <ian@iandouglasscott.com>
Previously this used a hard-coded value of 12 MHz, but this presumably
should use `BOARD_XOSC_FREQ`. Similarly to how it is done in pico-sdk.
It looks like all boards are currently defined to use 12 MHz XOSC
clocks, so this won't change behavior with any of them.
Signed-off-by: Ian Douglas Scott <ian@iandouglasscott.com>
This adds support for QEMU Cortex-R5 virtual processor on existing QEMU
Cortex-A7 code base with profile support in `armv7-r/` and `armv7-a/`.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
This revise armv7-r/ header files needed to support QEMU cortex-r5
virtual process for armv7-r family.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
This fixes compilation error:
```
/tmp/nuttx/arch/arm/src/armv7-r/gic.h:699:17: error:
'GIC_ICDSGIR_NSATT_GRP1' undeclared; did you mean 'GIC_ICDSGIR_NSATT'?
```
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
copied over files, not modified properly yet
Squashing lots of define errors to get ethernet.c working
quick path rename
Fix STM32_EMAC_BASE (and ICACHE/DCACHE Bases). Enable ETH, ETHTX, and ETHRX with CONFIG_STM32H5_ETHMAC (like H7 does).
Fixed stm32_get_uniqueid
Previously, an exception occurred as a result of calling this function. The problem turned out to be this line: uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i);. Dereferencing a 32-bit register as a 8-bit register seemed to be causing this issue. I think this function is better anyway, fewer register accesses and loop iterations.
Turn on SBS peripheral when using Ethernet
The SBS peripheral is required to be turned on because the ETH_SEL_PHY bits need to be set. Without turning this on, RMII mode is not possible. MII may not work either.
Style Updates
This moves ARM_HAVE_PSCI selection to virtual processor level as
armv7-r chips like Cortex-R5 doesn't have it.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
reason:
We decouple semcount from business logic
by using an independent counting variable,
which allows us to remove critical sections in many cases.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
reason:
In kernel mode, sighand_test() may failed.
because nxsig_unmask_pendingsignal may change tcb->xcp.regs,and we should update return value(regs).
Signed-off-by: hujun5 <hujun5@xiaomi.com>
This moves ARM_HAVE_NEON from QEMU ARM family level down to the
processor level as not all processors have it (e.g. Cortex R5).
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
It was dis overed during debug of the ethernet driver that the EMAC base was incorrect. After examination, it was determined that ICACHE and DCACHE also had incorrect base addresses. This commit fixes the base addresses according to the reference manual.
Sumamry:
Adjust VIRT_FLASH_PSECTION from 0x00000000-0x08000000 -> 0x00600000-0x08000000
The above changes avoid the problem of directly restarting when the process accesses/executes at address 0x0 without causing assert
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
It will be used to distinguish between hardware KASan and software KASan. Hardware KASan does not need to use plug-in
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
| commit c96b8cdfdd
| Author: hujun5 <hujun5@xiaomi.com>
| Date: Mon Dec 23 16:59:20 2024 +0800
|
| use small lock in following files:
Signed-off-by: chao an <anchao.archer@bytedance.com>
reason:
In AMP mode, we can also use SGI as an inter-core interrupt,
and ensure that arm_gic0_initialize is called only once.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Added support for using timers with ADCs. Updated Kconfig to support TRGO2, although driver support for TRGO and TRGO2 not developed yet. Updated hardware/stm32_tim.h with missing CCER bits needed for compilation.
