imx9_dmapreflight() rejected unaligned buffers unconditionally, but
dmarecvsetup() has a bounce path via priv->rxbuffer for small
transfers. Add a buflen > sizeof(priv->rxbuffer) check so that
small reads (e.g. ext_csd 512-byte stack buffer) can use the
bounce buffer instead of failing with -EFAULT.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Port USDHC1 (eMMC) driver to the i.MX95 FRDM EVK board:
- Create imx95_pinmux.h with SD1/USDHC1 pin definitions
- Add USDHC1 pin macros to board.h
- Create board-level imx9_usdhc.c glue code
- Update imx9_bringup.c with DMA allocator and USDHC init
- Add SCMI clock guards in imx9_usdhc.c (imx95 clock roots
are owned by System Manager, direct CCM writes are no-ops)
- Fix CCM_CR_USDHC2 copy-paste bug to CCM_CR_USDHC1
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Add imx95 GPIO register definitions (same IP block as imx93), fill
g_gpio_base[] array for imx95, include imx95_gpio.h from the common
header, and compile imx9_gpio.c/imx9_gpiobase.c for imx95 in cmake.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Rename IMX9_IRQ_uSDHC{1,2,3} to IMX9_IRQ_USDHC{1,2,3} in both arm
and arm64 imx95_irq.h to follow the all-caps naming convention used
by imx93_irq.h and the rest of the NuttX codebase. Remove the now
unnecessary USDHC IRQ alias block from arm64 imx95_irq.h.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
arm64_modifyreg8.c, arm64_modifyreg16.c, arm64_modifyreg32.c were
present in Make.defs but missing from CMakeLists.txt, causing link
errors when building with cmake.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Correct duplicate "is is" word found in 181 files throughout the
codebase.
In most cases "is is" was changed to "is", but in contexts like
"MCU is is sleep mode" it was corrected to "MCU in sleep mode".
Also fixes a "the the" typo in net/inet/inet_sockif.c.
This is a pure style/documentation fix that improves code readability.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Fix 269 occurrences of duplicate "the" word typo found in 209 files
across source code, header files, and configuration.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Remove the CONFIG_K210_WITH_QEMU option and associated conditional
code paths. The reasons for removal are:
* Simplifies code path for real hardware by removing QEMU workarounds
* The current QEMU target uses sifive_u machine, which is not designed
for K210 emulation
* For RISC-V QEMU simulation, the qemu-rv (rv-virt) target is a better
choice
* Renode can be used as an alternative for K210 simulation if needed
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Fix duplicate watchdog prompts in Kconfig by using unique WDOG0, WDOG1,
WDOG2 names instead of generic 'watchdog' label. This matches the UART
peripheral naming convention in the same file and makes it clear which
watchdog is being configured in menuconfig.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Add WDT driver for K210 with support for both WDT0 and WDT1 peripherals.
This includes:
- Add k210_wdt.c and k210_wdt.h driver files with interrupt-based
watchdog timer functionality
- Add hardware register definitions in k210_wdt.h
- Add K210_WDT, K210_WDT0, K210_WDT1 Kconfig options
- Add memory map definitions for WDT0 (0x50400000) and WDT1 (0x50410000)
- Reorder WDT IRQ definitions (IRQ 21, 22) before UART0 (IRQ 33) in irq.h
- Add WDT initialization in board bringup for maix-bit
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Add ESP32-S3 CAM controller driver implementing the NuttX imgdata
interface. Supports 8-bit DVP camera input with DMA-based frame
capture, VSYNC interrupt handling, and PSRAM frame buffer allocation.
The driver is sensor-agnostic: resolution and pixel format are
negotiated at runtime through the V4L2 pipeline. XCLK output
(24 MHz) is started during initialization for sensor communication.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Add sysctl driver for K210 SoC providing clock and reset control:
- Clock enable/disable with two-stage APB/peripheral enable pattern
- Peripheral reset control with proper timing
- Clock frequency query for PLL, CPU, APB buses, and peripherals
- PLL frequency calculation and CPU frequency configuration
The sysctl driver is built unconditionally for K210 boards as it
provides essential clock and reset control functionality.
Add Kconfig option:
- K210_CPU_FREQ: Target CPU frequency in Hz (default 400MHz)
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Add nxboot bootloader board integration for nucleo-h743zi.
nxboot uses a three-slot layout (primary, secondary, tertiary) with
no scratch partition.
- add STM32_APP_FORMAT_NXBOOT board support and nxboot-specific OTA
slot defaults
- gate scratch partition configuration on MCUboot, where it applies
- select nxboot linker scripts in the board build logic
- add tertiary OTA partition support in stm32_progmem.c
- add nxboot-loader and nxboot-app defconfigs and linker scripts
- validate the fixed nxboot flash layout used by this board so
mismatched config values fail at build time instead of producing
a silently broken image
Signed-off-by: Neil Berkman <neil@xuku.com>
Three fixes to make LPUART1 work as NSH console on Nucleo-L552ZE-Q:
1. stm32l5_lowputc: add LPUART-specific BRR formula (256 * fCK / baud)
instead of reusing the standard USART divisor calculation.
2. stm32_boot: enable VDDIO2 and reconfigure LPUART1 GPIOs (PG7/PG8)
in board_initialize. The low-level setup runs before VDDIO2 is
enabled, so GPIOG writes silently fail.
3. stm32l5_serial: fix LPUART1 apbclock (PCLK1 not PCLK2), add
LPUART BRR branch in setformat, cast to uint64_t to prevent
32-bit overflow in (fCK << 8).
Also switch nsh defconfig from USART3 to LPUART1, add GPIO_LPUART1
pin definitions in board.h, and update board documentation.
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
This PR fixes a typo at `--help--` that causes NuttX Builds to fail, it should have been `---help---`. This is a recurring problem, NuttX CI uses a different way of handling NuttX Configs (it doesn't use `tools/configure.sh`)
https://github.com/lupyuen/nuttx-riscv64/actions/runs/22929878852/job/66548808341#step:5:161
```
$ tools/configure.sh rv-virt:nsh
arch/tricore/Kconfig:124: syntax error
arch/tricore/Kconfig:123: unknown option "--help--"
arch/tricore/Kconfig:124:warning: ignoring unsupported character ','
arch/tricore/Kconfig:124: unknown option "In"
```
Signed-off-by: Lup Yuen Lee <luppy@appkaki.com>
This commit adds support for the Espressif's RISC-V-based ESP32-P4
chip along with its ESP32-P4-Function-EV-Board board.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
* Fix GPIO unspecified behavior on some GPIO ports.
* Fix GPIO undefined behavior caused by uncleared set or reset bits.
Signed-off-by: Saurav Pal <resyfer.dev@gmail.com>
Add definition to setup appropriate reduced SRAM sizes
CONFIG_STM32H7_STM32H72XXX_OR_STM32H73XXX.
The define should make addition of other STM32H72X
and TM32H73X chips easier.
Signed-off-by: Pavel Pisa <pisa@fel.cvut.cz>
Update SIM configuration and CMake toolchain to resolve
linker errors when building on macOS. Adjust POSIX host
implementation to ensure successful compilation and
proper behavior of the sim target.
Modified:
- arch/sim/Kconfig
- arch/sim/src/cmake/Toolchain.cmake
- arch/sim/src/sim/posix/sim_hostmisc.c
Signed-off-by: Aditya Yadav <166515021+aditya0yadav@users.noreply.github.com>
GPIO PIN base address calculation had double right shift, thus call
to SAM_PION_BASE was always with port = 0 instead of correct port
number. As a result, function sam_gpioirq didn't correctly configure
additional interrupt modes (only rising or falling edge and level
interrupts).
The issue occured on SAMv7 and SAM34 platforms (likely copy-pasted
from one to another).
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit updates the common-source integration for RISC-V-based
Espressif devices (ESP32-C3, ESP32-C6, and ESP32-H2). This is part of a
larger common-source update split by architecture for better maintainability
of the already-supported devices and upcoming devices.
Major components updated:
- IRQ allocator refactoring with intr_alloc integration
- Common-source drivers (GPIO, RMT, I2C, SPI, UART, etc.)
- Espressif components upgrade to release/master.b
- Peripheral drivers (ADC, PWM, LEDC, MCPWM, PCNT, Temperature Sensor, etc.)
- Wireless adapters (Wi-Fi and BLE)
- Board defconfigs for all RISC-V Espressif boards
- Critical section handling improvements
Key architectural changes:
- IRQ Allocator: The new interrupt allocator enables multiple mapping
options from interrupt sources to CPU interrupts, providing flexibility
required by modern peripherals. Although this introduces breaking changes
to the interrupt handling API, the required ARCH_MINIMAL_VECTORTABLE
Kconfig option is explicitly checked during startup to ensure proper
configuration. This validation prevents runtime issues from configuration
mismatches.
Note: This is a large commit to maintain bisectability. Breaking the
changes into smaller commits would result in non-building intermediate
states across the common-source infrastructure update.
Tested configurations:
- All defconfigs were built and tested, inclusing `ostest`.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
To be merged with RISC-V implementation
