boot mode is configured
1. Explicitly define the .rtc_reserved section to ensure RTC data
that requires fixed address is correctly placed and does not
conflict with other sections
2. When legacy boot is configured, vecbase must also be set and
clear the BSS section
3. Cache must be disabled during Flash operations, so all
Flash-operation-related functions must be placed in IRAM
(internal RAM). Update the linker script for legacy boot mode
Signed-off-by: nuttxs <zhaoqing.zhang@sony.com>
Added stm32_cap_rstcounter() function to reset the capture counter
by generating an update event. The function is integrated into the
capture operations structure and exposed via STM32_CAP_RSTCOUNTER
macro. Also added TI3 and TI4 input mappings for extended capture
channel support.
Signed-off-by: Alexey Matveev <tippet@yandex.ru>
Enable SYSCALL_HOOKS architecture capability for TriCore platform.
This allows runtime interception and hooking of system calls on
TriCore architecture, enabling profiling, tracing, and debugging features.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Add ARCH_HAVE_PERF_EVENTS_USER_ACCESS capability to allow applications
to directly access hardware perf counters via perf_gettime() from
userspace, enabling performance monitoring and profiling without syscalls.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
dd ARCH_PERF_COUNT_BITWIDTH configuration to support architectures
with different perf counter bit widths (TriCore 31-bit, others 32-bit),
enabling proper overflow correction across diverse platforms.
Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
Extract fixed MPU region configuration into arm64_mpu_init_regiions() function to
allow board-specific initialization. Refactor memory layout to minimize fixed region
requirements and improve dynamic MPU configuration flexibility for FVP platform.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Reduce macro definition duplication by consolidating REGION_*_ATTR macros into a unified
SHAREABLE_MSK definition. This improves code maintainability and reduces configuration
complexity while preserving all attribute functionality.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Refactor mpu_modify_region() and mpu_configure_region() functions to use direct parameters
(base, size, flags) instead of struct pointers. This ensures consistent interface across
all ARM64 MPU implementations including Cortex-R82, improving code uniformity.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Rename MPU region attribute macros (REGION_RAM_ATTR → REGION_RW_NA_ATTR,
REGION_URAM_ATTR → REGION_RW_RW_ATTR) to explicitly indicate access permissions.
Add new REGION_RO_RO_ATTR and REGION_RO_NA_ATTR macros for read-only region definitions.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
According to ARM GIC documentation, GICD_CTLR.DS bit is read-only and cannot be
modified by software. Remove the unnecessary runtime check that attempts to set this bit
for CONFIG_ARCH_SINGLE_SECURITY_STATE configuration, simplifying the GIC initialization flow.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Add mpu_usedregion() function to query the number of MPU regions currently in use.
This interface complements existing mpu_allocregion() and mpu_freeregion() functions,
allowing callers to determine the occupancy of the MPU region pool.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Enable SCTLR_EL1.BR bit to activate MPU background region support. This simplifies MPU
configuration by providing a default MAIR attribute for unmapped regions, reducing the
need for exhaustive region coverage and improving MPU flexibility.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
ARM specifies that SysTick RELOAD must be programmed with N-1 to get a period of N CPU cycles.
Adjust the timeout/reload conversions accordingly: subtract 1 when writing RELOAD and add 1 back when converting RELOAD to a timeout/interval.
Also clamp RELOAD to the valid 24-bit range (1..0x00ffffff) for Armv7-M/Armv8-M to avoid invalid values.
Reference: https://developer.arm.com/documentation/dui0646/c/Cortex-M7-Peripherals/System-timer--SysTick/SysTick-Reload-Value-Register
Signed-off-by: Gao Jiawei <gaojiawei@xiaomi.com>
Replace CONFIG_ARM64_SMP_BUSY_WAIT_FLAG_ADDR with global variable g_smp_busy_wait_flag for
SMP CPU synchronization. This improves flexibility over fixed memory addresses and aligns
with standard kernel variable patterns for multi-core startup.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Enable fvp_userspace.c compilation when
CONFIG_BUILD_PROTECTED is enabled, providing user-space
isolation support for FVP platform. Include
board memory map definitions for protected build
configuration and update MPU regions for
kernel/user space separation.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Add CONFIG_BUILD_PROTECTED support alongside
CONFIG_BUILD_KERNEL for saved register
pointers and task startup functions. Fix
arm64_fork() to properly handle Thumb bit masking.
Enable weak_function for up_allocate_kheap()
to support board-specific heap allocation.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
When setting the timeout value, an overflow occurs. Also, if
NRF52_TIMER_PER > 1000000, the macro will evaluate to zero in
its current form.
Signed-off-by: Max Kriegleder <max.kriegleder@gmail.com>
Add support for handling non-maskable interrupts (NMI) on TriCore
platforms. The NMI trap handler `tricore_nmitrap()` is provided as a weak
function that prints diagnostic information and invokes a panic with
register context. The main trap dispatcher will invoke `tricore_nmitrap`
when an NMI trap class is detected.
This change improves diagnostics when watchdog-induced NMIs or other
non-maskable exceptions occur during runtime.
Signed-off-by: yukangzhi <yukangzhi@xiaomi.com>
Extend CONFIG_LIBCXXTOOLCHAIN support to all remaining platforms
in CMake builds by explicitly locating and linking libstdc++.a
from the toolchain. This prevents build failures caused by STL
header/library mismatches where toolchain headers are included
without the corresponding library.
* Adds nuttx_find_toolchain_lib() calls for all platforms.
* Aligns CMake behavior with Make build system.
Signed-off-by: trns1997 <trns1997@gmail.com>
Some Aurix Boot-FW configurations leave watchdogs enabled by default,
which can cause unexpected resets during early bring-up. This change
explicitly disables the CPU and system watchdogs during core0 startup to
ensure reliable system initialization.
- For TC3XX chips, call `IfxScuWdt_disableCpuWatchdog()` and
`IfxScuWdt_disableSafetyWatchdog()`.
- For TC4XX chips, call `IfxWtu_disableCpuWatchdog()` and
`IfxWtu_disableSystemWatchdog()`.
This is a low-risk startup change and does not alter watchdog behavior
after system initialization.
Signed-off-by: yukangzhi <yukangzhi@xiaomi.com>
At certain optimization levels, GCC/Clang may insert UD2 if it detects undefined behavior (such as integer overflow or illegal pointer access), causing the program to crash immediately instead of executing unpredictable code.
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
The return address stored in the frame should point to the instruction
after the call. To get the actual call site, we need to subtract the
instruction size (sizeof(void *)) from the saved return address.
This ensures that backtrace addresses correctly point to the calling
instruction rather than the next instruction.
Signed-off-by: yinshengkai <yinshengkai@bytedance.com>
Add validation to ensure allocated stack size does not exceed TLS_MAXSTACK when
CONFIG_TLS_ALIGNED is enabled, and verify proper stack alignment using STACK_ALIGN_MASK
across all architectures. This improves stack safety and prevents potential TLS overflow conditions.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Remove return status from void tickless_rtc functions in nrf52, nrf53,
and nrf91 boards. Also add missing newline at end of nrf91_modem_os.c.
Signed-off-by: Bartosz <bartol2205@gmail.com>
In some scenarios (e.g. testing, debugging, etc.) where we want to trigger a memmanage fault without panic the system, we can use this Memory Management Fault skip operation.
Signed-off-by: pangzhen1 <pangzhen1@xiaomi.com>
Rename arm64_addrenv.c to arm64_addrenv_mmu.c to separate MMU-specific logic.
Add new arm64_addrenv_mpu.c with stub implementations of address environment
functions for MPU-based systems. Enable address environment support in FVP ARMv8-R
Kconfig to support kernel stacks in protected mode. Conditionally build MPU or
MMU address environment code based on CONFIG_ARCH_USE_MMU/CONFIG_ARCH_USE_MPU.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
The limit register contains the enable/disable bit for the MPU region,
so it must be written first before writing the base register to ensure
proper region disable operation.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Rename STACK_ALIGNMENT macro to STACKFRAME_ALIGN throughout the codebase
to provide clearer naming semantics. The new name better reflects the macro's
purpose of frame alignment rather than general stack alignment.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Do not compile up_putc functions in stm32_serial.c to avoid conflicts
with implementation from arm_semi_syslog.c when semihosting is enabled.
Signed-off-by: Jean THOMAS <jean@lambdaconcept.com>
Use 1u/~1u constants for TPIDRPRW bit operations.
Avoid implicit conversion to a different underlying type (MISRA Rule 10.3).
No functional change to task pointer tagging logic.
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
When the system startup from the PL1 SYS mode, the initialization
of the PL2 HYP register needs to be skipped. Put the Hypervisor
initialization code together and skip it all at once.
Signed-off-by: yukangzhi <yukangzhi@xiaomi.com>
Add default values (0x0) for ARCH_TEXT_VBASE, ARCH_DATA_VBASE, and
ARCH_HEAP_VBASE to resolve cmake configuration warnings when these
values are not explicitly set during initialization.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Remove restore_critical_section() call from up_switch_context() in simulator
as it is not necessary during interrupt context switching. The critical
section state is properly managed elsewhere in the interrupt handling flow.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Remove restore_critical_section() call from common_handler() in x86_64 interrupt
processing as it is not necessary during interrupt handling. The critical section
state is properly managed by the interrupt framework elsewhere.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
the virtual address of the page table (PT) is saved into the page directory (PD) entry, but the PD entry should store the physical address instead
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
When an interrupt occurs, the hardware automatically pushes the current RIP/RSP onto the interrupt stack. During the interrupt return, the iretq instruction pops them back. The problem is that the RIP/RSP modified by the signal is stored in the XCP context, whereas iretq operates on the interrupt stack. As a result, the RIP/RSP modified by the signal does not take effect in the iretq instruction, causing the task receiving the signal to fail to jump correctly to the signal handler. This behavior appears as if the signal is lost
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
Move stack alignment and kernel stack macros from architecture-specific internal
headers to public include/nuttx/irq.h. Consolidates duplicate definitions across
17 architecture families, reducing code duplication while enabling common code
to access these core alignment utilities without architecture dependencies.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
