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arm64_mpu.h: rename some MPU ATTR

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Rename MPU region attribute macros (REGION_RAM_ATTR → REGION_RW_NA_ATTR,
REGION_URAM_ATTR → REGION_RW_RW_ATTR) to explicitly indicate access permissions.
Add new REGION_RO_RO_ATTR and REGION_RO_NA_ATTR macros for read-only region definitions.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
This commit is contained in:
hujun5 2025-06-17 13:59:18 +08:00 • committed by Xiang Xiao
parent a6e15f6fbd
commit 386457440a
2 changed files with 41 additions and 20 deletions
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53
arch/arm64/src/common/arm64_mpu.h
View file

@ -213,45 +213,74 @@
}
#ifdef CONFIG_SMP
# define REGION_RAM_ATTR \
# define REGION_RW_NA_ATTR \
{ \
/* AP, XN, SH */ \
.rbar = (NOT_EXEC | P_RW_U_NA_MSK | INNER_SHAREABLE_MSK), \
/* Cache-ability */ \
.mair_idx = MPU_MAIR_INDEX_SRAM, \
}
# define REGION_URAM_ATTR \
# define REGION_RW_RW_ATTR \
{ \
/* AP, XN, SH */ \
.rbar = (NOT_EXEC | P_RW_U_RW_MSK | INNER_SHAREABLE_MSK), \
/* Cache-ability */ \
.mair_idx = MPU_MAIR_INDEX_SRAM, \
}
# define REGION_RO_RO_ATTR \
{ \
/* AP, XN, SH */ \
.rbar = NOT_EXEC | P_RO_U_RO_MSK | INNER_SHAREABLE_MSK, \
/* Cache-ability */ \
.mair_idx = MPU_MAIR_INDEX_SRAM, \
}
# define REGION_RO_NA_ATTR \
{ \
/* AP, XN, SH */ \
.rbar = NOT_EXEC | P_RO_U_NA_MSK | INNER_SHAREABLE_MSK, \
/* Cache-ability */ \
.mair_idx = MPU_MAIR_INDEX_SRAM, \
}
#else
# define REGION_RAM_ATTR \
# define REGION_RW_NA_ATTR \
{ \
/* AP, XN, SH */ \
.rbar = NOT_EXEC | P_RW_U_NA_MSK | NON_SHAREABLE_MSK, \
/* Cache-ability */ \
.mair_idx = MPU_MAIR_INDEX_SRAM, \
}
# define REGION_URAM_ATTR \
# define REGION_RW_RW_ATTR \
{ \
/* AP, XN, SH */ \
.rbar = NOT_EXEC | P_RW_U_RW_MSK | NON_SHAREABLE_MSK, \
/* Cache-ability */ \
.mair_idx = MPU_MAIR_INDEX_SRAM, \
}
# define REGION_RO_RO_ATTR \
{ \
/* AP, XN, SH */ \
.rbar = NOT_EXEC | P_RO_U_RO_MSK | NON_SHAREABLE_MSK, \
/* Cache-ability */ \
.mair_idx = MPU_MAIR_INDEX_SRAM, \
}
# define REGION_RO_NA_ATTR \
{ \
/* AP, XN, SH */ \
.rbar = NOT_EXEC | P_RO_U_NA_MSK | NON_SHAREABLE_MSK, \
/* Cache-ability */ \
.mair_idx = MPU_MAIR_INDEX_SRAM, \
}
#endif
#ifdef CONFIG_SMP
# define REGION_RAM_TEXT_ATTR \
# define REGION_KTEXT_ATTR \
{ \
/* AP, XN, SH */ \
.rbar = P_RO_U_NA_MSK | INNER_SHAREABLE_MSK, \
/* Cache-ability */ \
.mair_idx = MPU_MAIR_INDEX_SRAM, \
}
# define REGION_RAM_UTEXT_ATTR \
# define REGION_UTEXT_ATTR \
{ \
/* AP, XN, SH */ \
.rbar = P_RO_U_RO_MSK | INNER_SHAREABLE_MSK, \
@ -259,14 +288,14 @@
.mair_idx = MPU_MAIR_INDEX_SRAM, \
}
#else
# define REGION_RAM_TEXT_ATTR \
# define REGION_KTEXT_ATTR \
{ \
/* AP, XN, SH */ \
/* Cache-ability */ \
.rbar = P_RO_U_NA_MSK | NON_SHAREABLE_MSK, \
.mair_idx = MPU_MAIR_INDEX_SRAM, \
}
# define REGION_RAM_UTEXT_ATTR \
# define REGION_UTEXT_ATTR \
{ \
/* AP, XN, SH */ \
.rbar = P_RO_U_RO_MSK | NON_SHAREABLE_MSK, \
@ -275,14 +304,6 @@
}
#endif
#define REGION_RAM_RO_ATTR \
{ \
/* AP, XN, SH */ \
.rbar = NOT_EXEC | P_RO_U_RO_MSK | NON_SHAREABLE_MSK, \
/* Cache-ability */ \
.mair_idx = MPU_MAIR_INDEX_SRAM, \
}
#ifndef __ASSEMBLY__
struct arm64_mpu_region_attr

8
arch/arm64/src/fvp-v8r/fvp_boot.c
View file

@ -57,14 +57,14 @@ static const struct arm64_mpu_region g_mpu_regions[] =
MPU_REGION_ENTRY("nx_ktext",
(uint64_t)KTEXT_START,
(uint64_t)KTEXT_END,
REGION_RAM_TEXT_ATTR),
REGION_KTEXT_ATTR),
/* Region 1 NuttX kdata */
MPU_REGION_ENTRY("nx_kdata",
(uint64_t)KSRAM_START,
(uint64_t)KSRAM_END,
REGION_RAM_ATTR),
REGION_RW_NA_ATTR),
#ifdef CONFIG_BUILD_PROTECTED
/* Region 2 NuttX utext */
@ -72,14 +72,14 @@ static const struct arm64_mpu_region g_mpu_regions[] =
MPU_REGION_ENTRY("nx_utext",
(uint64_t)UTEXT_START,
(uint64_t)UTEXT_END,
REGION_RAM_UTEXT_ATTR),
REGION_UTEXT_ATTR),
/* Region 3 NuttX udata */
MPU_REGION_ENTRY("nx_udata",
(uint64_t)USRAM_START,
(uint64_t)USRAM_END,
REGION_URAM_ATTR),
REGION_RW_RW_ATTR),
#endif
/* Region 4 device region */