From 386457440ad0c8f3fa72e76172bcc5cd15d620e7 Mon Sep 17 00:00:00 2001 From: hujun5 Date: Tue, 17 Jun 2025 13:59:18 +0800 Subject: [PATCH] arm64_mpu.h: rename some MPU ATTR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename MPU region attribute macros (REGION_RAM_ATTR → REGION_RW_NA_ATTR, REGION_URAM_ATTR → REGION_RW_RW_ATTR) to explicitly indicate access permissions. Add new REGION_RO_RO_ATTR and REGION_RO_NA_ATTR macros for read-only region definitions. Signed-off-by: hujun5 --- arch/arm64/src/common/arm64_mpu.h | 53 +++++++++++++++++++++---------- arch/arm64/src/fvp-v8r/fvp_boot.c | 8 ++--- 2 files changed, 41 insertions(+), 20 deletions(-) diff --git a/arch/arm64/src/common/arm64_mpu.h b/arch/arm64/src/common/arm64_mpu.h index e88ca5b6381..36b1d776b6e 100644 --- a/arch/arm64/src/common/arm64_mpu.h +++ b/arch/arm64/src/common/arm64_mpu.h @@ -213,45 +213,74 @@ } #ifdef CONFIG_SMP -# define REGION_RAM_ATTR \ +# define REGION_RW_NA_ATTR \ { \ /* AP, XN, SH */ \ .rbar = (NOT_EXEC | P_RW_U_NA_MSK | INNER_SHAREABLE_MSK), \ /* Cache-ability */ \ .mair_idx = MPU_MAIR_INDEX_SRAM, \ } -# define REGION_URAM_ATTR \ +# define REGION_RW_RW_ATTR \ { \ /* AP, XN, SH */ \ .rbar = (NOT_EXEC | P_RW_U_RW_MSK | INNER_SHAREABLE_MSK), \ /* Cache-ability */ \ .mair_idx = MPU_MAIR_INDEX_SRAM, \ } +# define REGION_RO_RO_ATTR \ + { \ + /* AP, XN, SH */ \ + .rbar = NOT_EXEC | P_RO_U_RO_MSK | INNER_SHAREABLE_MSK, \ + /* Cache-ability */ \ + .mair_idx = MPU_MAIR_INDEX_SRAM, \ + } +# define REGION_RO_NA_ATTR \ + { \ + /* AP, XN, SH */ \ + .rbar = NOT_EXEC | P_RO_U_NA_MSK | INNER_SHAREABLE_MSK, \ + /* Cache-ability */ \ + .mair_idx = MPU_MAIR_INDEX_SRAM, \ + } #else -# define REGION_RAM_ATTR \ +# define REGION_RW_NA_ATTR \ { \ /* AP, XN, SH */ \ .rbar = NOT_EXEC | P_RW_U_NA_MSK | NON_SHAREABLE_MSK, \ /* Cache-ability */ \ .mair_idx = MPU_MAIR_INDEX_SRAM, \ } -# define REGION_URAM_ATTR \ +# define REGION_RW_RW_ATTR \ { \ /* AP, XN, SH */ \ .rbar = NOT_EXEC | P_RW_U_RW_MSK | NON_SHAREABLE_MSK, \ /* Cache-ability */ \ .mair_idx = MPU_MAIR_INDEX_SRAM, \ } +# define REGION_RO_RO_ATTR \ + { \ + /* AP, XN, SH */ \ + .rbar = NOT_EXEC | P_RO_U_RO_MSK | NON_SHAREABLE_MSK, \ + /* Cache-ability */ \ + .mair_idx = MPU_MAIR_INDEX_SRAM, \ + } +# define REGION_RO_NA_ATTR \ + { \ + /* AP, XN, SH */ \ + .rbar = NOT_EXEC | P_RO_U_NA_MSK | NON_SHAREABLE_MSK, \ + /* Cache-ability */ \ + .mair_idx = MPU_MAIR_INDEX_SRAM, \ + } #endif + #ifdef CONFIG_SMP -# define REGION_RAM_TEXT_ATTR \ +# define REGION_KTEXT_ATTR \ { \ /* AP, XN, SH */ \ .rbar = P_RO_U_NA_MSK | INNER_SHAREABLE_MSK, \ /* Cache-ability */ \ .mair_idx = MPU_MAIR_INDEX_SRAM, \ } -# define REGION_RAM_UTEXT_ATTR \ +# define REGION_UTEXT_ATTR \ { \ /* AP, XN, SH */ \ .rbar = P_RO_U_RO_MSK | INNER_SHAREABLE_MSK, \ @@ -259,14 +288,14 @@ .mair_idx = MPU_MAIR_INDEX_SRAM, \ } #else -# define REGION_RAM_TEXT_ATTR \ +# define REGION_KTEXT_ATTR \ { \ /* AP, XN, SH */ \ /* Cache-ability */ \ .rbar = P_RO_U_NA_MSK | NON_SHAREABLE_MSK, \ .mair_idx = MPU_MAIR_INDEX_SRAM, \ } -# define REGION_RAM_UTEXT_ATTR \ +# define REGION_UTEXT_ATTR \ { \ /* AP, XN, SH */ \ .rbar = P_RO_U_RO_MSK | NON_SHAREABLE_MSK, \ @@ -275,14 +304,6 @@ } #endif -#define REGION_RAM_RO_ATTR \ - { \ - /* AP, XN, SH */ \ - .rbar = NOT_EXEC | P_RO_U_RO_MSK | NON_SHAREABLE_MSK, \ - /* Cache-ability */ \ - .mair_idx = MPU_MAIR_INDEX_SRAM, \ - } - #ifndef __ASSEMBLY__ struct arm64_mpu_region_attr diff --git a/arch/arm64/src/fvp-v8r/fvp_boot.c b/arch/arm64/src/fvp-v8r/fvp_boot.c index 8dcc1445541..ca72d6524f4 100644 --- a/arch/arm64/src/fvp-v8r/fvp_boot.c +++ b/arch/arm64/src/fvp-v8r/fvp_boot.c @@ -57,14 +57,14 @@ static const struct arm64_mpu_region g_mpu_regions[] = MPU_REGION_ENTRY("nx_ktext", (uint64_t)KTEXT_START, (uint64_t)KTEXT_END, - REGION_RAM_TEXT_ATTR), + REGION_KTEXT_ATTR), /* Region 1 NuttX kdata */ MPU_REGION_ENTRY("nx_kdata", (uint64_t)KSRAM_START, (uint64_t)KSRAM_END, - REGION_RAM_ATTR), + REGION_RW_NA_ATTR), #ifdef CONFIG_BUILD_PROTECTED /* Region 2 NuttX utext */ @@ -72,14 +72,14 @@ static const struct arm64_mpu_region g_mpu_regions[] = MPU_REGION_ENTRY("nx_utext", (uint64_t)UTEXT_START, (uint64_t)UTEXT_END, - REGION_RAM_UTEXT_ATTR), + REGION_UTEXT_ATTR), /* Region 3 NuttX udata */ MPU_REGION_ENTRY("nx_udata", (uint64_t)USRAM_START, (uint64_t)USRAM_END, - REGION_URAM_ATTR), + REGION_RW_RW_ATTR), #endif /* Region 4 device region */