Commit graph

58150 commits

Author SHA1 Message Date
Eren Terzioglu
97ff8906e4 arch/esp[s2|s3]: Update common layer version
Update common layer version of Xtensa based Espressif devices

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-04-08 22:53:58 +08:00
Eren Terzioglu
22601e2074 boards/esp32[s2|s3]: Add common I2S board layer support
Add common I2S board layer support for Xtensa based Espressif devices

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-04-08 22:53:58 +08:00
Eren Terzioglu
873a6319bb arch/esp32[s2|s3]: Add common I2S arch layer support
Add common I2S arch layer support for Xtensa based Espressif devices

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-04-08 22:53:58 +08:00
Eren Terzioglu
fd4914b953 arch/xtensa/esp32[s3]: Add more dma functions
Add dma function to use peripheral more efficiently

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-04-08 22:53:58 +08:00
Ville Juven
850cfb545a Revert "includes/nuttx: fix _SCHED_GET(T/P/PP)ID definition issue"
This reverts commit 9369b75ee5.

Signed-off-by: Ville Juven <ville.juven@unikie.com>
2025-04-08 22:53:10 +08:00
Ville Juven
04e760b1c2 sched/gettid: Move thread ID to TLS
There is no need for a gettid() syscall, as the thread ID is stable through
the life of the process. It is safe to put a copy of TID to TLS. This way
a user processes can access TID quickly via its own stack, instead of
having to use an expensive syscall.

Signed-off-by: Ville Juven <ville.juven@unikie.com>
2025-04-08 22:53:10 +08:00
chenxiaoyi
b3567fe964 xtensa/esp32s2: enable sysclk and deassert reset signal for uart1
The uart1 is found be in reset state, and the sysclk is not enabled
for it.

Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
2025-04-08 22:44:59 +08:00
Jukka Laitinen
84cb21791f libc/semaphore: Read semaphore value by using NXSEM_COUNT macro
We should not access semaphore internals directly outside sched/semaphore.

Just read it via the NXSEM_COUNT macro provided.

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
2025-04-08 16:12:17 +08:00
Tiago Medicci Serrano
9967593009 boards/esp32s3-devkit: Update ESP32-S3's WROOM-2-N32R8V defconfigs
The defconfigs that select the ESP32-S3's WROOM-2-N32R8V module
contains an octal SPI flash chip and a octal SPIRAM module.
This commit updates the defconfig to avoid errors while booting the
device.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2025-04-08 14:44:38 +08:00
Tiago Medicci Serrano
622355b5c3 arch/xtensa/esp32s3: Fix bug regarding SPI flash operation mode
SPI flash operation modes - Dual Output (dout), Dual I/O (dio),
Quad Output (qout), Quad I/O (qio) and Octal (opi) were not being
properly selected. This commit fixes this behavior and the device
is now able to boot and initialize the proper SPI flash mode.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2025-04-08 14:44:38 +08:00
raiden00pl
b81c4d3aa6 boards/nucleo-c071rb: add watchdog support
boards/nucleo-c071rb: add watchdog support and enable IWDG for jumbo configuration

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-04-07 23:28:47 +08:00
raiden00pl
5d66f2c973 arch/stm32f0l0g0: add support for IWDG and WWDG
add IWDG and WWDG support for stm32f0l0g0.

ported from arch/stm32.

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-04-07 23:28:47 +08:00
Jukka Laitinen
4b14b206db sched: Replace direct semaphore value access with nxsem_get_value
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
2025-04-07 16:29:57 +08:00
Jukka Laitinen
cd84da8714 sched/pthread: Set the protocol of underlying semaphore to SEM_TYPE_MUTEX in pthread_mutex_init
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
2025-04-07 16:29:57 +08:00
liujp
32c5667d5d Optimize double buffering implementation
optimize the implemented dual buffer support to avoid compilation errors on other development boards.

Signed-off-by: liujp <liujp@xiaomi.com>
2025-04-07 16:28:30 +08:00
liujp
e421e2c9e5 arch/arm/stm32h7: add support for STM32H750B
modify the compilation configuration of stm32h7, add compilation options for stm32h750.

Signed-off-by: liujp <liujp@xiaomi.com>
2025-04-07 16:28:30 +08:00
liujp
c309c452d6 boards/arm/stm32h7: add support for stm32h750b-dk board
Support for development using STM32H750B-DK, including configuration of onboard memory, flash, etc., and configuration of LVGL runtime environment has been added.

Signed-off-by: liujp <liujp@xiaomi.com>
2025-04-07 16:28:30 +08:00
wangjianyu3
0a74293f11 boards/szpi-esp32s3: Remove FAR qualifier
Remove FAR qualifier for szpi-esp32s3.

Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
2025-04-07 16:26:16 +08:00
wangjianyu3
25443a37ee boards/szpi-esp32s3: Set default backlight for LCD
Set default brightness of LCD backlight to about 10%.

Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
2025-04-07 16:26:16 +08:00
Kye Morton
a8b862396e arch/arm: Add CMakeLists for the stm32l4 architecture.
boards/arm: Add CMakeLists for the nucleo-l476rg.

Adds CMakeLists files for the STM32L4 architectures
and one of the development boards. Files are adapted
from the similar STM32F7 boards, but built to reflect
the existing Make.defs.

Signed-off-by: Kye Morton <pryre.dev@outlook.com>
2025-04-07 12:10:40 +08:00
chao an
53836fc18a libs/libc/crc16: add support of CRC-16/ANSI(aka CRC-16/IBM)
Compatible CRC16 with Linux Kernel:
https://github.com/torvalds/linux/blob/master/lib/crc16.c

- CRC-16/CCITT, CRC-16/CCITT-TRUE, CRC-16/KERMIT
poly: 0x8005 (0xA001) initial seed: 0x0000, xor output: 0x0000

: width=16
: poly=0x8005
: init=0x0000
: refin=true
: refout=true
: xorout=0x0000
: check=0xbb3d
: residue=0x0000
: name="CRC-16/ARC"

https://reveng.sourceforge.io/crc-catalogue/16.htm#crc.cat.crc-16-arc

Signed-off-by: chao an <anchao.archer@bytedance.com>
2025-04-07 12:10:05 +08:00
Alin Jerpelea
2d7cf5e5b1 Documentation: add NuttX-12.9.0 release notes
Add release notes for 12.9.0 release

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2025-04-07 10:47:06 +08:00
Rodrigo Sim
b28bb29bf9 boards/arm/stm32f401rc-rs485: Add support to BMP180 Sensor
This commit adds support for the BMP180 sensor on the
STM32F401RC-RS485 board and updates the board documentation
accordingly. It also enables the BMP180 UORB driver in the
STM32 common logic.

Signed-off-by: Rodrigo Sim <rcsim10@gmail.com>
2025-04-07 10:45:05 +08:00
chao an
921ffc7319 libs/libc/crc16: move crc16 table to rodata
move crc16 table from data to rodata

Signed-off-by: chao an <anchao.archer@bytedance.com>
2025-04-07 09:02:01 +08:00
chao an
4e2f6eabb3 libs/libc/crc16: add some comments for crc16ccitt
The search table of ccitt should describe more algorithm details:

- CRC-16/CCITT, CRC-16/CCITT-TRUE, CRC-16/KERMIT
initial seed: 0x0000, xor output: 0x0000

: width=16
: poly=0x1021
: init=0x0000
: refin=true
: refout=true
: xorout=0x0000
: check=0x2189
: residue=0x0000
: name="CRC-16/KERMIT"

https://reveng.sourceforge.io/crc-catalogue/16.htm#crc.cat.crc-16-kermit

Signed-off-by: chao an <anchao.archer@bytedance.com>
2025-04-07 09:02:01 +08:00
raiden00pl
c061bb08c4 boards/arm: add nucleo-c071rb support
add nucleo-c071rb support

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-04-05 11:23:40 -03:00
raiden00pl
57d1dee7e1 arch/arm: add stm32c0 support
add stm32c0 support

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-04-05 11:23:40 -03:00
Tiago Medicci Serrano
80559890ff espressif: Simplify the selection of the SPI flash frequency
This commit simplifies the selection of the SPI flash frequency for
Espressif SoCs by using a standardized Kconfig-defined macro.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2025-04-05 11:26:32 +08:00
Tiago Medicci Serrano
1e8250d918 boards/xtensa/esp32s3: Move some .bss sections to the external RAM
This commit moves some internal libraries' .bss sections to the
external PSRAM chip, freeing internal memory for other usages. Note
that it is necessary to update `esp32s3-devkit:python` defconfig
otherwise it would fail to build.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2025-04-05 11:24:58 +08:00
raiden00pl
23ef48e673 arch/stm32f0l0g0/stm32_adc.c: fix ADC calibration
Fix and enable ADC calibration. The ADC voltage regulator must be
enabled and regulator start-up time must be respected.

tested on nucleo-c071rb and b-l072z-lrwan1

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-04-05 11:23:47 +08:00
Jinliang Li
d5db7d1cee libc/arm: optimize crc32/crc32c for arm
Optimize crc32 standard(poly:0x04C11DB7) and crc32
castagnoli(poly:0x1EDC6F41) with arm crc32 extension instructions.

For example, crc32 standard caculates(lookup crc32 table) 1812 bytes data,
reduced the time from 118 us to 14 us through optimization.

Performance improved ~700%

Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
2025-04-04 09:51:50 -03:00
wangjianyu3
586d216a40 boards/szpi-esp32s3: Add support for FT5X06
Add support for FT5X06 touchscreen driver.

Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
2025-04-04 09:50:19 -03:00
wangjianyu3
7ffa06a78d drivers/ft5x06: Remove wakeup and nreset check
Remove unused wakeup and nreset check of FT5X06.

Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
2025-04-04 09:50:19 -03:00
Laczen JMS
dfc0053c2d boards/xtensa/esp32/esp32-devkitc: update espnow
Update the esp32-devkitc board for espnow changes.

Signed-off-by: Laczen JMS <laczenjms@gmail.com>
2025-04-04 06:49:50 +08:00
Laczen JMS
34bb3c88a2 arch/xtensa/src/esp32: remove espnow
remove espnow pktradio from arch/xtensa/src/esp32

Signed-off-by: Laczen JMS <laczenjms@gmail.com>
2025-04-04 06:49:50 +08:00
Laczen JMS
58463d9484 arch/xtensa/src/common/espressif: Introduce espnow
Move espnow:
 arch/xtensa/src/esp32 -> arch/xtensa/src/common/espressif

Signed-off-by: Laczen JMS <laczenjms@gmail.com>
2025-04-04 06:49:50 +08:00
chao an
58ed9934c2 syscall/csv: add nxsem_tickwait() to userspace
mutex_tickwait() depends on this API

Signed-off-by: chao an <anchao.archer@bytedance.com>
2025-04-03 20:13:55 +08:00
chao an
0d6de4c0a7 sched/mutex: add ticked lock version for mutex/rmutex
Added ticked lock version for mutex to reduce time calculation overhead

Signed-off-by: chao an <anchao.archer@bytedance.com>
2025-04-03 20:13:55 +08:00
Ville Juven
cc64c026d9 mpfs/mpfs_entrypoints.c: Change atomic_load > atomic_read
Otherwise we get an undefined symbol error when LIBC_ARCH_ATOMIC is
defined.

Signed-off-by: Ville Juven <ville.juven@unikie.com>
2025-04-03 18:34:11 +08:00
YAMAMOTO Takashi
90e9b2426d add a comment on littlefs_attr_s to explain what it is
i couldn't find any documenation about this attribute.
this comment is purely based on my reading of the code.

Signed-off-by: YAMAMOTO Takashi <yamamoto@midokura.com>
2025-04-03 16:23:42 +08:00
Jani Paalijarvi
02c9030e88 drivers/bch: Add CONFIG_BCH_FORCE_INDIRECT
This implements similar functionality than CONFIG_FAT_FORCE_INDIRECT
because in some use cases (e.g. when CONFIG_BUILD_KERNEL) it is not possible to
write directly from user buffer.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2025-04-03 16:21:51 +08:00
Jinliang Li
95ba78e1bd arch/armv8-r: Enable fpu before arm_el_init
In the arm_el_init function, the FPU might be used, for example, the
assembly optimization of memcpy in arm_tcm_load uses FPU and NEON
instructions and registers.
Therefore, it's important to initialize the
FPU as early as possible to prevent system hangs that could occur if the
FPU is used without being initialized.

Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
2025-04-02 21:07:54 +08:00
buxiasen
41cbbb0c12 arch/arm/imx6: fix missed comma
Will Compile error if enable IMX6_UART2..5

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2025-04-02 21:05:52 +08:00
chao an
0bfb850b52 drivers/serial/uart_rpmsg: simplify initialization process of uart_rpmsg
Merge multiple heap allocate into one

Signed-off-by: chao an <anchao.archer@bytedance.com>
2025-04-02 20:56:01 +08:00
raiden00pl
5d2e0f8c80 arch/esp32s3/esp32s3_wdt_lowerhalf.c: fix printf warning
fix printf warning:

chip/esp32s3_wdt_lowerhalf.c:497:17: error: format '%u' expects argument of
type 'unsigned int', but argument 4 has type 'long unsigned int'

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-04-02 08:29:00 -03:00
raiden00pl
649e979f58 arch/esp32s2/esp32s2_wdt_lowerhalf.c: fix printf warning
fix printf warning:

chip/esp32s2_wdt_lowerhalf.c:493:17: error: format '%u' expects argument of
type 'unsigned int', but argument 4 has type 'long unsigned int'

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-04-02 08:29:00 -03:00
raiden00pl
1a6cb4c784 arch/esp32s3/esp32s3_ble_adapter.c: fix printf warning
fix printf warning:

chip/esp32s3_ble_adapter.c:1065:13: error: format '%u' expects argument of
type 'unsigned int', but argument 3 has type 'long unsigned int'

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-04-02 08:29:00 -03:00
raiden00pl
ea28e08be4 arch/esp32/esp32_ble_adapter.c: fix printf warning
fix printf warning:

  chip/esp32_ble_adapter.c:1137:13: error: format '%u' expects argument of
  type 'unsigned int', but argument 3 has type 'long unsigned int'

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-04-02 08:29:00 -03:00
Kerogit
ac42add946 nuttx/clock: make NSEC_PER_USEC and others long
On AVR architecture, the compiler apparently sometimes truncates NSEC_PER_TICK
to 16bit value, leading to clock_time2ticks returning incorrect results. This
was encountered while attempting to add tickless OS support for AVR
architecture but seemed to affect non-tickless mode of operation as well.

This patch marks NSEC_PER_USEC (and to be safe, USEC_PER_MSEC and MSEC_PER_SEC
too) as long.
2025-04-02 08:29:00 -03:00
ouyangxiangzhen
87c217ad93 arch/x86_64: Fix strict-prototype warning.
This commit fixed a strict-prototype warning.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
2025-04-02 12:01:46 +08:00