Gregory Nutt
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c1c5e195ce
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SAMA5 EHCI: Add IOC error handling
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2013-08-22 09:23:01 -06:00 |
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Gregory Nutt
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73efdf8d05
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SAMA5 EHCI: transfer termination logic. Incomplete
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2013-08-21 17:08:12 -06:00 |
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Gregory Nutt
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7e9832f955
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SAMA5 EHCI: transfer termination logic. Incomplete
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2013-08-21 17:08:12 -06:00 |
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Gregory Nutt
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f831c8fe94
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SAMA5 EHCI: Hardware initialization logic
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2013-08-21 13:45:54 -06:00 |
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Gregory Nutt
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a5eb830544
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SAMA5 EHCI: Hardware initialization logic
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2013-08-21 13:45:54 -06:00 |
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Gregory Nutt
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3d59f1f61c
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Move all SAMA5 EHCI interrupt handling to the worker thread
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2013-08-21 11:07:42 -06:00 |
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Gregory Nutt
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c109c39be7
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Move all SAMA5 EHCI interrupt handling to the worker thread
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2013-08-21 11:07:42 -06:00 |
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Gregory Nutt
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b1864a995e
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Move all SAMA5 EHCI interrupt handling to the worker thread
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2013-08-21 11:07:42 -06:00 |
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Gregory Nutt
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e5208a6e92
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ENC28J60 errors reported by Max Holtzberg
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2013-08-21 08:10:32 -06:00 |
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Gregory Nutt
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9f6ae9332f
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SAMA5 EHCI: At list-oriented cache operations
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2013-08-20 18:06:04 -06:00 |
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Gregory Nutt
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85aa2c1a8d
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SAMA5 EHCI: At list-oriented cache operations
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2013-08-20 18:06:04 -06:00 |
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Gregory Nutt
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514826eeb1
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Add SAMA5 EHCI list traversal logic
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2013-08-20 17:01:30 -06:00 |
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Gregory Nutt
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0f2ce573e4
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Add SAMA5 EHCI list traversal logic
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2013-08-20 17:01:30 -06:00 |
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Gregory Nutt
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bc57cd5684
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Beginning of support for SAMA5 EHCI. Not much there yet
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2013-08-20 15:46:36 -06:00 |
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Gregory Nutt
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6a79cea2c0
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Beginning of support for SAMA5 EHCI. Not much there yet
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2013-08-20 15:46:36 -06:00 |
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Gregory Nutt
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320a2e2a0a
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Beginning of support for SAMA5 EHCI. Not much there yet
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2013-08-20 15:46:36 -06:00 |
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Gregory Nutt
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609dc65235
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Add kernel/user memalign functions. Not fully integrated
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2013-08-20 13:04:49 -06:00 |
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Gregory Nutt
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e3a76b2e64
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Add kernel/user memalign functions. Not fully integrated
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2013-08-20 13:04:49 -06:00 |
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Gregory Nutt
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4d5789dfdd
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SAMA5 OHCI+EHCI mostly cosmetic changes
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2013-08-19 15:03:14 -06:00 |
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Gregory Nutt
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b04ea3efa6
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SAMA5 OHCI+EHCI mostly cosmetic changes
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2013-08-19 15:03:14 -06:00 |
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Gregory Nutt
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4bf3dbe149
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USB host: Add device address management support in preparation for USB hub support
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2013-08-18 14:31:57 -06:00 |
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Gregory Nutt
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19d7c90d4e
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USB host: Add device address management support in preparation for USB hub support
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2013-08-18 14:31:57 -06:00 |
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Gregory Nutt
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1d56a5c9fd
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Add few more EHCI definitions
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2013-08-18 13:01:13 -06:00 |
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Gregory Nutt
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a6e6b4ba2d
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Add few more EHCI definitions
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2013-08-18 13:01:13 -06:00 |
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Gregory Nutt
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0524688c71
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Add few more EHCI definitions
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2013-08-18 13:01:13 -06:00 |
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Gregory Nutt
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7b617b01f2
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Completes EHCI header file
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2013-08-18 09:01:16 -06:00 |
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Gregory Nutt
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44dd71de4e
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Completes EHCI header file
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2013-08-18 09:01:16 -06:00 |
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Gregory Nutt
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07bd7c2168
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STM32 F1 I2C: Fix a typo that crept in with some recent changes. From Yiran Liao
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2013-08-18 07:45:14 -06:00 |
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Gregory Nutt
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dc07d65e14
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STM32 F1 I2C: Fix a typo that crept in with some recent changes. From Yiran Liao
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2013-08-18 07:45:14 -06:00 |
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Gregory Nutt
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b33de2b618
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Add EHCI header file (not quite complete)
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2013-08-17 14:19:18 -06:00 |
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Gregory Nutt
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e2f68ac85f
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Add EHCI header file (not quite complete)
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2013-08-17 14:19:18 -06:00 |
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Gregory Nutt
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a0837fca6c
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SAMA5 OHCI: Driver is now basically functional
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2013-08-16 13:13:21 -06:00 |
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Gregory Nutt
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11086f34d0
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SAMA5 OHCI: Driver is now basically functional
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2013-08-16 13:13:21 -06:00 |
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Gregory Nutt
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111a707511
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SAMA5 OHCI: Re-organize some endpoint list data structures.. Strange things happen when semaphores lie in DMA memory which is occasionally invalidated
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2013-08-16 11:36:51 -06:00 |
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Gregory Nutt
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db42d9350c
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SAMA5 OHCI: Re-organize some endpoint list data structures.. Strange things happen when semaphores lie in DMA memory which is occasionally invalidated
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2013-08-16 11:36:51 -06:00 |
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Gregory Nutt
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1fb80e0917
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SAMA5 OHCI: Re-organize some endpoint list data structures.. Strange things happen when semaphores lie in DMA memory which is occasionally invalidated
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2013-08-16 11:36:51 -06:00 |
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Gregory Nutt
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ddc93e1da3
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STM32 SPI: nbits interface extended to handle LSB- or MSB-first operation. From Teemu Pirinen
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2013-08-16 11:35:22 -06:00 |
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Gregory Nutt
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10daf06976
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STM32 SPI: nbits interface extended to handle LSB- or MSB-first operation. From Teemu Pirinen
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2013-08-16 11:35:22 -06:00 |
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Gregory Nutt
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94bcdc66b0
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SAMA5 OHCI: Don't prealloc RH port TDs and EDs. Allocate from a free list like other cases
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2013-08-15 17:15:08 -06:00 |
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Gregory Nutt
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ca739ce76d
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SAMA5 OHCI: Don't prealloc RH port TDs and EDs. Allocate from a free list like other cases
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2013-08-15 17:15:08 -06:00 |
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Gregory Nutt
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41c068f652
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SAMA5 OHCI: Fix errors in cache handling; Don't add ED to control list until port is connected
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2013-08-15 15:28:27 -06:00 |
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Gregory Nutt
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7f733b0472
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SAMA5 OHCI: Fix errors in cache handling; Don't add ED to control list until port is connected
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2013-08-15 15:28:27 -06:00 |
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Gregory Nutt
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91a2700f31
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SAMA5: Correct the PLL 48MHz divisor. It was off by a factor of two... no idea why
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2013-08-14 19:38:48 -06:00 |
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Gregory Nutt
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371639637f
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SAMA5: Correct the PLL 48MHz divisor. It was off by a factor of two... no idea why
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2013-08-14 19:38:48 -06:00 |
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Gregory Nutt
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e23a92243c
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SAMA5: ports should not be reset state (seems to make no difference)
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2013-08-14 17:33:31 -06:00 |
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Gregory Nutt
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589386a5ce
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SAMA5: ports should not be reset state (seems to make no difference)
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2013-08-14 17:33:31 -06:00 |
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Gregory Nutt
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0098c9ec5f
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SAMA5: ports should not be reset state (seems to make no difference)
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2013-08-14 17:33:31 -06:00 |
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Gregory Nutt
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49f3831e11
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SAMA5: Alternatie clock configuration that yields a perfect 48MHz full speed USB clock and a CPU clock of 384MHz
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2013-08-14 15:16:04 -06:00 |
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Gregory Nutt
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8686c040ac
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SAMA5: Alternatie clock configuration that yields a perfect 48MHz full speed USB clock and a CPU clock of 384MHz
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2013-08-14 15:16:04 -06:00 |
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Gregory Nutt
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fe73fe2e23
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SAMA5: Alternatie clock configuration that yields a perfect 48MHz full speed USB clock and a CPU clock of 384MHz
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2013-08-14 15:16:04 -06:00 |
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