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SAMA5: Alternatie clock configuration that yields a perfect 48MHz full speed USB clock and a CPU clock of 384MHz

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This commit is contained in:
Gregory Nutt 2013-08-14 15:16:04 -06:00
parent e32b60a78c
commit 49f3831e11
3 changed files with 4 additions and 4 deletions
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2
arch/arm/src/sama5/chip/sam_hsmci.h
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@ -174,7 +174,7 @@
#define HSMCI_MR_WRPROOF (1 << 12) /* Bit 12: Write Proof Enable */
#define HSMCI_MR_FBYTE (1 << 13) /* Bit 13: Force Byte Transfer */
#define HSMCI_MR_PADV (1 << 14) /* Bit 14: Padding Value */
#define HSMCI_MR_CLKODD (1 << 15) /* Bit 15: Clock divider is odd */
#define HSMCI_MR_CLKODD (1 << 16) /* Bit 15: Clock divider is odd */
/* HSMCI Data Timeout Register */

2
arch/arm/src/sama5/sam_clockconfig.c
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@ -374,7 +374,7 @@ static inline void sam_usbclockconfig(void)
* Description:
* Called to initialize the SAM3/4. This does whatever setup is needed to
* put the SoC in a usable state. This includes the initialization of
* clocking using the settings in board.h. (After power-on reset, the SAM3/4
* clocking using the settings in board.h. (After power-on reset, the SAMA5
* is initially running on a 12MHz internal RC clock). This function also
* performs other low-level chip initialization of the chip including master
* clock, IRQ & watchdog configuration.

4
arch/arm/src/sama5/sam_hsmci.c
View file

@ -1612,10 +1612,10 @@ static void sam_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
uint32_t regval;
bool enable = true;
/* Fetch the current mode register and mask out the clkdiv (and pwsdiv) */
/* Fetch the current mode register and mask out the clkdiv+clockodd (and pwsdiv) */
regval = sam_getreg(priv, SAM_HSMCI_MR_OFFSET);
regval &= ~(HSMCI_MR_CLKDIV_MASK | HSMCI_MR_PWSDIV_MASK);
regval &= ~(HSMCI_MR_CLKDIV_MASK | HSMCI_MR_PWSDIV_MASK | HSMCI_MR_CLKODD);
/* These clock devisor values that must be defined in the board-specific
* board.h header file: HSMCI_INIT_CLKDIV, HSMCI_MMCXFR_CLKDIV,