This revise armv7-r/ header files needed to support QEMU cortex-r5
virtual process for armv7-r family.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
As armv7-a addrenv layout is not in line with other archs, we need
align it with others by defining ARCH_DATA_RESERVE_SIZE as same as
MM_PGSIZE for now to keep gnu-elf.ld.in unified.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
This fixes compilation error:
```
/tmp/nuttx/arch/arm/src/armv7-r/gic.h:699:17: error:
'GIC_ICDSGIR_NSATT_GRP1' undeclared; did you mean 'GIC_ICDSGIR_NSATT'?
```
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
Summary:
- Replace direct use of `fence.i` instruction with `__ISB()` macro for instruction synchronization
- This change improves portability while maintaining the same functionality
Impact:
- No functional changes - both `fence.i` and `__ISB()` ensure instruction
synchronization on RISC-V
- Makes the code more maintainable by using the architecture abstraction
layer
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Summary:
- Removed explicit -std=c99 flag from Make.defs
- The project-wide C standard is already set at a higher level
- Keeps build configuration consistent across the codebase
Impact:
- No functional changes to the code
- Maintains consistency with project-wide C standard settings
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
copied over files, not modified properly yet
Squashing lots of define errors to get ethernet.c working
quick path rename
Fix STM32_EMAC_BASE (and ICACHE/DCACHE Bases). Enable ETH, ETHTX, and ETHRX with CONFIG_STM32H5_ETHMAC (like H7 does).
Fixed stm32_get_uniqueid
Previously, an exception occurred as a result of calling this function. The problem turned out to be this line: uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i);. Dereferencing a 32-bit register as a 8-bit register seemed to be causing this issue. I think this function is better anyway, fewer register accesses and loop iterations.
Turn on SBS peripheral when using Ethernet
The SBS peripheral is required to be turned on because the ETH_SEL_PHY bits need to be set. Without turning this on, RMII mode is not possible. MII may not work either.
Style Updates
Summary:
When spinlock.h is enabled in a single-core scenario, spinlock reentry and exceptions may occur when spin_lock_irqsave_wo_note is used in syslog_add_intbuffer
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
This moves ARM_HAVE_PSCI selection to virtual processor level as
armv7-r chips like Cortex-R5 doesn't have it.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
These options are unistd-specific and should not be filesystem dependent,
and also not suitable for define in the sched directory.
Signed-off-by: chao an <anchao.archer@bytedance.com>
Corrected CAN FD messages sending in character driver mode.
Assign CAN FD format flag in reception of CAN FD messages.
Corrected some defines mismatches.
The code has been tested in QEMU
qemu-system-x86_64 -m 2G -enable-kvm -smp 1 \
-cpu host,+pcid,+x2apic,+tsc-deadline,+xsave,+rdrand \
-kernel nuttx/nuttx \
-nographic -serial mon:stdio \
-object can-bus,id=canbus0-bus \
-object can-host-socketcan,if=can0,canbus=canbus0-bus,id=canbus0-socketcan \
-device ctucan_pci,canbus0=canbus0-bus,canbus1=canbus0-bus
The overall state of this third party CTU CAN FD driver in NuttX
is far from ideal. It would worth to consult and follow more
closely our Linux kernel driver and even better RTEMS CAN/CAN FD
stack design
https://canbus.pages.fel.cvut.cz/#cancan-fd-subsystem-and-drivers-for-rtems
Signed-off-by: Pavel Pisa <pisa@fel.cvut.cz>
reason:
We decouple semcount from business logic
by using an independent counting variable,
which allows us to remove critical sections in many cases.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
reason:
In kernel mode, sighand_test() may failed.
because nxsig_unmask_pendingsignal may change tcb->xcp.regs,and we should update return value(regs).
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Fix a memory corruption & deadlocks while calling gran_free.
The function expects a GRAN_HANDLE as a paramter, not a pointer to it.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
In up_addrenv_kmap_pages, the MMU_MT_NORMAL_FLAGS are needed for the MMU
mappings in order for the memory & caches to function normally
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
update sensors documentation:
- add info about different sensor frameworks in one place
- fix headers style for sensors_uorb.rst: headers
- fix long lines for sensors_uorb.rst so it's possible to read this file in terminal IDE
- add code sections for sensors_uorb.rst
Signed-off-by: raiden00pl <raiden00@railab.me>
This moves ARM_HAVE_NEON from QEMU ARM family level down to the
processor level as not all processors have it (e.g. Cortex R5).
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
It was dis overed during debug of the ethernet driver that the EMAC base was incorrect. After examination, it was determined that ICACHE and DCACHE also had incorrect base addresses. This commit fixes the base addresses according to the reference manual.
