SAMV7_EMAC0_RMII should not depend on ARCH_CHIP_SAM4E as this is
a completely different chip. This is likely a relict from copying
the code base.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
- fix chip/imxrt_clockconfig_ver1.h:23: error: header guard '__ARCH_ARM_SRC_IMXRT_IMXRT_CLOCKCONFIG_VER1_H' followed by '#define' of a different macro [-Werror=header-guard]
Signed-off-by: simbit18 <simbit18@gmail.com>
the -ffunction-sections and -fdata-sections are also supported by
greenhills, and these two compile options can benefit with section
layout optimization, and thus reduce the final image size
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
According to the Greenhills documentation, the "-Wall" option is
deprecated for use. Instead, the "-ghstd=last" option is recommended.
Compared with "-Wall", the "-ghstd=last" option can capture more
warnings and has stricter rules.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
In Green Hills, if the name of the file to be preprocessed ends with ".ld",
this file must be renamed to ".ld.i". Otherwise, the following error will be reported:
ccarm: Error: -o out/build/cmake_out/mann_dcu_evb_ghs_ap/gnu-elf.ld has wrong suffix for -P option (expect .i)
Currently, based on the documentation and actual operations, only files
ending with "*.ld" can trigger this preprocessing error. There are no such
issues in other cases.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
The TLS initialization logic needs to be updated to match the modified
linker script section definitions. The previous implementation assumed
that _END_TDATA and _START_TBSS were contiguous, but there may be
padding between these sections for alignment purposes.
This commit updates up_tls_initialize() to explicitly account for the
padding gap between _END_TDATA and _START_TBSS when zeroing the .tbss
section. The size calculation in up_tls_size() is also updated to use
_END_TBSS instead of the previous _END_TXXX definition to match the
current linker script layout.
Changes:
- Calculate padding gap: (_START_TBSS - _END_TDATA)
- Zero .tbss at correct offset accounting for padding
- Update size calculation to use proper section boundaries
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
Reimplement __aeabi_read_tp using naked function with inline assembly
to strictly follow ARM EABI TLS helper specification.
The ARM EABI specifies that __aeabi_read_tp may only modify r0, and
compilers rely on this guarantee by NOT saving r1-r3 registers when
calling this function. The previous simple C implementation could
potentially clobber these registers through compiler optimizations,
violating the ABI contract and causing subtle bugs.
Changes:
- Add __aeabi_read_tp_core() helper to allow tls_get_info() macro
expansion in C context
- Explicitly preserve r1-r3 registers per EABI requirement
This ensures proper register usage compliance for all calling contexts
while maintaining the ability to use tls_get_info() macro correctly.
Reference: ARM EABI TLS Helper Specification
https://github.com/ARM-software/abi-aa/blob/main/rtabi32/rtabi32.rst#thread-local-storage-new-in-v2-01
Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com>
Ensure the CMake build explicitly locates and links libstdc++.a
when CONFIG_LIBCXXTOOLCHAIN is enabled. This aligns CMake behavior
with the Make build system and fixes STL/libc header conflicts
observed on xmc4800-relax:nsh.
Signed-off-by: trns1997 <trns1997@gmail.com>
When compiling with O2 optimization, the compiler optimizes the code
in a way that causes irq variable to be corrupted. The getipsr()
function reads IPSR into r0, but the subsequent inline assembly that
sets FPSCR also uses r0 without declaring it as clobbered. This causes
the compiler to reuse r0 for the immediate value (0x40000), overwriting
the IRQ number read from IPSR.
The issue manifests as:
- getipsr() correctly reads IPSR (e.g., 0xf for IRQ 15)
- Compiler optimizes and reuses r0 for ARM_FPSCR_LTPSIZE_NONE (0x40000)
- irq variable gets the wrong value 0x40000 instead of actual IRQ number
- This leads to assertion failures in irq_dispatch due to invalid IRQ
Root cause analysis from disassembly:
mrs r0, IPSR ; Read IPSR to r0
mov.w r0, #262144 ; Compiler overwrites r0 with 0x40000!
vmsr fpscr, r0 ; Set FPSCR
str r0, [sp, #4] ; Store corrupted 0x40000 as irq
...
ldr r0, [sp, #4] ; Load corrupted value
bl irq_dispatch ; Call with wrong IRQ number 0x40000
Fix by adding r0 to the clobber list in the inline assembly, which
forces the compiler to save irq value before using r0 for FPSCR setup.
This issue only occurs at O2 optimization level and affects ARMv8-M
architecture with FPU enabled.
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
armv8m:use ip save pc
armv7m:use ip save pc, r11 save sp
nsh_main backtrace before:
```
0 nxsem_wait_slow (sem=0x10001e0 <g_uart0port+32>) at semaphore/sem_wait.c:202
1 0x0000882c in nxsem_wait (sem=0x10001e0 <g_uart0port+32>) at semaphore/sem_wait.c:270
2 0x0000e7e2 in uart_read (filep=0x608037d4, buffer=0x60c013eb " h\024\300`", buflen=1)
at serial/serial.c:1203
3 0x0001aad4 in file_readv_compat (filep=0x608037d4, uio=0x60c01344) at vfs/fs_read.c:81
4 0x0001abae in file_readv (filep=0x608037d4, uio=0x60c01344) at vfs/fs_read.c:165
5 0x0001ac2e in nx_readv (fd=0, iov=0x60c01388, iovcnt=1) at vfs/fs_read.c:256
6 0x0001ac84 in readv (fd=0, iov=0x60c01388, iovcnt=1) at vfs/fs_read.c:318
7 0x0001acca in read (fd=0, buf=0x60c013eb, nbytes=1) at vfs/fs_read.c:352
8 0x000100ea in STUB_read (nbr=56, parm1=0, parm2=1623200747, parm3=1) at stubs/STUB_read.c:9
9 0x000014d2 in dispatch_syscall () at armv8-m/arm_svcall.c:82
```
nsh_main backtrace after:
```
0 nxsem_wait_slow (sem=0x10001f0 <g_uart0port+32>) at semaphore/sem_wait.c:202
1 0x000088c0 in nxsem_wait (sem=0x10001f0 <g_uart0port+32>) at semaphore/sem_wait.c:270
2 0x0000e882 in uart_read (filep=0x6080380c, buffer=0x60c013eb " h\024\300`", buflen=1)
at serial/serial.c:1203
3 0x0001ab74 in file_readv_compat (filep=0x6080380c, uio=0x60c01344) at vfs/fs_read.c:81
4 0x0001ac4e in file_readv (filep=0x6080380c, uio=0x60c01344) at vfs/fs_read.c:165
5 0x0001acce in nx_readv (fd=0, iov=0x60c01388, iovcnt=1) at vfs/fs_read.c:256
6 0x0001ad24 in readv (fd=0, iov=0x60c01388, iovcnt=1) at vfs/fs_read.c:318
7 0x0001ad6a in read (fd=0, buf=0x60c013eb, nbytes=1) at vfs/fs_read.c:352
8 0x0001018a in STUB_read (nbr=56, parm1=0, parm2=1623200747, parm3=1) at stubs/STUB_read.c:9
9 0x00001ece in dispatch_syscall () at armv8-m/arm_dispatch_syscall.S:111
10 0x2000a874 in read (parm1=0, parm2=0x60c013eb, parm3=1) at proxies/PROXY_read.c:9
11 0x20001152 in readline_getc (vtbl=0x60c01468) at readline_fd.c:73
12 0x20003994 in readline_common (vtbl=0x60c01468, buf=0x60c017f8 "\n", buflen=80)
at readline_common.c:513
13 0x200012ec in readline_fd (buf=0x60c017f8 "\n", buflen=80, infd=0, outfd=1) at readline_fd.c:236
14 0x200010a8 in nsh_session (pstate=0x60c01540, login=1, argc=1, argv=0x60c00548)
at nsh_session.c:229
15 0x20000eb0 in nsh_consolemain (argc=1, argv=0x60c00548) at nsh_consolemain.c:75
16 0x20000e4c in nsh_main (argc=1, argv=0x60c00548) at nsh_main.c:74
17 0x20000062 in nxtask_startup (entrypt=0x20000e11 <nsh_main>, argc=1, argv=0x60c00548)
at sched/task_startup.c:72
18 0x00009ac4 in nxtask_start () at task/task_start.c:106
19 0x60c00548 in ?? ()
Backtrace stopped: previous frame identical to this frame (corrupt stack?)
```
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
* Explicit registration of ttys0 when no console defined
* Fixes overwriting registration of lpuart1 on ttys1 when no console on ttys0
* Change regstration logic to check for console assignment
* See issue 17116
Signed-off-by: dirksavage88 <dirksavage88@gmail.com>
Previously only up to 31 PIO instructions were accepted.
But the hardware allowed 32 instructions.
Now we accept 32 instructions.
See the corresponding commit in the pico-sdk repository:
6f7dc67791
Signed-off-by: Lars Kruse <devel@sumpfralle.de>
The specific Cortex-R52 implementation could be configured with
a Single-Precision-only FPU (SP-only) and no Neon unit.
Executing double-precision instructions (e.g., `vadd.f64`) triggers
an Undefined Instruction exception.
The standard `-mfpu=fp-armv8` implicitly enables double-precision,
which is unsafe for this hardware.
`-mfpu=fpv5-sp-d16` is selected as the closest architectural match.
- It enforces Single Precision code generation (preventing crashes).
- It enables VFPv4/FPv5 features like FMA (Fused Multiply-Add) supported by the CR52 FPU.
- It restricts the register set to d0-d15, matching the hardware constraints.
This ensures the compiler utilizes hardware FPU and FMA acceleration
without emitting illegal double-precision instructions.
Signed-off-by: xiezhanpeng3 <xiezhanpeng3@lixiang.com>
Initial commit for adding rs-485 support to serial driver. More is needed as well as testing.
Style fixes.
Added unconfigure functionality.
Added Unconfigure configs to CONFIG.
More style fixes.
Changed depend spacing from 4 spaces to tab.
Fixed priv types, changed serialin to getreg.
Do not unconfigure tx/rx/dir pins by default.
Signed-off-by: kywwilson11 <kwilson@2g-eng.com>
The parameter count of read had to be a multiple of 4, otherwise the
result was truncated. Now all values are possible.
Signed-off-by: Mathias Duckeck <mathias.duckeck@avat.de>
- Fix EtherCAT signals drive strengh (from errata PORTS_CM.H002), caused bus faults.
- Changed xmc4_ecat.c for compile time pin definition.
- Fixed xmc4_ecat.c register not written (reset value already used).
- Removed EXTCLK for xmc4800 as pin is used for ECAT.
- Clean xmc4 familly board.h and clocks config.
Signed-off-by: adriendesp <adrien.desproges@gmail.com>
This commit adds support for SPI_SETDELAY operation on SAMv7 QSPI
peripheral running in SPI mode. The logic is the same as for standard
SPI peripheral, just different registers. The change allows to set
custom delays between transfers, chip selects and so on.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
During I2C read, one-too-many byte is read, which can lead to the I2C bus
getting stuck. This is likely due to the STOP condition being set at the
wrong time or being missed completely. The chip offers a shortcut, such
that the STOP condition is set automatically after the last byte is being
written/read.
Signed-off-by: Max Kriegleder <max.kriegleder@gmail.com>
When TICKLESS not enabled, up_alarm_set_lowerhalf will call start, if we
overwrite the compare register will cause TICK mode no longer isr.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
In multi-core environment where NuttX runs on each core, if one core
sets the RTC time, the RTC value gotten on other cores is incorrect.
This is caused by clock_gettime(CLOCK_MONOTONIC) function used to get
elapsed time, which uses a core-specific global varaiable g_basetime
as the base time.
To fix this, update the g_basetime from the backup SRAM that can be
shared between cores in setting/getting the RTC time.
Signed-off-by: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
