arch/arm/include/imx6/irq.h looks to originally be for i.MX6 Quad
and includes multiple (re)definitions of IRQ names, some of which are
different or don't exist on i.MX6 SoloLite/Solo/Dual/DualLite.
Update irq.h to specify/reserve IRQ names/numbers as defined by the
IM6SDLRM, IMX6DLRM, and IMX6DQRM reference manuals.
Signed-off-by Peter Barada <peter.barada@gmail.com>
The struct stm32_mdio_bus_s aka g_stm32_mdio_bus
has not been referenced at all, because mdio_register()
allocates its own structure. Then lower half drivers
receive only their respective part in mdio_read()
and mdio_write() because MDIO_WRITE/MDIO_READ provides
only d->lower to the specific lower level drivers.
Signed-off-by: Pavel Pisa <pisa@fel.cvut.cz>
arm_dispatch_syscall in armv7-m clobbered r11 with 'mov r11, sp' and the
user-space callee-saved register value leaked back through the exception
frame when SYS_syscall_return restored the context, resulting in corrupted
parameters on subsequent syscalls and system hangs in protected builds.
In armv6-m, r4 was used to load g_stublookup (Thumb-1 cannot use ip for
indexed addressing) but was not restored before SYS_syscall_return,
causing the same class of register corruption.
Fix with minimal changes:
- armv7-m: remove 'mov r11, sp' to stop clobbering user r11
- armv6-m: restore r4 from the stack frame before SYS_syscall_return
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
debug.h is a NuttX-specific, non-POSIX header. Placing it in the
top-level include/ directory creates naming conflicts with external
projects that define their own debug.h.
This commit moves the canonical header to include/nuttx/debug.h,
following the NuttX convention for non-POSIX/non-standard headers,
and updates all in-tree references.
A backward-compatibility shim is left at include/debug.h that
emits a deprecation #warning and re-includes <nuttx/debug.h>,
allowing out-of-tree code to continue building while migrating.
Signed-off-by: Piyush Patle <piyushpatle228@gmail.com>
Use static lower-half instances per timer and select the channel
through Kconfig and board data instead of passing runtime PWM
routing into the driver.
This keeps the HT32 PWM support aligned with the existing NuttX
pattern and documents the esk32 single-device TMR3 routing.
Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
Document the HT32F491x3 ESK32 board, build steps,
flashing flow, and validation commands. Add WSL and
PowerShell flash backends plus a Python wrapper.
Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
Add initial HT32F491x3 support with startup, IRQ handling,
serial console, GPIO helpers, custom vectors, and CMake build files.
Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
include/cxx contains NuttX's mini C++ ABI shims and must only be added
to the include path when CONFIG_LIBMINIABI is selected. tools/Config.mk
was adding it unconditionally for every non-LIBCXX/non-UCLIBCXX build,
and the platform.cmake files for arm, arm64, risc-v, x86_64 and tricore
were adding it inside the CONFIG_LIBCXXTOOLCHAIN block.
With an unpatched downloaded ARM GNU Toolchain, <cstdlib> uses
newlib's stdlib.h, defining div_t as an anonymous struct. A later
inclusion of NuttX's stdlib.h via <cstdio>->stdio.h->kmalloc.h then
redefines div_t with struct tag div_s, causing a conflicting declaration
error.
Guard the div_t/ldiv_t/lldiv_t definitions in stdlib.h with
redefinitions when a toolchain stdlib.h was already processed.
Also fix lldiv_s members typed as long instead of long long.
Signed-off-by: trns1997 <trns1997@gmail.com>
When a developer working on BSP wants UART1 with RTS, the following
needs to be added in the BSP's include/board.h file:
#define PIN_UART1_RTS PIN_UART1_RTS_1
which says that PIN_UART1_RTS_1 -- the first alternative pin with UART1
RTS function -- should be used for the UART1's RTS.
There are no alternative pins for PIN_UART2_RTS, therefore a similar
definition is not used for PIN_UART2_RTS.
However, that is a complication when we want PIN_UART2_RTS to be defined
as GPIO, for example:
#define PIN_UART2_RTS (GPIO_OUTPUT | PIN_PORTB | PIN2)
In such a case, PIN_UART2_RTS is later redefined to the only alternative
function from hardware/kinetis_???pinmux.h file.
This patch avoids the redefinition of already defined names.
We considered renaming PIN_UART2_RTS to PIN_UART2_RTS_1 in the
hardware/kinetis_???pinmux.h file, but that is breaking change. We try
to avoid breaking change.
Signed-off-by: Jiri Vlasak <jvlasak@elektroline.cz>
Because it is not needed anymore.
The original code here is from the initial implementation in the commit
66b873ef77.
Signed-off-by: Jiri Vlasak <jvlasak@elektroline.cz>
When using CONFIG_UART?_RS485CONTROL, RTS pin is set high when sending
data and low otherwise. PIN_UART?_RTS is defined in the board.h file as
the appropriate ALT functionality of the chip's port.
However, it may happen that PIN_UART?_RTS is wired to another pin of the
chip that does not support the RTS as ALT functionality of the UART? in
question. This commit addresses such a situation.
When UART?_RS485CONTROL_RTSISGPIO is set in menuconfig for the given
UART?, it is expected that the PIN_UART?_RTS is defined as GPIO_OUTPUT,
and the PIN_UART?_RTS is set high when sending data and low otherwise.
Signed-off-by: Jiri Vlasak <jvlasak@elektroline.cz>
Rename STM32_IRQ_NEXTINT to STM32_IRQ_NEXTINTS across all stm32
variants.
In stm32_dumpnvic() dynamically print NVIC enable and priority
registers based on STM32_IRQ_NEXTINTS.
Use PRIx32 format specifier instead of 'x' (since uint32_t on arm is
actually a long unsigned int).
Simplify if/else chain in stm32_irqinfo() to determine irq reg/bit.
There's no stm32_irqinfo.c; remove mention in stm32f0l0g0/Make.defs.
Signed-off-by Peter Barada <peter.barada@gmail.com>
When using a dummy memory address in DMA LLI transfers,
do not update the memory address.
Signed-off-by: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
Fix adc_oversample() where priv->trovs (a bool, 0 or 1) was OR'd
directly into setbits instead of using ADC_CFGR2_TROVS (bit 9).
This caused triggered oversampling to never actually be enabled.
Fix ANIOC_WDOG_UPPER and ANIOC_WDOG_LOWER ioctls where the TR1
register was overwritten with only the new threshold value, zeroing
out the opposite threshold and the AWDFILT digital filter bits.
Use read-modify-write to preserve the other fields.
Signed-off-by: kywwilson11 <kwilson@2g-eng.com>
Rename IMX9_IRQ_uSDHC{1,2,3} to IMX9_IRQ_USDHC{1,2,3} in both arm
and arm64 imx95_irq.h to follow the all-caps naming convention used
by imx93_irq.h and the rest of the NuttX codebase. Remove the now
unnecessary USDHC IRQ alias block from arm64 imx95_irq.h.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Correct duplicate "is is" word found in 181 files throughout the
codebase.
In most cases "is is" was changed to "is", but in contexts like
"MCU is is sleep mode" it was corrected to "MCU in sleep mode".
Also fixes a "the the" typo in net/inet/inet_sockif.c.
This is a pure style/documentation fix that improves code readability.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Fix 269 occurrences of duplicate "the" word typo found in 209 files
across source code, header files, and configuration.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Add nxboot bootloader board integration for nucleo-h743zi.
nxboot uses a three-slot layout (primary, secondary, tertiary) with
no scratch partition.
- add STM32_APP_FORMAT_NXBOOT board support and nxboot-specific OTA
slot defaults
- gate scratch partition configuration on MCUboot, where it applies
- select nxboot linker scripts in the board build logic
- add tertiary OTA partition support in stm32_progmem.c
- add nxboot-loader and nxboot-app defconfigs and linker scripts
- validate the fixed nxboot flash layout used by this board so
mismatched config values fail at build time instead of producing
a silently broken image
Signed-off-by: Neil Berkman <neil@xuku.com>
Three fixes to make LPUART1 work as NSH console on Nucleo-L552ZE-Q:
1. stm32l5_lowputc: add LPUART-specific BRR formula (256 * fCK / baud)
instead of reusing the standard USART divisor calculation.
2. stm32_boot: enable VDDIO2 and reconfigure LPUART1 GPIOs (PG7/PG8)
in board_initialize. The low-level setup runs before VDDIO2 is
enabled, so GPIOG writes silently fail.
3. stm32l5_serial: fix LPUART1 apbclock (PCLK1 not PCLK2), add
LPUART BRR branch in setformat, cast to uint64_t to prevent
32-bit overflow in (fCK << 8).
Also switch nsh defconfig from USART3 to LPUART1, add GPIO_LPUART1
pin definitions in board.h, and update board documentation.
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Add definition to setup appropriate reduced SRAM sizes
CONFIG_STM32H7_STM32H72XXX_OR_STM32H73XXX.
The define should make addition of other STM32H72X
and TM32H73X chips easier.
Signed-off-by: Pavel Pisa <pisa@fel.cvut.cz>
GPIO PIN base address calculation had double right shift, thus call
to SAM_PION_BASE was always with port = 0 instead of correct port
number. As a result, function sam_gpioirq didn't correctly configure
additional interrupt modes (only rising or falling edge and level
interrupts).
The issue occured on SAMv7 and SAM34 platforms (likely copy-pasted
from one to another).
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Add hardware register headers and driver support for the NXP i.MX93
Cortex-M33 core. All new and modified code is guarded by
ARCH_CHIP_IMX93_M33 preprocessor defines; existing i.MX95-M7 builds
are unaffected.
New drivers:
- imx9_xcache.c - off core cache init and maintenance
- imx9_ccm.c - generic CCM abstraction layer
Signed-off-by: Maarten Zanders <maarten@zanders.be>
Rename imx95_mu_* functions to imx9_mu_*, decoupling the MU driver
API from the iMX95-specific naming in preparation for iMX93-M33
support.
Add ARCH_CHIP_IMX95_M7 dependency to the MU instance Kconfig entries
so they are only visible for the appropriate target.
Switch imx9_mu.c to include the generic imx9_memorymap.h instead of
the imx95-specific header.
Fix incorrect help text for MU8 (was copy-pasted from MU5).
Signed-off-by: Maarten Zanders <maarten@zanders.be>
Extract chip-specific constants from imx9_rptun.c and imx9_rsctable.c
into new dispatch headers:
- hardware/imx9_rsctable.h: VDEV0_VRING_BASE and RESOURCE_TABLE_BASE,
selected per ARCH_CHIP define
- hardware/imx9_rptun.h: MU_INSTANCE, selected per ARCH_CHIP define
Rename the misnamed VRING_SHMEM constant in imx9_rptun.c to
RESOURCE_TABLE_BASE, which correctly reflects that this address points
to the resource table, not the vring shared memory region.
No functional change for i.MX95-M7 builds.
Signed-off-by: Maarten Zanders <maarten@zanders.be>
Use NVIC_IRQ_ENABLE(n) and NVIC_IRQ_PRIORITY(n) macros in
imx9_dumpnvic() to iterate over all NVIC registers programmatically
based on CONFIG_ARCH_NINTS (IMX9_IRQ_NEXTINT), rather than
enumerating named per-range register defines. Output is grouped
4-per-line for priority and 4-per-line for enable registers,
matching the original layout.
This avoids accessing registers which don't exist when extending
the interrupt count.
Also replace named NVIC_IRQxx_yy_ENABLE constants in imx9_irqinfo()
with NVIC_IRQ_ENABLE(n), avoiding naming conflicts between chips
with different IRQ counts.
Fix the upper boundary in the >192 IRQ branch from 219 to 224 to
align with the 32-interrupt register granularity.
Change %08x to %08lx to silence warnings from the compiler for
the debug dump.
No functional change for existing i.MX95-M7 builds.
Signed-off-by: Maarten Zanders <maarten@zanders.be>
The GPIO mux range check in imx9_iomux_gpio() used a hardcoded
IOMUXC_MUX_CTL_GPIO_IO37_OFFSET as the upper bound, which is
i.MX95-specific. Move the define to imx95_iomuxc.h as an alias of
the last GPIO_IO entry, and use the named constant in the comparison.
No functional change; i.MX95 builds are unaffected.
Signed-off-by: Maarten Zanders <maarten@zanders.be>
- Guard imx9_gpc.h inclusion with CONFIG_IMX9_WFI_AWAKES_AT_SYSTICK
to avoid a GPC dependency on chips that lack GPC
- Add depends on ARCH_CHIP_IMX95_M7 to IMX9_WFI_AWAKES_AT_SYSTICK
since GPC wake configuration is i.MX95-specific
- Move XTAL_FREQ and ROOT_CLOCK_OFFSET defines to imx95_clock.h
- Make imx9_sm_setrootclock() and imx9_sm_getipfreq() static;
they are not referenced outside this translation unit
Signed-off-by: Maarten Zanders <maarten@zanders.be>
When testing tickless scheme with default arm_systick.c, we found the
count writed to systick register is too smaller the expected, just the
ticks not count, and os runing abnormally with too much interrupter.
Add necessary coversion, then system run well.
Signed-off-by: taoliu <taoliu@asrmicro.com>
Changes the default value for CONFIG_BOARD_LOOPSPERMSEC to -1, which is
invalid. All boards that forget to configure this value will encounter a
static assertion at compile time, enforcing that configurations
upstreamed to NuttX have calibrated values for correct delay timings.
Boards which implement ALARM_ARCH or TIMER_ARCH do not rely on the
busy-loop delay implementation and thus only have a run-time check to
ensure proper delay-timings (in the case where delays are used before
the alarm/timer driver is registered).
Some boards already in the NuttX upstream do not have calibrated values,
but there are no users who currently own the board to submit a
calibrated value for the configurations to use. In this scenario, the
value is temporarily set to 0 and a warning is displayed so that users
of these boards are informed of the calibration process.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
