Add a Peripheral Support section to the board page listing the GPIO and
MCU_MCSPI0 drivers, and replace the "UART console only" warning on both
the chip and board pages -- it no longer describes the port. The
replacement states what actually constrains the port: NuttX runs on the
R5F under RemoteProc and depends on the bootloader or Linux Device
Manager having powered and clocked the peripherals, because there is no
TISCI client yet.
Assisted-by: Claude Code:claude-opus-5
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Allow sim HCI socket users to select the host-side HCI target at runtime
with --bt-dev. Passing --bt-dev=hciN overrides CONFIG_SIM_HCISOCKET_DEVID
for the BlueZ HCI user channel, while omitting the option keeps the existing
configured default behavior.
Also allow --bt-dev=/path/to/socket to connect to an H:4 stream exposed
through a Unix-domain socket. This lets sim applications use a controller
provided by another host process or by a UART-to-Unix-socket bridge without
requiring BlueZ raw HCI privileges for the NuttX process.
Use host-side output for early --bt-dev parse errors, since NuttX stdio is
not initialized before nx_start().
Document the BlueZ and Unix socket modes, including the capability
requirements for BlueZ and the socat bridge example for Unix socket mode.
Testing:
Host: Ubuntu 22.04 x86_64
Board/config: sim:bthcisock
Style checks:
git diff --check HEAD~2..HEAD
PATH=/home/mi/bsim-auto-test/.venv/bin:$PATH \
./tools/checkpatch.sh -c -u -m -g HEAD~2..HEAD
Clean build:
make distclean
./tools/configure.sh -l -a ../../nuttx-apps sim:bthcisock
kconfig-tweak --file .config --set-val STACK_USAGE_WARNING 0
make olddefconfig
make -j16
Invalid runtime argument smoke test:
./nuttx --bt-dev=invalid
Verified the command exits with status 1 and reports the invalid target
without crashing before nx_start().
Unix socket HCI smoke test:
socat -d -d UNIX-LISTEN:/tmp/hci.sock,fork,reuseaddr \
/dev/ttyACM2,b1000000,raw,echo=0,crtscts=1
printf 'ifconfig\nbt bnep0 info\npoweroff\n' | \
timeout 20s ./nuttx --bt-dev=/tmp/hci.sock
Verified the sim registers the Bluetooth network device as bnep0 and
bt bnep0 info reads the controller state through the Unix-socket HCI
path, including BDAddr aa:bb:cc:dd:ee:ff from the attached controller.
Assisted-by: OpenAI Codex
Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
Add support for using a BabbleSim PHY as the monotonic time source for
the Linux sim target. When CONFIG_SIM_BSIM_TIME is enabled, the sim
host build links a small host-side time helper against the BabbleSim
PhyCom and Util libraries. The helper joins the BabbleSim PHY wait
protocol and advances NuttX monotonic time through PB_MSG_WAIT requests
instead of Linux wall-time sleeps.
A SIM binary built with CONFIG_SIM_BSIM_TIME enabled joins BabbleSim time
at startup. Runtime options allow the test runner to select the
BabbleSim simulation id, PHY id, and device number:
--sim-bsim-sid=<simulation-id>
--sim-bsim-pid=<phy-id>
--sim-bsim-dev=<device-number>
Keep the integration inside the sim host time path rather than exposing
a new application API. RTC/realtime reads still use the host realtime
clock; the BabbleSim source is used only for monotonic time after the sim
has joined the PHY. The Kconfig option depends on the sleep based
walltime mode and is disabled for SMP and non-Linux hosts.
The build requires BSIM_COMPONENTS_PATH for headers and either
BSIM_OUT_PATH or BSIM_LIBS_DIR for shared libraries. The path checks are
skipped for clean, distclean, clean_context, and context targets so a
tree with CONFIG_SIM_BSIM_TIME enabled can still be cleaned without
exporting the BabbleSim environment first.
Document the configuration, build environment, runtime options, and the
requirement that the BabbleSim PHY process is started separately by the
test runner.
Testing:
Host: Ubuntu 22.04 x86_64
Board/config: sim:nsh
Style check:
git diff --check
Default sim build and smoke test:
./tools/configure.sh -l -a ../nuttx-apps sim:nsh
make -j16
printf 'help\npoweroff\n' | timeout 20s ./nuttx
BabbleSim-enabled build:
kconfig-tweak --file .config \
-e SIM_WALLTIME_SLEEP \
-d SIM_WALLTIME_SIGNAL \
-e SIM_BSIM_TIME
make olddefconfig
BSIM_OUT_PATH=/tmp/bsworld/build/babblesim/bsim \
BSIM_COMPONENTS_PATH=/tmp/bsworld/build/babblesim/bsim/components \
make -j16
Verified actual BabbleSim PHY time integration without a controller by
starting bs_2G4_phy_v1 and running NSH usleep through the PHY wait
barrier:
bs_2G4_phy_v1 -s=<sid> -D=1 -defmodem=BLE_simple -nodump
printf 'usleep 1000000\npoweroff\n' | \
./nuttx --sim-bsim-sid=<sid> \
--sim-bsim-pid=2G4 \
--sim-bsim-dev=0
The same 1 second simulated sleep completed in 19 ms wall time when no
handbrake device was present. With handbrake registered as device 1:
bs_2G4_phy_v1 -s=<sid> -D=2 -defmodem=BLE_simple -nodump
bs_device_handbrake -s=<sid> -p=2G4 -d=1 -pp=50000 -r=1
the same NuttX usleep test completed in 985 ms wall time. A shorter
200 ms check showed the same behavior: 27 ms without handbrake and
172 ms with handbrake. This verifies that NuttX sim time advances
through the BabbleSim PHY and that the handbrake affects the NuttX sim
device.
Also verified make distclean succeeds after CONFIG_SIM_BSIM_TIME was
enabled and without exporting BSIM_COMPONENTS_PATH.
BSWorld out-of-tree native BLE examples:
./tools/configure.sh -l /path/to/bsim-auto-test/tests/nuttx/native_ble/source/advertiser/config
make -j16
exodus --tarball -o /path/to/bsim-auto-test/tests/nuttx/native_ble/source/advertiser/prebuilt/nuttx.tgz nuttx
./tools/configure.sh -l /path/to/bsim-auto-test/tests/nuttx/native_ble/source/scanner/config
make -j16
exodus --tarball -o /path/to/bsim-auto-test/tests/nuttx/native_ble/source/scanner/prebuilt/nuttx.tgz nuttx
pytest tests/nuttx/native_ble -q --no-ellisys
Assisted-by: OpenAI Codex
Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
bitbucket.org/nuttx/buildroot returns 404, as does every other repository
under that Bitbucket organisation. The buildroot that still carries the
NuttX toolchain, ldnxflat included, is github.com/patacongo/buildroot.
Thirty three files carried the dead address, most of them as a "Bitbucket
download site" for a board's toolchain. There are no downloads to offer, so
those now name the repository, and the surrounding prose says so.
The other dead Bitbucket addresses are left alone: nuttx/nuttx, nuttx/tools,
nuttx/uclibc and nuttx/nxwidgets need a decision each about what replaces
them, which is not this patch. patacongo/obsoleted is still there.
Assisted-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
Add a "fastboot_usb" section to the waveshare-rp2040-zero and
waveshare-rp2040-lcd-1.28 board doc pages, describing the USB fastboot
composite configuration added by the previous commits: fastbootd runs
on boot instead of NSH, composed together with CDC/ACM for the
console, and reachable on the host via fastboot devices/getvar/reboot.
Assisted-by: OpenCode:claude-sonnet-5
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Drives the speed of the four application cores. The rate is set to any
of the operating points the vendor validates, all of which share a core
voltage, so this touches no regulator.
The cores run from the PLL being reprogrammed, so they park on a slower
clock first, through a selector the vendor names as glitch free. While
parked the PLL is stopped, given new dividers, restarted and watched
until it locks; if it never locks the cores stay parked, since returning
them to an unlocked PLL does not fail safely.
Above a gigahertz the bus ratio must be two to one before the cores
return: the bus fabric does not reach beyond about eight hundred
megahertz. That is the one step in the sequence software cannot recover
from, so the mux is moved before the ratio.
The rate is measured rather than derived. The cores are counted against
the crystal derived time counter and the result reported beside what the
clock tree computes, because the manual and the vendor's code number the
CPU PLL's outputs differently. The core selector's parent is
cpupll_fout1, and the three CPU PLL outputs are marked
CLK_GET_RATE_NOCACHE since this driver reprograms that PLL at run time.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Justin Hammond <justin@dynam.ac>
Add a Testing section for sim:tflm and document Makefile tflm_hello,
AllocateTensors, and generic ops so the in-tree docs match the apps
TFLM changes.
Assisted-by: Cursor:Grok-4.6
Signed-off-by: Abhishek Mishra <mishra.abhishek2808@gmail.com>
The apps tree is apps/mlearning, but documentation lived under the
misspelled mlearing path as title-only stubs. TensorFlow Lite Micro and
standalone CMSIS-NN had no pages.
Rename the directory to mlearning, document each package from the
current Kconfig and build files, and add the sim:tflm board
configuration.
Assisted-by: Cursor:Grok-4.6
Signed-off-by: Abhishek Mishra <mishra.abhishek2808@gmail.com>
Wire the RTL8721F (amebagreen2) into the shared Ameba timer driver
(arch/arm/src/common/ameba/ameba_timer.c), registered at /dev/timer0
(TIM1) and /dev/timer1 (TIM2). Only the per-chip base addresses, RCC
masks and IRQs differ, so this adds a small ameba_timer_chip.h (the two
32-bit basic LTIM timers at 0x40819200 / 0x40819400, 32.768 kHz,
APBPeriph_LTIM1/2, IRQ_TIMER1/2, verified against the SoC hal_platform.h
/ sysreg_lsys.h / vector table) plus the Make.defs/CMakeLists build
hooks, the fwlib ram_common/ameba_tim.c RAM source (now also pulled in
by CONFIG_AMEBA_TIMER, matching the PWM rule), the board bring-up
registration and a timer defconfig. The shared driver is unchanged.
TIM0 is left untouched because the boot ROM claims it as the always-on
system timer; reprogramming it would break every SDK delay.
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Wire the RTL8720F into the shared Ameba timer driver
(arch/arm/src/common/ameba/ameba_timer.c), registered at /dev/timer0
(TIM1) and /dev/timer1 (TIM2). Only the per-chip base addresses, RCC
masks and IRQs differ, so this adds a small ameba_timer_chip.h (the two
32-bit basic LTIM timers at 0x40808200 / 0x40808400, 32.768 kHz,
APBPeriph_LTIM1/2, IRQ_TIMER1/2, verified against the SoC hal_platform.h
/ sysreg_lsys.h / vector table) plus the Make.defs/CMakeLists build
hooks, the fwlib ram_common/ameba_tim.c RAM source (now also pulled in
by CONFIG_AMEBA_TIMER, matching the PWM rule), the board bring-up
registration and a timer defconfig. The shared driver is unchanged.
TIM0 is left untouched because the boot ROM claims it as the always-on
system timer; reprogramming it would break every SDK delay.
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Add a parameterised NuttX timer lower-half for the Realtek Ameba
general-purpose timers, sitting on the SDK fwlib RTIM register layer and
registered at /dev/timerN. The shared driver
(arch/arm/src/common/ameba/ameba_timer.c) reads a per-chip instance
table (ameba_timer_chip.h) for each timer's base, input clock, RCC gate
masks and IRQ; the period is programmed directly in microseconds and
converted to the 32-bit auto-reload with one clkfreq formula.
On the pke8721daf two of the 32.768 kHz "basic" (LTIM) timers are
exposed: /dev/timer0 is TIM1 and /dev/timer1 is TIM2. TIM0 is left
untouched because the boot ROM claims it as the always-on system timer
(SYSTIMER); reprogramming it would break every SDK delay. The RTIM
time-base entry points resolve to ROM, while the interrupt-clear and
period-change helpers come from the fwlib RAM source ameba_tim.c (shared
with the PWM driver).
Verified on hardware with examples/timer against both devices: the
update interrupt fires at the requested 1 s interval (measured with the
independent ROM SYSTIMER = 32768 ticks = 1.000 s).
Also whitelist the vendor RTIM_ symbol prefix in tools/nxstyle.c,
alongside the existing RCC_/SYSTIMER_ Ameba SDK entries.
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
The Tab5 ships in two hardware variants and the board supported only
one of them. The earlier units carry an ILI9881C panel and a GT911
touch controller, the later ones a ST7121/ST7123 panel and a ST7123
touch controller, and the two always come as a pair. On an earlier
unit the panel stays lit but black, and the touch bring-up fails with
"failed to register ST7123: -5".
Add the ILI9881C initialization table, taken from the Espressif BSP,
along with the display timings it needs, which differ from the ST7123
ones in the DPI clock (60 MHz instead of 70 MHz) and in every porch.
The panel identification lives on command page 1 and is read and
logged during bring-up, so the boot log says which panel answered.
Add the GT911 to the touch controller choice. These units have a
pull-up to 3V3 on the touch interrupt line that keeps the controller
from scanning, so the line is driven low instead of being used as an
interrupt, and contacts are picked up when the device is read. The
controller identification is logged the same way.
Split esp32p4_touch.c into one file per controller, which is how the
panels are already handled, and document both variants together with
the I2C scan that tells which one is fitted. The defaults are
unchanged, so an existing configuration still selects the ST7121
panel and the ST7123 touch controller.
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
Adopt the zbus message bus on the linum-stm32h753bi (first adopter
board):
- scripts/flash.ld: include the iterable sections common fragments
(2 lines: common-rom.ld inside .text, common-ram.ld inside .data).
- configs/zbus/defconfig: board configuration enabling zbus with all
observer types, the zbus example and its cmocka test suite
(./tools/configure.sh linum-stm32h753bi:zbus).
- Board documentation: describe the new configuration.
Validated on hardware: the 16-test cmocka suite passes twice in the
same boot and the zbus example produces the expected output.
Assisted-by: Claude Code
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
This commit introduces EDID reading and parsing to the JZ4780 display
driver, replacing hardcoded resolution limits with dynamic mode selection
based on the connected display's capabilities.
Specific changes include:
- Implemented I2C DDC master communication for the HDMI controller to
read EDID blocks from monitors.
- Added dynamic mode selection to calculate bandwidth and pick the best
supported resolution, prioritizing the EDID preferred mode.
- Dynamically allocated framebuffer bounds (g_planeinfo and g_videoinfo)
based on parsed EDID dimensions.
- Configured GPIO pin multiplexing for HDMI power, DDC, and control pins
(POWER_EN, CEC, SCL, SDA) to enable display power and communication
on the CI20 board.
Signed-off-by: Lwazi Dube <lwazeh@gmail.com>
Wire the RTL8721F (amebagreen2) into the shared Ameba watchdog driver
(arch/arm/src/common/ameba/ameba_wdg.c), registered as /dev/watchdog0.
Only the per-chip base address and IRQ differ, so this adds a small
ameba_wdg_chip.h (WDG2 non-secure system watchdog at 0x4080AD80,
CPU0_NS_WDG IRQ 69, verified against the SoC hal_platform.h and
ameba_vector_table.h) plus the Make.defs/CMakeLists build hooks, the
board bring-up registration, and a wdg defconfig. The shared driver is
unchanged.
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Wire the RTL8720F into the shared Ameba watchdog driver
(arch/arm/src/common/ameba/ameba_wdg.c), registered as /dev/watchdog0.
Only the per-chip base address and IRQ differ, so this adds a small
ameba_wdg_chip.h (WDG2 non-secure system watchdog at 0x40801D80,
KM4TZ_NS_WDG IRQ 52, verified against the SoC hal_platform.h and
ameba_vector_table.h) plus the Make.defs/CMakeLists build hooks, the
board bring-up registration, and a wdg defconfig. The shared driver is
unchanged.
Also corrects the RTL8720F row in the rtl8721dx chip-header reference
table (the non-secure system WDG IRQ is KM4TZ_NS_WDG = 52).
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Add a NuttX watchdog lower-half for the Ameba KM4 non-secure system
watchdog (WDG2), registered as /dev/watchdog0. The fwlib WDG API is
ROM-resident, so no board.mk change is needed.
The hardware cannot be stopped once enabled, so stop() is emulated via
the early interrupt (EI) auto-refreshing the counter, and capture()
delivers a pre-timeout callback through the same EI. The EI has a
three-part timing contract, all handled here: it must be armed with
EIMOD=ENABLE at WDG_Init, its EIE gate only takes effect after
WDG_Enable, and -- because the EI is level-based -- a pure capture path
must mask EIE after the one-shot callback to avoid re-entrant storming
while the reset is pending. The EI flag is cleared twice per the slow
WDG clock.
Per-chip base address and IRQ live in ameba_wdg_chip.h so the shared
driver needs no change to port to another Ameba IC.
Verified on pke8721daf: timeout reset (BOOT REASON WDG2), stop()
suppressing the reset, and capture() firing ~EICNT ms before the reset.
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Wire the shared Ameba RTC driver (arch/arm/src/common/ameba/ameba_rtc.c)
into RTL8721F (amebagreen2). The driver is chip-agnostic and reads only
per-chip macros from ameba_rtc_chip.h; RTL8721F differs from amebadplus
only in the RTC interrupt vector (RTL8721F_IRQ_RTC, vector 41). The
APBPeriph_RTC masks and RTC_BASE_YEAR (1900) are identical across all
current Ameba chips.
- ameba_rtc_chip.h: per-chip RTC IRQ / clock masks / base year
- Make.defs, ameba_board.mk: compile ameba_rtc.c and the fwlib RAM
RTC source when CONFIG_AMEBA_RTC=y
- board: rtl8721f_rtc.c registers /dev/rtc0 from bringup
- configs/rtc: examples/alarm profile
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Wire the shared Ameba RTC driver (arch/arm/src/common/ameba/ameba_rtc.c)
into RTL8720F. The driver is chip-agnostic and reads only per-chip macros
from ameba_rtc_chip.h; RTL8720F differs from amebadplus only in the RTC
interrupt vector (RTL8720F_IRQ_RTC, vector 33). The APBPeriph_RTC masks
and RTC_BASE_YEAR (1900) are identical across all current Ameba chips.
- ameba_rtc_chip.h: per-chip RTC IRQ / clock masks / base year
- Make.defs, ameba_board.mk: compile ameba_rtc.c and the fwlib RAM
RTC source when CONFIG_AMEBA_RTC=y
- board: rtl8720f_rtc.c registers /dev/rtc0 from bringup
- configs/rtc: examples/alarm profile
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Expose the Ameba on-chip RTC as a NuttX date/time RTC at /dev/rtc0
(rdtime/settime) with a single one-shot alarm (setalarm/rdalarm/
cancelalarm/setrelative) that fires the RTC interrupt and the upper-half
callback. The same hardware also backs the arch date/time RTC hooks
(up_rtc_initialize/getdatetime/settime, g_rtc_enabled) so the NuttX
system time is seeded from it.
The driver sits on the SDK fwlib RTC API (mirrored structures + local
externs, no vendor headers pulled into the NuttX include world). The
fwlib RTC API lives in the RAM source ameba_rtc.c, so it is added to the
board fwlib build under CONFIG_AMEBA_RTC. The hardware keeps a year plus
a day-of-year (no month/day register); the driver bridges that to the
NuttX month/day calendar with the libc UTC routines (timegm/gmtime_r),
which is exact and reversible.
The only per-chip fact -- the RTC interrupt vector -- lives in the
per-chip ameba_rtc_chip.h; the shared driver is never edited for a new
Ameba chip. A configs/rtc profile (examples/alarm) is added for
verification.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
List every peripheral implemented by STM32U3C5, and update the common GPIO, EXTI
and USART driver paths after the Cortex-M33 migration.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Add an NXTerm framebuffer configuration for QEMU and Intel64 hardware.
Enable USB keyboard input, PCI serial logging, CPython, and serial fallback.
Signed-off-by: raiden00pl <raiden00@railab.me>
Add HSI48 clock selection, USB pull-up control, automatic CDC/ACM registration during board bring-up, USB test configurations, and board documentation.
Assisted-by: OpenAI Codex
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
Wire the shared Ameba ADC driver into the RTL8721F build: add the
per-chip ameba_adc_chip.h (12 channels, CH0..CH7 external on
PA20,PA19,PA18,PA17,PA15,PA14,PA13,PA12, PINMUX function 5), the
board ADC table and registration, the adc board config, and build
glue for both cmake and make (including the fwlib RAM-layer
ameba_adc.c in ameba_board.mk). Document the ADC on the board index.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Wire the shared Ameba ADC driver into the RTL8720F build: add the
per-chip ameba_adc_chip.h (9 channels, CH0..CH5 external on
PA13..PA18, PINMUX function 5, APB clock on bit24), the board ADC
table and registration, the adc board config, and build glue for
both cmake and make (including the fwlib RAM-layer ameba_adc.c in
ameba_board.mk). Document the ADC on the board index.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Add a NuttX ADC lower-half for the Ameba SoC family, wired for the
amebadplus/pke8721daf as /dev/adc0. The driver uses the fwlib ROM
API and drives on-demand polled conversions via ADC_ReceiveBuf with
the hardware auto channel-switch FIFO, because amebadplus disables the
ADC software-trigger path. Per-chip wiring (channel count, pinmux
function id, APB clock bits, optional aux clock) lives in a chip
header so a new IC only supplies its own values without touching the
shared driver.
Reports raw conversion codes per the NuttX convention (12-bit
effective, 0..~3876 for 0..3.3V), consistent with the STM32/i.MXRT/
Tiva ADC drivers.
Verified on hardware: 0V->121, 3.3V->3876 on CH0(PB19) while
CH1(PB18) held steady, confirming sampling, full-scale and
multi-channel switch-list isolation.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Document the USART2 NSH console, USB FS pins, HSI48/CRS clock source and
the usb-cdc configuration that exposes a separate USB CDC/ACM serial
device.
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
Adds reference to the sdmmc_spi defconfig of esp32p4-tab5, with mounting
instructions for the SD Card.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Update the MIPS Creator CI20 board documentation to include a detailed
peripherals support table. This replaces the basic bulleted list with
comprehensive status details for CPU cores, RAM, Display, Ethernet,
GPIO, TRNG, Timers, UART0, USB Host, and Watchdog.
Signed-off-by: Lwazi Dube <lwazeh@gmail.com>
Document the usb-cdc-uart configuration, which keeps NSH on the USART2
ST-LINK virtual COM port and exposes a separate USB CDC/ACM serial
device on the STM32 USB FS connector.
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
Add initial Apache NuttX support for the Allwinner D1 / T-Head C906
running in supervisor mode under OpenSBI.
Add support for:
- RV64 D1 architecture definitions
- Lichee RV 86 Panel board configuration
- UART0 console at 115200 baud
- D1 PLIC interrupt controller
- native D1 Timer1 scheduler tick
- early inherited-watchdog disable
- FLAT S-mode NSH configuration
The port has been tested on physical Sipeed Lichee RV / 86 Panel
hardware and boots to an interactive NuttShell.
The scheduler tick uses OSC24M Timer1 at 1000 Hz. The Timer1 interval
register is programmed with 23999 to produce exactly 24000 input clocks
per tick on the physical D1.
Assisted-by: OpenAI Codex:gpt-5.6-sol
Signed-off-by: Lance Harvie <lanceharvie@gmail.com>
