On ESP32-P4 rev < v3, the 768KB HP L2MEM is split into two
non-contiguous regions: sram_low and sram_high. Previously only
sram_low was used for the heap, wasting 384KB of sram_high.
Export _sram_high_heap_start and _sram_high_heap_end symbols from
the linker script and add sram_high to the heap via kumm_addregion()
in riscv_addregion() when MM_REGIONS > 1.
Signed-off-by: likun17 <likun17@xiaomi.com>
The chip revision check was disabled with #if 0 for v1.0 bringup.
Restore the original #ifndef ESP32P4_IGNORE_CHIP_REVISION_CHECK
guard so boards can selectively bypass the PANIC by defining
this macro, while keeping the warning message in the #else branch.
Signed-off-by: likun17 <likun17@xiaomi.com>
Add ESPRESSIF_FLASH_32M Kconfig option and the corresponding
esptool flash size mapping in Config.mk to support boards with
32MB NOR flash.
Signed-off-by: likun17 <likun17@xiaomi.com>
Document the HT32F491x3 ESK32 board, build steps,
flashing flow, and validation commands. Add WSL and
PowerShell flash backends plus a Python wrapper.
Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
Add initial HT32F491x3 support with startup, IRQ handling,
serial console, GPIO helpers, custom vectors, and CMake build files.
Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
include/cxx contains NuttX's mini C++ ABI shims and must only be added
to the include path when CONFIG_LIBMINIABI is selected. tools/Config.mk
was adding it unconditionally for every non-LIBCXX/non-UCLIBCXX build,
and the platform.cmake files for arm, arm64, risc-v, x86_64 and tricore
were adding it inside the CONFIG_LIBCXXTOOLCHAIN block.
With an unpatched downloaded ARM GNU Toolchain, <cstdlib> uses
newlib's stdlib.h, defining div_t as an anonymous struct. A later
inclusion of NuttX's stdlib.h via <cstdio>->stdio.h->kmalloc.h then
redefines div_t with struct tag div_s, causing a conflicting declaration
error.
Guard the div_t/ldiv_t/lldiv_t definitions in stdlib.h with
redefinitions when a toolchain stdlib.h was already processed.
Also fix lldiv_s members typed as long instead of long long.
Signed-off-by: trns1997 <trns1997@gmail.com>
- Remove debug polling loop from esp32s3_cam_start_capture() that
busy-waited on DMA status register.
- Fix DMA ISR race: stop DMA before invoking capture callback to
prevent ISR re-triggering while callback processes the buffer.
Check priv->capturing before restarting DMA in ISR.
- Move DMA descriptors from struct to heap allocation, avoiding
stack/BSS alignment issues with cache-line-aligned descriptors.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Export qemu_rv_configure_mpu() and invoke it on the secondary-hart
boot path before riscv_cpu_boot().
This keeps protected SMP builds from faulting on !CPU0 when userspace
work is first scheduled there.
Signed-off-by: Shunchao Hu <ankohuu@gmail.com>
This commit updates the common-source integration for Xtensa-based
Espressif devices (ESP32, ESP32-S2, and ESP32-S3). This is part of a larger
common-source update split by architecture for better maintainability.
Major components updated:
- IRQ allocator refactoring with intr_alloc integration
- Common-source drivers (GPIO, RMT, I2C, SPI, UART, etc.)
- Espressif components upgrade to release/master.b-test
- Peripheral drivers (ADC, PWM, LEDC, MCPWM, PCNT, Temperature Sensor, etc.)
- Wireless adapters (Wi-Fi and BLE)
- esp_timer migration to the common-source path for Xtensa devices
- Common-source power management implementation (auto-sleep and wakeup paths)
- Board defconfigs for all Xtensa Espressif boards
- SMP support improvements for ESP32-S3
- Critical section handling improvements
Key architectural changes:
- IRQ Allocator: The new interrupt allocator enables multiple mapping
options from interrupt sources to CPU interrupts, providing flexibility
required by modern peripherals. Although this introduces breaking changes
to the interrupt handling API, the required ARCH_MINIMAL_VECTORTABLE
Kconfig option is explicitly checked during startup to ensure proper
configuration. This validation prevents runtime issues from configuration
mismatches.
- Xtensa-specific interrupt handling via esp_xtensa_intr.c providing
NuttX-native implementations of xt_ints_on/off and interrupt handlers,
avoiding conflicts with NuttX's core Xtensa macros.
- Timer/RTC unification: ESP32/ESP32-S2/ESP32-S3 move from chip-specific
RTC/RT-timer code to common-source Espressif integration, including
esp_timer_adapter/esp_rtc paths and the required bringup/defconfig updates.
- Power management consolidation: Xtensa PM follows the common-source
implementation, including common-source auto-sleep behavior, UART/Wi-Fi
wakeup coordination, and tickless-safe sleep flow compatibility.
Note: This is a large commit to maintain bisectability. Breaking the
changes into smaller commits would result in non-building intermediate
states across the common-source infrastructure update.
Tested configurations:
- All defconfigs were tested, including `ostest`.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
When a developer working on BSP wants UART1 with RTS, the following
needs to be added in the BSP's include/board.h file:
#define PIN_UART1_RTS PIN_UART1_RTS_1
which says that PIN_UART1_RTS_1 -- the first alternative pin with UART1
RTS function -- should be used for the UART1's RTS.
There are no alternative pins for PIN_UART2_RTS, therefore a similar
definition is not used for PIN_UART2_RTS.
However, that is a complication when we want PIN_UART2_RTS to be defined
as GPIO, for example:
#define PIN_UART2_RTS (GPIO_OUTPUT | PIN_PORTB | PIN2)
In such a case, PIN_UART2_RTS is later redefined to the only alternative
function from hardware/kinetis_???pinmux.h file.
This patch avoids the redefinition of already defined names.
We considered renaming PIN_UART2_RTS to PIN_UART2_RTS_1 in the
hardware/kinetis_???pinmux.h file, but that is breaking change. We try
to avoid breaking change.
Signed-off-by: Jiri Vlasak <jvlasak@elektroline.cz>
Because it is not needed anymore.
The original code here is from the initial implementation in the commit
66b873ef77.
Signed-off-by: Jiri Vlasak <jvlasak@elektroline.cz>
When using CONFIG_UART?_RS485CONTROL, RTS pin is set high when sending
data and low otherwise. PIN_UART?_RTS is defined in the board.h file as
the appropriate ALT functionality of the chip's port.
However, it may happen that PIN_UART?_RTS is wired to another pin of the
chip that does not support the RTS as ALT functionality of the UART? in
question. This commit addresses such a situation.
When UART?_RS485CONTROL_RTSISGPIO is set in menuconfig for the given
UART?, it is expected that the PIN_UART?_RTS is defined as GPIO_OUTPUT,
and the PIN_UART?_RTS is set high when sending data and low otherwise.
Signed-off-by: Jiri Vlasak <jvlasak@elektroline.cz>
Rename STM32_IRQ_NEXTINT to STM32_IRQ_NEXTINTS across all stm32
variants.
In stm32_dumpnvic() dynamically print NVIC enable and priority
registers based on STM32_IRQ_NEXTINTS.
Use PRIx32 format specifier instead of 'x' (since uint32_t on arm is
actually a long unsigned int).
Simplify if/else chain in stm32_irqinfo() to determine irq reg/bit.
There's no stm32_irqinfo.c; remove mention in stm32f0l0g0/Make.defs.
Signed-off-by Peter Barada <peter.barada@gmail.com>
When using a dummy memory address in DMA LLI transfers,
do not update the memory address.
Signed-off-by: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
Fix adc_oversample() where priv->trovs (a bool, 0 or 1) was OR'd
directly into setbits instead of using ADC_CFGR2_TROVS (bit 9).
This caused triggered oversampling to never actually be enabled.
Fix ANIOC_WDOG_UPPER and ANIOC_WDOG_LOWER ioctls where the TR1
register was overwritten with only the new threshold value, zeroing
out the opposite threshold and the AWDFILT digital filter bits.
Use read-modify-write to preserve the other fields.
Signed-off-by: kywwilson11 <kwilson@2g-eng.com>
imx9_dmapreflight() rejected unaligned buffers unconditionally, but
dmarecvsetup() has a bounce path via priv->rxbuffer for small
transfers. Add a buflen > sizeof(priv->rxbuffer) check so that
small reads (e.g. ext_csd 512-byte stack buffer) can use the
bounce buffer instead of failing with -EFAULT.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Port USDHC1 (eMMC) driver to the i.MX95 FRDM EVK board:
- Create imx95_pinmux.h with SD1/USDHC1 pin definitions
- Add USDHC1 pin macros to board.h
- Create board-level imx9_usdhc.c glue code
- Update imx9_bringup.c with DMA allocator and USDHC init
- Add SCMI clock guards in imx9_usdhc.c (imx95 clock roots
are owned by System Manager, direct CCM writes are no-ops)
- Fix CCM_CR_USDHC2 copy-paste bug to CCM_CR_USDHC1
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Add imx95 GPIO register definitions (same IP block as imx93), fill
g_gpio_base[] array for imx95, include imx95_gpio.h from the common
header, and compile imx9_gpio.c/imx9_gpiobase.c for imx95 in cmake.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Rename IMX9_IRQ_uSDHC{1,2,3} to IMX9_IRQ_USDHC{1,2,3} in both arm
and arm64 imx95_irq.h to follow the all-caps naming convention used
by imx93_irq.h and the rest of the NuttX codebase. Remove the now
unnecessary USDHC IRQ alias block from arm64 imx95_irq.h.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
arm64_modifyreg8.c, arm64_modifyreg16.c, arm64_modifyreg32.c were
present in Make.defs but missing from CMakeLists.txt, causing link
errors when building with cmake.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Correct duplicate "is is" word found in 181 files throughout the
codebase.
In most cases "is is" was changed to "is", but in contexts like
"MCU is is sleep mode" it was corrected to "MCU in sleep mode".
Also fixes a "the the" typo in net/inet/inet_sockif.c.
This is a pure style/documentation fix that improves code readability.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Fix 269 occurrences of duplicate "the" word typo found in 209 files
across source code, header files, and configuration.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Remove the CONFIG_K210_WITH_QEMU option and associated conditional
code paths. The reasons for removal are:
* Simplifies code path for real hardware by removing QEMU workarounds
* The current QEMU target uses sifive_u machine, which is not designed
for K210 emulation
* For RISC-V QEMU simulation, the qemu-rv (rv-virt) target is a better
choice
* Renode can be used as an alternative for K210 simulation if needed
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Fix duplicate watchdog prompts in Kconfig by using unique WDOG0, WDOG1,
WDOG2 names instead of generic 'watchdog' label. This matches the UART
peripheral naming convention in the same file and makes it clear which
watchdog is being configured in menuconfig.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Add WDT driver for K210 with support for both WDT0 and WDT1 peripherals.
This includes:
- Add k210_wdt.c and k210_wdt.h driver files with interrupt-based
watchdog timer functionality
- Add hardware register definitions in k210_wdt.h
- Add K210_WDT, K210_WDT0, K210_WDT1 Kconfig options
- Add memory map definitions for WDT0 (0x50400000) and WDT1 (0x50410000)
- Reorder WDT IRQ definitions (IRQ 21, 22) before UART0 (IRQ 33) in irq.h
- Add WDT initialization in board bringup for maix-bit
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
