Adds a dedicated page (matching the lsm6dso32 one, the closest
register-compatible driver already documented) instead of a plain list
entry: chip description, registration examples for both polling and
interrupt-driven mode -- including the single-shared-INT-pin
config_s/attach() shape this driver actually uses, unlike sensors that
need one interrupt pin per sub-sensor -- and the two custom ioctls
(SNIOC_WHO_AM_I, SNIOC_SETFULLSCALE) with their argument units.
Requested in review on this PR.
Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
This commit introduces EDID reading and parsing to the JZ4780 display
driver, replacing hardcoded resolution limits with dynamic mode selection
based on the connected display's capabilities.
Specific changes include:
- Implemented I2C DDC master communication for the HDMI controller to
read EDID blocks from monitors.
- Added dynamic mode selection to calculate bandwidth and pick the best
supported resolution, prioritizing the EDID preferred mode.
- Dynamically allocated framebuffer bounds (g_planeinfo and g_videoinfo)
based on parsed EDID dimensions.
- Configured GPIO pin multiplexing for HDMI power, DDC, and control pins
(POWER_EN, CEC, SCL, SDA) to enable display power and communication
on the CI20 board.
Signed-off-by: Lwazi Dube <lwazeh@gmail.com>
Wire the RTL8721F (amebagreen2) into the shared Ameba watchdog driver
(arch/arm/src/common/ameba/ameba_wdg.c), registered as /dev/watchdog0.
Only the per-chip base address and IRQ differ, so this adds a small
ameba_wdg_chip.h (WDG2 non-secure system watchdog at 0x4080AD80,
CPU0_NS_WDG IRQ 69, verified against the SoC hal_platform.h and
ameba_vector_table.h) plus the Make.defs/CMakeLists build hooks, the
board bring-up registration, and a wdg defconfig. The shared driver is
unchanged.
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Wire the RTL8720F into the shared Ameba watchdog driver
(arch/arm/src/common/ameba/ameba_wdg.c), registered as /dev/watchdog0.
Only the per-chip base address and IRQ differ, so this adds a small
ameba_wdg_chip.h (WDG2 non-secure system watchdog at 0x40801D80,
KM4TZ_NS_WDG IRQ 52, verified against the SoC hal_platform.h and
ameba_vector_table.h) plus the Make.defs/CMakeLists build hooks, the
board bring-up registration, and a wdg defconfig. The shared driver is
unchanged.
Also corrects the RTL8720F row in the rtl8721dx chip-header reference
table (the non-secure system WDG IRQ is KM4TZ_NS_WDG = 52).
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Add a NuttX watchdog lower-half for the Ameba KM4 non-secure system
watchdog (WDG2), registered as /dev/watchdog0. The fwlib WDG API is
ROM-resident, so no board.mk change is needed.
The hardware cannot be stopped once enabled, so stop() is emulated via
the early interrupt (EI) auto-refreshing the counter, and capture()
delivers a pre-timeout callback through the same EI. The EI has a
three-part timing contract, all handled here: it must be armed with
EIMOD=ENABLE at WDG_Init, its EIE gate only takes effect after
WDG_Enable, and -- because the EI is level-based -- a pure capture path
must mask EIE after the one-shot callback to avoid re-entrant storming
while the reset is pending. The EI flag is cleared twice per the slow
WDG clock.
Per-chip base address and IRQ live in ameba_wdg_chip.h so the shared
driver needs no change to port to another Ameba IC.
Verified on pke8721daf: timeout reset (BOOT REASON WDG2), stop()
suppressing the reset, and capture() firing ~EICNT ms before the reset.
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Add a user documentation page for the grep system command covering
overview, configuration options, usage, options, exit status and
examples. The command lives in apps/system/grep and is enabled with
CONFIG_SYSTEM_GREP (depends on CONFIG_LIBC_REGEX).
This documents the command added in
https://github.com/apache/nuttx-apps/pull/3741.
Signed-off-by: Junbo Zheng <zhengjunbo1@xiaomi.com>
The link support is no longer limited to the pseudo file system and now
covers both soft (symbolic) links and hard links across the VFS. Rename
the configuration option PSEUDOFS_SOFTLINKS to the more accurate FS_LINKS
and update all references in the source, headers, Kconfig, documentation
and board defconfigs accordingly.
This is a configuration rename; any out-of-tree defconfig that still
selects PSEUDOFS_SOFTLINKS must be updated to FS_LINKS.
Signed-off-by: zhengyu16 <zhengyu16@xiaomi.com>
Wire the shared Ameba RTC driver (arch/arm/src/common/ameba/ameba_rtc.c)
into RTL8721F (amebagreen2). The driver is chip-agnostic and reads only
per-chip macros from ameba_rtc_chip.h; RTL8721F differs from amebadplus
only in the RTC interrupt vector (RTL8721F_IRQ_RTC, vector 41). The
APBPeriph_RTC masks and RTC_BASE_YEAR (1900) are identical across all
current Ameba chips.
- ameba_rtc_chip.h: per-chip RTC IRQ / clock masks / base year
- Make.defs, ameba_board.mk: compile ameba_rtc.c and the fwlib RAM
RTC source when CONFIG_AMEBA_RTC=y
- board: rtl8721f_rtc.c registers /dev/rtc0 from bringup
- configs/rtc: examples/alarm profile
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Wire the shared Ameba RTC driver (arch/arm/src/common/ameba/ameba_rtc.c)
into RTL8720F. The driver is chip-agnostic and reads only per-chip macros
from ameba_rtc_chip.h; RTL8720F differs from amebadplus only in the RTC
interrupt vector (RTL8720F_IRQ_RTC, vector 33). The APBPeriph_RTC masks
and RTC_BASE_YEAR (1900) are identical across all current Ameba chips.
- ameba_rtc_chip.h: per-chip RTC IRQ / clock masks / base year
- Make.defs, ameba_board.mk: compile ameba_rtc.c and the fwlib RAM
RTC source when CONFIG_AMEBA_RTC=y
- board: rtl8720f_rtc.c registers /dev/rtc0 from bringup
- configs/rtc: examples/alarm profile
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Expose the Ameba on-chip RTC as a NuttX date/time RTC at /dev/rtc0
(rdtime/settime) with a single one-shot alarm (setalarm/rdalarm/
cancelalarm/setrelative) that fires the RTC interrupt and the upper-half
callback. The same hardware also backs the arch date/time RTC hooks
(up_rtc_initialize/getdatetime/settime, g_rtc_enabled) so the NuttX
system time is seeded from it.
The driver sits on the SDK fwlib RTC API (mirrored structures + local
externs, no vendor headers pulled into the NuttX include world). The
fwlib RTC API lives in the RAM source ameba_rtc.c, so it is added to the
board fwlib build under CONFIG_AMEBA_RTC. The hardware keeps a year plus
a day-of-year (no month/day register); the driver bridges that to the
NuttX month/day calendar with the libc UTC routines (timegm/gmtime_r),
which is exact and reversible.
The only per-chip fact -- the RTC interrupt vector -- lives in the
per-chip ameba_rtc_chip.h; the shared driver is never edited for a new
Ameba chip. A configs/rtc profile (examples/alarm) is added for
verification.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
List every peripheral implemented by STM32U3C5, and update the common GPIO, EXTI
and USART driver paths after the Cortex-M33 migration.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Rename the U3 and U5 family-local Cortex-M33 RCC headers to
stm32_rcc_m33.h and dispatch to that private name for the two families
in the common RCC header.
This lets the shared M33 USART implementation use one include name
while RCC registers and clock definitions remain family-local. Extend
the stm32_ports.rst naming rules with the M33 header, source, and
Kconfig symbol conventions.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Add generic support for link-time registration of struct instances,
modeled after the Zephyr STRUCT_SECTION_* mechanism:
- include/nuttx/iterable_sections.h: STRUCT_SECTION_ITERABLE/DECLARE/
FOREACH/GET/COUNT macros placing instances in name-sorted linker
sections delimited by _<type>_list_start/_end symbols (attributes
through the nuttx/compiler.h macros; FOREACH takes a caller-declared
iterator, like list_for_every_entry).
- include/nuttx/linker/iterable_sections.ld: ITERABLE_SECTION() macro
emitting the KEEP + SORT_BY_NAME collection statements (linker
scripts in ARCHSCRIPT are CPP-preprocessed).
- include/nuttx/linker/common-rom.ld / common-ram.ld: central
aggregators meant to be included by board linker scripts (inside
.text and .data respectively); subsystems register their sections
here guarded by their Kconfig options, so the fragments expand to
nothing on configurations that do not use them.
- CONFIG_ITERABLE_SECTIONS_LINKER_INSERT + include/nuttx/linker/
common-insert.ld (added before the board script by tools/Config.mk and
by the top-level CMakeLists.txt): optional zero-touch mode that
supplements the board script through GNU ld INSERT AFTER, collecting
the subsystems' ITERABLE_SECTION blocks in one output section; the
common-rom.ld/common-ram.ld fragments expand to nothing in that mode.
See the option help for the constraints.
- Documentation/components/iterable_sections.rst.
First user: the Zephyr zbus message bus port (apps/system/zbus in
nuttx-apps); its board integration comes in a companion PR.
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
Reviewers on apps#3751 (support compound command and resetcause-based
triggers) asked for documentation of the new features. Add two
sections to the nxinit doc:
- "Built-in Properties": describes the sys.boot.reason property set
by NXInit at startup from BOARDIOC_RESET_CAUSE, its two value forms
(hardware cause with numeric subreason, or software reset reason
string), and behavior when CONFIG_BOARDCTL_RESET_CAUSE is disabled
or the boardctl() call fails.
- "Compound Commands": describes the && / || short-circuit semantics
for chaining commands on a single action line, including quoting
behavior.
Assisted-by: GitHubCopilot:claude-sonnet-5
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Add an NXTerm framebuffer configuration for QEMU and Intel64 hardware.
Enable USB keyboard input, PCI serial logging, CPython, and serial fallback.
Signed-off-by: raiden00pl <raiden00@railab.me>
Add HSI48 clock selection, USB pull-up control, automatic CDC/ACM registration during board bring-up, USB test configurations, and board documentation.
Assisted-by: OpenAI Codex
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
The CH422G offers eight bi-directional pins, IO0-IO7, and four open-drain
outputs, OC0-OC3. It appears on boards that have run out of usable GPIOs
once a parallel RGB panel has taken its share, the Waveshare
ESP32-S3-Touch-LCD-7 among them, where it holds the panel and touch
controller in and out of reset and switches the backlight.
Two things about the device do not fit the shape a register-per-address
I2C driver usually takes, and both are handled here rather than pushed on
to board logic:
- A register is selected by the I2C address the transfer is addressed
to, not by a register address written ahead of the data. Each access
carries a single byte to one of four addresses.
- None of the write-only registers can be read back, so the driver
keeps a shadow copy of each and updates it in step with the device.
IO0-IO7 have no individual direction control; one bit of the system
parameter register drives the whole group. The driver records the
direction asked of each pin and puts the group in output mode once at
least one of them is an output, which is what a board that drives some of
the pins would expect. Reading a pin of a group held in output mode
reports the value last written, because the hardware cannot report the
level, and that is documented rather than hidden.
The four open-drain outputs are presented as pins 8-11 of the same
ioexpander_dev_s so that one instance covers the chip, which means
CONFIG_IOEXPANDER_NPINS must be at least 12.
Builds clean with no new warnings on esp32s3-touch-lcd7:usbnsh and passes
nxstyle.
Signed-off-by: Alan Carvalho de Assis <acassis@gmail.com>
Assisted-by: Claude Code
Wire the shared Ameba ADC driver into the RTL8721F build: add the
per-chip ameba_adc_chip.h (12 channels, CH0..CH7 external on
PA20,PA19,PA18,PA17,PA15,PA14,PA13,PA12, PINMUX function 5), the
board ADC table and registration, the adc board config, and build
glue for both cmake and make (including the fwlib RAM-layer
ameba_adc.c in ameba_board.mk). Document the ADC on the board index.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Wire the shared Ameba ADC driver into the RTL8720F build: add the
per-chip ameba_adc_chip.h (9 channels, CH0..CH5 external on
PA13..PA18, PINMUX function 5, APB clock on bit24), the board ADC
table and registration, the adc board config, and build glue for
both cmake and make (including the fwlib RAM-layer ameba_adc.c in
ameba_board.mk). Document the ADC on the board index.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Add a NuttX ADC lower-half for the Ameba SoC family, wired for the
amebadplus/pke8721daf as /dev/adc0. The driver uses the fwlib ROM
API and drives on-demand polled conversions via ADC_ReceiveBuf with
the hardware auto channel-switch FIFO, because amebadplus disables the
ADC software-trigger path. Per-chip wiring (channel count, pinmux
function id, APB clock bits, optional aux clock) lives in a chip
header so a new IC only supplies its own values without touching the
shared driver.
Reports raw conversion codes per the NuttX convention (12-bit
effective, 0..~3876 for 0..3.3V), consistent with the STM32/i.MXRT/
Tiva ADC drivers.
Verified on hardware: 0V->121, 3.3V->3876 on CH0(PB19) while
CH1(PB18) held steady, confirming sampling, full-scale and
multi-channel switch-list isolation.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Add a real ESP32-S3 touchscreen photograph to the NXStore guide so the
companion documentation shows the package catalog on target hardware.
Assisted-by: OpenAI Codex:gpt-5.6-sol
Signed-off-by: aviralgarg05 <gargaviral99@gmail.com>
Document the USART2 NSH console, USB FS pins, HSI48/CRS clock source and
the usb-cdc configuration that exposes a separate USB CDC/ACM serial
device.
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
Adds reference to the sdmmc_spi defconfig of esp32p4-tab5, with mounting
instructions for the SD Card.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
status() reads one reset line at a time, and only for a caller that
already knows the id. Nothing else in the interface says how many lines
a controller has or what any of them resets, so the lines a board is
holding cannot be surveyed.
Adds an optional get_line method describing one line as a structure: its
name, and a text member for controller specific fields the structure
does not cover. The asserted state stays with status(), which already
reports it, so a controller does not supply the same fact twice.
Returning -ENODEV reports an id that names no line, which is how
controllers with gaps in their numbering are handled.
reset_controller_dev gains the line count that bounds the ids.
CONFIG_RESET_PROCFS adds /proc/reset, one key:value line per reset line,
every line the same tokens in the same order so the file is machine
parseable. A controller without get_line is listed by name and a note.
The controller list already existed for reset_control_get() to search,
so the renderer only walks what was there. /proc/reset is claimed when
the first controller registers; procfs_register() requires that procfs
is not yet mounted, which holds because controllers register during
board or architecture start up, and it appends without checking for
duplicates, so the entry is claimed once for the lifetime of the system.
Documents the framework, which had a page with nothing on it: the
consumer interface and what shared and exclusive handles mean, the
controller interface, the new method, and /proc/reset.
Off by default and costs nothing when off. No in-tree configuration
enables RESET, so this builds only when a board turns it on.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Justin Hammond <justin@dynam.ac>
The pinctrl interface is write only: every operation sets a property,
and nothing reports what a pin currently holds.
Adds an optional get_pad method describing one pad as a structure: the
settable fields, each with a validity bit because a pad need not have
them all, and a text member for the controller specific fields the
structure does not cover. The structure embeds its strings rather than
pointing at them, so the same shape serves both callers.
The first caller is /proc/pinctrl, which renders one key:value line per
pad, every line the same tokens in the same order with - for a field the
pad does not have, so the file is machine parseable. The framework owns
the format; controllers only supply data.
The second is a new PINCTRLC_GETPAD ioctl, which gives userspace the
read-back that text cannot: reading a pad back after setting it.
PINCTRL_PADNAME() and two lookup helpers let a controller declare its
pad and function-select names in one table instead of inventing its own.
Registration keeps a list, which the renderer iterates; pinctrl_dev_s
gains the pad count. /proc/pinctrl is claimed when the first controller
appears; procfs_register() requires that procfs is not yet mounted,
which holds because controllers register during board or architecture
start up.
Documents the method, the validity bits and the optional naming, and
records that /proc/pinctrl exists.
Off by default and costs nothing when off. No in-tree configuration
enables PINCTRL, so this builds only when a board turns it on.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Justin Hammond <justin@dynam.ac>
Update the MIPS Creator CI20 board documentation to include a detailed
peripherals support table. This replaces the basic bulleted list with
comprehensive status details for CPU cores, RAM, Display, Ethernet,
GPIO, TRNG, Timers, UART0, USB Host, and Watchdog.
Signed-off-by: Lwazi Dube <lwazeh@gmail.com>
Document the usb-cdc-uart configuration, which keeps NSH on the USART2
ST-LINK virtual COM port and exposes a separate USB CDC/ACM serial
device on the STM32 USB FS connector.
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
Add initial Apache NuttX support for the Allwinner D1 / T-Head C906
running in supervisor mode under OpenSBI.
Add support for:
- RV64 D1 architecture definitions
- Lichee RV 86 Panel board configuration
- UART0 console at 115200 baud
- D1 PLIC interrupt controller
- native D1 Timer1 scheduler tick
- early inherited-watchdog disable
- FLAT S-mode NSH configuration
The port has been tested on physical Sipeed Lichee RV / 86 Panel
hardware and boots to an interactive NuttShell.
The scheduler tick uses OSC24M Timer1 at 1000 Hz. The Timer1 interval
register is programmed with 23999 to produce exactly 24000 input clocks
per tick on the physical D1.
Assisted-by: OpenAI Codex:gpt-5.6-sol
Signed-off-by: Lance Harvie <lanceharvie@gmail.com>
Add initial NuttX port for the original (white) BeagleBone board, which is
powered by the TI AM335x Sitara Cortex-A8 processor.
This commit includes:
- Board documentation
- Board support package files derived from BeagleBone black
- Architecture-specific page allocator for memory management in kernel build.
- Default configurations for both flat (`nsh`) and kernel (`knsh`) builds
running via U-Boot from a microSD card.
Signed-off-by: Lwazi Dube <lwazeh@gmail.com>
ESWIN's own evaluation board for this SoC. Where the StarPro64 is a
single board computer built around the chip, the EVB brings out most of
the SoC's interfaces.
Everything shared with the StarPro64 is already in the common directory,
so this carries the board's own facts: which UART reaches which connector,
which pads carry the boot straps, where its memory sits, and a
configuration starting from the same place the StarPro64's does.
The summary tables on sheet 3 of both boards' schematics are inherited
from ESWIN's reference design and describe that design rather than either
board. On this board the console is UART0 through the FT4232 bridge,
UART1 goes to the M.2 socket and a header, and UART2 reaches the RS232
port.
The documentation page follows the board template: a photograph, the
board's features, the console and its port on the FT4232 bridge, power,
the build and TFTP boot procedure, and what NuttX drives so far.
Boots to an NSH prompt over UART0 with all four harts running.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Justin Hammond <justin@dynam.ac>
The port had one board directory holding one board, with everything in it
whether it described the SoC or the PCB. A second EIC7700X board follows,
so this adopts the common-plus-board layout NuttX provides, as mpfs uses.
boards/risc-v/eic7700x/common holds what is true of the SoC: the boot path
that mounts the RAM disk and /proc before calling the board's own bring
up, the linker script, the start up scripts and the image builder.
ARCH_CHIP_EIC7700X selects ARCH_BOARD_COMMON, so the symlinks the build
makes always point at code that compiles.
The board directory keeps what is a fact about the PCB: its own board.h
and board_memorymap.h, since the include fallback is all or nothing, a
bring up that owns the order its devices register in, and a board_config.h
declaring what that bring up may call.
The image builder moves to common/tools and derives its output name from
the configuration. It computes the padding between the kernel and the RAM
disk from _ebss rather than assuming 64 KiB, which fails once BSS grows
past it: the disk lands below _ebss and the BSS clear zeroes it before
anything searches for it.
The StarPro64 configuration gains what the port now needs: four harts,
960 MiB of RAM, a larger task stack, a backtrace on assert, the system log
in RAM for dmesg, and ELF applications, for which ARCH_CHIP_EIC7700X now
selects ARCH_HAVE_ELF_EXECUTABLE.
board.h loses its LED definitions. CONFIG_ARCH_LEDS is not set, nothing
implements board_autoled_on(), and the indices they gave named no LED.
The documentation pages gain the tags the template asks for.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Justin Hammond <justin@dynam.ac>
The pins a board publishes are visible in /dev and each can be read
through its own node, but surveying a whole board that way means an open
and two ioctls per pin, and the signal and interrupt counters the upper
half keeps are not reachable through any of them.
Adds a list of registered pins and publishes it as /proc/gpio, behind
GPIO_PROCFS: a quality of life view of the same kind as /proc/pinctrl
and /proc/reset. Every common field comes from state the upper half
already holds: the pin type, the value through go_read(), how many times
the pin has been registered for signals, and how many interrupts it has
taken. Lines carry the same key:value tokens in the same order, so the
file is machine parseable.
Lower halves may supply an optional go_describe() adding what only they
can say, such as which pad carries the line or how its trigger is
configured. It writes text into a caller supplied buffer and the upper
half owns the line, so a lower half needs no procfs knowledge. A lower
half without it is listed with the common tokens alone.
The pin type index is bounded before use: it comes from the lower half
and the name table cannot cover a type the enumeration does not define.
A pin that cannot be read reports val:- rather than a zero that would
read as a real level.
procfs_register() appends without checking for duplicates, so the entry
is claimed once for the lifetime of the system rather than whenever the
list is empty; pins come and go at run time.
The name is held in a buffer as long as the one gpio_pin_register()
accepts, so a listing always names the same string as /dev.
The pin type name table is declared without an explicit size so that the
assertion beside it compares against the enumeration and can fail; sized
as [GPIO_NPINTYPES] it would have been tautological.
Documents the entry, its tokens, and how a lower half describes a pin.
Off by default: with GPIO_PROCFS unset the list, the lock and the procfs
entry are compiled out, and go_describe() is one more member at the end
of a structure existing lower halves do not reach.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Justin Hammond <justin@dynam.ac>
Add a defconfig that runs CPython on qemu-intel64 (flat build) and
place the .PyRuntime section (created by the apps CPython port) in
.data so it is covered by the kernel physical mapping.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
