common/espressif/esp_pcnt.c: In function 'esp_pcnt_isr_default':
common/espressif/esp_pcnt.c:396:41: warning: passing argument 1 of 'spin_lock_irqsave' makes pointer from integer without a cast [-Wint-conversion]
396 | flags = spin_lock_irqsave(unit->lock);
| ~~~~^~~~~~
| |
| spinlock_t {aka unsigned char}
In file included from common/espressif/esp_pcnt.c:44:
/home/hujun5/下载/vela_sim/nuttx/include/nuttx/spinlock.h:507:55: note: expected 'volatile spinlock_t *' {aka 'volatile unsigned char *'} but argument is of type 'spinlock_t' {aka 'unsigned char'}
507 | irqstate_t spin_lock_irqsave(FAR volatile spinlock_t *lock)
| ~~~~~~~~~~~~~~~~~~~~~^~~~
Signed-off-by: hujun5 <hujun5@xiaomi.com>
This follows the formula in the "Startup Delay" section of the
datasheets, where `BOARD_XOSC_STARTUPDELAY` is the time in milliseconds,
which is then multiplied by the clock fequency in kHz, divided by 256
cycles, and rounded up.
This differs from `pico-sdk`, which just multiplied the value of the
expression it previously used by a `PICO_XOSC_STARTUP_DELAY_MULTIPLIER`.
This seems less correct, though it should be essentially the same except
rounding. (`BOARD_XOSC_STARTUPDELAY_MULTIPLIER` also wouldn't fit nicely
the way the `#define`s are aligned.)
This sets `BOARD_XOSC_STARTUPDELAY` to `1` for all boards, so this will
produce the same output and not change behavior.
Signed-off-by: Ian Douglas Scott <ian@iandouglasscott.com>
Previously this used a hard-coded value of 12 MHz, but this presumably
should use `BOARD_XOSC_FREQ`. Similarly to how it is done in pico-sdk.
It looks like all boards are currently defined to use 12 MHz XOSC
clocks, so this won't change behavior with any of them.
Signed-off-by: Ian Douglas Scott <ian@iandouglasscott.com>
No reason to keep asking for these over and over. Also fix bumping
the CPU booted counter when SBI is enabled.
Must also read g_hart_use_sbi before bumping the CPU booted counter.
This adds support for QEMU Cortex-R5 virtual processor on existing QEMU
Cortex-A7 code base with profile support in `armv7-r/` and `armv7-a/`.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
This revise armv7-r/ header files needed to support QEMU cortex-r5
virtual process for armv7-r family.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
This fixes compilation error:
```
/tmp/nuttx/arch/arm/src/armv7-r/gic.h:699:17: error:
'GIC_ICDSGIR_NSATT_GRP1' undeclared; did you mean 'GIC_ICDSGIR_NSATT'?
```
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
copied over files, not modified properly yet
Squashing lots of define errors to get ethernet.c working
quick path rename
Fix STM32_EMAC_BASE (and ICACHE/DCACHE Bases). Enable ETH, ETHTX, and ETHRX with CONFIG_STM32H5_ETHMAC (like H7 does).
Fixed stm32_get_uniqueid
Previously, an exception occurred as a result of calling this function. The problem turned out to be this line: uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i);. Dereferencing a 32-bit register as a 8-bit register seemed to be causing this issue. I think this function is better anyway, fewer register accesses and loop iterations.
Turn on SBS peripheral when using Ethernet
The SBS peripheral is required to be turned on because the ETH_SEL_PHY bits need to be set. Without turning this on, RMII mode is not possible. MII may not work either.
Style Updates
This moves ARM_HAVE_PSCI selection to virtual processor level as
armv7-r chips like Cortex-R5 doesn't have it.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
reason:
We decouple semcount from business logic
by using an independent counting variable,
which allows us to remove critical sections in many cases.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
reason:
In kernel mode, sighand_test() may failed.
because nxsig_unmask_pendingsignal may change tcb->xcp.regs,and we should update return value(regs).
Signed-off-by: hujun5 <hujun5@xiaomi.com>
In up_addrenv_kmap_pages, the MMU_MT_NORMAL_FLAGS are needed for the MMU
mappings in order for the memory & caches to function normally
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This moves ARM_HAVE_NEON from QEMU ARM family level down to the
processor level as not all processors have it (e.g. Cortex R5).
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
It was dis overed during debug of the ethernet driver that the EMAC base was incorrect. After examination, it was determined that ICACHE and DCACHE also had incorrect base addresses. This commit fixes the base addresses according to the reference manual.
Summary:
This commit removes the riscv_mhartid function and replaces all its
usages with up_cpu_index. The functionality is consolidated into
up_cpu_index which provides a more consistent API for getting the
current CPU/hart ID across different execution modes (machine/supervisor).
Impact:
- Removes riscv_mhartid.S and its references from build systems
- Updates all arch-specific code to use up_cpu_index instead
- Adds more detailed documentation for up_cpu_index behavior
- Changes the implementation of up_cpu_index to use percpu scratch
register in supervisor mode
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Summary:
- Separated CPU index functionality from CPU ID mapping configuration
- Moved CPU ID mapping functions to new riscv_cpuidmap.c file
- Made up_cpu_index() implementation dependent on ARCH_USE_S_MODE
- Updated build system to handle new file organization
Impact:
- Improves code organization by separating concerns between basic CPU index
functionality and advanced CPU ID mapping features
- Makes CPU index functionality available independently of CPU ID mapping
- Reduces conditional compilation complexity in header files
- Better aligns with RISC-V architecture modes (M-mode vs S-mode)
Testing:
GitHub CI and local testing
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Sumamry:
Adjust VIRT_FLASH_PSECTION from 0x00000000-0x08000000 -> 0x00600000-0x08000000
The above changes avoid the problem of directly restarting when the process accesses/executes at address 0x0 without causing assert
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
It will be used to distinguish between hardware KASan and software KASan. Hardware KASan does not need to use plug-in
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
| commit c96b8cdfdd
| Author: hujun5 <hujun5@xiaomi.com>
| Date: Mon Dec 23 16:59:20 2024 +0800
|
| use small lock in following files:
Signed-off-by: chao an <anchao.archer@bytedance.com>
reason:
In AMP mode, we can also use SGI as an inter-core interrupt,
and ensure that arm_gic0_initialize is called only once.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
