Add support for handling non-maskable interrupts (NMI) on TriCore
platforms. The NMI trap handler `tricore_nmitrap()` is provided as a weak
function that prints diagnostic information and invokes a panic with
register context. The main trap dispatcher will invoke `tricore_nmitrap`
when an NMI trap class is detected.
This change improves diagnostics when watchdog-induced NMIs or other
non-maskable exceptions occur during runtime.
Signed-off-by: yukangzhi <yukangzhi@xiaomi.com>
Extend CONFIG_LIBCXXTOOLCHAIN support to all remaining platforms
in CMake builds by explicitly locating and linking libstdc++.a
from the toolchain. This prevents build failures caused by STL
header/library mismatches where toolchain headers are included
without the corresponding library.
* Adds nuttx_find_toolchain_lib() calls for all platforms.
* Aligns CMake behavior with Make build system.
Signed-off-by: trns1997 <trns1997@gmail.com>
Some Aurix Boot-FW configurations leave watchdogs enabled by default,
which can cause unexpected resets during early bring-up. This change
explicitly disables the CPU and system watchdogs during core0 startup to
ensure reliable system initialization.
- For TC3XX chips, call `IfxScuWdt_disableCpuWatchdog()` and
`IfxScuWdt_disableSafetyWatchdog()`.
- For TC4XX chips, call `IfxWtu_disableCpuWatchdog()` and
`IfxWtu_disableSystemWatchdog()`.
This is a low-risk startup change and does not alter watchdog behavior
after system initialization.
Signed-off-by: yukangzhi <yukangzhi@xiaomi.com>
At certain optimization levels, GCC/Clang may insert UD2 if it detects undefined behavior (such as integer overflow or illegal pointer access), causing the program to crash immediately instead of executing unpredictable code.
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
The return address stored in the frame should point to the instruction
after the call. To get the actual call site, we need to subtract the
instruction size (sizeof(void *)) from the saved return address.
This ensures that backtrace addresses correctly point to the calling
instruction rather than the next instruction.
Signed-off-by: yinshengkai <yinshengkai@bytedance.com>
Add validation to ensure allocated stack size does not exceed TLS_MAXSTACK when
CONFIG_TLS_ALIGNED is enabled, and verify proper stack alignment using STACK_ALIGN_MASK
across all architectures. This improves stack safety and prevents potential TLS overflow conditions.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Remove return status from void tickless_rtc functions in nrf52, nrf53,
and nrf91 boards. Also add missing newline at end of nrf91_modem_os.c.
Signed-off-by: Bartosz <bartol2205@gmail.com>
In some scenarios (e.g. testing, debugging, etc.) where we want to trigger a memmanage fault without panic the system, we can use this Memory Management Fault skip operation.
Signed-off-by: pangzhen1 <pangzhen1@xiaomi.com>
Rename arm64_addrenv.c to arm64_addrenv_mmu.c to separate MMU-specific logic.
Add new arm64_addrenv_mpu.c with stub implementations of address environment
functions for MPU-based systems. Enable address environment support in FVP ARMv8-R
Kconfig to support kernel stacks in protected mode. Conditionally build MPU or
MMU address environment code based on CONFIG_ARCH_USE_MMU/CONFIG_ARCH_USE_MPU.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
The limit register contains the enable/disable bit for the MPU region,
so it must be written first before writing the base register to ensure
proper region disable operation.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Rename STACK_ALIGNMENT macro to STACKFRAME_ALIGN throughout the codebase
to provide clearer naming semantics. The new name better reflects the macro's
purpose of frame alignment rather than general stack alignment.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Do not compile up_putc functions in stm32_serial.c to avoid conflicts
with implementation from arm_semi_syslog.c when semihosting is enabled.
Signed-off-by: Jean THOMAS <jean@lambdaconcept.com>
Use 1u/~1u constants for TPIDRPRW bit operations.
Avoid implicit conversion to a different underlying type (MISRA Rule 10.3).
No functional change to task pointer tagging logic.
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
When the system startup from the PL1 SYS mode, the initialization
of the PL2 HYP register needs to be skipped. Put the Hypervisor
initialization code together and skip it all at once.
Signed-off-by: yukangzhi <yukangzhi@xiaomi.com>
Add default values (0x0) for ARCH_TEXT_VBASE, ARCH_DATA_VBASE, and
ARCH_HEAP_VBASE to resolve cmake configuration warnings when these
values are not explicitly set during initialization.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Remove restore_critical_section() call from up_switch_context() in simulator
as it is not necessary during interrupt context switching. The critical
section state is properly managed elsewhere in the interrupt handling flow.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Remove restore_critical_section() call from common_handler() in x86_64 interrupt
processing as it is not necessary during interrupt handling. The critical section
state is properly managed by the interrupt framework elsewhere.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
the virtual address of the page table (PT) is saved into the page directory (PD) entry, but the PD entry should store the physical address instead
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
When an interrupt occurs, the hardware automatically pushes the current RIP/RSP onto the interrupt stack. During the interrupt return, the iretq instruction pops them back. The problem is that the RIP/RSP modified by the signal is stored in the XCP context, whereas iretq operates on the interrupt stack. As a result, the RIP/RSP modified by the signal does not take effect in the iretq instruction, causing the task receiving the signal to fail to jump correctly to the signal handler. This behavior appears as if the signal is lost
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
Move stack alignment and kernel stack macros from architecture-specific internal
headers to public include/nuttx/irq.h. Consolidates duplicate definitions across
17 architecture families, reducing code duplication while enabling common code
to access these core alignment utilities without architecture dependencies.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
The SRN number in TriCore far exceeds the PN number.
Using IRQ as the PN number would result in an overflow.
Therefore, MINIMAL_VECTORTABLE is used to ensure that
the PN number does not overflow.
Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
1.add application link dependencies for all elf
2.add a global custom target to hold proptry in the toolchain file
3.add startup obj target
4.fix cpp lds error with kernel mod link elf lds
usage:
./build.sh qemu-armv7a:knsh --cmake
elf install in ${CMAKE_BINARY_DIR}/bin
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
Configuration/Tool: qemu-armv8a/mte
5282026-01-16 13:11:30
529------------------------------------------------------------------------------------
530 Cleaning...
531 Configuring...
532 Building NuttX...
533Makefile:142: target 'arm64_hwdebug.o' given more than once in the same rule
534Makefile:142: target 'arm64_hwdebug.o' given more than once in the same rule
535Makefile:142: target 'arm64_hwdebug.o' given more than once in the same rule
536Makefile:142: target 'arm64_hwdebug.o' given more than once in the same rule
537Makefile:142: target 'arm64_hwdebug.o' given more than once in the same rule
538
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
Support user pass it own heap struct to the mm_initialize_heap() to
avoid the heap struct is reserved from the heap range
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
