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I2C(RIIC) support for RX65N

Browse source 
Addressed review comments in rx65n_definitions.h and rx65n_bringup.c
This commit is contained in:
rajeshwaribhat 2020-08-21 19:20:06 +05:30 • committed by Alan Carvalho de Assis
parent 37d8799d07
commit fe4a1eb96a
22 changed files with 4266 additions and 172 deletions
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4
arch/renesas/Kconfig
View file

@ -32,12 +32,16 @@ config ARCH_CHIP_R5F565NEDDFC
config ARCH_CHIP_R5F565NEHDFC
bool "R5F565NEHDFC"
select ARCH_RX65N_RSK2MB
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_SPI_BITORDER
---help---
Renesas RX65N on RSKRX65N-2MB
config ARCH_CHIP_R5F565NEHDFP
bool "R5F565NEHDFP"
select ARCH_RX65N_GRROSE
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_SPI_BITORDER
---help---
Renesas RX65N on GR-ROSE

24
arch/renesas/include/rx65n/irq.h
View file

@ -152,25 +152,31 @@
#endif
#ifdef CONFIG_RX65N_RIIC1
# define RX65N_RIIC1_RXI1_IRQ (RX65N_RIIC1_IRQBASE + RX_RXI_IRQ_OFFSET)
# define RX65N_RIIC1_TXI1_IRQ (RX65N_RIIC1_IRQBASE + RX_TXI_IRQ_OFFSET)
# define RX65N_RIIC0_IRQBASE (RX65N_RIIC1_IRQBASE + RX_SCI_NIRQS)
# define RX65N_RIIC1_RXI1_IRQ (RX65N_RIIC1_IRQBASE)
# define RX65N_RIIC1_TXI1_IRQ (RX65N_RIIC1_IRQBASE + 1)
# define RX65N_RIIC1_TEI1_IRQ (RX65N_RIIC1_IRQBASE + 2)
# define RX65N_RIIC1_EEI1_IRQ (RX65N_RIIC1_IRQBASE + 3)
# define RX65N_RIIC0_IRQBASE (RX65N_RIIC1_IRQBASE + 4)
#else
# define RX65N_RIIC0_IRQBASE (RX65N_RIIC1_IRQBASE)
#endif
#ifdef CONFIG_RX65N_RIIC0
# define RX65N_RIIC0_RXI0_IRQ (RX65N_RIIC0_IRQBASE + RX_RXI_IRQ_OFFSET)
# define RX65N_RIIC0_TXI0_IRQ (RX65N_RIIC0_IRQBASE + RX_TXI_IRQ_OFFSET)
# define RX65N_RIIC2_IRQBASE (RX65N_RIIC0_IRQBASE + RX_SCI_NIRQS)
# define RX65N_RIIC0_RXI0_IRQ (RX65N_RIIC0_IRQBASE)
# define RX65N_RIIC0_TXI0_IRQ (RX65N_RIIC0_IRQBASE + 1)
# define RX65N_RIIC0_TEI0_IRQ (RX65N_RIIC0_IRQBASE + 2)
# define RX65N_RIIC0_EEI0_IRQ (RX65N_RIIC0_IRQBASE + 3)
# define RX65N_RIIC2_IRQBASE (RX65N_RIIC0_IRQBASE + 4)
#else
# define RX65N_RIIC2_IRQBASE (RX65N_RIIC0_IRQBASE)
#endif
#ifdef CONFIG_RX65N_RIIC2
# define RX65N_RIIC2_RXI2_IRQ (RX65N_RIIC2_IRQBASE + RX_RXI_IRQ_OFFSET)
# define RX65N_RIIC2_TXI2_IRQ (RX65N_RIIC2_IRQBASE + RX_TXI_IRQ_OFFSET)
# define RX65N_SCI0_IRQBASE (RX65N_RIIC2_IRQBASE + RX_SCI_NIRQS)
# define RX65N_RIIC2_RXI2_IRQ (RX65N_RIIC2_IRQBASE)
# define RX65N_RIIC2_TXI2_IRQ (RX65N_RIIC2_IRQBASE + 1)
# define RX65N_RIIC2_TEI2_IRQ (RX65N_RIIC2_IRQBASE + 2)
# define RX65N_RIIC2_EEI2_IRQ (RX65N_RIIC2_IRQBASE + 3)
# define RX65N_SCI0_IRQBASE (RX65N_RIIC2_IRQBASE + 4)
#else
# define RX65N_SCI0_IRQBASE (RX65N_RIIC2_IRQBASE)
#endif

274
arch/renesas/src/rx65n/Kconfig
View file

@ -203,6 +203,143 @@ config RX65N_RTC
config RX65N_CARRY
bool "RTC"
default y
config RX65N_RIIC0
bool "RIIC0"
default n
depends on I2C && I2C_DRIVER
if RX65N_RIIC0
config RX65N_RIIC0_BITRATE
int "RIIC0 Bus Bit Rate"
default 400000
config RX65N_RIIC0_NF
bool "Enable Noise Filter for RIIC0"
default y
if RX65N_RIIC0_NF
config RX65N_RIIC0_NF_STAGE
int "RIIC0 Noise Filter Stages"
default 2
endif #RX65N_RIIC0_NF
config RX65N_RIIC0_SDA_DELAY
bool "Enable SDA Output Delay"
default n
if RX65N_RIIC0_SDA_DELAY
config RX65N_RIIC0_DELAY_CNT
int "Number of Cycles Delay"
default 1
endif #RX65N_RIIC0_SDA_DELAY
config RX65N_RIIC0_RCV_CONTINUOUS
bool "RIIC0 receive continuously"
default n
config RX65N_RIIC0_RCV_IN_BYTE_UNITS
bool "RIIC0 receive in byte units"
default y
depends on !RX65N_RIIC0_RCV_CONTINUOUS
endif #RX65N_RIIC0
config RX65N_RIIC1
bool "RIIC1"
default n
depends on I2C && I2C_DRIVER
if RX65N_RIIC1
config RX65N_RIIC1_BITRATE
int "RIIC1 Bus Bit Rate"
default 400000
config RX65N_RIIC1_NF
bool "Enable Noise Filter"
default y
if RX65N_RIIC1_NF
config RX65N_RIIC1_NF_STAGE
int "RIIC1 Noise Filter Stages"
default 2
endif #RX65N_RIIC1_NF
config RX65N_RIIC1_SDA_DELAY
bool "Enable SDA Output Delay"
default n
if RX65N_RIIC1_SDA_DELAY
config RX65N_RIIC1_DELAY_CNT
int "Number of Cycles Delay"
default 1
endif #RX65N_RIIC1_SDA_DELAY
config RX65N_RIIC1_RCV_CONTINUOUS
bool "RIIC1 receive continuously"
default n
config RX65N_RIIC1_RCV_IN_BYTE_UNITS
bool "RIIC1 receive in byte units"
default y
depends on !RX65N_RIIC1_RCV_CONTINUOUS
endif #RX65N_RIIC1
config RX65N_RIIC2
bool "RIIC2"
default n
depends on I2C && I2C_DRIVER
if RX65N_RIIC2
config RX65N_RIIC2_BITRATE
int "RIIC2 Bus Bit Rate"
default 400000
config RX65N_RIIC2_NF
bool "Enable Noise Filter"
default y
if RX65N_RIIC2_NF
config RX65N_RIIC2_NF_STAGE
int "RIIC2 Noise Filter Stages"
default 2
endif #RX65N_RIIC2_NF
config RX65N_RIIC2_SDA_DELAY
bool "Enable SDA Output Delay for RIIC2"
default n
if RX65N_RIIC2_SDA_DELAY
config RX65N_RIIC2_DELAY_CNT
int "Number of Cycles Delay"
default 1
endif #RX65N_RIIC2_SDA_DELAY
config RX65N_RIIC2_RCV_CONTINUOUS
bool "RIIC2 receive continuously"
default n
config RX65N_RIIC2_RCV_IN_BYTE_UNITS
bool "RIIC2 receive in byte units"
default y
depends on !RX65N_RIIC2_RCV_CONTINUOUS
endif #RX65N_RIIC2
endmenu # RX65N Peripheral Selections
endif
@ -336,6 +473,143 @@ config RX65N_EMAC0
select NETDEVICES
select ARCH_HAVE_PHY
config RX65N_RIIC0
bool "RIIC0"
default n
depends on I2C && I2C_DRIVER
if RX65N_RIIC0
config RX65N_RIIC0_BITRATE
int "RIIC0 Bus Bit Rate"
default 400000
config RX65N_RIIC0_NF
bool "Enable Noise Filter for RIIC0"
default y
if RX65N_RIIC0_NF
config RX65N_RIIC0_NF_STAGE
int "RIIC0 Noise Filter Stages"
default 2
endif #RX65N_RIIC0_NF
config RX65N_RIIC0_SDA_DELAY
bool "Enable SDA Output Delay"
default n
if RX65N_RIIC0_SDA_DELAY
config RX65N_RIIC0_DELAY_CNT
int "Number of Cycles Delay"
default 1
endif #RX65N_RIIC0_SDA_DELAY
config RX65N_RIIC0_RCV_CONTINUOUS
bool "RIIC0 receive continuously"
default n
config RX65N_RIIC0_RCV_IN_BYTE_UNITS
bool "RIIC0 receive in byte units"
default y
depends on !RX65N_RIIC0_RCV_CONTINUOUS
endif #RX65N_RIIC0
config RX65N_RIIC1
bool "RIIC1"
default n
depends on I2C && I2C_DRIVER
if RX65N_RIIC1
config RX65N_RIIC1_BITRATE
int "RIIC1 Bus Bit Rate"
default 400000
config RX65N_RIIC1_NF
bool "Enable Noise Filter for RIIC1"
default y
if RX65N_RIIC1_NF
config RX65N_RIIC1_NF_STAGE
int "RIIC1 Noise Filter Stages"
default 2
endif #RX65N_RIIC1_NF
config RX65N_RIIC1_SDA_DELAY
bool "Enable SDA Output Delay"
default n
if RX65N_RIIC1_SDA_DELAY
config RX65N_RIIC1_DELAY_CNT
int "Number of Cycles Delay"
default 1
endif #RX65N_RIIC1_SDA_DELAY
config RX65N_RIIC1_RCV_CONTINUOUS
bool "RIIC1 receive continuously"
default n
config RX65N_RIIC1_RCV_IN_BYTE_UNITS
bool "RIIC1 receive in byte units"
default y
depends on !RX65N_RIIC1_RCV_CONTINUOUS
endif #RX65N_RIIC1
config RX65N_RIIC2
bool "RIIC2"
default n
depends on I2C && I2C_DRIVER
if RX65N_RIIC2
config RX65N_RIIC2_BITRATE
int "RIIC2 Bus Bit Rate"
default 400000
config RX65N_RIIC2_NF
bool "Enable Noise Filter for RIIC2"
default y
if RX65N_RIIC2_NF
config RX65N_RIIC2_NF_STAGE
int "RIIC2 Noise Filter Stages"
default 2
endif #RX65N_RIIC2_NF
config RX65N_RIIC2_SDA_DELAY
bool "Enable SDA Output Delay"
default n
if RX65N_RIIC2_SDA_DELAY
config RX65N_RIIC2_DELAY_CNT
int "Number of Cycles Delay"
default 1
endif #RX65N_RIIC2_SDA_DELAY
config RX65N_RIIC2_RCV_CONTINUOUS
bool "RIIC2 receive continuously"
default n
config RX65N_RIIC2_RCV_IN_BYTE_UNITS
bool "RIIC2 receive in byte units"
default y
depends on !RX65N_RIIC2_RCV_CONTINUOUS
endif #RX65N_RIIC2
endmenu # RX65N Peripheral Selections
endif

3
arch/renesas/src/rx65n/Make.defs
View file

@ -57,4 +57,7 @@ endif
ifeq ($(CONFIG_RTC_DRIVER),y)
CHIP_CSRCS += rx65n_rtc_lowerhalf.c
endif
ifeq ($(CONFIG_I2C),y)
CHIP_CSRCS += rx65n_riic.c
endif

43
arch/renesas/src/rx65n/rx65n_cmtw0.c
View file

@ -1,35 +1,20 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_cmtw0.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author:Surya Prakash <surya.prakash@tataelxsi.co.in>
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* http://www.apache.org/licenses/LICENSE-2.0
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
@ -46,8 +31,8 @@
#include <errno.h>
#include "rx65n_cmtw0.h"
#include "rx65n/iodefine.h"
#include "rx65n/irq.h"
#include "arch/rx65n/iodefine.h"
#include "arch/rx65n/irq.h"
#include "rx65n_definitions.h"
#include <nuttx/irq.h>
#include "rx65n_eth.h"

303
arch/renesas/src/rx65n/rx65n_definitions.h
View file

@ -26,7 +26,7 @@
****************************************************************************/
#include <nuttx/config.h>
#include "rx65n/iodefine.h"
#include "arch/rx65n/iodefine.h"
#include "arch/board/board.h"
/****************************************************************************
@ -133,7 +133,7 @@
/* Bit 7: TDR does not contain valid transmit data */
#define RX_SCISSR_TDRE (0x80)
#define RX_SCISSR_TDRE (0x80)
#define RX65N_CMT_CMSTR0_ADDR (0x00088000) /* 8-bits wide */
#define RX65N_CMT0_CMCNT_ADDR (0x00088004)
#define RX65N_CMT0_CMCOR_ADDR (0x00088006)
@ -158,6 +158,7 @@
#define rx65n_cmtw0_timeout 2
#define RX65N_MSTPCRA_ADDR (0x00080010)
#define RX65N_MSTPCRB_ADDR (0x00080014)
#define RX65N_CMT0_TICKFREQ (100) /* 100Hz tick frequency */
#define RX65N_CMT_DIV32 (0x0001)
#define RX65N_CMT0_DIV_VALUE (32)
@ -212,10 +213,16 @@
#define RX65N_GRPBL0_ERI6_MASK (1U << 13) /* (0x00002000) */
#define RX65N_GRPBL0_TEI7_MASK (1U << 14) /* (0x00004000) */
#define RX65N_GRPBL0_ERI7_MASK (1U << 15) /* (0x00008000) */
#define RX65N_GRPBL1_TEI0_MASK (1U << 13)
#define RX65N_GRPBL1_EEI0_MASK (1U << 14)
#define RX65N_GRPBL1_TEI2_MASK (1U << 15)
#define RX65N_GRPBL1_EEI2_MASK (1U << 16)
#define RX65N_GRPBL1_TEI8_MASK (1U << 24)
#define RX65N_GRPBL1_ERI8_MASK (1U << 25)
#define RX65N_GRPBL1_TEI9_MASK (1U << 26)
#define RX65N_GRPBL1_ERI9_MASK (1U << 27)
#define RX65N_GRPBL1_TEI1_MASK (1U << 28)
#define RX65N_GRPBL1_EEI1_MASK (1U << 29)
#define RX65N_GRPAL0_TEI10_MASK (1U << 8)
#define RX65N_GRPAL0_ERI10_MASK (1U << 9)
#define RX65N_GRPAL0_TEI11_MASK (1U << 12)
@ -433,11 +440,11 @@
/* EDMAC Transmit Request Register's bit */
#define ETHD_EDRRR_TR (1) /* Transmit Request */
#define ETHD_EDRRR_TR (1) /* Transmit Request */
/* EDMAC Receive Request Register's bit */
#define ETHD_EDRRR_RR (1) /* Receive descriptor read,
#define ETHD_EDRRR_RR (1) /* Receive descriptor read,
* and receive function is enabled
*/
@ -470,17 +477,17 @@
/* PHY Interface Register's bit and values */
#define ETH_PIR_MDC (1) /* MII/RMII Management Data Clock */
#define ETH_PIR_MMD (1<<1) /* MII/RMII Management Mode */
#define ETH_PIR_MDO (1<<2) /* MII/RMII Management Data-Out */
#define ETH_PIR_MDI (1<<3) /* MII/RMII Management Data-In */
#define ETH_PIR_MDC (1) /* MII/RMII Management Data Clock */
#define ETH_PIR_MMD (1<<1) /* MII/RMII Management Mode */
#define ETH_PIR_MDO (1<<2) /* MII/RMII Management Data-Out */
#define ETH_PIR_MDI (1<<3) /* MII/RMII Management Data-In */
#define ETH_PIR_RESET_ALL (0x00000000) /* Reset All Flags of PIR */
#define ETH_PIR_SET_MDC (0x00000001) /* Setting MDC of PIR */
#define ETH_PIR_SET_MMD (0x00000002) /* Setting MMD of PIR */
#define ETH_PIR_SET_MMD_MDC (0x00000003) /* Setting MMD and MDC */
#define ETH_PIR_SET_MDO_MMD (0x00000006) /* Setting MDO and MMD */
#define ETH_PIR_SET_MDO_MMD_MDC (0x00000007) /* Setting MDO, MMD and MDC */
#define ETH_PIR_RESET_ALL (0x00000000) /* Reset All Flags of PIR */
#define ETH_PIR_SET_MDC (0x00000001) /* Setting MDC of PIR */
#define ETH_PIR_SET_MMD (0x00000002) /* Setting MMD of PIR */
#define ETH_PIR_SET_MMD_MDC (0x00000003) /* Setting MMD and MDC */
#define ETH_PIR_SET_MDO_MMD (0x00000006) /* Setting MDO and MMD */
#define ETH_PIR_SET_MDO_MMD_MDC (0x00000007) /* Setting MDO, MMD and MDC */
/* Ethernet Control Register's bit and value */
@ -520,64 +527,66 @@
#define RX65N_RTC_RCR4_OFFSET (0x0028)
#define RX65N_RTC_RADJ_OFFSET (0x002e)
#define RX65N_RTC_BASE (0x0008c400)
#define RX65N_RTC_R64CNT (RX65N_RTC_BASE + RX65N_RTC_R64CNT_OFFSET)
#define RX65N_RTC_RSECCNT (RX65N_RTC_BASE + RX65N_RTC_RSECCNT_OFFSET)
#define RX65N_RTC_RMINCNT (RX65N_RTC_BASE + RX65N_RTC_RMINCNT_OFFSET)
#define RX65N_RTC_RHRCNT (RX65N_RTC_BASE + RX65N_RTC_RHRCNT_OFFSET)
#define RX65N_RTC_RWKCNT (RX65N_RTC_BASE + RX65N_RTC_RWKCNT_OFFSET)
#define RX65N_RTC_RDAYCNT (RX65N_RTC_BASE + RX65N_RTC_RDAYCNT_OFFSET)
#define RX65N_RTC_RMONCNT (RX65N_RTC_BASE + RX65N_RTC_RMONCNT_OFFSET)
#define RX65N_RTC_RYRCNT (RX65N_RTC_BASE + RX65N_RTC_RYRCNT_OFFSET)
#define RX65N_RTC_RSECAR (RX65N_RTC_BASE + RX65N_RTC_RSECAR_OFFSET)
#define RX65N_RTC_RMINAR (RX65N_RTC_BASE + RX65N_RTC_RMINAR_OFFSET)
#define RX65N_RTC_RHRAR (RX65N_RTC_BASE + RX65N_RTC_RHRAR_OFFSET)
#define RX65N_RTC_RWKAR (RX65N_RTC_BASE + RX65N_RTC_RWKAR_OFFSET)
#define RX65N_RTC_RDAYAR (RX65N_RTC_BASE + RX65N_RTC_RDAYAR_OFFSET)
#define RX65N_RTC_RMONAR (RX65N_RTC_BASE + RX65N_RTC_RMONAR_OFFSET)
#define RX65N_RTC_RYRAR (RX65N_RTC_BASE + RX65N_RTC_RYRAR_OFFSET)
#define RX65N_RTC_RYRAREN (RX65N_RTC_BASE + RX65N_RTC_RYRAREN_OFFSET)
#define RX65N_RTC_RCR1 (RX65N_RTC_BASE + RX65N_RTC_RCR1_OFFSET)
#define RX65N_RTC_RCR2 (RX65N_RTC_BASE + RX65N_RTC_RCR2_OFFSET)
#define RX65N_RTC_RCR3 (RX65N_RTC_BASE + RX65N_RTC_RCR3_OFFSET)
#define RX65N_RTC_RCR4 (RX65N_RTC_BASE + RX65N_RTC_RCR4_OFFSET)
#define RX65N_RTC_RADJ (RX65N_RTC_BASE + RX65N_RTC_RADJ_OFFSET)
#define RX65N_RTC_BASE (0x0008c400)
#define RX65N_RTC_R64CNT (RX65N_RTC_BASE + RX65N_RTC_R64CNT_OFFSET)
#define RX65N_RTC_RSECCNT (RX65N_RTC_BASE + RX65N_RTC_RSECCNT_OFFSET)
#define RX65N_RTC_RMINCNT (RX65N_RTC_BASE + RX65N_RTC_RMINCNT_OFFSET)
#define RX65N_RTC_RHRCNT (RX65N_RTC_BASE + RX65N_RTC_RHRCNT_OFFSET)
#define RX65N_RTC_RWKCNT (RX65N_RTC_BASE + RX65N_RTC_RWKCNT_OFFSET)
#define RX65N_RTC_RDAYCNT (RX65N_RTC_BASE + RX65N_RTC_RDAYCNT_OFFSET)
#define RX65N_RTC_RMONCNT (RX65N_RTC_BASE + RX65N_RTC_RMONCNT_OFFSET)
#define RX65N_RTC_RYRCNT (RX65N_RTC_BASE + RX65N_RTC_RYRCNT_OFFSET)
#define RX65N_RTC_RSECAR (RX65N_RTC_BASE + RX65N_RTC_RSECAR_OFFSET)
#define RX65N_RTC_RMINAR (RX65N_RTC_BASE + RX65N_RTC_RMINAR_OFFSET)
#define RX65N_RTC_RHRAR (RX65N_RTC_BASE + RX65N_RTC_RHRAR_OFFSET)
#define RX65N_RTC_RWKAR (RX65N_RTC_BASE + RX65N_RTC_RWKAR_OFFSET)
#define RX65N_RTC_RDAYAR (RX65N_RTC_BASE + RX65N_RTC_RDAYAR_OFFSET)
#define RX65N_RTC_RMONAR (RX65N_RTC_BASE + RX65N_RTC_RMONAR_OFFSET)
#define RX65N_RTC_RYRAR (RX65N_RTC_BASE + RX65N_RTC_RYRAR_OFFSET)
#define RX65N_RTC_RYRAREN (RX65N_RTC_BASE + RX65N_RTC_RYRAREN_OFFSET)
#define RX65N_RTC_RCR1 (RX65N_RTC_BASE + RX65N_RTC_RCR1_OFFSET)
#define RX65N_RTC_RCR2 (RX65N_RTC_BASE + RX65N_RTC_RCR2_OFFSET)
#define RX65N_RTC_RCR3 (RX65N_RTC_BASE + RX65N_RTC_RCR3_OFFSET)
#define RX65N_RTC_RCR4 (RX65N_RTC_BASE + RX65N_RTC_RCR4_OFFSET)
#define RX65N_RTC_RADJ (RX65N_RTC_BASE + RX65N_RTC_RADJ_OFFSET)
#define RTC_RTC_ALRDIS (0x00)
#define RTC_RCR4_RCKSEL (0x00)
#define RTC_RCR3_RTCEN (0x01)
#define RTC_RCR3_RTCDV (0x02)
#define RTC_RCR2_START (0x01)
#define RTC_RCR2_CNTMD (0x00)
#define RTC_RCR2_RESET (0x01)
#define RTC_ALARM_INT_ENABLE (0x01)
#define RTC_CARRY_INT_ENABLE (0x02)
#define RTC_PERIOD_INT_ENABLE (0x04)
#define RTC_PERIODIC_INT_PERIOD_1 (0xe0)
#define _04_FOUR_READ_COUNT (0x04)
#define RTC_1_64_SEC_CYCLE (0x0005b8d9)
#define _0F_RTC_PRIORITY_LEVEL15 (0x0f)
#define RTC_RCR1_CUP (0x02)
#define RX65N_SUBCLKOSC_SOSCCR (0x00080033)
#define SUBCLKOSC_SOSCCR_SOSTP (0x01)
#define RX65N_SUBCLKOSC_SOSCWTCR (0x0008c293)
#define RTC_SOSCWTCR_VALUE (0x21)
#define RTC_DUMMY_READ (3)
#define _00_RTC_PRIORITY_LEVEL0 (0)
#define _04_RTC_PERIOD_INT_ENABLE (0x04)
#define RTC_RTC_CARRYDIS (0xe5)
#define RTC_RTC_PERDIS (0xe3)
#define RTC_RADJ_INITVALUE (0x0)
#define RTC_RCR2_AADJE (0x10)
#define RTC_RCR2_AADJP (0x20)
#define RTC_RTC_ALRDIS (0x00)
#define RTC_RCR4_RCKSEL (0x00)
#define RTC_RCR3_RTCEN (0x01)
#define RTC_RCR3_RTCDV (0x02)
#define RTC_RCR2_START (0x01)
#define RTC_RCR2_CNTMD (0x00)
#define RTC_RCR2_RESET (0x01)
#define RTC_ALARM_INT_ENABLE (0x01)
#define RTC_CARRY_INT_ENABLE (0x02)
#define RTC_PERIOD_INT_ENABLE (0x04)
#define RTC_PERIODIC_INT_PERIOD_1 (0xe0)
#define _04_FOUR_READ_COUNT (0x04)
#define RTC_1_64_SEC_CYCLE (0x0005b8d9)
#define _0F_RTC_PRIORITY_LEVEL15 (0x0f)
#define RTC_RCR1_CUP (0x02)
#define RX65N_SUBCLKOSC_SOSCCR (0x00080033)
#define SUBCLKOSC_SOSCCR_SOSTP (0x01)
#define RX65N_SUBCLKOSC_SOSCWTCR (0x0008c293)
#define RTC_SOSCWTCR_VALUE (0x21)
#define RTC_DUMMY_READ (3)
#define _00_RTC_PRIORITY_LEVEL0 (0)
#define _04_RTC_PERIOD_INT_ENABLE (0x04)
#define RTC_RTC_CARRYDIS (0xe5)
#define RTC_RTC_PERDIS (0xe3)
#define RTC_RADJ_INITVALUE (0x0)
#define RTC_RCR2_AADJE (0x10)
#define RTC_RCR2_AADJP (0x20)
#if defined(CONFIG_RTC) || defined(CONFIG_RTC_DRIVER)
#define HAVE_RTC_DRIVER 1
#define HAVE_RTC_DRIVER 1
#endif
#define RX65N_RTC_WAIT_PERIOD 184
/* Constant values used in RTC */
#define RX65N_RTC_WAIT_PERIOD 184
#define RTC_RCR2_HR24 (0x40)
#define RTC_PERIODIC_INTERRUPT_2_SEC (0xf)
@ -585,6 +594,170 @@
#define RX65N_SBRAM_BASE 0x000a4000
/* RIIC related definitions */
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_DRIVER)
#define HAVE_RIIC_DRIVER 1
#endif
/* RIIC Channel Base Address definitions */
#define RX65N_RIIC0_BASE (uint32_t)&RIIC0
#define RX65N_RIIC1_BASE (uint32_t)&RIIC1
#define RX65N_RIIC2_BASE (uint32_t)&RIIC2
/* RIIC Register Offset definitions */
#define RX65N_RIIC_ICCR1_OFFSET (0x0000)
#define RX65N_RIIC_ICCR2_OFFSET (0x0001)
#define RX65N_RIIC_ICMR1_OFFSET (0x0002)
#define RX65N_RIIC_ICMR2_OFFSET (0x0003)
#define RX65N_RIIC_ICMR3_OFFSET (0x0004)
#define RX65N_RIIC_ICFER_OFFSET (0x0005)
#define RX65N_RIIC_ICSER_OFFSET (0x0006)
#define RX65N_RIIC_ICIER_OFFSET (0x0007)
#define RX65N_RIIC_ICSR1_OFFSET (0x0008)
#define RX65N_RIIC_ICSR2_OFFSET (0x0009)
#define RX65N_RIIC_SARL0_OFFSET (0x000a)
#define RX65N_RIIC_SARU0_OFFSET (0x000b)
#define RX65N_RIIC_SARL1_OFFSET (0x000c)
#define RX65N_RIIC_SARU1_OFFSET (0x000d)
#define RX65N_RIIC_SARL2_OFFSET (0x000e)
#define RX65N_RIIC_SARU2_OFFSET (0x000f)
#define RX65N_RIIC_ICBRL_OFFSET (0x0010)
#define RX65N_RIIC_ICBRH_OFFSET (0x0011)
#define RX65N_RIIC_ICDRT_OFFSET (0x0012)
#define RX65N_RIIC_ICDRR_OFFSET (0x0013)
/* RIIC register address definitions */
#define RX65N_RIIC0_ICCR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICCR1_OFFSET)
#define RX65N_RIIC0_ICCR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICCR2_OFFSET)
#define RX65N_RIIC0_ICMR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR1_OFFSET)
#define RX65N_RIIC0_ICMR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR2_OFFSET)
#define RX65N_RIIC0_ICMR3 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR3_OFFSET)
#define RX65N_RIIC0_ICFER (RX65N_RIIC0_BASE + RX65N_RIIC_ICFER_OFFSET)
#define RX65N_RIIC0_ICSER (RX65N_RIIC0_BASE + RX65N_RIIC_ICSER_OFFSET)
#define RX65N_RIIC0_ICIER (RX65N_RIIC0_BASE + RX65N_RIIC_ICIER_OFFSET)
#define RX65N_RIIC0_ICSR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICSR1_OFFSET)
#define RX65N_RIIC0_ICSR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICSR2_OFFSET)
#define RX65N_RIIC0_SARL0 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL0_OFFSET)
#define RX65N_RIIC0_SARU0 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU0_OFFSET)
#define RX65N_RIIC0_SARL1 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL1_OFFSET)
#define RX65N_RIIC0_SARU1 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU1_OFFSET)
#define RX65N_RIIC0_SARL2 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL2_OFFSET)
#define RX65N_RIIC0_SARU2 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU2_OFFSET)
#define RX65N_RIIC0_ICBRL (RX65N_RIIC0_BASE + RX65N_RIIC_ICBRL_OFFSET)
#define RX65N_RIIC0_ICBRH (RX65N_RIIC0_BASE + RX65N_RIIC_ICBRH_OFFSET)
#define RX65N_RIIC0_ICDRT (RX65N_RIIC0_BASE + RX65N_RIIC_ICDRT_OFFSET)
#define RX65N_RIIC0_ICDRR (RX65N_RIIC0_BASE + RX65N_RIIC_ICDRR_OFFSET)
#define RX65N_RIIC1_ICCR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICCR1_OFFSET)
#define RX65N_RIIC1_ICCR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICCR2_OFFSET)
#define RX65N_RIIC1_ICMR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR1_OFFSET)
#define RX65N_RIIC1_ICMR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR2_OFFSET)
#define RX65N_RIIC1_ICMR3 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR3_OFFSET)
#define RX65N_RIIC1_ICFER (RX65N_RIIC1_BASE + RX65N_RIIC_ICFER_OFFSET)
#define RX65N_RIIC1_ICSER (RX65N_RIIC1_BASE + RX65N_RIIC_ICSER_OFFSET)
#define RX65N_RIIC1_ICIER (RX65N_RIIC1_BASE + RX65N_RIIC_ICIER_OFFSET)
#define RX65N_RIIC1_ICSR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICSR1_OFFSET)
#define RX65N_RIIC1_ICSR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICSR2_OFFSET)
#define RX65N_RIIC1_SARL0 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL0_OFFSET)
#define RX65N_RIIC1_SARU0 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU0_OFFSET)
#define RX65N_RIIC1_SARL1 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL1_OFFSET)
#define RX65N_RIIC1_SARU1 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU1_OFFSET)
#define RX65N_RIIC1_SARL2 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL2_OFFSET)
#define RX65N_RIIC1_SARU2 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU2_OFFSET)
#define RX65N_RIIC1_ICBRL (RX65N_RIIC1_BASE + RX65N_RIIC_ICBRL_OFFSET)
#define RX65N_RIIC1_ICBRH (RX65N_RIIC1_BASE + RX65N_RIIC_ICBRH_OFFSET)
#define RX65N_RIIC1_ICDRT (RX65N_RIIC1_BASE + RX65N_RIIC_ICDRT_OFFSET)
#define RX65N_RIIC1_ICDRR (RX65N_RIIC1_BASE + RX65N_RIIC_ICDRR_OFFSET)
#define RX65N_RIIC2_ICCR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICCR1_OFFSET)
#define RX65N_RIIC2_ICCR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICCR2_OFFSET)
#define RX65N_RIIC2_ICMR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR1_OFFSET)
#define RX65N_RIIC2_ICMR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR2_OFFSET)
#define RX65N_RIIC2_ICMR3 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR3_OFFSET)
#define RX65N_RIIC2_ICFER (RX65N_RIIC2_BASE + RX65N_RIIC_ICFER_OFFSET)
#define RX65N_RIIC2_ICSER (RX65N_RIIC2_BASE + RX65N_RIIC_ICSER_OFFSET)
#define RX65N_RIIC2_ICIER (RX65N_RIIC2_BASE + RX65N_RIIC_ICIER_OFFSET)
#define RX65N_RIIC2_ICSR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICSR1_OFFSET)
#define RX65N_RIIC2_ICSR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICSR2_OFFSET)
#define RX65N_RIIC2_SARL0 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL0_OFFSET)
#define RX65N_RIIC2_SARU0 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU0_OFFSET)
#define RX65N_RIIC2_SARL1 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL1_OFFSET)
#define RX65N_RIIC2_SARU1 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU1_OFFSET)
#define RX65N_RIIC2_SARL2 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL2_OFFSET)
#define RX65N_RIIC2_SARU2 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU2_OFFSET)
#define RX65N_RIIC2_ICBRL (RX65N_RIIC2_BASE + RX65N_RIIC_ICBRL_OFFSET)
#define RX65N_RIIC2_ICBRH (RX65N_RIIC2_BASE + RX65N_RIIC_ICBRH_OFFSET)
#define RX65N_RIIC2_ICDRT (RX65N_RIIC2_BASE + RX65N_RIIC_ICDRT_OFFSET)
#define RX65N_RIIC2_ICDRR (RX65N_RIIC2_BASE + RX65N_RIIC_ICDRR_OFFSET)
/* RIIC register field/bit value definitions */
#define RX65N_RIIC_ICCR1_ICE_RST (0x7f)
#define RX65N_RIIC_ICCR1_IICRST_SET (0x40)
#define RX65N_RIIC_ICCR2_ST_SET (0x02)
#define RX65N_RIIC_ICCR2_SP_SET (0x08)
#define RX65N_RIIC_ICCR2_RS_SET (0x04)
#define RX65N_RIIC_ICSR2_STOP_SET (0x08)
#define RX65N_RIIC_ICSR2_START_SET (0x04)
#define RX65N_RIIC_ICMR1_CKS_MASK (0x8f)
#define RX65N_RIIC_ICMR2_SDDL0 (0x06)
#define RX65N_RIIC_ICMR2_SDDL1 (0x16)
#define RX65N_RIIC_ICMR2_SDDL2 (0x26)
#define RX65N_RIIC_ICMR2_SDDL3 (0x36)
#define RX65N_RIIC_ICMR2_SDDL4 (0x46)
#define RX65N_RIIC_ICMR2_SDDL5 (0x56)
#define RX65N_RIIC_ICMR2_SDDL6 (0x66)
#define RX65N_RIIC_ICMR2_SDDL7 (0x76)
#define RX65N_RIIC_ICMR3_NF1 (0x00)
#define RX65N_RIIC_ICMR3_NF2 (0x01)
#define RX65N_RIIC_ICMR3_NF3 (0x02)
#define RX65N_RIIC_ICMR3_NF4 (0x03)
#define RX65N_RIIC_ICMR3_WAIT_SET (0x40)
#define RX65N_RIIC_ICMR3_ACKWP_SET (0x10)
#define RX65N_RIIC_ICMR3_ACKBT_SET (0x08)
#define RX65N_RIIC_ICMR3_ACKWP_CLR (0xEF)
#define RX65N_RIIC_ICMR3_RDRFS_SET (0x20)
#define RX65N_RIIC_ICIER_ALIE (0x02)
#define RX65N_RIIC_ICIER_ST_NAK_AL (0x16)
#define RX65N_RIIC_ICIER_SP_NAK_AL (0x1a)
#define RX65N_RIIC_ICIER_SP_AL (0x0a)
#define RX65N_RIIC_ICIER_TMO (0x01)
#define RX65N_RIIC_ICIER_TEND_NAK_AL (0x52)
#define RX65N_RIIC_ICIER_RX_NAK_AL (0x32)
#define RX65N_RIIC_ICFER_TMOE_SET (0x01)
#define RX65N_RIIC_ICFER_NFE_SET (0x20)
#define RX65N_RIIC_ICFER_NFE_RST (0xdf)
#define RX65N_RIIC_ICSER_SET (0x00)
#define RX65N_RIIC_ICBRL_MASK (0xe0)
#define RX65N_RIIC_ICBRH_MASK (0xe0)
#define RX65N_I2C_SLV_ADDR (0x80)
#define RX65N_RIIC_READ_MASK (0x01)
#define RX65N_RIIC_10BIT_SARU_MASK (0x0300)
#define RX65N_RIIC_10BIT_SARL_MASK (0x00ff)
#define BUS_CHECK_COUNTER (1000)
#define RIIC_REG_INIT (0x00)
#define RIIC_BUS_BUSY ((bool)(1))
#define RIIC_BUS_FREE ((bool)(0))
/* End of RIIC related definitions */
/****************************************************************************
* Public Types
****************************************************************************/

2
arch/renesas/src/rx65n/rx65n_dumpstate.c
View file

@ -34,7 +34,7 @@
#include "up_internal.h"
#include "sched/sched.h"
#include "chip.h"
#include "rx65n/irq.h"
#include "arch/rx65n/irq.h"
#ifdef CONFIG_ARCH_STACKDUMP

1
arch/renesas/src/rx65n/rx65n_eth.h
View file

@ -26,6 +26,7 @@
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/wdog.h>
#include "chip.h"
/****************************************************************************

2
arch/renesas/src/rx65n/rx65n_initialstate.c
View file

@ -31,7 +31,7 @@
#include "chip/chip.h"
#include "up_internal.h"
#include "up_arch.h"
#include "rx65n/irq.h"
#include "arch/rx65n/irq.h"
/****************************************************************************
* Pre-processor Definitions

144
arch/renesas/src/rx65n/rx65n_irq.c
View file

@ -27,7 +27,7 @@
#include <stdint.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include "rx65n/iodefine.h"
#include "arch/rx65n/iodefine.h"
#include "up_internal.h"
@ -426,6 +426,77 @@ void up_disable_irq(int irq)
#endif
#endif
#ifdef CONFIG_RX65N_RIIC0
if (irq == RX65N_RIIC0_RXI0_IRQ)
{
ICU.IER[6].BIT.IEN4 = 0;
}
if (irq == RX65N_RIIC0_TXI0_IRQ)
{
ICU.IER[6].BIT.IEN5 = 0;
}
if (irq == RX65N_RIIC0_TEI0_IRQ)
{
ICU.GRPBL1.BIT.IS13 = 0;
ICU.GENBL1.BIT.EN13 = 0;
}
if (irq == RX65N_RIIC0_EEI0_IRQ)
{
ICU.GRPBL1.BIT.IS14 = 0;
ICU.GENBL1.BIT.EN14 = 0;
}
#endif
#ifdef CONFIG_RX65N_RIIC1
if (irq == RX65N_RIIC1_RXI1_IRQ)
{
ICU.IER[6].BIT.IEN2 = 0;
}
if (irq == RX65N_RIIC1_TXI1_IRQ)
{
ICU.IER[6].BIT.IEN3 = 0;
}
if (irq == RX65N_RIIC1_TEI1_IRQ)
{
ICU.GRPBL1.BIT.IS28 = 0;
ICU.GENBL1.BIT.EN28 = 0;
}
if (irq == RX65N_RIIC1_EEI1_IRQ)
{
ICU.GRPBL1.BIT.IS29 = 0;
ICU.GENBL1.BIT.EN29 = 0;
}
#endif
#ifdef CONFIG_RX65N_RIIC2
if (irq == RX65N_RIIC2_RXI2_IRQ)
{
ICU.IER[6].BIT.IEN6 = 0;
}
if (irq == RX65N_RIIC2_TXI2_IRQ)
{
ICU.IER[6].BIT.IEN7 = 0;
}
if (irq == RX65N_RIIC2_TEI2_IRQ)
{
ICU.GRPBL1.BIT.IS15 = 0;
ICU.GENBL1.BIT.EN15 = 0;
}
if (irq == RX65N_RIIC2_EEI2_IRQ)
{
ICU.GRPBL1.BIT.IS16 = 0;
ICU.GENBL1.BIT.EN16 = 0;
}
#endif
}
/****************************************************************************
@ -785,4 +856,75 @@ void up_enable_irq(int irq)
#endif
#endif
#ifdef CONFIG_RX65N_RIIC0
if (irq == RX65N_RIIC0_RXI0_IRQ)
{
ICU.IER[6].BIT.IEN4 = 1;
}
if (irq == RX65N_RIIC0_TXI0_IRQ)
{
ICU.IER[6].BIT.IEN5 = 1;
}
if (irq == RX65N_RIIC0_TEI0_IRQ)
{
ICU.GRPBL1.BIT.IS13 = 1;
ICU.GENBL1.BIT.EN13 = 1;
}
if (irq == RX65N_RIIC0_EEI0_IRQ)
{
ICU.GRPBL1.BIT.IS14 = 1;
ICU.GENBL1.BIT.EN14 = 1;
}
#endif
#ifdef CONFIG_RX65N_RIIC1
if (irq == RX65N_RIIC1_RXI1_IRQ)
{
ICU.IER[6].BIT.IEN2 = 1;
}
if (irq == RX65N_RIIC1_TXI1_IRQ)
{
ICU.IER[6].BIT.IEN3 = 1;
}
if (irq == RX65N_RIIC1_TEI1_IRQ)
{
ICU.GRPBL1.BIT.IS28 = 1;
ICU.GENBL1.BIT.EN28 = 1;
}
if (irq == RX65N_RIIC1_EEI1_IRQ)
{
ICU.GRPBL1.BIT.IS29 = 1;
ICU.GENBL1.BIT.EN29 = 1;
}
#endif
#ifdef CONFIG_RX65N_RIIC2
if (irq == RX65N_RIIC2_RXI2_IRQ)
{
ICU.IER[6].BIT.IEN6 = 1;
}
if (irq == RX65N_RIIC2_TXI2_IRQ)
{
ICU.IER[6].BIT.IEN7 = 1;
}
if (irq == RX65N_RIIC2_TEI2_IRQ)
{
ICU.GRPBL1.BIT.IS15 = 1;
ICU.GENBL1.BIT.EN15 = 1;
}
if (irq == RX65N_RIIC2_EEI2_IRQ)
{
ICU.GRPBL1.BIT.IS16 = 1;
ICU.GENBL1.BIT.EN16 = 1;
}
#endif
}

2
arch/renesas/src/rx65n/rx65n_macrodriver.h
View file

@ -25,7 +25,7 @@
* Included Files
****************************************************************************/
#include "rx65n/iodefine.h"
#include "arch/rx65n/iodefine.h"
#ifndef TRUE
#define TRUE (1)

3131
arch/renesas/src/rx65n/rx65n_riic.c Normal file
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File diff suppressed because it is too large Load diff

95
arch/renesas/src/rx65n/rx65n_riic.h Normal file
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@ -0,0 +1,95 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_riic.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RENESAS_SRC_RX65N_RX65N_RIIC_H
#define __ARCH_RENESAS_SRC_RX65N_RX65N_RIIC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/i2c/i2c_master.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define SCL_RISE_TIME_FASTPLUS 120E-9
#define SCL_FALL_TIME_FASTPLUS 120E-9
#define SCL_RISE_TIME_FAST 300E-9
#define SCL_FALL_TIME_FAST 300E-9
#define SCL_RISE_TIME_STANDARD 1000E-9
#define SCL_FALL_TIME_STANDARD 300E-9
#define RIIC_MAX_DIV 0x08
#define RIIC_CALC_MAX 32
#define RIIC_INTERRUPT_PRIO (0x0f)
#define RIIC_RATE_CALC (0xff)
#define RIIC_SUCCESS 0 /* Successful operation */
#define RIIC_ERR_NO_INIT 1 /* Uninitialized state */
#define RIIC_ERR_BUS_BUSY 2 /* Channel is on communication. */
#define RIIC_ERR_AL 3 /* Arbitration lost error */
#define RIIC_ERR_TMO 4 /* Time Out error */
#define RIIC_ERR_NACK 5 /* NACK reception */
#define RIIC_ERR_OTHER 6 /* Other error */
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: rx65n_i2cbus_initialize
*
* Description:
* Initialize the selected RIIC channel. And return a unique instance of
* struct i2c_master_s. This function may be called to obtain multiple
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
* Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
* Valid I2C device structure reference on success; a NULL on failure
*
****************************************************************************/
FAR struct i2c_master_s *rx65n_i2cbus_initialize(int channel);
/****************************************************************************
* Name: rx65n_i2cbus_uninitialize
*
* Description:
* De-initialize the selected I2C port, and power down the device.
*
* Input Parameters:
* Device structure as returned by the rx65n_i2cbus_initialize()
*
* Returned Value:
* OK on success, ERROR when internal reference count mismatch or dev
* points to invalid hardware device.
*
****************************************************************************/
int rx65n_i2cbus_uninitialize(FAR struct i2c_master_s *dev);
#endif /* __ARCH_RENESAS_SRC_RX65N_RX65N_RIIC_H */

4
arch/renesas/src/rx65n/rx65n_serial.c
View file

@ -37,13 +37,13 @@
#include <nuttx/arch.h>
#include <nuttx/serial/serial.h>
#include "rx65n_macrodriver.h"
#include "rx65n/iodefine.h"
#include "arch/rx65n/iodefine.h"
#include "chip.h"
#include "up_arch.h"
#include "up_internal.h"
#include "rx65n_definitions.h"
#include "rx65n_sci.h"
#include "rx65n/irq.h"
#include "arch/rx65n/irq.h"
/****************************************************************************
* Pre-processor Definitions

4
arch/renesas/src/rx65n/rx65n_timerisr.c
View file

@ -30,11 +30,11 @@
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/board/board.h>
#include "rx65n/irq.h"
#include "arch/rx65n/irq.h"
#include "clock/clock.h"
#include "up_internal.h"
#include "up_arch.h"
#include "rx65n/iodefine.h"
#include "arch/rx65n/iodefine.h"
#include "chip.h"
#include "rx65n_cmt.h"

57
arch/renesas/src/rx65n/rx65n_vector.S
View file

@ -1,36 +1,20 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_vector.S
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
* Surya <surya.prakash@tataelxsi.co.in>
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* http://www.apache.org/licenses/LICENSE-2.0
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
@ -42,7 +26,7 @@
#include <arch/board/board.h> /* Board-specific settings */
#include <arch/irq.h> /* IRQ definitions */
#include "up_internal.h"
#include "rx65n/iodefine.h"
#include "arch/rx65n/iodefine.h"
#include "rx65n_definitions.h"
/****************************************************************************
@ -564,6 +548,21 @@ _uprx65_groupbl1_handler:
multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 27, RX65N_ERI9_IRQ
#endif /* CONFIG_RX65N_SCI9 */
#ifdef CONFIG_RX65N_RIIC0
multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 13, RX65N_RIIC0_TEI0_IRQ
multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 14, RX65N_RIIC0_EEI0_IRQ
#endif /* CONFIG_RX65N_RIIC0 */
#ifdef CONFIG_RX65N_RIIC2
multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 15, RX65N_RIIC2_TEI2_IRQ
multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 16, RX65N_RIIC2_EEI2_IRQ
#endif /* CONFIG_RX65N_RIIC2 */
#ifdef CONFIG_RX65N_RIIC1
multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 28, RX65N_RIIC1_TEI1_IRQ
multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 29, RX65N_RIIC1_EEI1_IRQ
#endif /* CONFIG_RX65N_RIIC1 */
/* TODO: Please write the others with
* definition RX65N_XXX_IRQ in irq.h as IRQ number
*/

53
boards/renesas/rx65n/rx65n-grrose/include/rx65n_gpio.h
View file

@ -228,5 +228,58 @@ void sci6_init_port(void);
#ifdef CONFIG_RX65N_SCI8
void sci8_init_port(void);
#endif
/****************************************************************************
* Name: riic0_init_port
*
* Description:
* RIIC0 Initialization RX65N GRROSE
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RX65N_RIIC0
void riic0_init_port(void);
#endif
/****************************************************************************
* Name: riic1_init_port
*
* Description:
* RIIC1 Initialization RX65N GRROSE
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RX65N_RIIC1
void riic1_init_port(void);
#endif
/****************************************************************************
* Name: riic2_init_port
*
* Description:
* RIIC2 Initialization RX65N GRROSE
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RX65N_RIIC2
void riic2_init_port(void);
#endif
#endif /* __BOARDS_RENESAS_RX65N_RX65N_GRROSE_INCLUDE_RX65N_GPIO_H */

39
boards/renesas/rx65n/rx65n-grrose/src/rx65n_bringup.c
View file

@ -43,6 +43,10 @@
# include "rx65n_rtc.h"
#endif
#ifdef HAVE_RIIC_DRIVER
# include <nuttx/i2c/i2c_master.h>
# include "rx65n_riic.h"
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -129,6 +133,41 @@ int rx65n_bringup(void)
/* Initialize battery-backed RAM */
(void)rx65n_sbram_int();
#endif
#ifdef HAVE_RIIC_DRIVER
FAR struct i2c_master_s *i2c;
/* Get the I2C lower half instance */
#ifdef CONFIG_RX65N_RIIC0
#ifdef CONFIG_RX65N_SCI2
i2cerr("Port is initialized for RIIC0. SCI2 cannot be used\n");
#endif
riic0_init_port();
i2c = rx65n_i2cbus_initialize(0);
if (i2c == NULL)
{
i2cerr("ERROR: Initialization of RIIC Channel 0 failed: %d\n", ret);
}
else
{
/* Register the I2C character driver */
ret = i2c_register(i2c, 0);
if (ret < 0)
{
i2cerr("ERROR: Failed to register RIIC device: %d\n", ret);
}
}
#endif
#ifdef CONFIG_RX65N_RIIC1
i2cerr("RIIC1 setting is not supported on GR-ROSE Board\n");
#endif
#ifdef CONFIG_RX65N_RIIC2
i2cerr("RIIC2 setting is not supported on GR-ROSE Board\n");
i2cerr("It is used for USB port and cannot be configured\n");
#endif
#endif
return OK;
}

83
boards/renesas/rx65n/rx65n-grrose/src/rx65n_gpio.c
View file

@ -158,23 +158,6 @@ void r_ether_pheriperal_enable(void)
MPC.PA6PFS.BYTE = 0x12u;
PORTA.PMR.BIT.B6 = 1u;
/* Set VBUS pin for USB */
/* Referred from r_usb_basic_pinset.c */
MPC.P16PFS.BYTE = 0x12u;
/* PORT1.PMR.BYTE |= 0x40; */
PORT1.PMR.BIT.B6 = 1u;
/* Set USB0_OVRCURA pin */
/* GR Rose does not contain any of OVRCURA/B inputs
* MPC.P14PFS.BYTE = 0x12u;
* PORT1.PMR.BIT.B4 = 1u;
*/
}
#endif
@ -355,4 +338,70 @@ inline void sci8_init_port(void)
PORTC.PMR.BIT.B7 = 1u;
}
#endif
/****************************************************************************
* Name: riic0_init_port
*
* Description:
* RIIC0 Initialization RX65N GRROSE
****************************************************************************/
#ifdef CONFIG_RX65N_RIIC0
inline void riic0_init_port(void)
{
/* Set SCL0 pin (P12) */
MPC.P12PFS.BYTE = 0x0fu;
PORT1.PMR.BIT.B2 = 1u;
/* Set SDA0 pin (P13) */
MPC.P13PFS.BYTE = 0x0fu;
PORT1.PMR.BIT.B3 = 1u;
}
#endif
/****************************************************************************
* Name: riic1_init_port
*
* Description:
* RIIC1 Initialization RX65N RSK2MB
****************************************************************************/
#ifdef CONFIG_RX65N_RIIC1
inline void riic1_init_port(void)
{
/* Set SCL0 pin (P21) */
MPC.P21PFS.BYTE = 0x0fu;
PORT2.PMR.BIT.B1 = 1u;
/* Set SDA0 pin (P20) */
MPC.P20PFS.BYTE = 0x0fu;
PORT2.PMR.BIT.BT0 = 1u;
}
#endif
/****************************************************************************
* Name: riic2_init_port
*
* Description:
* RIIC2 Initialization RX65N RSK2MB
****************************************************************************/
#ifdef CONFIG_RX65N_RIIC2
inline void riic2_init_port(void)
{
/* Set SCL0 pin (P16) */
MPC.P16PFS.BYTE = 0x0fu;
PORT1.PMR.BIT.B6 = 1u;
/* Set SDA0 pin (P17) */
MPC.P17PFS.BYTE = 0x0fu;
PORT1.PMR.BIT.B7 = 1u;
}
#endif
#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */

39
boards/renesas/rx65n/rx65n-rsk2mb/include/rx65n_gpio.h
View file

@ -174,4 +174,43 @@ void sci8_init_port(void);
#ifdef CONFIG_RX65N_SCI12
void sci12_init_port(void);
#endif
/****************************************************************************
* Name: riic0_init_port
*
* Description:
* RIIC0 Initialization RX65N RSK2MB
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RX65N_RIIC0
void riic0_init_port(void);
#endif
/****************************************************************************
* Name: riic1_init_port
*
* Description:
* RIIC1 Initialization RX65N RSK2MB
****************************************************************************/
#ifdef CONFIG_RX65N_RIIC1
void riic1_init_port(void);
#endif
/****************************************************************************
* Name: riic2_init_port
*
* Description:
* RIIC2 Initialization RX65N RSK2MB
****************************************************************************/
#ifdef CONFIG_RX65N_RIIC2
void riic2_init_port(void);
#endif
#endif /* __BOARDS_RENESAS_RX65N_RX65N_RSK2MB_INCLUDE_RX65N_GPIO_H */

50
boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_bringup.c
View file

@ -43,6 +43,10 @@
# include "rx65n_rtc.h"
#endif
#ifdef HAVE_RIIC_DRIVER
# include <nuttx/i2c/i2c_master.h>
# include "rx65n_riic.h"
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -129,6 +133,52 @@ int rx65n_bringup(void)
/* Initialize standby RAM */
(void)rx65n_sbram_int();
#endif
#ifdef HAVE_RIIC_DRIVER
FAR struct i2c_master_s *i2c;
/* Get the I2C lower half instance */
#ifdef CONFIG_RX65N_RIIC0
i2c = rx65n_i2cbus_initialize(0);
if (i2c == NULL)
{
i2cerr("ERROR: Initialization of RIIC Channel 0 failed: %d\n", ret);
}
else
{
/* Register the I2C character driver */
ret = i2c_register(i2c, 0);
if (ret < 0)
{
i2cerr("ERROR: Failed to register RIIC device: %d\n", ret);
}
}
#endif
#ifdef CONFIG_RX65N_RIIC1
i2c = rx65n_i2cbus_initialize(1);
if (i2c == NULL)
{
i2cerr("ERROR: Initialization of RIIC Channel 1 failed: %d\n", ret);
}
else
{
/* Register the I2C character driver */
ret = i2c_register(i2c, 1);
if (ret < 0)
{
i2cerr("ERROR: Failed to register RIIC device: %d\n", ret);
}
}
#endif
#ifdef CONFIG_RX65N_RIIC2
i2cerr("RIIC2 setting is not supported on RSK-2MB Board\n");
i2cerr("It is used for USB port and cannot be configured\n");
#endif
#endif
return OK;
}

81
boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_gpio.c
View file

@ -196,21 +196,6 @@ void r_ether_pheriperal_enable(void)
MPC.P34PFS.BYTE = 0x11u;
PORT3.PMR.BIT.B4 = 1u;
/* Set VBUS pin for USB */
/* Referred from r_usb_basic_pinset.c */
MPC.P16PFS.BYTE = 0x12u;
/* PORT1.PMR.BYTE |= 0x40; */
PORT1.PMR.BIT.B6 = 1u;
/* Set USB0_OVRCURA pin */
MPC.P14PFS.BYTE = 0x12u;
PORT1.PMR.BIT.B4 = 1u;
}
#endif
@ -318,4 +303,70 @@ inline void sci12_init_port(void)
*/
}
#endif
/****************************************************************************
* Name: riic0_init_port
*
* Description:
* RIIC0 Initialization RX65N RSK2MB
****************************************************************************/
#ifdef CONFIG_RX65N_RIIC0
inline void riic0_init_port(void)
{
/* Set SCL0 pin (P12) */
MPC.P12PFS.BYTE = 0x0fu;
PORT1.PMR.BIT.B2 = 1u;
/* Set SDA0 pin (P13) */
MPC.P13PFS.BYTE = 0x0fu;
PORT1.PMR.BIT.B3 = 1u;
}
#endif
/****************************************************************************
* Name: riic1_init_port
*
* Description:
* RIIC1 Initialization RX65N RSK2MB
****************************************************************************/
#ifdef CONFIG_RX65N_RIIC1
inline void riic1_init_port(void)
{
/* Set SCL0 pin (P21) */
MPC.P21PFS.BYTE = 0x0fu;
PORT2.PMR.BIT.B1 = 1u;
/* Set SDA0 pin (P20) */
MPC.P20PFS.BYTE = 0x0fu;
PORT2.PMR.BIT.BT0 = 1u;
}
#endif
/****************************************************************************
* Name: riic2_init_port
*
* Description:
* RIIC2 Initialization RX65N RSK2MB
****************************************************************************/
#ifdef CONFIG_RX65N_RIIC2
inline void riic2_init_port(void)
{
/* Set SCL0 pin (P16) */
MPC.P16PFS.BYTE = 0x0fu;
PORT1.PMR.BIT.B6 = 1u;
/* Set SDA0 pin (P17) */
MPC.P17PFS.BYTE = 0x0fu;
PORT1.PMR.BIT.B7 = 1u;
}
#endif
#endif /* CONFIG_ARCH_BOARD_RX65N_RSK2MB */