From fe4a1eb96ae5cc6d9df892fd55b048ba0060f850 Mon Sep 17 00:00:00 2001 From: rajeshwaribhat Date: Fri, 21 Aug 2020 19:20:06 +0530 Subject: [PATCH] I2C(RIIC) support for RX65N Addressed review comments in rx65n_definitions.h and rx65n_bringup.c --- arch/renesas/Kconfig | 4 + arch/renesas/include/rx65n/irq.h | 24 +- arch/renesas/src/rx65n/Kconfig | 274 ++ arch/renesas/src/rx65n/Make.defs | 3 + arch/renesas/src/rx65n/rx65n_cmtw0.c | 43 +- arch/renesas/src/rx65n/rx65n_definitions.h | 303 +- arch/renesas/src/rx65n/rx65n_dumpstate.c | 2 +- arch/renesas/src/rx65n/rx65n_eth.h | 1 + arch/renesas/src/rx65n/rx65n_initialstate.c | 2 +- arch/renesas/src/rx65n/rx65n_irq.c | 144 +- arch/renesas/src/rx65n/rx65n_macrodriver.h | 2 +- arch/renesas/src/rx65n/rx65n_riic.c | 3131 +++++++++++++++++ arch/renesas/src/rx65n/rx65n_riic.h | 95 + arch/renesas/src/rx65n/rx65n_serial.c | 4 +- arch/renesas/src/rx65n/rx65n_timerisr.c | 4 +- arch/renesas/src/rx65n/rx65n_vector.S | 57 +- .../rx65n/rx65n-grrose/include/rx65n_gpio.h | 53 + .../rx65n/rx65n-grrose/src/rx65n_bringup.c | 39 + .../rx65n/rx65n-grrose/src/rx65n_gpio.c | 83 +- .../rx65n/rx65n-rsk2mb/include/rx65n_gpio.h | 39 + .../rx65n/rx65n-rsk2mb/src/rx65n_bringup.c | 50 + .../rx65n/rx65n-rsk2mb/src/rx65n_gpio.c | 81 +- 22 files changed, 4266 insertions(+), 172 deletions(-) create mode 100644 arch/renesas/src/rx65n/rx65n_riic.c create mode 100644 arch/renesas/src/rx65n/rx65n_riic.h diff --git a/arch/renesas/Kconfig b/arch/renesas/Kconfig index 5c6e46736c1..f46b000e481 100644 --- a/arch/renesas/Kconfig +++ b/arch/renesas/Kconfig @@ -32,12 +32,16 @@ config ARCH_CHIP_R5F565NEDDFC config ARCH_CHIP_R5F565NEHDFC bool "R5F565NEHDFC" select ARCH_RX65N_RSK2MB + select ARCH_HAVE_I2CRESET + select ARCH_HAVE_SPI_BITORDER ---help--- Renesas RX65N on RSKRX65N-2MB config ARCH_CHIP_R5F565NEHDFP bool "R5F565NEHDFP" select ARCH_RX65N_GRROSE + select ARCH_HAVE_I2CRESET + select ARCH_HAVE_SPI_BITORDER ---help--- Renesas RX65N on GR-ROSE diff --git a/arch/renesas/include/rx65n/irq.h b/arch/renesas/include/rx65n/irq.h index f4a2ced801e..f39a267a7cb 100644 --- a/arch/renesas/include/rx65n/irq.h +++ b/arch/renesas/include/rx65n/irq.h @@ -152,25 +152,31 @@ #endif #ifdef CONFIG_RX65N_RIIC1 -# define RX65N_RIIC1_RXI1_IRQ (RX65N_RIIC1_IRQBASE + RX_RXI_IRQ_OFFSET) -# define RX65N_RIIC1_TXI1_IRQ (RX65N_RIIC1_IRQBASE + RX_TXI_IRQ_OFFSET) -# define RX65N_RIIC0_IRQBASE (RX65N_RIIC1_IRQBASE + RX_SCI_NIRQS) +# define RX65N_RIIC1_RXI1_IRQ (RX65N_RIIC1_IRQBASE) +# define RX65N_RIIC1_TXI1_IRQ (RX65N_RIIC1_IRQBASE + 1) +# define RX65N_RIIC1_TEI1_IRQ (RX65N_RIIC1_IRQBASE + 2) +# define RX65N_RIIC1_EEI1_IRQ (RX65N_RIIC1_IRQBASE + 3) +# define RX65N_RIIC0_IRQBASE (RX65N_RIIC1_IRQBASE + 4) #else # define RX65N_RIIC0_IRQBASE (RX65N_RIIC1_IRQBASE) #endif #ifdef CONFIG_RX65N_RIIC0 -# define RX65N_RIIC0_RXI0_IRQ (RX65N_RIIC0_IRQBASE + RX_RXI_IRQ_OFFSET) -# define RX65N_RIIC0_TXI0_IRQ (RX65N_RIIC0_IRQBASE + RX_TXI_IRQ_OFFSET) -# define RX65N_RIIC2_IRQBASE (RX65N_RIIC0_IRQBASE + RX_SCI_NIRQS) +# define RX65N_RIIC0_RXI0_IRQ (RX65N_RIIC0_IRQBASE) +# define RX65N_RIIC0_TXI0_IRQ (RX65N_RIIC0_IRQBASE + 1) +# define RX65N_RIIC0_TEI0_IRQ (RX65N_RIIC0_IRQBASE + 2) +# define RX65N_RIIC0_EEI0_IRQ (RX65N_RIIC0_IRQBASE + 3) +# define RX65N_RIIC2_IRQBASE (RX65N_RIIC0_IRQBASE + 4) #else # define RX65N_RIIC2_IRQBASE (RX65N_RIIC0_IRQBASE) #endif #ifdef CONFIG_RX65N_RIIC2 -# define RX65N_RIIC2_RXI2_IRQ (RX65N_RIIC2_IRQBASE + RX_RXI_IRQ_OFFSET) -# define RX65N_RIIC2_TXI2_IRQ (RX65N_RIIC2_IRQBASE + RX_TXI_IRQ_OFFSET) -# define RX65N_SCI0_IRQBASE (RX65N_RIIC2_IRQBASE + RX_SCI_NIRQS) +# define RX65N_RIIC2_RXI2_IRQ (RX65N_RIIC2_IRQBASE) +# define RX65N_RIIC2_TXI2_IRQ (RX65N_RIIC2_IRQBASE + 1) +# define RX65N_RIIC2_TEI2_IRQ (RX65N_RIIC2_IRQBASE + 2) +# define RX65N_RIIC2_EEI2_IRQ (RX65N_RIIC2_IRQBASE + 3) +# define RX65N_SCI0_IRQBASE (RX65N_RIIC2_IRQBASE + 4) #else # define RX65N_SCI0_IRQBASE (RX65N_RIIC2_IRQBASE) #endif diff --git a/arch/renesas/src/rx65n/Kconfig b/arch/renesas/src/rx65n/Kconfig index 7d211a9357b..5a96160a3a9 100644 --- a/arch/renesas/src/rx65n/Kconfig +++ b/arch/renesas/src/rx65n/Kconfig @@ -203,6 +203,143 @@ config RX65N_RTC config RX65N_CARRY bool "RTC" default y +config RX65N_RIIC0 + bool "RIIC0" + default n + depends on I2C && I2C_DRIVER + +if RX65N_RIIC0 + +config RX65N_RIIC0_BITRATE + int "RIIC0 Bus Bit Rate" + default 400000 + +config RX65N_RIIC0_NF + bool "Enable Noise Filter for RIIC0" + default y + +if RX65N_RIIC0_NF + +config RX65N_RIIC0_NF_STAGE + int "RIIC0 Noise Filter Stages" + default 2 + +endif #RX65N_RIIC0_NF + +config RX65N_RIIC0_SDA_DELAY + bool "Enable SDA Output Delay" + default n + +if RX65N_RIIC0_SDA_DELAY + +config RX65N_RIIC0_DELAY_CNT + int "Number of Cycles Delay" + default 1 + +endif #RX65N_RIIC0_SDA_DELAY + +config RX65N_RIIC0_RCV_CONTINUOUS + bool "RIIC0 receive continuously" + default n + +config RX65N_RIIC0_RCV_IN_BYTE_UNITS + bool "RIIC0 receive in byte units" + default y + depends on !RX65N_RIIC0_RCV_CONTINUOUS + +endif #RX65N_RIIC0 + +config RX65N_RIIC1 + bool "RIIC1" + default n + depends on I2C && I2C_DRIVER + +if RX65N_RIIC1 + +config RX65N_RIIC1_BITRATE + int "RIIC1 Bus Bit Rate" + default 400000 + +config RX65N_RIIC1_NF + bool "Enable Noise Filter" + default y + +if RX65N_RIIC1_NF + +config RX65N_RIIC1_NF_STAGE + int "RIIC1 Noise Filter Stages" + default 2 + +endif #RX65N_RIIC1_NF + +config RX65N_RIIC1_SDA_DELAY + bool "Enable SDA Output Delay" + default n + +if RX65N_RIIC1_SDA_DELAY + +config RX65N_RIIC1_DELAY_CNT + int "Number of Cycles Delay" + default 1 + +endif #RX65N_RIIC1_SDA_DELAY + +config RX65N_RIIC1_RCV_CONTINUOUS + bool "RIIC1 receive continuously" + default n + +config RX65N_RIIC1_RCV_IN_BYTE_UNITS + bool "RIIC1 receive in byte units" + default y + depends on !RX65N_RIIC1_RCV_CONTINUOUS + +endif #RX65N_RIIC1 + +config RX65N_RIIC2 + bool "RIIC2" + default n + depends on I2C && I2C_DRIVER + +if RX65N_RIIC2 + +config RX65N_RIIC2_BITRATE + int "RIIC2 Bus Bit Rate" + default 400000 + +config RX65N_RIIC2_NF + bool "Enable Noise Filter" + default y + +if RX65N_RIIC2_NF + +config RX65N_RIIC2_NF_STAGE + int "RIIC2 Noise Filter Stages" + default 2 + +endif #RX65N_RIIC2_NF + +config RX65N_RIIC2_SDA_DELAY + bool "Enable SDA Output Delay for RIIC2" + default n + +if RX65N_RIIC2_SDA_DELAY + +config RX65N_RIIC2_DELAY_CNT + int "Number of Cycles Delay" + default 1 + +endif #RX65N_RIIC2_SDA_DELAY + +config RX65N_RIIC2_RCV_CONTINUOUS + bool "RIIC2 receive continuously" + default n + +config RX65N_RIIC2_RCV_IN_BYTE_UNITS + bool "RIIC2 receive in byte units" + default y + depends on !RX65N_RIIC2_RCV_CONTINUOUS + +endif #RX65N_RIIC2 endmenu # RX65N Peripheral Selections endif @@ -336,6 +473,143 @@ config RX65N_EMAC0 select NETDEVICES select ARCH_HAVE_PHY +config RX65N_RIIC0 + bool "RIIC0" + default n + depends on I2C && I2C_DRIVER + +if RX65N_RIIC0 + +config RX65N_RIIC0_BITRATE + int "RIIC0 Bus Bit Rate" + default 400000 + +config RX65N_RIIC0_NF + bool "Enable Noise Filter for RIIC0" + default y + +if RX65N_RIIC0_NF + +config RX65N_RIIC0_NF_STAGE + int "RIIC0 Noise Filter Stages" + default 2 + +endif #RX65N_RIIC0_NF + +config RX65N_RIIC0_SDA_DELAY + bool "Enable SDA Output Delay" + default n + +if RX65N_RIIC0_SDA_DELAY + +config RX65N_RIIC0_DELAY_CNT + int "Number of Cycles Delay" + default 1 + +endif #RX65N_RIIC0_SDA_DELAY + +config RX65N_RIIC0_RCV_CONTINUOUS + bool "RIIC0 receive continuously" + default n + +config RX65N_RIIC0_RCV_IN_BYTE_UNITS + bool "RIIC0 receive in byte units" + default y + depends on !RX65N_RIIC0_RCV_CONTINUOUS + +endif #RX65N_RIIC0 + +config RX65N_RIIC1 + bool "RIIC1" + default n + depends on I2C && I2C_DRIVER + +if RX65N_RIIC1 + +config RX65N_RIIC1_BITRATE + int "RIIC1 Bus Bit Rate" + default 400000 + +config RX65N_RIIC1_NF + bool "Enable Noise Filter for RIIC1" + default y + +if RX65N_RIIC1_NF + +config RX65N_RIIC1_NF_STAGE + int "RIIC1 Noise Filter Stages" + default 2 + +endif #RX65N_RIIC1_NF + +config RX65N_RIIC1_SDA_DELAY + bool "Enable SDA Output Delay" + default n + +if RX65N_RIIC1_SDA_DELAY + +config RX65N_RIIC1_DELAY_CNT + int "Number of Cycles Delay" + default 1 + +endif #RX65N_RIIC1_SDA_DELAY + +config RX65N_RIIC1_RCV_CONTINUOUS + bool "RIIC1 receive continuously" + default n + +config RX65N_RIIC1_RCV_IN_BYTE_UNITS + bool "RIIC1 receive in byte units" + default y + depends on !RX65N_RIIC1_RCV_CONTINUOUS + +endif #RX65N_RIIC1 + +config RX65N_RIIC2 + bool "RIIC2" + default n + depends on I2C && I2C_DRIVER + +if RX65N_RIIC2 + +config RX65N_RIIC2_BITRATE + int "RIIC2 Bus Bit Rate" + default 400000 + +config RX65N_RIIC2_NF + bool "Enable Noise Filter for RIIC2" + default y + +if RX65N_RIIC2_NF + +config RX65N_RIIC2_NF_STAGE + int "RIIC2 Noise Filter Stages" + default 2 + +endif #RX65N_RIIC2_NF + +config RX65N_RIIC2_SDA_DELAY + bool "Enable SDA Output Delay" + default n + +if RX65N_RIIC2_SDA_DELAY + +config RX65N_RIIC2_DELAY_CNT + int "Number of Cycles Delay" + default 1 + +endif #RX65N_RIIC2_SDA_DELAY + +config RX65N_RIIC2_RCV_CONTINUOUS + bool "RIIC2 receive continuously" + default n + +config RX65N_RIIC2_RCV_IN_BYTE_UNITS + bool "RIIC2 receive in byte units" + default y + depends on !RX65N_RIIC2_RCV_CONTINUOUS + +endif #RX65N_RIIC2 endmenu # RX65N Peripheral Selections endif diff --git a/arch/renesas/src/rx65n/Make.defs b/arch/renesas/src/rx65n/Make.defs index 2773f13111b..fe45e9b1688 100644 --- a/arch/renesas/src/rx65n/Make.defs +++ b/arch/renesas/src/rx65n/Make.defs @@ -57,4 +57,7 @@ endif ifeq ($(CONFIG_RTC_DRIVER),y) CHIP_CSRCS += rx65n_rtc_lowerhalf.c +endif +ifeq ($(CONFIG_I2C),y) +CHIP_CSRCS += rx65n_riic.c endif \ No newline at end of file diff --git a/arch/renesas/src/rx65n/rx65n_cmtw0.c b/arch/renesas/src/rx65n/rx65n_cmtw0.c index f0b452c7da2..730f37627e4 100644 --- a/arch/renesas/src/rx65n/rx65n_cmtw0.c +++ b/arch/renesas/src/rx65n/rx65n_cmtw0.c @@ -1,35 +1,20 @@ /**************************************************************************** * arch/renesas/src/rx65n/rx65n_cmtw0.c * - * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. - * Author:Surya Prakash + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -46,8 +31,8 @@ #include #include "rx65n_cmtw0.h" -#include "rx65n/iodefine.h" -#include "rx65n/irq.h" +#include "arch/rx65n/iodefine.h" +#include "arch/rx65n/irq.h" #include "rx65n_definitions.h" #include #include "rx65n_eth.h" diff --git a/arch/renesas/src/rx65n/rx65n_definitions.h b/arch/renesas/src/rx65n/rx65n_definitions.h index 0f50081eea3..a15a037f9f0 100644 --- a/arch/renesas/src/rx65n/rx65n_definitions.h +++ b/arch/renesas/src/rx65n/rx65n_definitions.h @@ -26,7 +26,7 @@ ****************************************************************************/ #include -#include "rx65n/iodefine.h" +#include "arch/rx65n/iodefine.h" #include "arch/board/board.h" /**************************************************************************** @@ -133,7 +133,7 @@ /* Bit 7: TDR does not contain valid transmit data */ -#define RX_SCISSR_TDRE (0x80) +#define RX_SCISSR_TDRE (0x80) #define RX65N_CMT_CMSTR0_ADDR (0x00088000) /* 8-bits wide */ #define RX65N_CMT0_CMCNT_ADDR (0x00088004) #define RX65N_CMT0_CMCOR_ADDR (0x00088006) @@ -158,6 +158,7 @@ #define rx65n_cmtw0_timeout 2 #define RX65N_MSTPCRA_ADDR (0x00080010) +#define RX65N_MSTPCRB_ADDR (0x00080014) #define RX65N_CMT0_TICKFREQ (100) /* 100Hz tick frequency */ #define RX65N_CMT_DIV32 (0x0001) #define RX65N_CMT0_DIV_VALUE (32) @@ -212,10 +213,16 @@ #define RX65N_GRPBL0_ERI6_MASK (1U << 13) /* (0x00002000) */ #define RX65N_GRPBL0_TEI7_MASK (1U << 14) /* (0x00004000) */ #define RX65N_GRPBL0_ERI7_MASK (1U << 15) /* (0x00008000) */ +#define RX65N_GRPBL1_TEI0_MASK (1U << 13) +#define RX65N_GRPBL1_EEI0_MASK (1U << 14) +#define RX65N_GRPBL1_TEI2_MASK (1U << 15) +#define RX65N_GRPBL1_EEI2_MASK (1U << 16) #define RX65N_GRPBL1_TEI8_MASK (1U << 24) #define RX65N_GRPBL1_ERI8_MASK (1U << 25) #define RX65N_GRPBL1_TEI9_MASK (1U << 26) #define RX65N_GRPBL1_ERI9_MASK (1U << 27) +#define RX65N_GRPBL1_TEI1_MASK (1U << 28) +#define RX65N_GRPBL1_EEI1_MASK (1U << 29) #define RX65N_GRPAL0_TEI10_MASK (1U << 8) #define RX65N_GRPAL0_ERI10_MASK (1U << 9) #define RX65N_GRPAL0_TEI11_MASK (1U << 12) @@ -433,11 +440,11 @@ /* EDMAC Transmit Request Register's bit */ -#define ETHD_EDRRR_TR (1) /* Transmit Request */ +#define ETHD_EDRRR_TR (1) /* Transmit Request */ /* EDMAC Receive Request Register's bit */ -#define ETHD_EDRRR_RR (1) /* Receive descriptor read, +#define ETHD_EDRRR_RR (1) /* Receive descriptor read, * and receive function is enabled */ @@ -470,17 +477,17 @@ /* PHY Interface Register's bit and values */ -#define ETH_PIR_MDC (1) /* MII/RMII Management Data Clock */ -#define ETH_PIR_MMD (1<<1) /* MII/RMII Management Mode */ -#define ETH_PIR_MDO (1<<2) /* MII/RMII Management Data-Out */ -#define ETH_PIR_MDI (1<<3) /* MII/RMII Management Data-In */ +#define ETH_PIR_MDC (1) /* MII/RMII Management Data Clock */ +#define ETH_PIR_MMD (1<<1) /* MII/RMII Management Mode */ +#define ETH_PIR_MDO (1<<2) /* MII/RMII Management Data-Out */ +#define ETH_PIR_MDI (1<<3) /* MII/RMII Management Data-In */ -#define ETH_PIR_RESET_ALL (0x00000000) /* Reset All Flags of PIR */ -#define ETH_PIR_SET_MDC (0x00000001) /* Setting MDC of PIR */ -#define ETH_PIR_SET_MMD (0x00000002) /* Setting MMD of PIR */ -#define ETH_PIR_SET_MMD_MDC (0x00000003) /* Setting MMD and MDC */ -#define ETH_PIR_SET_MDO_MMD (0x00000006) /* Setting MDO and MMD */ -#define ETH_PIR_SET_MDO_MMD_MDC (0x00000007) /* Setting MDO, MMD and MDC */ +#define ETH_PIR_RESET_ALL (0x00000000) /* Reset All Flags of PIR */ +#define ETH_PIR_SET_MDC (0x00000001) /* Setting MDC of PIR */ +#define ETH_PIR_SET_MMD (0x00000002) /* Setting MMD of PIR */ +#define ETH_PIR_SET_MMD_MDC (0x00000003) /* Setting MMD and MDC */ +#define ETH_PIR_SET_MDO_MMD (0x00000006) /* Setting MDO and MMD */ +#define ETH_PIR_SET_MDO_MMD_MDC (0x00000007) /* Setting MDO, MMD and MDC */ /* Ethernet Control Register's bit and value */ @@ -520,64 +527,66 @@ #define RX65N_RTC_RCR4_OFFSET (0x0028) #define RX65N_RTC_RADJ_OFFSET (0x002e) -#define RX65N_RTC_BASE (0x0008c400) -#define RX65N_RTC_R64CNT (RX65N_RTC_BASE + RX65N_RTC_R64CNT_OFFSET) -#define RX65N_RTC_RSECCNT (RX65N_RTC_BASE + RX65N_RTC_RSECCNT_OFFSET) -#define RX65N_RTC_RMINCNT (RX65N_RTC_BASE + RX65N_RTC_RMINCNT_OFFSET) -#define RX65N_RTC_RHRCNT (RX65N_RTC_BASE + RX65N_RTC_RHRCNT_OFFSET) -#define RX65N_RTC_RWKCNT (RX65N_RTC_BASE + RX65N_RTC_RWKCNT_OFFSET) -#define RX65N_RTC_RDAYCNT (RX65N_RTC_BASE + RX65N_RTC_RDAYCNT_OFFSET) -#define RX65N_RTC_RMONCNT (RX65N_RTC_BASE + RX65N_RTC_RMONCNT_OFFSET) -#define RX65N_RTC_RYRCNT (RX65N_RTC_BASE + RX65N_RTC_RYRCNT_OFFSET) -#define RX65N_RTC_RSECAR (RX65N_RTC_BASE + RX65N_RTC_RSECAR_OFFSET) -#define RX65N_RTC_RMINAR (RX65N_RTC_BASE + RX65N_RTC_RMINAR_OFFSET) -#define RX65N_RTC_RHRAR (RX65N_RTC_BASE + RX65N_RTC_RHRAR_OFFSET) -#define RX65N_RTC_RWKAR (RX65N_RTC_BASE + RX65N_RTC_RWKAR_OFFSET) -#define RX65N_RTC_RDAYAR (RX65N_RTC_BASE + RX65N_RTC_RDAYAR_OFFSET) -#define RX65N_RTC_RMONAR (RX65N_RTC_BASE + RX65N_RTC_RMONAR_OFFSET) -#define RX65N_RTC_RYRAR (RX65N_RTC_BASE + RX65N_RTC_RYRAR_OFFSET) -#define RX65N_RTC_RYRAREN (RX65N_RTC_BASE + RX65N_RTC_RYRAREN_OFFSET) -#define RX65N_RTC_RCR1 (RX65N_RTC_BASE + RX65N_RTC_RCR1_OFFSET) -#define RX65N_RTC_RCR2 (RX65N_RTC_BASE + RX65N_RTC_RCR2_OFFSET) -#define RX65N_RTC_RCR3 (RX65N_RTC_BASE + RX65N_RTC_RCR3_OFFSET) -#define RX65N_RTC_RCR4 (RX65N_RTC_BASE + RX65N_RTC_RCR4_OFFSET) -#define RX65N_RTC_RADJ (RX65N_RTC_BASE + RX65N_RTC_RADJ_OFFSET) +#define RX65N_RTC_BASE (0x0008c400) +#define RX65N_RTC_R64CNT (RX65N_RTC_BASE + RX65N_RTC_R64CNT_OFFSET) +#define RX65N_RTC_RSECCNT (RX65N_RTC_BASE + RX65N_RTC_RSECCNT_OFFSET) +#define RX65N_RTC_RMINCNT (RX65N_RTC_BASE + RX65N_RTC_RMINCNT_OFFSET) +#define RX65N_RTC_RHRCNT (RX65N_RTC_BASE + RX65N_RTC_RHRCNT_OFFSET) +#define RX65N_RTC_RWKCNT (RX65N_RTC_BASE + RX65N_RTC_RWKCNT_OFFSET) +#define RX65N_RTC_RDAYCNT (RX65N_RTC_BASE + RX65N_RTC_RDAYCNT_OFFSET) +#define RX65N_RTC_RMONCNT (RX65N_RTC_BASE + RX65N_RTC_RMONCNT_OFFSET) +#define RX65N_RTC_RYRCNT (RX65N_RTC_BASE + RX65N_RTC_RYRCNT_OFFSET) +#define RX65N_RTC_RSECAR (RX65N_RTC_BASE + RX65N_RTC_RSECAR_OFFSET) +#define RX65N_RTC_RMINAR (RX65N_RTC_BASE + RX65N_RTC_RMINAR_OFFSET) +#define RX65N_RTC_RHRAR (RX65N_RTC_BASE + RX65N_RTC_RHRAR_OFFSET) +#define RX65N_RTC_RWKAR (RX65N_RTC_BASE + RX65N_RTC_RWKAR_OFFSET) +#define RX65N_RTC_RDAYAR (RX65N_RTC_BASE + RX65N_RTC_RDAYAR_OFFSET) +#define RX65N_RTC_RMONAR (RX65N_RTC_BASE + RX65N_RTC_RMONAR_OFFSET) +#define RX65N_RTC_RYRAR (RX65N_RTC_BASE + RX65N_RTC_RYRAR_OFFSET) +#define RX65N_RTC_RYRAREN (RX65N_RTC_BASE + RX65N_RTC_RYRAREN_OFFSET) +#define RX65N_RTC_RCR1 (RX65N_RTC_BASE + RX65N_RTC_RCR1_OFFSET) +#define RX65N_RTC_RCR2 (RX65N_RTC_BASE + RX65N_RTC_RCR2_OFFSET) +#define RX65N_RTC_RCR3 (RX65N_RTC_BASE + RX65N_RTC_RCR3_OFFSET) +#define RX65N_RTC_RCR4 (RX65N_RTC_BASE + RX65N_RTC_RCR4_OFFSET) +#define RX65N_RTC_RADJ (RX65N_RTC_BASE + RX65N_RTC_RADJ_OFFSET) -#define RTC_RTC_ALRDIS (0x00) -#define RTC_RCR4_RCKSEL (0x00) -#define RTC_RCR3_RTCEN (0x01) -#define RTC_RCR3_RTCDV (0x02) -#define RTC_RCR2_START (0x01) -#define RTC_RCR2_CNTMD (0x00) -#define RTC_RCR2_RESET (0x01) -#define RTC_ALARM_INT_ENABLE (0x01) -#define RTC_CARRY_INT_ENABLE (0x02) -#define RTC_PERIOD_INT_ENABLE (0x04) -#define RTC_PERIODIC_INT_PERIOD_1 (0xe0) -#define _04_FOUR_READ_COUNT (0x04) -#define RTC_1_64_SEC_CYCLE (0x0005b8d9) -#define _0F_RTC_PRIORITY_LEVEL15 (0x0f) -#define RTC_RCR1_CUP (0x02) -#define RX65N_SUBCLKOSC_SOSCCR (0x00080033) -#define SUBCLKOSC_SOSCCR_SOSTP (0x01) -#define RX65N_SUBCLKOSC_SOSCWTCR (0x0008c293) -#define RTC_SOSCWTCR_VALUE (0x21) -#define RTC_DUMMY_READ (3) -#define _00_RTC_PRIORITY_LEVEL0 (0) -#define _04_RTC_PERIOD_INT_ENABLE (0x04) -#define RTC_RTC_CARRYDIS (0xe5) -#define RTC_RTC_PERDIS (0xe3) -#define RTC_RADJ_INITVALUE (0x0) -#define RTC_RCR2_AADJE (0x10) -#define RTC_RCR2_AADJP (0x20) +#define RTC_RTC_ALRDIS (0x00) +#define RTC_RCR4_RCKSEL (0x00) +#define RTC_RCR3_RTCEN (0x01) +#define RTC_RCR3_RTCDV (0x02) +#define RTC_RCR2_START (0x01) +#define RTC_RCR2_CNTMD (0x00) +#define RTC_RCR2_RESET (0x01) +#define RTC_ALARM_INT_ENABLE (0x01) +#define RTC_CARRY_INT_ENABLE (0x02) +#define RTC_PERIOD_INT_ENABLE (0x04) +#define RTC_PERIODIC_INT_PERIOD_1 (0xe0) +#define _04_FOUR_READ_COUNT (0x04) +#define RTC_1_64_SEC_CYCLE (0x0005b8d9) +#define _0F_RTC_PRIORITY_LEVEL15 (0x0f) +#define RTC_RCR1_CUP (0x02) +#define RX65N_SUBCLKOSC_SOSCCR (0x00080033) +#define SUBCLKOSC_SOSCCR_SOSTP (0x01) +#define RX65N_SUBCLKOSC_SOSCWTCR (0x0008c293) +#define RTC_SOSCWTCR_VALUE (0x21) +#define RTC_DUMMY_READ (3) +#define _00_RTC_PRIORITY_LEVEL0 (0) +#define _04_RTC_PERIOD_INT_ENABLE (0x04) +#define RTC_RTC_CARRYDIS (0xe5) +#define RTC_RTC_PERDIS (0xe3) +#define RTC_RADJ_INITVALUE (0x0) +#define RTC_RCR2_AADJE (0x10) +#define RTC_RCR2_AADJP (0x20) #if defined(CONFIG_RTC) || defined(CONFIG_RTC_DRIVER) -#define HAVE_RTC_DRIVER 1 +#define HAVE_RTC_DRIVER 1 #endif -#define RX65N_RTC_WAIT_PERIOD 184 +/* Constant values used in RTC */ + +#define RX65N_RTC_WAIT_PERIOD 184 #define RTC_RCR2_HR24 (0x40) #define RTC_PERIODIC_INTERRUPT_2_SEC (0xf) @@ -585,6 +594,170 @@ #define RX65N_SBRAM_BASE 0x000a4000 +/* RIIC related definitions */ + +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_DRIVER) + #define HAVE_RIIC_DRIVER 1 +#endif + +/* RIIC Channel Base Address definitions */ + +#define RX65N_RIIC0_BASE (uint32_t)&RIIC0 +#define RX65N_RIIC1_BASE (uint32_t)&RIIC1 +#define RX65N_RIIC2_BASE (uint32_t)&RIIC2 + +/* RIIC Register Offset definitions */ + +#define RX65N_RIIC_ICCR1_OFFSET (0x0000) +#define RX65N_RIIC_ICCR2_OFFSET (0x0001) +#define RX65N_RIIC_ICMR1_OFFSET (0x0002) +#define RX65N_RIIC_ICMR2_OFFSET (0x0003) +#define RX65N_RIIC_ICMR3_OFFSET (0x0004) +#define RX65N_RIIC_ICFER_OFFSET (0x0005) +#define RX65N_RIIC_ICSER_OFFSET (0x0006) +#define RX65N_RIIC_ICIER_OFFSET (0x0007) +#define RX65N_RIIC_ICSR1_OFFSET (0x0008) +#define RX65N_RIIC_ICSR2_OFFSET (0x0009) +#define RX65N_RIIC_SARL0_OFFSET (0x000a) +#define RX65N_RIIC_SARU0_OFFSET (0x000b) +#define RX65N_RIIC_SARL1_OFFSET (0x000c) +#define RX65N_RIIC_SARU1_OFFSET (0x000d) +#define RX65N_RIIC_SARL2_OFFSET (0x000e) +#define RX65N_RIIC_SARU2_OFFSET (0x000f) +#define RX65N_RIIC_ICBRL_OFFSET (0x0010) +#define RX65N_RIIC_ICBRH_OFFSET (0x0011) +#define RX65N_RIIC_ICDRT_OFFSET (0x0012) +#define RX65N_RIIC_ICDRR_OFFSET (0x0013) + +/* RIIC register address definitions */ + +#define RX65N_RIIC0_ICCR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICCR1_OFFSET) +#define RX65N_RIIC0_ICCR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICCR2_OFFSET) +#define RX65N_RIIC0_ICMR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR1_OFFSET) +#define RX65N_RIIC0_ICMR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR2_OFFSET) +#define RX65N_RIIC0_ICMR3 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR3_OFFSET) +#define RX65N_RIIC0_ICFER (RX65N_RIIC0_BASE + RX65N_RIIC_ICFER_OFFSET) +#define RX65N_RIIC0_ICSER (RX65N_RIIC0_BASE + RX65N_RIIC_ICSER_OFFSET) +#define RX65N_RIIC0_ICIER (RX65N_RIIC0_BASE + RX65N_RIIC_ICIER_OFFSET) +#define RX65N_RIIC0_ICSR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICSR1_OFFSET) +#define RX65N_RIIC0_ICSR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICSR2_OFFSET) +#define RX65N_RIIC0_SARL0 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL0_OFFSET) +#define RX65N_RIIC0_SARU0 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU0_OFFSET) +#define RX65N_RIIC0_SARL1 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL1_OFFSET) +#define RX65N_RIIC0_SARU1 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU1_OFFSET) +#define RX65N_RIIC0_SARL2 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL2_OFFSET) +#define RX65N_RIIC0_SARU2 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU2_OFFSET) +#define RX65N_RIIC0_ICBRL (RX65N_RIIC0_BASE + RX65N_RIIC_ICBRL_OFFSET) +#define RX65N_RIIC0_ICBRH (RX65N_RIIC0_BASE + RX65N_RIIC_ICBRH_OFFSET) +#define RX65N_RIIC0_ICDRT (RX65N_RIIC0_BASE + RX65N_RIIC_ICDRT_OFFSET) +#define RX65N_RIIC0_ICDRR (RX65N_RIIC0_BASE + RX65N_RIIC_ICDRR_OFFSET) + +#define RX65N_RIIC1_ICCR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICCR1_OFFSET) +#define RX65N_RIIC1_ICCR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICCR2_OFFSET) +#define RX65N_RIIC1_ICMR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR1_OFFSET) +#define RX65N_RIIC1_ICMR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR2_OFFSET) +#define RX65N_RIIC1_ICMR3 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR3_OFFSET) +#define RX65N_RIIC1_ICFER (RX65N_RIIC1_BASE + RX65N_RIIC_ICFER_OFFSET) +#define RX65N_RIIC1_ICSER (RX65N_RIIC1_BASE + RX65N_RIIC_ICSER_OFFSET) +#define RX65N_RIIC1_ICIER (RX65N_RIIC1_BASE + RX65N_RIIC_ICIER_OFFSET) +#define RX65N_RIIC1_ICSR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICSR1_OFFSET) +#define RX65N_RIIC1_ICSR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICSR2_OFFSET) +#define RX65N_RIIC1_SARL0 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL0_OFFSET) +#define RX65N_RIIC1_SARU0 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU0_OFFSET) +#define RX65N_RIIC1_SARL1 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL1_OFFSET) +#define RX65N_RIIC1_SARU1 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU1_OFFSET) +#define RX65N_RIIC1_SARL2 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL2_OFFSET) +#define RX65N_RIIC1_SARU2 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU2_OFFSET) +#define RX65N_RIIC1_ICBRL (RX65N_RIIC1_BASE + RX65N_RIIC_ICBRL_OFFSET) +#define RX65N_RIIC1_ICBRH (RX65N_RIIC1_BASE + RX65N_RIIC_ICBRH_OFFSET) +#define RX65N_RIIC1_ICDRT (RX65N_RIIC1_BASE + RX65N_RIIC_ICDRT_OFFSET) +#define RX65N_RIIC1_ICDRR (RX65N_RIIC1_BASE + RX65N_RIIC_ICDRR_OFFSET) + +#define RX65N_RIIC2_ICCR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICCR1_OFFSET) +#define RX65N_RIIC2_ICCR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICCR2_OFFSET) +#define RX65N_RIIC2_ICMR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR1_OFFSET) +#define RX65N_RIIC2_ICMR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR2_OFFSET) +#define RX65N_RIIC2_ICMR3 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR3_OFFSET) +#define RX65N_RIIC2_ICFER (RX65N_RIIC2_BASE + RX65N_RIIC_ICFER_OFFSET) +#define RX65N_RIIC2_ICSER (RX65N_RIIC2_BASE + RX65N_RIIC_ICSER_OFFSET) +#define RX65N_RIIC2_ICIER (RX65N_RIIC2_BASE + RX65N_RIIC_ICIER_OFFSET) +#define RX65N_RIIC2_ICSR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICSR1_OFFSET) +#define RX65N_RIIC2_ICSR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICSR2_OFFSET) +#define RX65N_RIIC2_SARL0 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL0_OFFSET) +#define RX65N_RIIC2_SARU0 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU0_OFFSET) +#define RX65N_RIIC2_SARL1 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL1_OFFSET) +#define RX65N_RIIC2_SARU1 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU1_OFFSET) +#define RX65N_RIIC2_SARL2 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL2_OFFSET) +#define RX65N_RIIC2_SARU2 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU2_OFFSET) +#define RX65N_RIIC2_ICBRL (RX65N_RIIC2_BASE + RX65N_RIIC_ICBRL_OFFSET) +#define RX65N_RIIC2_ICBRH (RX65N_RIIC2_BASE + RX65N_RIIC_ICBRH_OFFSET) +#define RX65N_RIIC2_ICDRT (RX65N_RIIC2_BASE + RX65N_RIIC_ICDRT_OFFSET) +#define RX65N_RIIC2_ICDRR (RX65N_RIIC2_BASE + RX65N_RIIC_ICDRR_OFFSET) + +/* RIIC register field/bit value definitions */ + +#define RX65N_RIIC_ICCR1_ICE_RST (0x7f) +#define RX65N_RIIC_ICCR1_IICRST_SET (0x40) + +#define RX65N_RIIC_ICCR2_ST_SET (0x02) +#define RX65N_RIIC_ICCR2_SP_SET (0x08) +#define RX65N_RIIC_ICCR2_RS_SET (0x04) + +#define RX65N_RIIC_ICSR2_STOP_SET (0x08) +#define RX65N_RIIC_ICSR2_START_SET (0x04) + +#define RX65N_RIIC_ICMR1_CKS_MASK (0x8f) + +#define RX65N_RIIC_ICMR2_SDDL0 (0x06) +#define RX65N_RIIC_ICMR2_SDDL1 (0x16) +#define RX65N_RIIC_ICMR2_SDDL2 (0x26) +#define RX65N_RIIC_ICMR2_SDDL3 (0x36) +#define RX65N_RIIC_ICMR2_SDDL4 (0x46) +#define RX65N_RIIC_ICMR2_SDDL5 (0x56) +#define RX65N_RIIC_ICMR2_SDDL6 (0x66) +#define RX65N_RIIC_ICMR2_SDDL7 (0x76) + +#define RX65N_RIIC_ICMR3_NF1 (0x00) +#define RX65N_RIIC_ICMR3_NF2 (0x01) +#define RX65N_RIIC_ICMR3_NF3 (0x02) +#define RX65N_RIIC_ICMR3_NF4 (0x03) + +#define RX65N_RIIC_ICMR3_WAIT_SET (0x40) +#define RX65N_RIIC_ICMR3_ACKWP_SET (0x10) +#define RX65N_RIIC_ICMR3_ACKBT_SET (0x08) +#define RX65N_RIIC_ICMR3_ACKWP_CLR (0xEF) +#define RX65N_RIIC_ICMR3_RDRFS_SET (0x20) + +#define RX65N_RIIC_ICIER_ALIE (0x02) +#define RX65N_RIIC_ICIER_ST_NAK_AL (0x16) +#define RX65N_RIIC_ICIER_SP_NAK_AL (0x1a) +#define RX65N_RIIC_ICIER_SP_AL (0x0a) +#define RX65N_RIIC_ICIER_TMO (0x01) +#define RX65N_RIIC_ICIER_TEND_NAK_AL (0x52) +#define RX65N_RIIC_ICIER_RX_NAK_AL (0x32) + +#define RX65N_RIIC_ICFER_TMOE_SET (0x01) +#define RX65N_RIIC_ICFER_NFE_SET (0x20) +#define RX65N_RIIC_ICFER_NFE_RST (0xdf) + +#define RX65N_RIIC_ICSER_SET (0x00) + +#define RX65N_RIIC_ICBRL_MASK (0xe0) +#define RX65N_RIIC_ICBRH_MASK (0xe0) + +#define RX65N_I2C_SLV_ADDR (0x80) +#define RX65N_RIIC_READ_MASK (0x01) + +#define RX65N_RIIC_10BIT_SARU_MASK (0x0300) +#define RX65N_RIIC_10BIT_SARL_MASK (0x00ff) + +#define BUS_CHECK_COUNTER (1000) +#define RIIC_REG_INIT (0x00) +#define RIIC_BUS_BUSY ((bool)(1)) +#define RIIC_BUS_FREE ((bool)(0)) + +/* End of RIIC related definitions */ + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/arch/renesas/src/rx65n/rx65n_dumpstate.c b/arch/renesas/src/rx65n/rx65n_dumpstate.c index 225131f9095..ed4d4a61a6c 100644 --- a/arch/renesas/src/rx65n/rx65n_dumpstate.c +++ b/arch/renesas/src/rx65n/rx65n_dumpstate.c @@ -34,7 +34,7 @@ #include "up_internal.h" #include "sched/sched.h" #include "chip.h" -#include "rx65n/irq.h" +#include "arch/rx65n/irq.h" #ifdef CONFIG_ARCH_STACKDUMP diff --git a/arch/renesas/src/rx65n/rx65n_eth.h b/arch/renesas/src/rx65n/rx65n_eth.h index 8ea35ce12da..416bcd365c3 100644 --- a/arch/renesas/src/rx65n/rx65n_eth.h +++ b/arch/renesas/src/rx65n/rx65n_eth.h @@ -26,6 +26,7 @@ ****************************************************************************/ #include +#include #include "chip.h" /**************************************************************************** diff --git a/arch/renesas/src/rx65n/rx65n_initialstate.c b/arch/renesas/src/rx65n/rx65n_initialstate.c index 70e208ae608..98d66ae5f86 100644 --- a/arch/renesas/src/rx65n/rx65n_initialstate.c +++ b/arch/renesas/src/rx65n/rx65n_initialstate.c @@ -31,7 +31,7 @@ #include "chip/chip.h" #include "up_internal.h" #include "up_arch.h" -#include "rx65n/irq.h" +#include "arch/rx65n/irq.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/renesas/src/rx65n/rx65n_irq.c b/arch/renesas/src/rx65n/rx65n_irq.c index d63255f6afb..cc4f4ca4527 100644 --- a/arch/renesas/src/rx65n/rx65n_irq.c +++ b/arch/renesas/src/rx65n/rx65n_irq.c @@ -27,7 +27,7 @@ #include #include #include -#include "rx65n/iodefine.h" +#include "arch/rx65n/iodefine.h" #include "up_internal.h" @@ -426,6 +426,77 @@ void up_disable_irq(int irq) #endif #endif +#ifdef CONFIG_RX65N_RIIC0 + if (irq == RX65N_RIIC0_RXI0_IRQ) + { + ICU.IER[6].BIT.IEN4 = 0; + } + + if (irq == RX65N_RIIC0_TXI0_IRQ) + { + ICU.IER[6].BIT.IEN5 = 0; + } + + if (irq == RX65N_RIIC0_TEI0_IRQ) + { + ICU.GRPBL1.BIT.IS13 = 0; + ICU.GENBL1.BIT.EN13 = 0; + } + + if (irq == RX65N_RIIC0_EEI0_IRQ) + { + ICU.GRPBL1.BIT.IS14 = 0; + ICU.GENBL1.BIT.EN14 = 0; + } +#endif + +#ifdef CONFIG_RX65N_RIIC1 + if (irq == RX65N_RIIC1_RXI1_IRQ) + { + ICU.IER[6].BIT.IEN2 = 0; + } + + if (irq == RX65N_RIIC1_TXI1_IRQ) + { + ICU.IER[6].BIT.IEN3 = 0; + } + + if (irq == RX65N_RIIC1_TEI1_IRQ) + { + ICU.GRPBL1.BIT.IS28 = 0; + ICU.GENBL1.BIT.EN28 = 0; + } + + if (irq == RX65N_RIIC1_EEI1_IRQ) + { + ICU.GRPBL1.BIT.IS29 = 0; + ICU.GENBL1.BIT.EN29 = 0; + } +#endif + +#ifdef CONFIG_RX65N_RIIC2 + if (irq == RX65N_RIIC2_RXI2_IRQ) + { + ICU.IER[6].BIT.IEN6 = 0; + } + + if (irq == RX65N_RIIC2_TXI2_IRQ) + { + ICU.IER[6].BIT.IEN7 = 0; + } + + if (irq == RX65N_RIIC2_TEI2_IRQ) + { + ICU.GRPBL1.BIT.IS15 = 0; + ICU.GENBL1.BIT.EN15 = 0; + } + + if (irq == RX65N_RIIC2_EEI2_IRQ) + { + ICU.GRPBL1.BIT.IS16 = 0; + ICU.GENBL1.BIT.EN16 = 0; + } +#endif } /**************************************************************************** @@ -785,4 +856,75 @@ void up_enable_irq(int irq) #endif #endif +#ifdef CONFIG_RX65N_RIIC0 + if (irq == RX65N_RIIC0_RXI0_IRQ) + { + ICU.IER[6].BIT.IEN4 = 1; + } + + if (irq == RX65N_RIIC0_TXI0_IRQ) + { + ICU.IER[6].BIT.IEN5 = 1; + } + + if (irq == RX65N_RIIC0_TEI0_IRQ) + { + ICU.GRPBL1.BIT.IS13 = 1; + ICU.GENBL1.BIT.EN13 = 1; + } + + if (irq == RX65N_RIIC0_EEI0_IRQ) + { + ICU.GRPBL1.BIT.IS14 = 1; + ICU.GENBL1.BIT.EN14 = 1; + } +#endif + +#ifdef CONFIG_RX65N_RIIC1 + if (irq == RX65N_RIIC1_RXI1_IRQ) + { + ICU.IER[6].BIT.IEN2 = 1; + } + + if (irq == RX65N_RIIC1_TXI1_IRQ) + { + ICU.IER[6].BIT.IEN3 = 1; + } + + if (irq == RX65N_RIIC1_TEI1_IRQ) + { + ICU.GRPBL1.BIT.IS28 = 1; + ICU.GENBL1.BIT.EN28 = 1; + } + + if (irq == RX65N_RIIC1_EEI1_IRQ) + { + ICU.GRPBL1.BIT.IS29 = 1; + ICU.GENBL1.BIT.EN29 = 1; + } +#endif + +#ifdef CONFIG_RX65N_RIIC2 + if (irq == RX65N_RIIC2_RXI2_IRQ) + { + ICU.IER[6].BIT.IEN6 = 1; + } + + if (irq == RX65N_RIIC2_TXI2_IRQ) + { + ICU.IER[6].BIT.IEN7 = 1; + } + + if (irq == RX65N_RIIC2_TEI2_IRQ) + { + ICU.GRPBL1.BIT.IS15 = 1; + ICU.GENBL1.BIT.EN15 = 1; + } + + if (irq == RX65N_RIIC2_EEI2_IRQ) + { + ICU.GRPBL1.BIT.IS16 = 1; + ICU.GENBL1.BIT.EN16 = 1; + } +#endif } diff --git a/arch/renesas/src/rx65n/rx65n_macrodriver.h b/arch/renesas/src/rx65n/rx65n_macrodriver.h index 6168841389e..72d84a8f5a9 100644 --- a/arch/renesas/src/rx65n/rx65n_macrodriver.h +++ b/arch/renesas/src/rx65n/rx65n_macrodriver.h @@ -25,7 +25,7 @@ * Included Files ****************************************************************************/ -#include "rx65n/iodefine.h" +#include "arch/rx65n/iodefine.h" #ifndef TRUE #define TRUE (1) diff --git a/arch/renesas/src/rx65n/rx65n_riic.c b/arch/renesas/src/rx65n/rx65n_riic.c new file mode 100644 index 00000000000..ab4dee1c010 --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_riic.c @@ -0,0 +1,3131 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_riic.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include "rx65n_riic.h" +#include "rx65n_definitions.h" +#include +#include +#include +#include +#include "up_arch.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +# define rx65n_getreg(addr) getreg8(addr) +# define rx65n_putreg(val,addr) putreg8(val,addr) + +#if defined(CONFIG_RX65N_RIIC0) || defined(CONFIG_RX65N_RIIC1) || \ + defined(CONFIG_RX65N_RIIC2) + +/**************************************************************************** + * Typedef definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +enum rx65n_i2c_mode_e +{ + RIIC_NONE = 0, /* Uninitialized state */ + RIIC_READY, /* Ready for operation */ + RIIC_M_TRANSMIT, /* Master transmission mode */ + RIIC_M_RECEIVE, /* Master reception mode */ + RIIC_FINISH, /* Successful operation */ +}; + +enum rx65n_i2c_dev_sts_e +{ + RIIC_STS_NO_INIT = 0, /* None initialization state */ + RIIC_STS_IDLE, /* Idle state */ + RIIC_STS_ST_COND_WAIT, /* Start condition generation completion wait state */ + RIIC_STS_SEND_SLVADR_W_WAIT, /* Slave address [Write] transmission completion wait state */ + RIIC_STS_SEND_SLVADR_R_WAIT, /* Slave address [Read] transmission completion wait state */ + RIIC_STS_SEND_DATA_WAIT, /* Data transmission completion wait state */ + RIIC_STS_RECEIVE_DATA_WAIT, /* Data reception completion wait state */ + RIIC_STS_SP_COND_WAIT, /* Stop condition generation completion wait state */ + RIIC_STS_AL, /* Detect Arbitration Lost */ + RIIC_STS_TMO, /* Detect Time out */ + RIIC_STS_MAX, /* Prohibition of setup above here */ +}; + +enum rx65n_i2c_event_e +{ + RIIC_EV_NONE = 0, + RIIC_EV_GEN_START_COND, /* Called function of Start condition generation */ + RIIC_EV_INT_START, /* Interrupted start codition generation */ + RIIC_EV_INT_ADD, /* Interrupted address sending */ + RIIC_EV_INT_SEND, /* Interrupted data sending */ + RIIC_EV_INT_RECEIVE, /* Interrupted data receiving */ + RIIC_EV_INT_STOP, /* Interrupted Stop condition generation */ + RIIC_EV_INT_AL, /* Interrupted Arbitration-Lost */ + RIIC_EV_INT_NACK, /* Interrupted No Acknowledge */ + RIIC_EV_INT_TXI, /* Interrupted transmitted buffer empty */ + RIIC_EV_INT_TMO, /* Interrupted Time out */ + RIIC_EV_MAX, /* Prohibition of setup above here */ +}; + +struct rx65n_i2c_dev_s +{ + uint32_t base; /* Base address of registers */ + uint32_t frequency; /* Configured kbps */ + uint8_t txi_irq; /* TXI IRQ Number */ + uint8_t rxi_irq; /* RXI IRQ Number */ + uint8_t tei_irq; /* TEI IRQ Number */ + uint8_t eei_irq; /* EEI IRQ Number */ + uint32_t grpbase; + uint32_t teimask; + uint32_t eeimask; +}; + +struct rx65n_i2c_priv_s +{ + const struct i2c_ops_s *ops; + const struct rx65n_i2c_dev_s *dev; + int refs; /* Referernce count */ + int bus; /* Bus number */ + volatile uint8_t mode; /* See enum rx65n_i2c_mode_e */ + volatile uint8_t dev_sts; /* See enum rx65n_i2c_dev_sts_e */ + volatile uint8_t event; /* See enum rx65n_i2c_event_e */ + sem_t sem_excl; /* Mutual exclusion semaphore */ + sem_t sem_isr; /* Interrupt wait semaphore */ + uint8_t msgc; /* Number of Messages */ + struct i2c_msg_s *msgv; /* Message list */ + uint8_t *ptr; /* Current message buffer */ + int dcnt; /* Bytes remaining to transfer */ + uint16_t flags; /* Current message flags */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int rx65n_riic_iicrst(FAR struct rx65n_i2c_priv_s *priv); +static void rx65n_riic_setclock(FAR struct rx65n_i2c_priv_s *priv, + uint32_t frequency); +static void rx65n_riic_init(FAR struct rx65n_i2c_priv_s *priv); +static int rx65n_riic_startcond(FAR struct rx65n_i2c_priv_s *priv); +static void rx65n_riic_restartcond(FAR struct rx65n_i2c_priv_s *priv); +static void rx65n_riic_send_slv_addr(FAR struct rx65n_i2c_priv_s *priv); +static void rx65n_riic_after_send_slvadr(FAR struct rx65n_i2c_priv_s *priv); +static void rx65n_riic_master_transmit(FAR struct rx65n_i2c_priv_s *priv); +static void rx65n_riic_master_receive(FAR struct rx65n_i2c_priv_s *priv); +static void rx65n_riic_stopcond(FAR struct rx65n_i2c_priv_s *priv); +static void rx65n_riic_advance(FAR struct rx65n_i2c_priv_s *priv); +static uint8_t rx65n_riic_read_data(FAR struct rx65n_i2c_priv_s *priv); +static void rx65n_riic_wait_set(FAR struct rx65n_i2c_priv_s *priv); +static void rx65n_riic_pre_end_set(FAR struct rx65n_i2c_priv_s *priv); +static void rx65n_riic_end_set(FAR struct rx65n_i2c_priv_s *priv); +static void rx65n_riic_nack(FAR struct rx65n_i2c_priv_s *priv); +static void rx65n_riic_set_sending_data(FAR struct rx65n_i2c_priv_s *priv, \ + uint8_t data); +static int rx65n_riic_after_stop(FAR struct rx65n_i2c_priv_s *priv); +static bool rx65n_riic_check_bus_busy(FAR struct rx65n_i2c_priv_s *priv); +static void rx65n_riic_set_icier(FAR struct rx65n_i2c_priv_s *priv, \ + uint8_t value); +static void rx65n_riic_timeout(FAR struct rx65n_i2c_priv_s *priv); + +/* RIIC Interrupt Handling */ + +static void rx65n_riic_int_disable(FAR struct rx65n_i2c_priv_s *priv); +static void rx65n_riic_int_enable(FAR struct rx65n_i2c_priv_s *priv); +static int rx65n_riic_irq_init(FAR struct rx65n_i2c_priv_s *priv); + +/* RIIC0 Channel Interrupt Handling */ + +static int rx65n_riic_rxi0interrupt(int irq, + FAR void *context, FAR void *arg); +static int rx65n_riic_txi0interrupt(int irq, + FAR void *context, FAR void *arg); +static int rx65n_riic_eei0interrupt(int irq, + FAR void *context, FAR void *arg); +static int rx65n_riic_tei0interrupt(int irq, + FAR void *context, FAR void *arg); + +/* RIIC1 Channel Interrupt Handling */ + +static int rx65n_riic_rxi1interrupt(int irq, + FAR void *context, FAR void *arg); +static int rx65n_riic_txi1interrupt(int irq, + FAR void *context, FAR void *arg); +static int rx65n_riic_eei1interrupt(int irq, + FAR void *context, FAR void *arg); +static int rx65n_riic_tei1interrupt(int irq, + FAR void *context, FAR void *arg); + +/* RIIC2 Channel Interrupt Handling */ + +static int rx65n_riic_rxi2interrupt(int irq, + FAR void *context, FAR void *arg); +static int rx65n_riic_txi2interrupt(int irq, + FAR void *context, FAR void *arg); +static int rx65n_riic_eei2interrupt(int irq, + FAR void *context, FAR void *arg); +static int rx65n_riic_tei2interrupt(int irq, + FAR void *context, FAR void *arg); + +/* I2C operations */ + +static int rx65n_i2c_transfer(FAR struct i2c_master_s *dev, \ + FAR struct i2c_msg_s *msgs, int count); +#ifdef CONFIG_I2C_RESET +static int rx65n_i2c_reset(FAR struct i2c_master_s *dev); +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +void up_enable_irq(int irq); +void up_disable_irq(int irq); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Device Structures, Instantiation */ + +static const struct i2c_ops_s rx65n_i2c_ops = +{ + .transfer = rx65n_i2c_transfer +#ifdef CONFIG_I2C_RESET + , .reset = rx65n_i2c_reset +#endif +}; + +#ifdef CONFIG_RX65N_RIIC0 +static const struct rx65n_i2c_dev_s rx65n_riic0_dev = +{ + .base = RX65N_RIIC0_BASE, + .frequency = CONFIG_RX65N_RIIC0_BITRATE, + .txi_irq = RX65N_RIIC0_TXI0_IRQ, + .rxi_irq = RX65N_RIIC0_RXI0_IRQ, + .tei_irq = RX65N_RIIC0_TEI0_IRQ, + .eei_irq = RX65N_RIIC0_EEI0_IRQ, + .grpbase = RX65N_GRPBL1_ADDR, + .teimask = RX65N_GRPBL1_TEI0_MASK, + .eeimask = RX65N_GRPBL1_EEI0_MASK, +}; + +static struct rx65n_i2c_priv_s rx65n_riic0_priv = +{ + .ops = &rx65n_i2c_ops, + .dev = &rx65n_riic0_dev, + .refs = 0, + .bus = 0, + .mode = RIIC_NONE, + .dev_sts = RIIC_STS_NO_INIT, + .event = RIIC_EV_NONE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, +}; +#endif + +#ifdef CONFIG_RX65N_RIIC1 +static const struct rx65n_i2c_dev_s rx65n_riic1_dev = +{ + .base = RX65N_RIIC1_BASE, + .frequency = CONFIG_RX65N_RIIC1_BITRATE, + .txi_irq = RX65N_RIIC1_TXI1_IRQ, + .rxi_irq = RX65N_RIIC1_RXI1_IRQ, + .tei_irq = RX65N_RIIC1_TEI1_IRQ, + .eei_irq = RX65N_RIIC1_EEI1_IRQ, + .grpbase = RX65N_GRPBL1_ADDR, + .teimask = RX65N_GRPBL1_TEI1_MASK, + .eeimask = RX65N_GRPBL1_EEI1_MASK, +}; + +static struct rx65n_i2c_priv_s rx65n_riic1_priv = +{ + .ops = &rx65n_i2c_ops, + .dev = &rx65n_riic1_dev, + .refs = 0, + .bus = 1, + .mode = RIIC_NONE, + .dev_sts = RIIC_STS_NO_INIT, + .event = RIIC_EV_NONE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, +}; +#endif + +#ifdef CONFIG_RX65N_RIIC2 +static const struct rx65n_i2c_dev_s rx65n_riic2_dev = +{ + .base = RX65N_RIIC2_BASE, + .frequency = CONFIG_RX65N_RIIC2_BITRATE, + .txi_irq = RX65N_RIIC2_TXI2_IRQ, + .rxi_irq = RX65N_RIIC2_RXI2_IRQ, + .tei_irq = RX65N_RIIC2_TEI2_IRQ, + .eei_irq = RX65N_RIIC2_EEI2_IRQ, + .grpbase = RX65N_GRPBL1_ADDR, + .teimask = RX65N_GRPBL1_TEI2_MASK, + .eeimask = RX65N_GRPBL1_EEI2_MASK, +}; + +static struct rx65n_i2c_priv_s rx65n_riic2_priv = +{ + .ops = &rx65n_i2c_ops, + .dev = &rx65n_riic2_dev, + .refs = 0, + .bus = 2, + .mode = RIIC_NONE, + .dev_sts = RIIC_STS_NO_INIT, + .event = RIIC_EV_NONE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: riic_mpc_enable + * + * Description: + * Enable writing to registers + ****************************************************************************/ + +static void riic_mpc_enable(void) +{ + /* Enable writing to registers related to operating modes, + * LPC, CGC and software reset + */ + + SYSTEM.PRCR.WORD = 0xa50b; + + /* Enable writing to MPC pin function control registers */ + + MPC.PWPR.BIT.B0WI = 0; + MPC.PWPR.BIT.PFSWE = 1; +} + +/**************************************************************************** + * Name: riic_mpc_disable + * + * Description: + * Disable writing to registers + ****************************************************************************/ + +static void riic_mpc_disable(void) +{ + /* Disable writing to MPC pin function control registers */ + + MPC.PWPR.BIT.PFSWE = 0; + MPC.PWPR.BIT.B0WI = 1; + + /* Enable protection */ + + SYSTEM.PRCR.WORD = 0xa500; +} + +/**************************************************************************** + * Name: rx65n_riic_iicrst + * + * Description: + * Disable writing to registers + ****************************************************************************/ + +static int rx65n_riic_iicrst(FAR struct rx65n_i2c_priv_s *priv) +{ + uint8_t regval; + + if (priv->bus == 0) + { + regval = rx65n_getreg(RX65N_RIIC0_ICCR1); + regval |= RX65N_RIIC_ICCR1_IICRST_SET; + rx65n_putreg(regval, RX65N_RIIC0_ICCR1); + regval = rx65n_getreg(RX65N_RIIC0_ICCR1); + + regval = rx65n_getreg(RX65N_RIIC0_ICCR1); + regval &= ~(RX65N_RIIC_ICCR1_IICRST_SET); + rx65n_putreg(regval, RX65N_RIIC0_ICCR1); + regval = rx65n_getreg(RX65N_RIIC0_ICCR1); + } + + else if (priv->bus == 1) + { + regval = rx65n_getreg(RX65N_RIIC1_ICCR1); + regval |= RX65N_RIIC_ICCR1_IICRST_SET; + rx65n_putreg(regval, RX65N_RIIC1_ICCR1); + regval = rx65n_getreg(RX65N_RIIC1_ICCR1); + + regval = rx65n_getreg(RX65N_RIIC1_ICCR1); + regval &= ~(RX65N_RIIC_ICCR1_IICRST_SET); + rx65n_putreg(regval, RX65N_RIIC1_ICCR1); + regval = rx65n_getreg(RX65N_RIIC1_ICCR1); + } + + else + { + regval = rx65n_getreg(RX65N_RIIC2_ICCR1); + regval |= RX65N_RIIC_ICCR1_IICRST_SET; + rx65n_putreg(regval, RX65N_RIIC2_ICCR1); + regval = rx65n_getreg(RX65N_RIIC2_ICCR1); + + regval = rx65n_getreg(RX65N_RIIC2_ICCR1); + regval &= ~(RX65N_RIIC_ICCR1_IICRST_SET); + rx65n_putreg(regval, RX65N_RIIC2_ICCR1); + regval = rx65n_getreg(RX65N_RIIC2_ICCR1); + } + + return OK; +} + +/**************************************************************************** + * Name: rx65n_riic_set_icier + * + * Description: + * Sets interrupt enable register ICIER for RIIC communication + * + ****************************************************************************/ + +static void rx65n_riic_set_icier(FAR struct rx65n_i2c_priv_s *priv, \ + uint8_t value) +{ + uint8_t regval; + regval = (value | RX65N_RIIC_ICIER_TMO); + + if (0 == priv->bus) + { + rx65n_putreg(regval, RX65N_RIIC0_ICIER); + regval = rx65n_getreg(RX65N_RIIC0_ICIER); + } + + else if (1 == priv->bus) + { + rx65n_putreg(regval, RX65N_RIIC1_ICIER); + regval = rx65n_getreg(RX65N_RIIC1_ICIER); + } + + else + { + rx65n_putreg(regval, RX65N_RIIC2_ICIER); + regval = rx65n_getreg(RX65N_RIIC2_ICIER); + } +} + +/**************************************************************************** + * Name: rx65n_riic_setclock + * + * Description: + * Sets the I2C bus clock frequency – frequency for the transfer + * + ****************************************************************************/ + +static void rx65n_riic_setclock(FAR struct rx65n_i2c_priv_s *priv, + uint32_t frequency) +{ + /* Divider array of RIIC clock */ + + uint8_t regval; + const uint8_t d_cks[RIIC_MAX_DIV] = + { 1, 2, 4, 8, 16, 32, 64, 128 + }; + + volatile double l_time; /* L Width period */ + volatile double h_time; /* H Width period */ + volatile double calc_val; /* Using for Calculation */ + double calc_val_tmp; + volatile uint8_t cnt; + + /* Calculation of L width time */ + + l_time = (1.0 / (2.0 * frequency)); /* Half period of frequency */ + h_time = l_time; + + /* Check I2C mode of Speed */ + + if (frequency > I2C_SPEED_FAST) + { + i2cinfo("Fast Plus Mode Selected - Transmission Rate: 1 Mbps\n"); + if (l_time < 0.5E-6) + { + /* Wnen L width less than 0.5us, subtract Rise up and down + * time for SCL from H/L width + */ + + l_time = 0.5E-6; + h_time = (((1.0 / frequency) - l_time) - SCL_RISE_TIME_FASTPLUS) \ + - SCL_FALL_TIME_FASTPLUS; + } + + else + { + /* Subtract Rise up and down time for SCL from H/L width */ + + l_time -= SCL_FALL_TIME_FASTPLUS; + h_time -= SCL_RISE_TIME_FASTPLUS; + } + } + + else if (frequency > I2C_SPEED_STANDARD) + { + i2cinfo("Fast Mode Selected - Transmission Rate: 400 kbps\n"); + if (l_time < 1.3E-6) + { + /* Wnen L width less than 1.3us, subtract Rise up and down + * time for SCL from H/L width + */ + + l_time = 1.3E-6; + h_time = (((1.0 / frequency) - l_time) - SCL_RISE_TIME_FAST) \ + - SCL_FALL_TIME_FAST; + } + + else + { + /* Subtract Rise up and down time for SCL from H/L width */ + + l_time -= SCL_FALL_TIME_FAST; + h_time -= SCL_RISE_TIME_FAST; + } + } + + else + { + i2cinfo("Standard Mode Selected - Transmission Rate: 100 kbps\n"); + + /* Subtract Rise up and down time for SCL from H/L width */ + + l_time -= SCL_FALL_TIME_STANDARD; + h_time -= SCL_RISE_TIME_STANDARD; + } + + /* Calculate ICBRL value */ + + for (calc_val = RIIC_RATE_CALC, cnt = 0; RIIC_CALC_MAX < calc_val; cnt++) + { + calc_val = l_time; /* Set L width time */ + + /* Check the range of divider of CKS */ + + if (cnt >= RIIC_MAX_DIV) + { + /* Cannot set bps */ + } + + calc_val_tmp = calc_val; + + /* Calculation of ICBRL value */ + + calc_val = (calc_val_tmp / (d_cks[cnt] / RX_PCLKB)); + calc_val = calc_val + 0.5; /* round off */ + } + + if (priv->bus == 0) + { + /* Set ICMR1.CKS bits. */ + + regval = rx65n_getreg(RX65N_RIIC0_ICMR1); + regval &= RX65N_RIIC_ICMR1_CKS_MASK; + regval |= (uint8_t) ((cnt - 1) << 4); + rx65n_putreg(regval, RX65N_RIIC0_ICMR1); + + /* Set value to ICBRL register */ + + regval = (uint8_t) ((uint8_t)(calc_val - 1) | RX65N_RIIC_ICBRL_MASK); + rx65n_putreg(regval, RX65N_RIIC0_ICBRL); + } + + else if (priv->bus == 1) + { + /* Set ICMR1.CKS bits. */ + + regval = rx65n_getreg(RX65N_RIIC1_ICMR1); + regval &= RX65N_RIIC_ICMR1_CKS_MASK; + regval |= (uint8_t) ((cnt - 1) << 4); + rx65n_putreg(regval, RX65N_RIIC1_ICMR1); + + /* Set value to ICBRL register */ + + regval = (uint8_t) ((uint8_t)(calc_val - 1) | RX65N_RIIC_ICBRL_MASK); + rx65n_putreg(regval, RX65N_RIIC1_ICBRL); + } + + else + { + /* Set ICMR1.CKS bits. */ + + regval = rx65n_getreg(RX65N_RIIC2_ICMR1); + regval &= RX65N_RIIC_ICMR1_CKS_MASK; + regval |= (uint8_t) ((cnt - 1) << 4); + rx65n_putreg(regval, RX65N_RIIC2_ICMR1); + + /* Set value to ICBRL register */ + + regval = (uint8_t) ((uint8_t)(calc_val - 1) | RX65N_RIIC_ICBRL_MASK); + rx65n_putreg(regval, RX65N_RIIC2_ICBRL); + } + + /* Calculate ICBRH value */ + + calc_val = h_time; + calc_val_tmp = calc_val; + + /* Calculation ICBRH value */ + + calc_val = (calc_val_tmp / (d_cks[cnt - 1] / RX_PCLKB)); + calc_val = (uint8_t) (calc_val + 0.5); /* Round off */ + + /* If the calculated value is less than 1, it rounded up to 1. */ + + if (1 > calc_val) + { + calc_val = 1; + } + + if (priv->bus == 0) + { + /* Set value to ICBRH register */ + + regval = (uint8_t) ((uint8_t) (calc_val - 1) | RX65N_RIIC_ICBRH_MASK); + rx65n_putreg(regval, RX65N_RIIC0_ICBRH); + } + + else if (priv->bus == 1) + { + /* Set value to ICBRH register */ + + regval = (uint8_t) ((uint8_t) (calc_val - 1) | RX65N_RIIC_ICBRH_MASK); + rx65n_putreg(regval, RX65N_RIIC1_ICBRH); + } + + else + { + /* Set value to ICBRH register */ + + regval = (uint8_t) ((uint8_t) (calc_val - 1) | RX65N_RIIC_ICBRH_MASK); + rx65n_putreg(regval, RX65N_RIIC2_ICBRH); + } +} + +/**************************************************************************** + * Name: rx65n_riic_int_enable + * + * Description: + * Enable Interrupts + * + ****************************************************************************/ + +static void rx65n_riic_int_enable(FAR struct rx65n_i2c_priv_s *priv) +{ + up_enable_irq(priv->dev->txi_irq); + up_enable_irq(priv->dev->rxi_irq); + up_enable_irq(priv->dev->tei_irq); + up_enable_irq(priv->dev->eei_irq); +} + +/**************************************************************************** + * Name: rx65n_riic_int_disable + * + * Description: + * Disable Interrupts + * + ****************************************************************************/ + +static void rx65n_riic_int_disable(FAR struct rx65n_i2c_priv_s *priv) +{ + up_disable_irq(priv->dev->txi_irq); + up_disable_irq(priv->dev->rxi_irq); + up_disable_irq(priv->dev->tei_irq); + up_disable_irq(priv->dev->eei_irq); +} + +/**************************************************************************** + * Name: rx65n_riic_irq_init + * + * Description: + * Setup the initial conditions of I2C interrupt handling + * + ****************************************************************************/ + +static int rx65n_riic_irq_init(FAR struct rx65n_i2c_priv_s *priv) +{ + int ret; + + IEN(ICU, GROUPBL1) = 0; /* Disable Group BL1 interrupts */ + IR(ICU, GROUPBL1) = 0; /* Clear interrupt flag */ + IPR(ICU, GROUPBL1) = RIIC_INTERRUPT_PRIO; + IEN(ICU, GROUPBL1) = 1; /* Enable Group BL1 interrupt */ + + if (priv->bus == 0) + { + IR(RIIC0, RXI0) = 0; + IPR(RIIC0, RXI0) = RIIC_INTERRUPT_PRIO; + + IR(RIIC0, TXI0) = 0; + IPR(RIIC0, TXI0) = RIIC_INTERRUPT_PRIO; + + ret = irq_attach(priv->dev->rxi_irq, rx65n_riic_rxi0interrupt, priv); + ret = irq_attach(priv->dev->txi_irq, rx65n_riic_txi0interrupt, priv); + ret = irq_attach(priv->dev->tei_irq, rx65n_riic_tei0interrupt, priv); + ret = irq_attach(priv->dev->eei_irq, rx65n_riic_eei0interrupt, priv); + } + + else if (priv->bus == 1) + { + IR(RIIC1, RXI1) = 0; + IPR(RIIC1, RXI1) = RIIC_INTERRUPT_PRIO; + + IR(RIIC1, TXI1) = 0; + IPR(RIIC1, TXI1) = RIIC_INTERRUPT_PRIO; + + ret = irq_attach(priv->dev->rxi_irq, rx65n_riic_rxi1interrupt, priv); + ret = irq_attach(priv->dev->txi_irq, rx65n_riic_txi1interrupt, priv); + ret = irq_attach(priv->dev->tei_irq, rx65n_riic_tei1interrupt, priv); + ret = irq_attach(priv->dev->eei_irq, rx65n_riic_eei1interrupt, priv); + } + + else + { + IR(RIIC2, RXI2) = 0; + IPR(RIIC2, RXI2) = RIIC_INTERRUPT_PRIO; + + IR(RIIC2, TXI2) = 0; + IPR(RIIC2, TXI2) = RIIC_INTERRUPT_PRIO; + + ret = irq_attach(priv->dev->rxi_irq, rx65n_riic_rxi2interrupt, priv); + ret = irq_attach(priv->dev->txi_irq, rx65n_riic_txi2interrupt, priv); + ret = irq_attach(priv->dev->tei_irq, rx65n_riic_tei2interrupt, priv); + ret = irq_attach(priv->dev->eei_irq, rx65n_riic_eei2interrupt, priv); + } + + rx65n_riic_int_enable(priv); + + return ret; +} + +/**************************************************************************** + * Name: rx65n_riic_init + * + * Description: + * Setup the initial conditions of I2C hardware and be ready for operation + * + ****************************************************************************/ + +static void rx65n_riic_init(FAR struct rx65n_i2c_priv_s *priv) +{ + uint8_t regval; + + /* Disable RXI, TXI,TEI and EEI interrupts */ + + rx65n_riic_int_disable(priv); + + /* RIIC registers initialization */ + + if (priv->bus == 0) + { + /* Release from the module-stop state */ + + MSTP_RIIC0 = 0; + + /* SCLn and SDAn pins not driven - RIIC disabled */ + + regval = rx65n_getreg(RX65N_RIIC0_ICCR1); + regval &= RX65N_RIIC_ICCR1_ICE_RST; + rx65n_putreg(regval, RX65N_RIIC0_ICCR1); + + /* RIIC Reset */ + + regval = rx65n_getreg(RX65N_RIIC0_ICCR1); + regval |= RX65N_RIIC_ICCR1_IICRST_SET; + rx65n_putreg(regval, RX65N_RIIC0_ICCR1); + + /* Internal reset, SCLn and SDAn pins in active state */ + + regval = rx65n_getreg(RX65N_RIIC0_ICCR1); + regval |= ~(RX65N_RIIC_ICCR1_ICE_RST); + rx65n_putreg(regval, RX65N_RIIC0_ICCR1); + + /* Set SARLy and SARUy */ + + rx65n_putreg(RIIC_REG_INIT, RX65N_RIIC0_SARL0); + rx65n_putreg(RIIC_REG_INIT, RX65N_RIIC0_SARU0); + rx65n_putreg(RIIC_REG_INIT, RX65N_RIIC0_SARL1); + rx65n_putreg(RIIC_REG_INIT, RX65N_RIIC0_SARU1); + rx65n_putreg(RIIC_REG_INIT, RX65N_RIIC0_SARL2); + rx65n_putreg(RIIC_REG_INIT, RX65N_RIIC0_SARU2); + + /* Set I2C bus frequency */ + + rx65n_riic_setclock(priv, priv->dev->frequency); + + regval = rx65n_getreg(RX65N_RIIC0_ICSER); + regval &= RX65N_RIIC_ICSER_SET; + rx65n_putreg(regval, RX65N_RIIC0_ICSER); + +#ifndef CONFIG_RX65N_RIIC0_NF + RIIC0.ICFER.BIT.NFE = 0; +#else + regval = rx65n_getreg(RX65N_RIIC0_ICMR3); + switch (CONFIG_RX65N_RIIC0_NF_STAGE) + { + case 1: + regval |= RX65N_RIIC_ICMR3_NF1; + break; + + case 2: + regval |= RX65N_RIIC_ICMR3_NF2; + break; + + case 3: + regval |= RX65N_RIIC_ICMR3_NF3; + break; + + case 4: + regval |= RX65N_RIIC_ICMR3_NF4; + break; + } + + rx65n_putreg(regval, RX65N_RIIC0_ICMR3); +#endif + + rx65n_putreg(RIIC_REG_INIT, RX65N_RIIC0_ICIER); + + regval = rx65n_getreg(RX65N_RIIC0_ICFER); + regval |= RX65N_RIIC_ICFER_TMOE_SET; + rx65n_putreg(regval, RX65N_RIIC0_ICFER); + +#ifdef CONFIG_RX65N_RIIC0_SDA_DELAY + RIIC0.ICMR2.BIT.DLCS = 1; + regval = rx65n_getreg(RX65N_RIIC0_ICMR2); + switch (CONFIG_RX65N_RIIC0_DELAY_CNT) + { + case 0: + regval |= RX65N_RIIC_ICMR2_SDDL0; + break; + + case 1: + regval |= RX65N_RIIC_ICMR2_SDDL1; + break; + + case 2: + regval |= RX65N_RIIC_ICMR2_SDDL2; + break; + + case 3: + regval |= RX65N_RIIC_ICMR2_SDDL3; + break; + + case 4: + regval |= RX65N_RIIC_ICMR2_SDDL4; + break; + + case 5: + regval |= RX65N_RIIC_ICMR2_SDDL5; + break; + + case 6: + regval |= RX65N_RIIC_ICMR2_SDDL6; + break; + + case 7: + regval |= RX65N_RIIC_ICMR2_SDDL7; + break; + } + + rx65n_putreg(regval, RX65N_RIIC0_ICMR2); +#endif + + rx65n_riic_irq_init(priv); + + regval = rx65n_getreg(RX65N_RIIC0_ICCR1); + regval &= ~(RX65N_RIIC_ICCR1_IICRST_SET); + rx65n_putreg(regval, RX65N_RIIC0_ICCR1); + } + + else if (priv->bus == 1) + { + /* Release from the module-stop state */ + + MSTP_RIIC1 = 0; + + /* SCLn and SDAn pins not driven - RIIC disabled */ + + regval = rx65n_getreg(RX65N_RIIC1_ICCR1); + regval &= RX65N_RIIC_ICCR1_ICE_RST; + rx65n_putreg(regval, RX65N_RIIC1_ICCR1); + + /* RIIC Reset */ + + regval = rx65n_getreg(RX65N_RIIC1_ICCR1); + regval |= RX65N_RIIC_ICCR1_IICRST_SET; + rx65n_putreg(regval, RX65N_RIIC1_ICCR1); + + /* Internal reset, SCLn and SDAn pins in active state */ + + regval = rx65n_getreg(RX65N_RIIC1_ICCR1); + regval |= ~(RX65N_RIIC_ICCR1_ICE_RST); + rx65n_putreg(regval, RX65N_RIIC1_ICCR1); + + /* Set SARLy and SARUy */ + + rx65n_putreg(RIIC_REG_INIT, RX65N_RIIC1_SARL0); + rx65n_putreg(RIIC_REG_INIT, RX65N_RIIC1_SARU0); + rx65n_putreg(RIIC_REG_INIT, RX65N_RIIC1_SARL1); + rx65n_putreg(RIIC_REG_INIT, RX65N_RIIC1_SARU1); + rx65n_putreg(RIIC_REG_INIT, RX65N_RIIC1_SARL2); + rx65n_putreg(RIIC_REG_INIT, RX65N_RIIC1_SARU2); + + /* Set I2C bus frequency */ + + rx65n_riic_setclock(priv, priv->dev->frequency); + + regval = rx65n_getreg(RX65N_RIIC1_ICSER); + regval &= RX65N_RIIC_ICSER_SET; + rx65n_putreg(regval, RX65N_RIIC1_ICSER); + +#ifndef CONFIG_RX65N_RIIC1_NF + RIIC1.ICFER.BIT.NFE = 0; +#else + regval = rx65n_getreg(RX65N_RIIC1_ICMR3); + switch (CONFIG_RX65N_RIIC1_NF_STAGE) + { + case 1: + regval |= RX65N_RIIC_ICMR3_NF1; + break; + + case 2: + regval |= RX65N_RIIC_ICMR3_NF2; + break; + + case 3: + regval |= RX65N_RIIC_ICMR3_NF3; + break; + + case 4: + regval |= RX65N_RIIC_ICMR3_NF4; + break; + } + + rx65n_putreg(regval, RX65N_RIIC1_ICMR3); +#endif + + rx65n_putreg(RIIC_REG_INIT, RX65N_RIIC1_ICIER); + + regval = rx65n_getreg(RX65N_RIIC1_ICFER); + regval |= RX65N_RIIC_ICFER_TMOE_SET; + rx65n_putreg(regval, RX65N_RIIC1_ICFER); + +#ifdef CONFIG_RX65N_RIIC1_SDA_DELAY + RIIC1.ICMR2.BIT.DLCS = 1; + regval = rx65n_getreg(RX65N_RIIC1_ICMR2); + switch (CONFIG_RX65N_RIIC1_DELAY_CNT) + { + case 0: + regval |= RX65N_RIIC_ICMR2_SDDL0; + break; + + case 1: + regval |= RX65N_RIIC_ICMR2_SDDL1; + break; + + case 2: + regval |= RX65N_RIIC_ICMR2_SDDL2; + break; + + case 3: + regval |= RX65N_RIIC_ICMR2_SDDL3; + break; + + case 4: + regval |= RX65N_RIIC_ICMR2_SDDL4; + break; + + case 5: + regval |= RX65N_RIIC_ICMR2_SDDL5; + break; + + case 6: + regval |= RX65N_RIIC_ICMR2_SDDL6; + break; + + case 7: + regval |= RX65N_RIIC_ICMR2_SDDL7; + break; + } + + rx65n_putreg(regval, RX65N_RIIC1_ICMR2); +#endif + + rx65n_riic_irq_init(priv); + + regval = rx65n_getreg(RX65N_RIIC1_ICCR1); + regval &= ~(RX65N_RIIC_ICCR1_IICRST_SET); + rx65n_putreg(regval, RX65N_RIIC1_ICCR1); + } + + else + { + /* Release from the module-stop state */ + + MSTP_RIIC2 = 0; + + /* SCLn and SDAn pins not driven - RIIC disabled */ + + regval = rx65n_getreg(RX65N_RIIC2_ICCR1); + regval &= RX65N_RIIC_ICCR1_ICE_RST; + rx65n_putreg(regval, RX65N_RIIC2_ICCR1); + + /* RIIC Reset */ + + regval = rx65n_getreg(RX65N_RIIC2_ICCR1); + regval |= RX65N_RIIC_ICCR1_IICRST_SET; + rx65n_putreg(regval, RX65N_RIIC2_ICCR1); + + /* Internal reset, SCLn and SDAn pins in active state */ + + regval = rx65n_getreg(RX65N_RIIC2_ICCR1); + regval |= ~(RX65N_RIIC_ICCR1_ICE_RST); + rx65n_putreg(regval, RX65N_RIIC2_ICCR1); + + /* Set SARLy and SARUy */ + + rx65n_putreg(RIIC_REG_INIT, RX65N_RIIC2_SARL0); + rx65n_putreg(RIIC_REG_INIT, RX65N_RIIC2_SARU0); + rx65n_putreg(RIIC_REG_INIT, RX65N_RIIC2_SARL1); + rx65n_putreg(RIIC_REG_INIT, RX65N_RIIC2_SARU1); + rx65n_putreg(RIIC_REG_INIT, RX65N_RIIC2_SARL2); + rx65n_putreg(RIIC_REG_INIT, RX65N_RIIC2_SARU2); + + /* Set I2C bus frequency */ + + rx65n_riic_setclock(priv, priv->dev->frequency); + + regval = rx65n_getreg(RX65N_RIIC2_ICSER); + regval &= RX65N_RIIC_ICSER_SET; + rx65n_putreg(regval, RX65N_RIIC2_ICSER); + +#ifndef CONFIG_RX65N_RIIC2_NF + RIIC2.ICFER.BIT.NFE = 0; +#else + regval = rx65n_getreg(RX65N_RIIC2_ICMR3); + switch (CONFIG_RX65N_RIIC2_NF_STAGE) + { + case 1: + regval |= RX65N_RIIC_ICMR3_NF1; + break; + + case 2: + regval |= RX65N_RIIC_ICMR3_NF2; + break; + + case 3: + regval |= RX65N_RIIC_ICMR3_NF3; + break; + + case 4: + regval |= RX65N_RIIC_ICMR3_NF4; + break; + } + + rx65n_putreg(regval, RX65N_RIIC2_ICMR3); +#endif + + rx65n_putreg(RIIC_REG_INIT, RX65N_RIIC2_ICIER); + + regval = rx65n_getreg(RX65N_RIIC2_ICFER); + regval |= RX65N_RIIC_ICFER_TMOE_SET; + rx65n_putreg(regval, RX65N_RIIC2_ICFER); + +#ifdef CONFIG_RX65N_RIIC2_SDA_DELAY + RIIC2.ICMR2.BIT.DLCS = 1; + regval = rx65n_getreg(RX65N_RIIC2_ICMR2); + switch (CONFIG_RX65N_RIIC2_DELAY_CNT) + { + case 0: + regval |= RX65N_RIIC_ICMR2_SDDL0; + break; + + case 1: + regval |= RX65N_RIIC_ICMR2_SDDL1; + break; + + case 2: + regval |= RX65N_RIIC_ICMR2_SDDL2; + break; + + case 3: + regval |= RX65N_RIIC_ICMR2_SDDL3; + break; + + case 4: + regval |= RX65N_RIIC_ICMR2_SDDL4; + break; + + case 5: + regval |= RX65N_RIIC_ICMR2_SDDL5; + break; + + case 6: + regval |= RX65N_RIIC_ICMR2_SDDL6; + break; + + case 7: + regval |= RX65N_RIIC_ICMR2_SDDL7; + break; + } + + rx65n_putreg(regval, RX65N_RIIC2_ICMR2); +#endif + + rx65n_riic_irq_init(priv); + + regval = rx65n_getreg(RX65N_RIIC2_ICCR1); + regval &= ~(RX65N_RIIC_ICCR1_IICRST_SET); + rx65n_putreg(regval, RX65N_RIIC2_ICCR1); + } + + priv->mode = RIIC_READY; + priv->dev_sts = RIIC_STS_IDLE; + + /* RIIC registers initialized */ +} + +/**************************************************************************** + * Function Name: rx65n_riic_set_sending_data + * Description : Transmit Data Processing. + * Sets transmission data to ICDRT register. + * Arguments : rx65n_i2c_priv_s *priv ; IIC Information + * Return Value : None + ****************************************************************************/ + +static void rx65n_riic_set_sending_data (FAR struct rx65n_i2c_priv_s *priv, \ + uint8_t data) +{ + if (0 == priv->bus) + { + /* Clears TXI interrupt request register. */ + + IR(RIIC0, TXI0) = 0; + + /* Sets the transmitting data. */ + + rx65n_putreg(data, RX65N_RIIC0_ICDRT); + data = rx65n_getreg(RX65N_RIIC0_ICDRT); + } + + else if (1 == priv->bus) + { + /* Clears TXI interrupt request register. */ + + IR(RIIC1, TXI1) = 0; + + /* Sets the transmitting data. */ + + rx65n_putreg(data, RX65N_RIIC1_ICDRT); + data = rx65n_getreg(RX65N_RIIC1_ICDRT); + } + + else + { + /* Clears TXI interrupt request register. */ + + IR(RIIC2, TXI2) = 0; + + /* Sets the transmitting data. */ + + rx65n_putreg(data, RX65N_RIIC2_ICDRT); + data = rx65n_getreg(RX65N_RIIC2_ICDRT); + } +} + +/**************************************************************************** + * Name: rx65n_riic_advance + * + * Description: + * Check if RIIC Bus is busy + * + ****************************************************************************/ + +static void rx65n_riic_advance(FAR struct rx65n_i2c_priv_s *priv) +{ + int ret; + + if ((RIIC_EV_INT_TMO == priv->event) || (RIIC_STS_TMO == priv->dev_sts)) + { + i2cerr("RIIC Transfer Timed Out\n"); + rx65n_riic_timeout(priv); + } + + if (RIIC_EV_INT_AL == priv->event) + { + rx65n_riic_iicrst(priv); + } + + if (RIIC_EV_INT_START == priv->event) + { + rx65n_riic_send_slv_addr(priv); + } + + if (RIIC_EV_INT_ADD == priv->event) + { + rx65n_riic_after_send_slvadr(priv); + } + + if (RIIC_EV_INT_SEND == priv->event) + { + rx65n_riic_master_transmit(priv); + } + + if (RIIC_EV_INT_RECEIVE == priv->event) + { + if (RIIC_STS_RECEIVE_DATA_WAIT == priv->dev_sts) + { + rx65n_riic_master_receive(priv); + } + + else + { + rx65n_riic_after_send_slvadr(priv); + } + } + + if (RIIC_EV_INT_NACK == priv->event) + { + rx65n_riic_nack(priv); + } + + if (RIIC_EV_INT_STOP == priv->event) + { + ret = rx65n_riic_after_stop(priv); + if (RIIC_SUCCESS == ret) + { + priv->mode = RIIC_FINISH; + } + } +} + +/**************************************************************************** + * Name: rx65n_riic_nack + * + * Description: + * NACK reception handler + * + ****************************************************************************/ + +static void rx65n_riic_nack(FAR struct rx65n_i2c_priv_s *priv) +{ + rx65n_riic_set_icier(priv, RX65N_RIIC_ICIER_SP_AL); + + priv->dev_sts = RIIC_STS_SP_COND_WAIT; + rx65n_riic_stopcond(priv); + + if (RIIC_M_RECEIVE == priv->mode) + { + rx65n_riic_read_data(priv); + } +} + +/**************************************************************************** + * Name: rx65n_riic_timeout + * + * Description: + * After Timeout condition processing + * + ****************************************************************************/ + +static void rx65n_riic_timeout(FAR struct rx65n_i2c_priv_s *priv) +{ + priv->mode = RIIC_FINISH; +} + +/**************************************************************************** + * Name: rx65n_riic_after_stop + * + * Description: + * After stop condition processing + * + ****************************************************************************/ + +static int rx65n_riic_after_stop(FAR struct rx65n_i2c_priv_s *priv) +{ + int ret; + bool bus; + + bus = rx65n_riic_check_bus_busy(priv); + + if (bus == RIIC_BUS_BUSY) + { + ret = RIIC_ERR_BUS_BUSY; + } + + else + { + if (RIIC_EV_INT_TMO == priv->event) + { + ret = RIIC_ERR_TMO; + } + + else + { + ret = RIIC_SUCCESS; + } + } + + return ret; +} + +/**************************************************************************** + * Name: rx65n_riic_check_bus_busy + * + * Description: + * Check if RIIC Bus is busy + * + ****************************************************************************/ + +static bool rx65n_riic_check_bus_busy(FAR struct rx65n_i2c_priv_s *priv) +{ + int i; + bool bus_state = RIIC_BUS_BUSY; + + if (priv->bus == 0) + { + for (i = BUS_CHECK_COUNTER; i >= 0; i--) + { + if ((0U == RIIC0.ICCR2.BIT.BBSY) && (1U == RIIC0.ICCR1.BIT.SCLI) && + (1U == RIIC0.ICCR1.BIT.SDAI)) + { + bus_state = RIIC_BUS_FREE; + break; + } + } + } + + if (priv->bus == 1) + { + for (i = BUS_CHECK_COUNTER; i >= 0; i--) + { + if ((0U == RIIC1.ICCR2.BIT.BBSY) && (1U == RIIC1.ICCR1.BIT.SCLI) && + (1U == RIIC1.ICCR1.BIT.SDAI)) + { + bus_state = RIIC_BUS_FREE; + break; + } + } + } + + else + { + for (i = BUS_CHECK_COUNTER; i >= 0; i--) + { + if ((0U == RIIC2.ICCR2.BIT.BBSY) && (1U == RIIC2.ICCR1.BIT.SCLI) && + (1U == RIIC2.ICCR1.BIT.SDAI)) + { + bus_state = RIIC_BUS_FREE; + break; + } + } + } + + return bus_state; +} + +/**************************************************************************** + * Name: rx65n_riic_startcond + * + * Description: + * Issue the start condition for Master transmission/reception + * + ****************************************************************************/ + +static int rx65n_riic_startcond(FAR struct rx65n_i2c_priv_s *priv) +{ + uint8_t regval; + int ret = RIIC_SUCCESS; + bool bus; + + if (priv->bus == 0) + { + bus = rx65n_riic_check_bus_busy(priv); + + if (bus == RIIC_BUS_FREE) + { + /* Clear stop */ + + regval = rx65n_getreg(RX65N_RIIC0_ICSR2); + regval &= ~(RX65N_RIIC_ICSR2_STOP_SET); + rx65n_putreg(regval, RX65N_RIIC0_ICSR2); + + regval = rx65n_getreg(RX65N_RIIC0_ICSR2); + while (0x00 != ((regval & RX65N_RIIC_ICSR2_START_SET) || \ + (regval & RX65N_RIIC_ICSR2_STOP_SET))) + { + regval = rx65n_getreg(RX65N_RIIC0_ICSR2); + } + + /* Set the internal status */ + + priv->dev_sts = RIIC_STS_ST_COND_WAIT; + + /* Clear ALIE bit */ + + regval = rx65n_getreg(RX65N_RIIC0_ICIER); + regval &= ~(RX65N_RIIC_ICIER_ALIE); + rx65n_putreg(regval, RX65N_RIIC0_ICIER); + + /* Interrupt setting */ + + rx65n_riic_set_icier(priv, RX65N_RIIC_ICIER_ST_NAK_AL); + + /* Generate the start condition */ + + /* Clear the start condition detection flag */ + + regval = rx65n_getreg(RX65N_RIIC0_ICSR2); + if (0x00 != ((regval & RX65N_RIIC_ICSR2_START_SET) >> 2U)) + { + /* Clears start condition detection flag. */ + + regval &= ~(RX65N_RIIC_ICSR2_START_SET); + rx65n_putreg(regval, RX65N_RIIC0_ICSR2); + regval = rx65n_getreg(RX65N_RIIC0_ICSR2); + } + + /* Generate start condition */ + + regval = rx65n_getreg(RX65N_RIIC0_ICCR2); + regval |= RX65N_RIIC_ICCR2_ST_SET; + rx65n_putreg(regval, RX65N_RIIC0_ICCR2); + regval = rx65n_getreg(RX65N_RIIC0_ICCR2); + } + + else + { + ret = RIIC_ERR_BUS_BUSY; + } + } + + else if (priv->bus == 1) + { + bus = rx65n_riic_check_bus_busy(priv); + + if (bus == RIIC_BUS_FREE) + { + /* Clear stop */ + + regval = rx65n_getreg(RX65N_RIIC1_ICSR2); + regval &= ~(RX65N_RIIC_ICSR2_STOP_SET); + rx65n_putreg(regval, RX65N_RIIC1_ICSR2); + + regval = rx65n_getreg(RX65N_RIIC1_ICSR2); + while (0x00 != ((regval & RX65N_RIIC_ICSR2_START_SET) || \ + (regval & RX65N_RIIC_ICSR2_STOP_SET))) + { + regval = rx65n_getreg(RX65N_RIIC1_ICSR2); + } + + priv->dev_sts = RIIC_STS_ST_COND_WAIT; + + regval = rx65n_getreg(RX65N_RIIC1_ICIER); + regval &= ~(RX65N_RIIC_ICIER_ALIE); + rx65n_putreg(regval, RX65N_RIIC1_ICIER); + + rx65n_riic_set_icier(priv, RX65N_RIIC_ICIER_ST_NAK_AL); + + regval = rx65n_getreg(RX65N_RIIC1_ICSR2); + if (0x00 != ((regval & RX65N_RIIC_ICSR2_START_SET) >> 2U)) + { + /* Clears start condition detection flag. */ + + regval &= ~(RX65N_RIIC_ICSR2_START_SET); + rx65n_putreg(regval, RX65N_RIIC1_ICSR2); + } + + /* Generate start condition */ + + regval = rx65n_getreg(RX65N_RIIC1_ICCR2); + regval |= RX65N_RIIC_ICCR2_ST_SET; + rx65n_putreg(regval, RX65N_RIIC1_ICCR2); + regval = rx65n_getreg(RX65N_RIIC1_ICCR2); + } + + else + { + ret = RIIC_ERR_BUS_BUSY; + } + } + + else + { + bus = rx65n_riic_check_bus_busy(priv); + + if (bus == RIIC_BUS_FREE) + { + /* Clear stop */ + + regval = rx65n_getreg(RX65N_RIIC2_ICSR2); + regval &= ~(RX65N_RIIC_ICSR2_STOP_SET); + rx65n_putreg(regval, RX65N_RIIC2_ICSR2); + + regval = rx65n_getreg(RX65N_RIIC2_ICSR2); + while (0x00 != ((regval & RX65N_RIIC_ICSR2_START_SET) || \ + (regval & RX65N_RIIC_ICSR2_STOP_SET))) + { + regval = rx65n_getreg(RX65N_RIIC2_ICSR2); + } + + priv->dev_sts = RIIC_STS_ST_COND_WAIT; + + regval = rx65n_getreg(RX65N_RIIC2_ICIER); + regval &= ~(RX65N_RIIC_ICIER_ALIE); + rx65n_putreg(regval, RX65N_RIIC2_ICIER); + + /* Timeout Detection */ + + rx65n_riic_set_icier(priv, RX65N_RIIC_ICIER_ST_NAK_AL); + + regval = rx65n_getreg(RX65N_RIIC2_ICSR2); + if (0x00 != ((regval & RX65N_RIIC_ICSR2_START_SET) >> 2U)) + { + /* Clears start condition detection flag. */ + + regval &= ~(RX65N_RIIC_ICSR2_START_SET); + rx65n_putreg(regval, RX65N_RIIC2_ICSR2); + } + + /* Generate start condition */ + + regval = rx65n_getreg(RX65N_RIIC2_ICCR2); + regval |= RX65N_RIIC_ICCR2_ST_SET; + rx65n_putreg(regval, RX65N_RIIC2_ICCR2); + regval = rx65n_getreg(RX65N_RIIC2_ICCR2); + } + + else + { + ret = RIIC_ERR_BUS_BUSY; + } + } + + return ret; +} + +/**************************************************************************** + * Name: rx65n_riic_restartcond + * + * Description: + * Issue Re-start condition for Master Transmission/Reception + * + ****************************************************************************/ + +static void rx65n_riic_restartcond(FAR struct rx65n_i2c_priv_s *priv) +{ + uint8_t regval; + + if (priv->bus == 0) + { + /* Clears start condition detection flag. */ + + regval = getreg8(RX65N_RIIC0_ICSR2); + if (0x00 != ((regval & RX65N_RIIC_ICSR2_START_SET) >> 2U)) + { + regval &= ~(RX65N_RIIC_ICSR2_START_SET); + rx65n_putreg(regval, RX65N_RIIC0_ICSR2); + } + + /* Generates a restart condition. */ + + regval = getreg8(RX65N_RIIC0_ICCR2); + regval |= RX65N_RIIC_ICCR2_RS_SET; /* Sets ICCR2.RS bit. */ + rx65n_putreg(regval, RX65N_RIIC0_ICCR2); + } + + else if (priv->bus == 1) + { + /* Clears start condition detection flag. */ + + regval = getreg8(RX65N_RIIC1_ICSR2); + if (0x00 != ((regval & RX65N_RIIC_ICSR2_START_SET) >> 2U)) + { + regval &= ~(RX65N_RIIC_ICSR2_START_SET); + rx65n_putreg(regval, RX65N_RIIC1_ICSR2); + } + + /* Generates a restart condition. */ + + regval = getreg8(RX65N_RIIC1_ICCR2); + regval |= RX65N_RIIC_ICCR2_RS_SET; /* Sets ICCR2.RS bit. */ + rx65n_putreg(regval, RX65N_RIIC1_ICCR2); + } + + else + { + /* Clears start condition detection flag. */ + + regval = getreg8(RX65N_RIIC2_ICSR2); + if (0x00 != ((regval & RX65N_RIIC_ICSR2_START_SET) >> 2U)) + { + regval &= ~(RX65N_RIIC_ICSR2_START_SET); + rx65n_putreg(regval, RX65N_RIIC2_ICSR2); + } + + /* Generates a restart condition. */ + + regval = getreg8(RX65N_RIIC2_ICCR2); + regval |= RX65N_RIIC_ICCR2_RS_SET; /* Sets ICCR2.RS bit. */ + rx65n_putreg(regval, RX65N_RIIC2_ICCR2); + } +} + +/**************************************************************************** + * Name: rx65n_riic_send_slv_addr + * + * Description: + * Transmit slave address for communication + * + ****************************************************************************/ + +static void rx65n_riic_send_slv_addr(FAR struct rx65n_i2c_priv_s *priv) +{ + uint16_t bit_addr; + uint8_t regval; + + if (priv->msgv->flags == I2C_M_TEN) + { + /* 10 bit slave address handling */ + + bit_addr = priv->msgv->addr; + bit_addr &= RX65N_RIIC_10BIT_SARU_MASK; + bit_addr >>= 8; + regval = (uint8_t) bit_addr; + + rx65n_riic_set_sending_data(priv, regval); + + /* Check ACK/NACK reception */ + + bit_addr = priv->msgv->addr; + bit_addr &= RX65N_RIIC_10BIT_SARL_MASK; + regval = (uint8_t) bit_addr; + } + + else + { + if (priv->flags == I2C_M_READ) + { + priv->mode = RIIC_M_RECEIVE; + rx65n_riic_set_icier(priv, RX65N_RIIC_ICIER_RX_NAK_AL); + + /* 7-bit slave address with READ code */ + + regval = (priv->msgv->addr); + regval <<= 1U; + regval |= RX65N_RIIC_READ_MASK; + + priv->dev_sts = RIIC_STS_SEND_SLVADR_R_WAIT; + } + + else + { + priv->mode = RIIC_M_TRANSMIT; + rx65n_riic_set_icier(priv, RX65N_RIIC_ICIER_TEND_NAK_AL); + + /* 7-bit slave address with WRITE code */ + + regval = (priv->msgv->addr); + regval <<= 1U; + regval &= ~(RX65N_RIIC_READ_MASK); + + priv->dev_sts = RIIC_STS_SEND_SLVADR_W_WAIT; + } + } + + /* Send slave address */ + + rx65n_riic_set_sending_data(priv, regval); +} + +/**************************************************************************** + * Name: rx65n_riic_after_send_slvadr + * + * Description: + * Processing after sending slave address + * + ****************************************************************************/ + +static void rx65n_riic_after_send_slvadr(FAR struct rx65n_i2c_priv_s *priv) +{ + uint8_t regval; + uint8_t *data; + + if (RIIC_M_TRANSMIT == priv->mode) + { + /* Pattern write 1: msg[0] is memory addressand msg[1] is data byte */ + + if (2U >= priv->msgc) + { + priv->dev_sts = RIIC_STS_SEND_DATA_WAIT; + rx65n_riic_set_icier(priv, RX65N_RIIC_ICIER_TEND_NAK_AL); + + /* Transmit first byte (memory address) */ + + if (0U != priv->dcnt) + { + data = priv->ptr; + regval = *data; + rx65n_riic_set_sending_data(priv, regval); + + priv->dcnt--; + priv->ptr++; + } + + else + { + /* Do nothing */ + } + } + + /* Pattern write 2: msg[0] is data byte */ + + else if (1U >= priv->msgc) + { + priv->dev_sts = RIIC_STS_SEND_DATA_WAIT; + rx65n_riic_set_icier(priv, RX65N_RIIC_ICIER_TEND_NAK_AL); + + /* Transmit data byte */ + + if (0U != priv->dcnt) + { + data = priv->ptr; + regval = *data; + rx65n_riic_set_sending_data(priv, regval); + + priv->dcnt--; + priv->ptr++; + } + + else + { + /* Do nothing */ + } + } + + /* Pattern write 3: transmit only slave address */ + + else if (0 == priv->msgc) + { + priv->dev_sts = RIIC_STS_SP_COND_WAIT; + rx65n_riic_set_icier(priv, RX65N_RIIC_ICIER_SP_NAK_AL); + + /* Generate stop condition */ + + rx65n_riic_stopcond(priv); + } + + else + { + /* Do nothing */ + } + } + + if (RIIC_M_RECEIVE == priv->mode) + { + priv->dev_sts = RIIC_STS_RECEIVE_DATA_WAIT; + + rx65n_riic_set_icier(priv, RX65N_RIIC_ICIER_RX_NAK_AL); + + if (2 >= priv->dcnt) + { + rx65n_riic_wait_set(priv); + } + + if (0x01 >= priv->dcnt) + { + rx65n_riic_pre_end_set(priv); + } + + /* Dummy read */ + + regval = rx65n_riic_read_data(priv); + } +} + +/**************************************************************************** + * Name: rx65n_riic_stopcond + * + * Description: + * Issue stop condition for Master Transmission/Reception + * + ****************************************************************************/ + +static void rx65n_riic_stopcond(FAR struct rx65n_i2c_priv_s *priv) +{ + uint8_t regval; + + if (priv->bus == 0) + { + regval = rx65n_getreg(RX65N_RIIC0_ICSR2); + if (0x00 != ((regval & RX65N_RIIC_ICSR2_STOP_SET) >> 3U)) + { + regval &= ~(RX65N_RIIC_ICSR2_STOP_SET); + rx65n_putreg(regval, RX65N_RIIC0_ICSR2); + regval = rx65n_getreg(RX65N_RIIC0_ICSR2); + } + + /* Generates a stop condition. */ + + regval = rx65n_getreg(RX65N_RIIC0_ICCR2); + regval |= RX65N_RIIC_ICCR2_SP_SET; /* Sets ICCR2.SP bit. */ + rx65n_putreg(regval, RX65N_RIIC0_ICCR2); + + regval = rx65n_getreg(RX65N_RIIC0_ICCR2); + } + + else if (priv->bus == 1) + { + /* Clears stop condition detection flag. */ + + regval = rx65n_getreg(RX65N_RIIC1_ICSR2); + if (0x00 != ((regval & RX65N_RIIC_ICSR2_STOP_SET) >> 3U)) + { + regval &= ~(RX65N_RIIC_ICSR2_STOP_SET); + rx65n_putreg(regval, RX65N_RIIC1_ICSR2); + } + + /* Generates a stop condition. */ + + regval = rx65n_getreg(RX65N_RIIC1_ICCR2); + regval |= RX65N_RIIC_ICCR2_SP_SET; /* Sets ICCR2.SP bit. */ + rx65n_putreg(regval, RX65N_RIIC1_ICCR2); + } + + else + { + /* Clears stop condition detection flag. */ + + regval = rx65n_getreg(RX65N_RIIC2_ICSR2); + if (0x00 != ((regval & RX65N_RIIC_ICSR2_STOP_SET) >> 3U)) + { + regval &= ~(RX65N_RIIC_ICSR2_STOP_SET); + rx65n_putreg(regval, RX65N_RIIC2_ICSR2); + } + + /* Generates a stop condition. */ + + regval = rx65n_getreg(RX65N_RIIC2_ICCR2); + regval |= RX65N_RIIC_ICCR2_SP_SET; /* Sets ICCR2.SP bit. */ + rx65n_putreg(regval, RX65N_RIIC2_ICCR2); + } +} + +/**************************************************************************** + * Name: rx65n_riic_master_transmit + * + * Description: + * Transmission of data from Master to Slave + * + ****************************************************************************/ + +static void rx65n_riic_master_transmit(FAR struct rx65n_i2c_priv_s *priv) +{ + uint8_t regval; + uint8_t *data; + + priv->dev_sts = RIIC_STS_SEND_DATA_WAIT; + + if (0U == priv->dcnt) + { + /* Moving to the next message */ + + priv->msgc--; + + if (0x00 == priv->msgc) + { + rx65n_riic_set_icier(priv, RX65N_RIIC_ICIER_SP_NAK_AL); + + priv->dev_sts = RIIC_STS_SP_COND_WAIT; + rx65n_riic_stopcond(priv); + } + + else + { + priv->msgv++; + priv->ptr = priv->msgv->buffer; + priv->flags = priv->msgv->flags; + priv->dcnt = priv->msgv->length; + + if (priv->flags == I2C_M_READ) + { + priv->mode = RIIC_M_RECEIVE; + priv->event = RIIC_EV_GEN_START_COND; + + rx65n_riic_set_icier(priv, RX65N_RIIC_ICIER_ST_NAK_AL); + + rx65n_riic_restartcond(priv); + } + } + } + + if (0U != priv->dcnt && priv->flags != I2C_M_READ) + { + rx65n_riic_set_icier(priv, RX65N_RIIC_ICIER_TEND_NAK_AL); + + data = priv->ptr; + regval = *data; + + /* send the byte */ + + rx65n_riic_set_sending_data(priv, regval); + + /* decrement the count */ + + priv->dcnt--; + priv->ptr++; + } +} + +/**************************************************************************** + * Name: rx65n_riic_read_data + * + * Description: + * Read received data from ICDRR + * + ****************************************************************************/ + +static uint8_t rx65n_riic_read_data(FAR struct rx65n_i2c_priv_s *priv) +{ + volatile uint8_t * regval; + + if (0 == priv->bus) + { + regval = (uint8_t *) (RX65N_RIIC0_ICDRR); + } + + else if (1 == priv->bus) + { + regval = (uint8_t *) (RX65N_RIIC1_ICDRR); + } + + else + { + regval = (uint8_t *) (RX65N_RIIC2_ICDRR); + } + + return *regval; +} + +/**************************************************************************** + * Name: rx65n_riic_wait_set + * + * Description: + * Receive "last byte - 2bytes" Setting Proccesing. + * Sets ICMR3.WAIT bit. + * + ****************************************************************************/ + +static void rx65n_riic_wait_set(FAR struct rx65n_i2c_priv_s *priv) +{ + uint8_t regval; + + if (0 == priv->bus) + { +#ifdef CONFIG_RX65N_RIIC0_RCV_IN_BYTE_UNITS + regval = rx65n_getreg(RX65N_RIIC0_ICMR3); + regval |= RX65N_RIIC_ICMR3_WAIT_SET; + rx65n_putreg(regval, RX65N_RIIC0_ICMR3); + regval = rx65n_getreg(RX65N_RIIC0_ICMR3); +#endif + } + + else if (1 == priv->bus) + { +#ifdef CONFIG_RX65N_RIIC1_RCV_IN_BYTE_UNITS + regval = rx65n_getreg(RX65N_RIIC1_ICMR3); + regval |= RX65N_RIIC_ICMR3_WAIT_SET; + rx65n_putreg(regval, RX65N_RIIC1_ICMR3); + regval = rx65n_getreg(RX65N_RIIC1_ICMR3); +#endif + } + + else + { +#ifdef CONFIG_RX65N_RIIC2_RCV_IN_BYTE_UNITS + regval = rx65n_getreg(RX65N_RIIC2_ICMR3); + regval |= RX65N_RIIC_ICMR3_WAIT_SET; + rx65n_putreg(regval, RX65N_RIIC2_ICMR3); + regval = rx65n_getreg(RX65N_RIIC2_ICMR3); +#endif + } +} + +/**************************************************************************** + * Name: rx65n_riic_pre_end_set + * + * Description: + * Receive "last byte - 1byte" Setting Processing. + * Sets ICMR3.RDRFS bit and ACKBT bit. + * + ****************************************************************************/ + +static void rx65n_riic_pre_end_set(FAR struct rx65n_i2c_priv_s *priv) +{ + if (0 == priv->bus) + { +#ifdef CONFIG_RX65N_RIIC0_RCV_IN_BYTE_UNITS + RIIC0.ICMR3.BIT.RDRFS = 1; +#endif + RIIC0.ICMR3.BIT.ACKWP = 1; + RIIC0.ICMR3.BIT.ACKBT = 1; + RIIC0.ICMR3.BIT.ACKWP = 0; + + (void)rx65n_getreg(RX65N_RIIC0_ICMR3); + } + + else if (1 == priv->bus) + { +#ifdef CONFIG_RX65N_RIIC1_RCV_IN_BYTE_UNITS + RIIC1.ICMR3.BIT.RDRFS = 1; +#endif + RIIC1.ICMR3.BIT.ACKWP = 1; + RIIC1.ICMR3.BIT.ACKBT = 1; + RIIC1.ICMR3.BIT.ACKWP = 0; + + (void)rx65n_getreg(RX65N_RIIC1_ICMR3); + } + + else + { +#ifdef CONFIG_RX65N_RIIC2_RCV_IN_BYTE_UNITS + RIIC2.ICMR3.BIT.RDRFS = 1; +#endif + RIIC2.ICMR3.BIT.ACKWP = 1; + RIIC2.ICMR3.BIT.ACKBT = 1; + RIIC2.ICMR3.BIT.ACKWP = 0; + + (void)rx65n_getreg(RX65N_RIIC2_ICMR3); + } +} + +/**************************************************************************** + * Name: rx65n_riic_end_set + * + * Description: + * Receive End Setting Processing. + * Sets ICMR3.ACKBT bit and clears ICMR3.WAIT bit. + * + ****************************************************************************/ + +static void rx65n_riic_end_set(FAR struct rx65n_i2c_priv_s *priv) +{ + if (0 == priv->bus) + { + RIIC0.ICMR3.BIT.ACKWP = 1; + RIIC0.ICMR3.BIT.ACKBT = 1; + RIIC0.ICMR3.BIT.ACKWP = 0; +#ifdef CONFIG_RX65N_RIIC0_RCV_IN_BYTE_UNITS + RIIC0.ICMR3.BIT.WAIT = 0; +#endif + + rx65n_getreg(RX65N_RIIC0_ICMR3); + } + + else if (1 == priv->bus) + { + RIIC1.ICMR3.BIT.ACKWP = 1; + RIIC1.ICMR3.BIT.ACKBT = 1; + RIIC1.ICMR3.BIT.ACKWP = 0; +#ifdef CONFIG_RX65N_RIIC1_RCV_IN_BYTE_UNITS + RIIC1.ICMR3.BIT.WAIT = 0; +#endif + + rx65n_getreg(RX65N_RIIC1_ICMR3); + } + + else + { + RIIC2.ICMR3.BIT.ACKWP = 1; + RIIC2.ICMR3.BIT.ACKBT = 1; + RIIC2.ICMR3.BIT.ACKWP = 0; +#ifdef CONFIG_RX65N_RIIC2_RCV_IN_BYTE_UNITS + RIIC2.ICMR3.BIT.WAIT = 0; +#endif + + rx65n_getreg(RX65N_RIIC2_ICMR3); + } +} + +/**************************************************************************** + * Name: rx65n_riic_master_receive + * + * Description: + * Transmission of data from Master to Slave + * + ****************************************************************************/ + +static void rx65n_riic_master_receive(FAR struct rx65n_i2c_priv_s *priv) +{ + uint8_t regval; + priv->dev_sts = RIIC_STS_RECEIVE_DATA_WAIT; + + /* The period between the ninth clock cycle and the first clock cycle + * is held low. Low-hold is released by reading the ICDRR register. + */ + + if (0x03 >= priv->dcnt) + { + rx65n_riic_wait_set(priv); + } + + if (0x02 >= priv->dcnt) + { + rx65n_riic_pre_end_set(priv); + } + + if (0x01 >= priv->dcnt) + { + rx65n_riic_set_icier(priv, RX65N_RIIC_ICIER_SP_NAK_AL); + + priv->dev_sts = RIIC_STS_SP_COND_WAIT; + rx65n_riic_stopcond(priv); + + if (0x00 != priv->dcnt) + { + regval = rx65n_riic_read_data(priv); + *(priv->msgv->buffer) = regval; + priv->msgv->buffer++; + *(priv->ptr) = regval; + priv->dcnt--; + } + + else + { + regval = rx65n_riic_read_data(priv); + } + + rx65n_riic_end_set(priv); + } + + else + { + regval = rx65n_riic_read_data(priv); + *(priv->msgv->buffer) = regval; + priv->msgv->buffer++; + *(priv->ptr) = regval; + priv->dcnt--; + } +} + +/**************************************************************************** + * Name: rx65n_riic_rxi0interrupt + * + * Description: + * Interrupt RIIC0 RXI0 handler – Received Data Full Interrupt Handler + * + * Occurs under following conditions: + * - Address/data transmission completed in Master Receive Mode + * - Reception of (last data – 1) completed in Master Receive Mode + * - Reception of last data completed in Master Receive Mode + * + ****************************************************************************/ + +static int rx65n_riic_rxi0interrupt(int irq, FAR void *context, \ + FAR void *arg) +{ + FAR struct rx65n_i2c_priv_s *priv = (struct rx65n_i2c_priv_s *)arg; + + priv->event = RIIC_EV_INT_RECEIVE; + + rx65n_riic_advance(priv); + return OK; +} + +/**************************************************************************** + * Name: rx65n_riic_rxi1interrupt + * + * Description: + * Interrupt RIIC1 RXI1 handler – Received Data Full Interrupt Handler + * + * Occurs under following conditions: + * - Address/data transmission completed in Master Receive Mode + * - Reception of (last data – 1) completed in Master Receive Mode + * - Reception of last data completed in Master Receive Mode + * + ****************************************************************************/ + +static int rx65n_riic_rxi1interrupt(int irq, FAR void *context, \ + FAR void *arg) +{ + FAR struct rx65n_i2c_priv_s *priv = (struct rx65n_i2c_priv_s *)arg; + + priv->event = RIIC_EV_INT_RECEIVE; + + rx65n_riic_advance(priv); + return OK; +} + +/**************************************************************************** + * Name: rx65n_i2c_rxi2interrupt + * + * Description: + * Interrupt RIIC2 RXI2 handler – Received Data Full Interrupt Handler + * + * Occurs under following conditions: + * - Address/data transmission completed in Master Receive Mode + * - Reception of (last data – 1) completed in Master Receive Mode + * - Reception of last data completed in Master Receive Mode + * + ****************************************************************************/ + +static int rx65n_riic_rxi2interrupt(int irq, FAR void *context, \ + FAR void *arg) +{ + FAR struct rx65n_i2c_priv_s *priv = (struct rx65n_i2c_priv_s *)arg; + priv->event = RIIC_EV_INT_RECEIVE; + + rx65n_riic_advance(priv); + return OK; +} + +/**************************************************************************** + * Name: rx65n_riic_txi0interrupt + * + * Description: + * Interrupt RIIC0 TXI0 handler – Transmit Data Empty Interrupt Handler + * + * Occurs under following conditions: + * - Transmit Buffer is empty + * + ****************************************************************************/ + +static int rx65n_riic_txi0interrupt(int irq, FAR void *context, \ + FAR void *arg) +{ + FAR struct rx65n_i2c_priv_s *priv = (struct rx65n_i2c_priv_s *)arg; + + /* Ideally, should never get here as this interrupt only occurs during + * Multi-master mode of operation and + * Slave transmission/recption mode + */ + + priv->event = RIIC_EV_INT_TXI; + + rx65n_riic_advance(priv); + return OK; +} + +/**************************************************************************** + * Name: rx65n_riic_txi1interrupt + * + * Description: + * Interrupt RIIC1 TXI1 handler – Transmit Data Empty Interrupt Handler + * + * Occurs under following conditions: + * - Transmit Buffer is empty + * + ****************************************************************************/ + +static int rx65n_riic_txi1interrupt(int irq, FAR void *context, \ + FAR void *arg) +{ + FAR struct rx65n_i2c_priv_s *priv = (struct rx65n_i2c_priv_s *)arg; + + /* Ideally, should never get here as this interrupt only occurs during + * Multi-master mode of operation and + * Slave transmission/recption mode + */ + + priv->event = RIIC_EV_INT_TXI; + + rx65n_riic_advance(priv); + return OK; +} + +/**************************************************************************** + * Name: rx65n_riic_txi2interrupt + * + * Description: + * Interrupt RIIC2 TXI2 handler – Transmit Data Empty Interrupt Handler + * + * Occurs under following conditions: + * - Transmit Buffer is empty + * + ****************************************************************************/ + +static int rx65n_riic_txi2interrupt(int irq, FAR void *context, \ + FAR void *arg) +{ + FAR struct rx65n_i2c_priv_s *priv = (struct rx65n_i2c_priv_s *)arg; + + /* Ideally, should never get here as this interrupt only occurs during + * Multi-master mode of operation and + * Slave transmission/recption mode + */ + + priv->event = RIIC_EV_INT_TXI; + + rx65n_riic_advance(priv); + return OK; +} + +/**************************************************************************** + * Name: rx65n_riic_tei0interrupt + * + * Description: + * Interrupt RIIC0 TEI0 handler – Transmission End Interrupt Handler + * + * Occurs under following conditions: + * - Address/data transmission completed + * + ****************************************************************************/ + +static int rx65n_riic_tei0interrupt(int irq, FAR void *context, \ + FAR void *arg) +{ + FAR struct rx65n_i2c_priv_s *priv = (struct rx65n_i2c_priv_s *)arg; + + RIIC0.ICSR2.BIT.TEND = 0U; + while (0U != RIIC0.ICSR2.BIT.TEND) + { + /* Do Nothing */ + } + + if ((RIIC_STS_SEND_SLVADR_W_WAIT == priv->dev_sts) || + (RIIC_STS_SEND_SLVADR_R_WAIT == priv->dev_sts)) + { + /* Sets interrupted address sending - slave address transmitted */ + + priv->event = RIIC_EV_INT_ADD; + } + + else if (RIIC_STS_SEND_DATA_WAIT == priv->dev_sts) + { + /* Sets interrupted data sending */ + + priv->event = RIIC_EV_INT_SEND; + } + + rx65n_riic_advance(priv); + return OK; +} + +/**************************************************************************** + * Name: rx65n_riic_tei1interrupt + * + * Description: + * Interrupt RIIC1 TEI1 handler – Transmission End Interrupt Handler + * + * Occurs under following conditions: + * - Address/data transmission completed + * + ****************************************************************************/ + +static int rx65n_riic_tei1interrupt(int irq, FAR void *context, \ + FAR void *arg) +{ + FAR struct rx65n_i2c_priv_s *priv = (struct rx65n_i2c_priv_s *)arg; + + RIIC1.ICSR2.BIT.TEND = 0U; + while (0U != RIIC1.ICSR2.BIT.TEND) + { + /* Do Nothing */ + } + + if ((RIIC_STS_SEND_SLVADR_W_WAIT == priv->dev_sts) || + (RIIC_STS_SEND_SLVADR_R_WAIT == priv->dev_sts)) + { + priv->event = RIIC_EV_INT_ADD; + } + + else if (RIIC_STS_SEND_DATA_WAIT == priv->dev_sts) + { + priv->event = RIIC_EV_INT_SEND; + } + + rx65n_riic_advance(priv); + return OK; +} + +/**************************************************************************** + * Name: rx65n_riic_tei2interrupt + * + * Description: + * Interrupt RIIC2 TEI2 handler – Transmission End Interrupt Handler + * + * Occurs under following conditions: + * - Address/data transmission completed + * + ****************************************************************************/ + +static int rx65n_riic_tei2interrupt(int irq, FAR void *context, \ + FAR void *arg) +{ + FAR struct rx65n_i2c_priv_s *priv = (struct rx65n_i2c_priv_s *)arg; + + RIIC2.ICSR2.BIT.TEND = 0U; + while (0U != RIIC2.ICSR2.BIT.TEND) + { + /* Do Nothing */ + } + + if ((RIIC_STS_SEND_SLVADR_W_WAIT == priv->dev_sts) || + (RIIC_STS_SEND_SLVADR_R_WAIT == priv->dev_sts)) + { + priv->event = RIIC_EV_INT_ADD; + } + + else if (RIIC_STS_SEND_DATA_WAIT == priv->dev_sts) + { + priv->event = RIIC_EV_INT_SEND; + } + + rx65n_riic_advance(priv); + return OK; +} + +/**************************************************************************** + * Name: rx65n_riic_eei0interrupt + * + * Description: + * Interrupt RIIC0 EEI0 handler – Event/Error Generation Interrupt Handler + * + * Occurs under following conditions: + * - START condition detected + * - RESTART condition detected + * - STOP condition detected + * - NACK detected + * - AL (arbitration-lost) detected + * - TMO (timeout detection) + * + ****************************************************************************/ + +static int rx65n_riic_eei0interrupt(int irq, FAR void *context, \ + FAR void *arg) +{ + FAR struct rx65n_i2c_priv_s *priv = (struct rx65n_i2c_priv_s *)arg; + + /* Check Timeout Condition */ + + if ((0U != RIIC0.ICSR2.BIT.TMOF) && (0U != RIIC0.ICIER.BIT.TMOIE)) + { + RIIC0.ICIER.BIT.TMOIE = 0U; + while (0U != RIIC0.ICIER.BIT.TMOIE) + { + /* Wait for reset to complete */ + } + + priv->event = RIIC_EV_INT_TMO; + } + + /* Check Arbitration-Lost Condition */ + + if ((0U != RIIC0.ICSR2.BIT.AL) && (0U != RIIC0.ICIER.BIT.ALIE)) + { + RIIC0.ICIER.BIT.ALIE = 0U; + while (0U != RIIC0.ICIER.BIT.ALIE) + { + /* Do Nothing */ + } + + priv->event = RIIC_EV_INT_AL; + } + + /* Check Stop Condition */ + + if ((0U != RIIC0.ICSR2.BIT.STOP) && (0U != RIIC0.ICIER.BIT.SPIE)) + { + RIIC0.ICIER.BIT.SPIE = 0U; + + RIIC0.ICMR3.BIT.RDRFS = 0U; + RIIC0.ICMR3.BIT.ACKWP = 1U; + RIIC0.ICMR3.BIT.ACKBT = 0U; + RIIC0.ICMR3.BIT.ACKWP = 0U; + + while ((0U != RIIC0.ICMR3.BIT.RDRFS) || \ + (0U != RIIC0.ICMR3.BIT.ACKBT)) + { + /* Do Nothing */ + } + + RIIC0.ICSR2.BIT.STOP = 0U; + while (0U != RIIC0.ICSR2.BIT.STOP) + { + /* Do Nothing */ + } + + priv->event = RIIC_EV_INT_STOP; + } + + /* Check NACK reception. */ + + if ((0U != RIIC0.ICSR2.BIT.NACKF) && (0U != RIIC0.ICIER.BIT.NAKIE)) + { + /* Prohibits NACK interrupt to generate stop condition. */ + + RIIC0.ICIER.BIT.NAKIE = 0U; + + /* Prohibits these interrupt. + * After NACK interrupt, these interrupts will occur + * when they do not stop the following interrupts. + */ + + RIIC0.ICIER.BIT.TEIE = 0U; + RIIC0.ICIER.BIT.TIE = 0U; + RIIC0.ICIER.BIT.RIE = 0U; + + while (((0U != RIIC0.ICIER.BIT.TEIE) || \ + (0U != RIIC0.ICIER.BIT.TIE)) || (0U != RIIC0.ICIER.BIT.RIE)) + { + /* Do Nothing */ + } + + if (0U == RIIC0.ICCR2.BIT.TRS) + { + IR(RIIC0, RXI0) = 0; + } + + priv->event = RIIC_EV_INT_NACK; + } + + /* Check Start condition detection. */ + + if ((0U != RIIC0.ICSR2.BIT.START) && (0U != RIIC0.ICIER.BIT.STIE)) + { + RIIC0.ICIER.BIT.STIE = 0U; + RIIC0.ICSR2.BIT.START = 0U; + while ((0U != RIIC0.ICSR2.BIT.START) || \ + (0U != RIIC0.ICIER.BIT.STIE)) + { + /* Wait till reset is completed */ + } + + /* Sets event flag. */ + + priv->event = RIIC_EV_INT_START; + } + + rx65n_riic_advance(priv); + return OK; +} + +/**************************************************************************** + * Name: rx65n_riic_eei1interrupt + * + * Description: + * Interrupt RIIC1 EEI1 handler – Event/Error Generation Interrupt Handler + * + * Occurs under following conditions: + * - START condition detected + * - RESTART condition detected + * - STOP condition detected + * - NACK detected + * - AL (arbitration-lost) detected + * - TMO (timeout detection) + * + ****************************************************************************/ + +static int rx65n_riic_eei1interrupt(int irq, FAR void *context, \ + FAR void *arg) +{ + FAR struct rx65n_i2c_priv_s *priv = (struct rx65n_i2c_priv_s *)arg; + + /* Check Timeout Condition */ + + if ((0U != RIIC1.ICSR2.BIT.TMOF) && (0U != RIIC1.ICIER.BIT.TMOIE)) + { + RIIC1.ICIER.BIT.TMOIE = 0U; + while (0U != RIIC1.ICIER.BIT.TMOIE) + { + /* Wait for reset to complete */ + } + + priv->event = RIIC_EV_INT_TMO; + } + + /* Check Arbitration-Lost Condition */ + + if ((0U != RIIC1.ICSR2.BIT.AL) && (0U != RIIC1.ICIER.BIT.ALIE)) + { + RIIC1.ICIER.BIT.ALIE = 0U; + while (0U != RIIC1.ICIER.BIT.ALIE) + { + /* Do Nothing */ + } + + priv->event = RIIC_EV_INT_AL; + } + + /* Check Stop Condition */ + + if ((0U != RIIC1.ICSR2.BIT.STOP) && (0U != RIIC1.ICIER.BIT.SPIE)) + { + RIIC1.ICIER.BIT.SPIE = 0U; + RIIC1.ICMR3.BIT.RDRFS = 0U; + RIIC1.ICMR3.BIT.ACKWP = 1U; + RIIC1.ICMR3.BIT.ACKBT = 0U; + RIIC1.ICMR3.BIT.ACKWP = 0U; + + while ((0U != RIIC1.ICMR3.BIT.RDRFS) || \ + (0U != RIIC1.ICMR3.BIT.ACKBT)) + { + /* Do Nothing */ + } + + RIIC1.ICSR2.BIT.STOP = 0U; + while (0U != RIIC1.ICSR2.BIT.STOP) + { + /* Do Nothing */ + } + + priv->event = RIIC_EV_INT_STOP; + } + + /* Check NACK reception. */ + + if ((0U != RIIC1.ICSR2.BIT.NACKF) && (0U != RIIC1.ICIER.BIT.NAKIE)) + { + /* Prohibits NACK interrupt to generate stop condition. */ + + RIIC1.ICIER.BIT.NAKIE = 0U; + + /* Prohibits these interrupt. + * After NACK interrupt, these interrupts will occur + * when they do not stop the following interrupts. + */ + + RIIC1.ICIER.BIT.TEIE = 0U; + RIIC1.ICIER.BIT.TIE = 0U; + RIIC1.ICIER.BIT.RIE = 0U; + + while (((0U != RIIC1.ICIER.BIT.TEIE) || \ + (0U != RIIC1.ICIER.BIT.TIE)) || (0U != RIIC1.ICIER.BIT.RIE)) + { + /* Do Nothing */ + } + + if (0U == RIIC1.ICCR2.BIT.TRS) + { + IR(RIIC1, RXI1) = 0; + } + + priv->event = RIIC_EV_INT_NACK; + } + + /* Check Start condition detection. */ + + if ((0U != RIIC1.ICSR2.BIT.START) && (0U != RIIC1.ICIER.BIT.STIE)) + { + RIIC1.ICIER.BIT.STIE = 0U; + RIIC1.ICSR2.BIT.START = 0U; + while ((0U != RIIC1.ICSR2.BIT.START) || (0U != RIIC1.ICIER.BIT.STIE)) + { + /* Wait till reset is completed */ + } + + priv->event = RIIC_EV_INT_START; + } + + rx65n_riic_advance(priv); + return OK; +} + +/**************************************************************************** + * Name: rx65n_riic_eei2interrupt + * + * Description: + * Interrupt RIIC2 EEI2 handler – Event/Error Generation Interrupt Handler + * + * Occurs under following conditions: + * - START condition detected + * - RESTART condition detected + * - STOP condition detected + * - NACK detected + * - AL (arbitration-lost) detected + * - TMO (timeout detection) + * + ****************************************************************************/ + +static int rx65n_riic_eei2interrupt(int irq, FAR void *context, \ + FAR void *arg) +{ + FAR struct rx65n_i2c_priv_s *priv = (struct rx65n_i2c_priv_s *)arg; + + /* Check Timeout Condition */ + + if ((0U != RIIC2.ICSR2.BIT.TMOF) && (0U != RIIC2.ICIER.BIT.TMOIE)) + { + RIIC2.ICIER.BIT.TMOIE = 0U; + while (0U != RIIC2.ICIER.BIT.TMOIE) + { + /* Wait for reset to complete */ + } + + priv->event = RIIC_EV_INT_TMO; + } + + /* Check Arbitration-Lost Condition */ + + if ((0U != RIIC2.ICSR2.BIT.AL) && (0U != RIIC2.ICIER.BIT.ALIE)) + { + RIIC2.ICIER.BIT.ALIE = 0U; + while (0U != RIIC2.ICIER.BIT.ALIE) + { + /* Do Nothing */ + } + + priv->event = RIIC_EV_INT_AL; + } + + /* Check Stop Condition */ + + if ((0U != RIIC2.ICSR2.BIT.STOP) && (0U != RIIC2.ICIER.BIT.SPIE)) + { + RIIC2.ICIER.BIT.SPIE = 0U; + + RIIC2.ICMR3.BIT.RDRFS = 0U; + RIIC2.ICMR3.BIT.ACKWP = 1U; + RIIC2.ICMR3.BIT.ACKBT = 0U; + RIIC2.ICMR3.BIT.ACKWP = 0U; + + while ((0U != RIIC2.ICMR3.BIT.RDRFS) || \ + (0U != RIIC2.ICMR3.BIT.ACKBT)) + { + /* Do Nothing */ + } + + RIIC2.ICSR2.BIT.STOP = 0U; + while (0U != RIIC2.ICSR2.BIT.STOP) + { + /* Do Nothing */ + } + + priv->event = RIIC_EV_INT_STOP; + } + + /* Check NACK reception. */ + + if ((0U != RIIC2.ICSR2.BIT.NACKF) && (0U != RIIC2.ICIER.BIT.NAKIE)) + { + /* Prohibits NACK interrupt to generate stop condition. */ + + RIIC2.ICIER.BIT.NAKIE = 0U; + + /* Prohibits these interrupt. + * After NACK interrupt, these interrupts will occur + * when they do not stop the following interrupts. + */ + + RIIC2.ICIER.BIT.TEIE = 0U; + RIIC2.ICIER.BIT.TIE = 0U; + RIIC2.ICIER.BIT.RIE = 0U; + + while (((0U != RIIC2.ICIER.BIT.TEIE) || \ + (0U != RIIC2.ICIER.BIT.TIE)) || (0U != RIIC2.ICIER.BIT.RIE)) + { + /* Do Nothing */ + } + + if (0U == RIIC2.ICCR2.BIT.TRS) + { + IR(RIIC2, RXI2) = 0; + } + + priv->event = RIIC_EV_INT_NACK; + } + + /* Check Start condition detection. */ + + if ((0U != RIIC2.ICSR2.BIT.START) && (0U != RIIC2.ICIER.BIT.STIE)) + { + RIIC2.ICIER.BIT.STIE = 0U; + RIIC2.ICSR2.BIT.START = 0U; + while ((0U != RIIC2.ICSR2.BIT.START) || \ + (0U != RIIC2.ICIER.BIT.STIE)) + { + /* Wait till reset is completed */ + } + + priv->event = RIIC_EV_INT_START; + } + + rx65n_riic_advance(priv); + return OK; +} + +/**************************************************************************** + * Name: rx65n_i2c_transfer + * + * Description: + * This function initializes the RIIC channel + * + ****************************************************************************/ + +static int rx65n_i2c_transfer(FAR struct i2c_master_s *dev, \ + FAR struct i2c_msg_s *msgs, int count) +{ + FAR struct rx65n_i2c_priv_s *priv = (struct rx65n_i2c_priv_s *)dev; + int ret = 0; + + DEBUGASSERT(dev != NULL && msgs != NULL && count > 0); + + /* Get exclusive access to the I2C bus */ + + nxsem_wait(&priv->sem_excl); + + priv->mode = RIIC_READY; + priv->dev_sts = RIIC_STS_IDLE; + priv->event = RIIC_EV_NONE; + + priv->dcnt = 0; + priv->ptr = NULL; + + priv->msgv = msgs; + priv->msgc = count; + + priv->ptr = priv->msgv->buffer; + priv->dcnt = priv->msgv->length; + priv->flags = priv->msgv->flags; + + /* Set reference clock for I2C bus */ + + rx65n_riic_setclock(priv, msgs->frequency); + + if ((priv->flags == 0) || (priv->flags == I2C_M_NOSTOP) + || (priv->flags == I2C_M_TEN)) + { + /* MASTER TRANSMISSION MODE + * No communication is in progress + * Initiate START condition and proceed with transfer + */ + + if (priv->mode == RIIC_READY) + { + /* Device is ready for communication */ + + priv->event = RIIC_EV_GEN_START_COND; + ret = rx65n_riic_startcond(priv); + if (ret == RIIC_ERR_BUS_BUSY) + { + priv->mode = RIIC_NONE; + priv->dev_sts = RIIC_STS_NO_INIT; + priv->event = RIIC_EV_NONE; + + /* Disable interrupts */ + + rx65n_riic_int_disable(priv); + } + } + } + + else if (priv->flags == I2C_M_READ) + { + /* MASTER RECEPTION MODE + * No communication is in progress + * Initiate START condition and proceed with transfer + */ + + if (priv->mode == RIIC_READY) + { + /* Device is ready for communication */ + + priv->event = RIIC_EV_GEN_START_COND; + ret = rx65n_riic_startcond(priv); + if (ret == RIIC_ERR_BUS_BUSY) + { + priv->mode = RIIC_NONE; + priv->dev_sts = RIIC_STS_NO_INIT; + priv->event = RIIC_EV_NONE; + + /* Disable interrupts */ + + rx65n_riic_int_disable(priv); + } + } + } + + else if (priv->flags == I2C_M_NOSTART) + { + /* COMMUNICATION IS IN PROGRESS */ + + if (priv->mode == RIIC_M_TRANSMIT) + { + priv->ptr = priv->msgv->buffer; + priv->dcnt = priv->msgv->length; + rx65n_riic_master_transmit(priv); + } + + else if (priv->mode == RIIC_M_RECEIVE) + { + rx65n_riic_master_receive(priv); + } + } + + nxsem_post(&priv->sem_excl); + + while (RIIC_FINISH != priv->mode && RIIC_NONE != priv->mode); + + if (0 == priv->bus) + { + if (1U == RIIC0.ICSR2.BIT.NACKF) + { + ret = -ENXIO; + } + + else if ((1U == RIIC0.ICCR2.BIT.BBSY) || (RIIC_ERR_BUS_BUSY == ret)) + { + ret = -EBUSY; + } + + else + { + ret = RIIC_SUCCESS; + } + } + + else if (1 == priv->bus) + { + if (1U == RIIC1.ICSR2.BIT.NACKF) + { + ret = -ENXIO; + } + + else if ((1U == RIIC1.ICCR2.BIT.BBSY) || (RIIC_ERR_BUS_BUSY == ret)) + { + ret = -EBUSY; + } + + else + { + ret = RIIC_SUCCESS; + } + } + + else + { + if (1U == RIIC2.ICSR2.BIT.NACKF) + { + ret = -ENXIO; + } + + else if ((1U == RIIC2.ICCR2.BIT.BBSY) || (RIIC_ERR_BUS_BUSY == ret)) + { + ret = -EBUSY; + } + + else + { + ret = RIIC_SUCCESS; + } + } + + rx65n_riic_iicrst(priv); + return ret; +} + +/**************************************************************************** + * Name: rx65n_i2c_reset + * + * Description: + * Resets the RIIC channel + * + ****************************************************************************/ + +#ifdef CONFIG_I2C_RESET +static int rx65n_i2c_reset(FAR struct i2c_master_s *dev) +{ + FAR struct rx65n_i2c_priv_s *priv = (struct rx65n_i2c_priv_s *)dev; + uint8_t regval; + + DEBUGASSERT(dev); + + DEBUGASSERT(priv->refs > 0); + + nxsem_wait(&priv->sem_excl); + + if (priv->bus == 0) + { + regval = rx65n_getreg(RX65N_RIIC0_ICCR1); + regval |= RX65N_RIIC_ICCR1_IICRST_SET; /* ICCR1.IICRST bit to 1. */ + rx65n_putreg(regval, RX65N_RIIC0_ICCR1); + regval = rx65n_getreg(RX65N_RIIC0_ICCR1); + + regval = rx65n_getreg(RX65N_RIIC0_ICCR1); + regval &= ~(RX65N_RIIC_ICCR1_IICRST_SET); /* ICCR1.IICRST bit to 0. */ + rx65n_putreg(regval, RX65N_RIIC0_ICCR1); + regval = rx65n_getreg(RX65N_RIIC0_ICCR1); + } + + else if (priv->bus == 1) + { + regval = rx65n_getreg(RX65N_RIIC1_ICCR1); + regval |= RX65N_RIIC_ICCR1_IICRST_SET; /* ICCR1.IICRST bit to 1. */ + rx65n_putreg(regval, RX65N_RIIC1_ICCR1); + + regval = rx65n_getreg(RX65N_RIIC1_ICCR1); + regval &= ~(RX65N_RIIC_ICCR1_IICRST_SET); /* ICCR1.IICRST bit to 0. */ + rx65n_putreg(regval, RX65N_RIIC1_ICCR1); + } + + else + { + regval = rx65n_getreg(RX65N_RIIC2_ICCR1); + regval |= RX65N_RIIC_ICCR1_IICRST_SET; /* ICCR1.IICRST bit to 1. */ + rx65n_putreg(regval, RX65N_RIIC2_ICCR1); + + regval = rx65n_getreg(RX65N_RIIC2_ICCR1); + regval &= ~(RX65N_RIIC_ICCR1_IICRST_SET); /* ICCR1.IICRST bit to 0. */ + rx65n_putreg(regval, RX65N_RIIC2_ICCR1); + } + + nxsem_post(&priv->sem_excl); + return OK; +} +#endif /* CONFIG_I2C_RESET */ + +/**************************************************************************** + * Name: rx65n_i2cbus_initialize + * + * Description: + * This function initializes the RIIC channel + * + ****************************************************************************/ + +FAR struct i2c_master_s *rx65n_i2cbus_initialize(int channel) +{ + struct rx65n_i2c_priv_s * priv = NULL; + irqstate_t irqs; + + /* Get I2C private structure */ + + i2cinfo("RX65N RIIC Bus Initialization:\n"); + riic_mpc_enable(); + switch (channel) + { +#ifdef CONFIG_RX65N_RIIC0 + case 0: + riic0_init_port(); + i2cinfo("RX65N RIIC0 Channel Initial Setup\n"); + priv = (struct rx65n_i2c_priv_s *)&rx65n_riic0_priv; + break; +#endif +#ifdef CONFIG_RX65N_RIIC1 + case 1: + riic1_init_port(); + i2cinfo("RX65N RIIC1 Channel Initial Setup\n"); + priv = (struct rx65n_i2c_priv_s *)&rx65n_riic1_priv; + break; +#endif +#ifdef CONFIG_RX65N_RIIC2 + case 2: + riic2_init_port(); + i2cinfo("RX65N RIIC2 Channel Initial Setup\n"); + priv = (struct rx65n_i2c_priv_s *)&rx65n_riic2_priv; + break; +#endif + default: + i2cerr("Channel %d is not supported by RX65N\n", channel); + riic_mpc_disable(); + return NULL; + } + + /* Initialize private data for the first time, increment reference count, + * initialize RIIC registers and attach IRQs + */ + + irqs = enter_critical_section(); + + if ((volatile int)priv->refs++ == 0) + { + /* Initialize semaphores */ + + nxsem_init(&priv->sem_excl, 0, 1); + nxsem_init(&priv->sem_isr, 0, 0); + + /* Initialize the RIIC registers */ + + rx65n_riic_init(priv); + } + + leave_critical_section(irqs); + riic_mpc_disable(); + return (struct i2c_master_s *)priv; +} + +/**************************************************************************** + * Name: rx65n_i2cbus_uninitialize + * + * Description: + * Uninitialize an RIIC device + * + ****************************************************************************/ + +int rx65n_i2cbus_uninitialize(FAR struct i2c_master_s *dev) +{ + FAR struct rx65n_i2c_priv_s *priv = (struct rx65n_i2c_priv_s *)dev; + irqstate_t flags; + + DEBUGASSERT(dev); + + /* Decrement reference count and check for underflow */ + + if (priv->refs == 0) + { + return ERROR; + } + + flags = enter_critical_section(); + + if (--priv->refs) + { + leave_critical_section(flags); + return OK; + } + + leave_critical_section(flags); + + /* Disable power and other HW resource (GPIO's) */ + + rx65n_riic_int_disable(priv); + + irq_detach(priv->dev->txi_irq); + irq_detach(priv->dev->rxi_irq); + irq_detach(priv->dev->tei_irq); + irq_detach(priv->dev->eei_irq); + + /* Release unused resources */ + + nxsem_destroy(&priv->sem_excl); + nxsem_destroy(&priv->sem_isr); + + return OK; +} + +#endif /* CONFIG_RX65N_RIIC0 || CONFIG_RX65N_RIIC1 || CONFIG_RX65N_RIIC2 */ diff --git a/arch/renesas/src/rx65n/rx65n_riic.h b/arch/renesas/src/rx65n/rx65n_riic.h new file mode 100644 index 00000000000..a3dde05fa57 --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_riic.h @@ -0,0 +1,95 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_riic.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RENESAS_SRC_RX65N_RX65N_RIIC_H +#define __ARCH_RENESAS_SRC_RX65N_RX65N_RIIC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SCL_RISE_TIME_FASTPLUS 120E-9 +#define SCL_FALL_TIME_FASTPLUS 120E-9 +#define SCL_RISE_TIME_FAST 300E-9 +#define SCL_FALL_TIME_FAST 300E-9 +#define SCL_RISE_TIME_STANDARD 1000E-9 +#define SCL_FALL_TIME_STANDARD 300E-9 +#define RIIC_MAX_DIV 0x08 +#define RIIC_CALC_MAX 32 +#define RIIC_INTERRUPT_PRIO (0x0f) +#define RIIC_RATE_CALC (0xff) + +#define RIIC_SUCCESS 0 /* Successful operation */ +#define RIIC_ERR_NO_INIT 1 /* Uninitialized state */ +#define RIIC_ERR_BUS_BUSY 2 /* Channel is on communication. */ +#define RIIC_ERR_AL 3 /* Arbitration lost error */ +#define RIIC_ERR_TMO 4 /* Time Out error */ +#define RIIC_ERR_NACK 5 /* NACK reception */ +#define RIIC_ERR_OTHER 6 /* Other error */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: rx65n_i2cbus_initialize + * + * Description: + * Initialize the selected RIIC channel. And return a unique instance of + * struct i2c_master_s. This function may be called to obtain multiple + * instances of the interface, each of which may be set up with a + * different frequency and slave address. + * + * Input Parameters: + * Port number (for hardware that has multiple I2C interfaces) + * + * Returned Value: + * Valid I2C device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +FAR struct i2c_master_s *rx65n_i2cbus_initialize(int channel); + +/**************************************************************************** + * Name: rx65n_i2cbus_uninitialize + * + * Description: + * De-initialize the selected I2C port, and power down the device. + * + * Input Parameters: + * Device structure as returned by the rx65n_i2cbus_initialize() + * + * Returned Value: + * OK on success, ERROR when internal reference count mismatch or dev + * points to invalid hardware device. + * + ****************************************************************************/ + +int rx65n_i2cbus_uninitialize(FAR struct i2c_master_s *dev); + +#endif /* __ARCH_RENESAS_SRC_RX65N_RX65N_RIIC_H */ \ No newline at end of file diff --git a/arch/renesas/src/rx65n/rx65n_serial.c b/arch/renesas/src/rx65n/rx65n_serial.c index 21ed15650e9..57d6b951ca5 100644 --- a/arch/renesas/src/rx65n/rx65n_serial.c +++ b/arch/renesas/src/rx65n/rx65n_serial.c @@ -37,13 +37,13 @@ #include #include #include "rx65n_macrodriver.h" -#include "rx65n/iodefine.h" +#include "arch/rx65n/iodefine.h" #include "chip.h" #include "up_arch.h" #include "up_internal.h" #include "rx65n_definitions.h" #include "rx65n_sci.h" -#include "rx65n/irq.h" +#include "arch/rx65n/irq.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/renesas/src/rx65n/rx65n_timerisr.c b/arch/renesas/src/rx65n/rx65n_timerisr.c index dfc2ad4993b..6234c6e1840 100644 --- a/arch/renesas/src/rx65n/rx65n_timerisr.c +++ b/arch/renesas/src/rx65n/rx65n_timerisr.c @@ -30,11 +30,11 @@ #include #include #include -#include "rx65n/irq.h" +#include "arch/rx65n/irq.h" #include "clock/clock.h" #include "up_internal.h" #include "up_arch.h" -#include "rx65n/iodefine.h" +#include "arch/rx65n/iodefine.h" #include "chip.h" #include "rx65n_cmt.h" diff --git a/arch/renesas/src/rx65n/rx65n_vector.S b/arch/renesas/src/rx65n/rx65n_vector.S index 7ca80e6924a..75ea3bb58d8 100644 --- a/arch/renesas/src/rx65n/rx65n_vector.S +++ b/arch/renesas/src/rx65n/rx65n_vector.S @@ -1,36 +1,20 @@ /**************************************************************************** * arch/renesas/src/rx65n/rx65n_vector.S * - * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. - * Author: Anjana - * Surya + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -42,7 +26,7 @@ #include /* Board-specific settings */ #include /* IRQ definitions */ #include "up_internal.h" -#include "rx65n/iodefine.h" +#include "arch/rx65n/iodefine.h" #include "rx65n_definitions.h" /**************************************************************************** @@ -564,6 +548,21 @@ _uprx65_groupbl1_handler: multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 27, RX65N_ERI9_IRQ #endif /* CONFIG_RX65N_SCI9 */ +#ifdef CONFIG_RX65N_RIIC0 + multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 13, RX65N_RIIC0_TEI0_IRQ + multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 14, RX65N_RIIC0_EEI0_IRQ +#endif /* CONFIG_RX65N_RIIC0 */ + +#ifdef CONFIG_RX65N_RIIC2 + multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 15, RX65N_RIIC2_TEI2_IRQ + multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 16, RX65N_RIIC2_EEI2_IRQ +#endif /* CONFIG_RX65N_RIIC2 */ + +#ifdef CONFIG_RX65N_RIIC1 + multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 28, RX65N_RIIC1_TEI1_IRQ + multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 29, RX65N_RIIC1_EEI1_IRQ +#endif /* CONFIG_RX65N_RIIC1 */ + /* TODO: Please write the others with * definition RX65N_XXX_IRQ in irq.h as IRQ number */ diff --git a/boards/renesas/rx65n/rx65n-grrose/include/rx65n_gpio.h b/boards/renesas/rx65n/rx65n-grrose/include/rx65n_gpio.h index f2adfba3d49..b5690540b70 100644 --- a/boards/renesas/rx65n/rx65n-grrose/include/rx65n_gpio.h +++ b/boards/renesas/rx65n/rx65n-grrose/include/rx65n_gpio.h @@ -228,5 +228,58 @@ void sci6_init_port(void); #ifdef CONFIG_RX65N_SCI8 void sci8_init_port(void); #endif +/**************************************************************************** + * Name: riic0_init_port + * + * Description: + * RIIC0 Initialization RX65N GRROSE + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_RX65N_RIIC0 +void riic0_init_port(void); +#endif + +/**************************************************************************** + * Name: riic1_init_port + * + * Description: + * RIIC1 Initialization RX65N GRROSE + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_RX65N_RIIC1 +void riic1_init_port(void); +#endif + +/**************************************************************************** + * Name: riic2_init_port + * + * Description: + * RIIC2 Initialization RX65N GRROSE + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_RX65N_RIIC2 +void riic2_init_port(void); +#endif #endif /* __BOARDS_RENESAS_RX65N_RX65N_GRROSE_INCLUDE_RX65N_GPIO_H */ diff --git a/boards/renesas/rx65n/rx65n-grrose/src/rx65n_bringup.c b/boards/renesas/rx65n/rx65n-grrose/src/rx65n_bringup.c index c83b3487a28..c756b9d04f0 100644 --- a/boards/renesas/rx65n/rx65n-grrose/src/rx65n_bringup.c +++ b/boards/renesas/rx65n/rx65n-grrose/src/rx65n_bringup.c @@ -43,6 +43,10 @@ # include "rx65n_rtc.h" #endif +#ifdef HAVE_RIIC_DRIVER +# include +# include "rx65n_riic.h" +#endif /**************************************************************************** * Public Functions ****************************************************************************/ @@ -129,6 +133,41 @@ int rx65n_bringup(void) /* Initialize battery-backed RAM */ (void)rx65n_sbram_int(); +#endif +#ifdef HAVE_RIIC_DRIVER + FAR struct i2c_master_s *i2c; + + /* Get the I2C lower half instance */ +#ifdef CONFIG_RX65N_RIIC0 +#ifdef CONFIG_RX65N_SCI2 + i2cerr("Port is initialized for RIIC0. SCI2 cannot be used\n"); +#endif + riic0_init_port(); + i2c = rx65n_i2cbus_initialize(0); + if (i2c == NULL) + { + i2cerr("ERROR: Initialization of RIIC Channel 0 failed: %d\n", ret); + } + + else + { + /* Register the I2C character driver */ + + ret = i2c_register(i2c, 0); + if (ret < 0) + { + i2cerr("ERROR: Failed to register RIIC device: %d\n", ret); + } + } + +#endif +#ifdef CONFIG_RX65N_RIIC1 + i2cerr("RIIC1 setting is not supported on GR-ROSE Board\n"); +#endif +#ifdef CONFIG_RX65N_RIIC2 + i2cerr("RIIC2 setting is not supported on GR-ROSE Board\n"); + i2cerr("It is used for USB port and cannot be configured\n"); +#endif #endif return OK; } diff --git a/boards/renesas/rx65n/rx65n-grrose/src/rx65n_gpio.c b/boards/renesas/rx65n/rx65n-grrose/src/rx65n_gpio.c index c2ecf76cfc8..ef81b5926f8 100644 --- a/boards/renesas/rx65n/rx65n-grrose/src/rx65n_gpio.c +++ b/boards/renesas/rx65n/rx65n-grrose/src/rx65n_gpio.c @@ -158,23 +158,6 @@ void r_ether_pheriperal_enable(void) MPC.PA6PFS.BYTE = 0x12u; PORTA.PMR.BIT.B6 = 1u; - - /* Set VBUS pin for USB */ - - /* Referred from r_usb_basic_pinset.c */ - - MPC.P16PFS.BYTE = 0x12u; - - /* PORT1.PMR.BYTE |= 0x40; */ - - PORT1.PMR.BIT.B6 = 1u; - - /* Set USB0_OVRCURA pin */ - - /* GR Rose does not contain any of OVRCURA/B inputs - * MPC.P14PFS.BYTE = 0x12u; - * PORT1.PMR.BIT.B4 = 1u; - */ } #endif @@ -355,4 +338,70 @@ inline void sci8_init_port(void) PORTC.PMR.BIT.B7 = 1u; } #endif + +/**************************************************************************** + * Name: riic0_init_port + * + * Description: + * RIIC0 Initialization RX65N GRROSE + ****************************************************************************/ + +#ifdef CONFIG_RX65N_RIIC0 +inline void riic0_init_port(void) +{ + /* Set SCL0 pin (P12) */ + + MPC.P12PFS.BYTE = 0x0fu; + PORT1.PMR.BIT.B2 = 1u; + + /* Set SDA0 pin (P13) */ + + MPC.P13PFS.BYTE = 0x0fu; + PORT1.PMR.BIT.B3 = 1u; +} +#endif + +/**************************************************************************** + * Name: riic1_init_port + * + * Description: + * RIIC1 Initialization RX65N RSK2MB + ****************************************************************************/ + +#ifdef CONFIG_RX65N_RIIC1 +inline void riic1_init_port(void) +{ + /* Set SCL0 pin (P21) */ + + MPC.P21PFS.BYTE = 0x0fu; + PORT2.PMR.BIT.B1 = 1u; + + /* Set SDA0 pin (P20) */ + + MPC.P20PFS.BYTE = 0x0fu; + PORT2.PMR.BIT.BT0 = 1u; +} +#endif + +/**************************************************************************** + * Name: riic2_init_port + * + * Description: + * RIIC2 Initialization RX65N RSK2MB + ****************************************************************************/ + +#ifdef CONFIG_RX65N_RIIC2 +inline void riic2_init_port(void) +{ + /* Set SCL0 pin (P16) */ + + MPC.P16PFS.BYTE = 0x0fu; + PORT1.PMR.BIT.B6 = 1u; + + /* Set SDA0 pin (P17) */ + + MPC.P17PFS.BYTE = 0x0fu; + PORT1.PMR.BIT.B7 = 1u; +} +#endif #endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */ \ No newline at end of file diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/include/rx65n_gpio.h b/boards/renesas/rx65n/rx65n-rsk2mb/include/rx65n_gpio.h index b81f30471f8..16b336e3b0e 100644 --- a/boards/renesas/rx65n/rx65n-rsk2mb/include/rx65n_gpio.h +++ b/boards/renesas/rx65n/rx65n-rsk2mb/include/rx65n_gpio.h @@ -174,4 +174,43 @@ void sci8_init_port(void); #ifdef CONFIG_RX65N_SCI12 void sci12_init_port(void); #endif +/**************************************************************************** + * Name: riic0_init_port + * + * Description: + * RIIC0 Initialization RX65N RSK2MB + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_RX65N_RIIC0 +void riic0_init_port(void); +#endif + +/**************************************************************************** + * Name: riic1_init_port + * + * Description: + * RIIC1 Initialization RX65N RSK2MB + ****************************************************************************/ + +#ifdef CONFIG_RX65N_RIIC1 +void riic1_init_port(void); +#endif + +/**************************************************************************** + * Name: riic2_init_port + * + * Description: + * RIIC2 Initialization RX65N RSK2MB + ****************************************************************************/ + +#ifdef CONFIG_RX65N_RIIC2 +void riic2_init_port(void); +#endif #endif /* __BOARDS_RENESAS_RX65N_RX65N_RSK2MB_INCLUDE_RX65N_GPIO_H */ \ No newline at end of file diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_bringup.c b/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_bringup.c index 1a0a3536280..7a566515750 100644 --- a/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_bringup.c +++ b/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_bringup.c @@ -43,6 +43,10 @@ # include "rx65n_rtc.h" #endif +#ifdef HAVE_RIIC_DRIVER +# include +# include "rx65n_riic.h" +#endif /**************************************************************************** * Public Functions ****************************************************************************/ @@ -129,6 +133,52 @@ int rx65n_bringup(void) /* Initialize standby RAM */ (void)rx65n_sbram_int(); +#endif +#ifdef HAVE_RIIC_DRIVER + FAR struct i2c_master_s *i2c; + + /* Get the I2C lower half instance */ + +#ifdef CONFIG_RX65N_RIIC0 + i2c = rx65n_i2cbus_initialize(0); + if (i2c == NULL) + { + i2cerr("ERROR: Initialization of RIIC Channel 0 failed: %d\n", ret); + } + else + { + /* Register the I2C character driver */ + + ret = i2c_register(i2c, 0); + if (ret < 0) + { + i2cerr("ERROR: Failed to register RIIC device: %d\n", ret); + } + } + +#endif +#ifdef CONFIG_RX65N_RIIC1 + i2c = rx65n_i2cbus_initialize(1); + if (i2c == NULL) + { + i2cerr("ERROR: Initialization of RIIC Channel 1 failed: %d\n", ret); + } + else + { + /* Register the I2C character driver */ + + ret = i2c_register(i2c, 1); + if (ret < 0) + { + i2cerr("ERROR: Failed to register RIIC device: %d\n", ret); + } + } + +#endif +#ifdef CONFIG_RX65N_RIIC2 + i2cerr("RIIC2 setting is not supported on RSK-2MB Board\n"); + i2cerr("It is used for USB port and cannot be configured\n"); +#endif #endif return OK; } diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_gpio.c b/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_gpio.c index 36c03fdb447..c9d35ffbdb1 100644 --- a/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_gpio.c +++ b/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_gpio.c @@ -196,21 +196,6 @@ void r_ether_pheriperal_enable(void) MPC.P34PFS.BYTE = 0x11u; PORT3.PMR.BIT.B4 = 1u; - - /* Set VBUS pin for USB */ - - /* Referred from r_usb_basic_pinset.c */ - - MPC.P16PFS.BYTE = 0x12u; - - /* PORT1.PMR.BYTE |= 0x40; */ - - PORT1.PMR.BIT.B6 = 1u; - - /* Set USB0_OVRCURA pin */ - - MPC.P14PFS.BYTE = 0x12u; - PORT1.PMR.BIT.B4 = 1u; } #endif @@ -318,4 +303,70 @@ inline void sci12_init_port(void) */ } #endif + +/**************************************************************************** + * Name: riic0_init_port + * + * Description: + * RIIC0 Initialization RX65N RSK2MB + ****************************************************************************/ + +#ifdef CONFIG_RX65N_RIIC0 +inline void riic0_init_port(void) +{ + /* Set SCL0 pin (P12) */ + + MPC.P12PFS.BYTE = 0x0fu; + PORT1.PMR.BIT.B2 = 1u; + + /* Set SDA0 pin (P13) */ + + MPC.P13PFS.BYTE = 0x0fu; + PORT1.PMR.BIT.B3 = 1u; +} +#endif + +/**************************************************************************** + * Name: riic1_init_port + * + * Description: + * RIIC1 Initialization RX65N RSK2MB + ****************************************************************************/ + +#ifdef CONFIG_RX65N_RIIC1 +inline void riic1_init_port(void) +{ + /* Set SCL0 pin (P21) */ + + MPC.P21PFS.BYTE = 0x0fu; + PORT2.PMR.BIT.B1 = 1u; + + /* Set SDA0 pin (P20) */ + + MPC.P20PFS.BYTE = 0x0fu; + PORT2.PMR.BIT.BT0 = 1u; +} +#endif + +/**************************************************************************** + * Name: riic2_init_port + * + * Description: + * RIIC2 Initialization RX65N RSK2MB + ****************************************************************************/ + +#ifdef CONFIG_RX65N_RIIC2 +inline void riic2_init_port(void) +{ + /* Set SCL0 pin (P16) */ + + MPC.P16PFS.BYTE = 0x0fu; + PORT1.PMR.BIT.B6 = 1u; + + /* Set SDA0 pin (P17) */ + + MPC.P17PFS.BYTE = 0x0fu; + PORT1.PMR.BIT.B7 = 1u; +} +#endif #endif /* CONFIG_ARCH_BOARD_RX65N_RSK2MB */ \ No newline at end of file