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esp32: enable APP_CPU cache earlier

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NuttX uses PSRAM, possibly using the APP_CPU cache MMU,
way before starting the APP_CPU in up_cpu_start().
Flushing the cache when launching the APP_CPU can cause
data corruptions on PSRAM.
Eg. mm_heap structures if the PSRAM is added to a heap.
This commit is contained in:
YAMAMOTO Takashi 2024-08-30 17:45:03 +09:00 • committed by Xiang Xiao
parent ebbd585f97
commit e8b1876f99
2 changed files with 9 additions and 7 deletions
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7
arch/xtensa/src/esp32/esp32_cpustart.c
View file

@ -57,8 +57,6 @@ static volatile spinlock_t g_appcpu_interlock;
* ROM function prototypes
****************************************************************************/
extern void cache_flush(int cpu);
extern void cache_read_enable(int cpu);
extern void ets_set_appcpu_boot_addr(uint32_t start);
/****************************************************************************
@ -245,11 +243,6 @@ int up_cpu_start(int cpu)
spin_initialize(&g_appcpu_interlock, SP_LOCKED);
/* Flush and enable I-cache for APP CPU */
cache_flush(cpu);
cache_read_enable(cpu);
/* Unstall the APP CPU */
regval = getreg32(RTC_CNTL_SW_CPU_STALL_REG);

9
arch/xtensa/src/esp32/esp32_spiram.c
View file

@ -68,6 +68,13 @@
# error "FLASH speed can only be equal to or higher than SRAM speed while SRAM is enabled!"
#endif
/****************************************************************************
* ROM Function Prototypes
****************************************************************************/
extern void cache_flush(int cpu);
extern void cache_read_enable(int cpu);
/****************************************************************************
* Private Data
****************************************************************************/
@ -238,6 +245,8 @@ void IRAM_ATTR esp_spiram_init_cache(void)
/* Flush and enable icache for APP CPU */
#ifdef CONFIG_SMP
cache_flush(APP_CPU_NUM);
cache_read_enable(APP_CPU_NUM);
regval = getreg32(DPORT_APP_CACHE_CTRL1_REG);
regval &= ~(1 << DPORT_APP_CACHE_MASK_DRAM1);
putreg32(regval, DPORT_APP_CACHE_CTRL1_REG);