From e8b1876f998c8709baff2df83a69a983b2b1a41f Mon Sep 17 00:00:00 2001 From: YAMAMOTO Takashi Date: Fri, 30 Aug 2024 17:45:03 +0900 Subject: [PATCH] esp32: enable APP_CPU cache earlier NuttX uses PSRAM, possibly using the APP_CPU cache MMU, way before starting the APP_CPU in up_cpu_start(). Flushing the cache when launching the APP_CPU can cause data corruptions on PSRAM. Eg. mm_heap structures if the PSRAM is added to a heap. --- arch/xtensa/src/esp32/esp32_cpustart.c | 7 ------- arch/xtensa/src/esp32/esp32_spiram.c | 9 +++++++++ 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c index 42fcf62acb7..ac168d821f3 100644 --- a/arch/xtensa/src/esp32/esp32_cpustart.c +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -57,8 +57,6 @@ static volatile spinlock_t g_appcpu_interlock; * ROM function prototypes ****************************************************************************/ -extern void cache_flush(int cpu); -extern void cache_read_enable(int cpu); extern void ets_set_appcpu_boot_addr(uint32_t start); /**************************************************************************** @@ -245,11 +243,6 @@ int up_cpu_start(int cpu) spin_initialize(&g_appcpu_interlock, SP_LOCKED); - /* Flush and enable I-cache for APP CPU */ - - cache_flush(cpu); - cache_read_enable(cpu); - /* Unstall the APP CPU */ regval = getreg32(RTC_CNTL_SW_CPU_STALL_REG); diff --git a/arch/xtensa/src/esp32/esp32_spiram.c b/arch/xtensa/src/esp32/esp32_spiram.c index 942b414c113..8eeb80b8c9e 100644 --- a/arch/xtensa/src/esp32/esp32_spiram.c +++ b/arch/xtensa/src/esp32/esp32_spiram.c @@ -68,6 +68,13 @@ # error "FLASH speed can only be equal to or higher than SRAM speed while SRAM is enabled!" #endif +/**************************************************************************** + * ROM Function Prototypes + ****************************************************************************/ + +extern void cache_flush(int cpu); +extern void cache_read_enable(int cpu); + /**************************************************************************** * Private Data ****************************************************************************/ @@ -238,6 +245,8 @@ void IRAM_ATTR esp_spiram_init_cache(void) /* Flush and enable icache for APP CPU */ #ifdef CONFIG_SMP + cache_flush(APP_CPU_NUM); + cache_read_enable(APP_CPU_NUM); regval = getreg32(DPORT_APP_CACHE_CTRL1_REG); regval &= ~(1 << DPORT_APP_CACHE_MASK_DRAM1); putreg32(regval, DPORT_APP_CACHE_CTRL1_REG);