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arch/arm/stm32h7: timestamp the received PTP frames.
Add STM32_ETH_TIMESTAMP_RX for the STM32H7, as the one of the legacy STM32 that provides the timestamp of the frames received. Timestamp the PTP version 2 messages, over Ethernet and over UDP, except for the announce, management and signaling messages. The MAC writes the timestamp in a context descriptor after the last descriptor of the frame. The driver reads it before giving the frame to the network stack and passes it in d_rxtime, in the time of the system time of the MAC, the same as /dev/ptp0. A frame that is not timestamped has a time of zero. The timestamp goes over the address of the buffer of the context descriptor, and the code that dropped the context descriptors used a pointer that was never set. Keep the address of the buffer of each RX descriptor, and restore it when a context descriptor is given back. The timestamps of the PTP frames of a grandmaster clock were checked on hardware against the system time of the MAC, and were within the delay of the reads. Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com> Assisted-by: Claude:claude-sonnet-5
This commit is contained in:
Daniel P. Carvalho
Xiang Xiao
parent
4e6b805a0d
commit
e3dfc9875d
3 changed files with 166 additions and 3 deletions
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@ -187,7 +187,7 @@ config STM32_ETH_PTP_RTC_HIRES
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config STM32_ETH_TIMESTAMP_RX
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bool "Hardware timestamping of received packets"
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depends on STM32_COMMON_LEGACY && STM32_ETH_PTP && NET_TIMESTAMP && STM32_ETH_ENHANCEDDESC
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depends on STM32_ETH_PTP && NET_TIMESTAMP && (STM32_COMMON_H7_H5 || (STM32_COMMON_LEGACY && STM32_ETH_ENHANCEDDESC))
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default n
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---help---
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Timestamp all received Ethernet packets.
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@ -363,6 +363,7 @@
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#define ETH_MACTSCR_TSMSTRENA (1 << 15) /* Bit 15: Enable snapshot for messages relevant to master */
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#define ETH_MACTSCR_SNAPTYPSEL_SHIFT (16) /* Bits 16-17: Select PTP packets for taking snapshots */
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#define ETH_MACTSCR_SNAPTYPSEL_MASK (0x3 << ETH_MACTSCR_SNAPTYPSEL_SHIFT)
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# define ETH_MACTSCR_SNAPTYPSEL_1 (1 << ETH_MACTSCR_SNAPTYPSEL_SHIFT)
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#define ETH_MACTSCR_TSENMACADDR (1 << 18) /* Bit 18: Enable MAC address for PTP packet filtering */
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#define ETH_MACTSCR_CSC (1 << 19) /* Bit 19: Checksum correction for PTP over UDP/IPv4 (one-step) */
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#define ETH_MACTSCR_TXTSSTSM (1 << 24) /* Bit 24: Transmit timestamp status mode */
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@ -275,6 +275,15 @@
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# define STM32_PTP_UPDATE_USTIMEOUT (1000)
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# ifdef CONFIG_STM32_ETH_TIMESTAMP_RX
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/* Time to wait for the DMA to write the context descriptor that follows
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* the last descriptor of a timestamped frame, in microseconds.
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*/
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# define STM32_PTP_CTX_USTIMEOUT (10)
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# endif
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/* The addend can be trimmed by up to 50% each way from its nominal value,
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* in parts per billion.
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*/
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@ -756,6 +765,8 @@ struct stm32_ethmac_s
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struct eth_desc_s *txchbase; /* TX descriptor ring base address */
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struct eth_desc_s *rxchbase; /* RX descriptor ring base address */
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uint32_t rxbuf[CONFIG_STM32_ETH_NRXDESC]; /* Buffer of each RX descriptor */
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struct eth_desc_s *txtail; /* First "in_flight" TX descriptor */
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struct eth_desc_s *rxcurr; /* First RX descriptor of the segment */
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uint16_t segments; /* RX segment count */
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@ -1762,6 +1773,124 @@ static void stm32_freesegment(struct stm32_ethmac_s *priv,
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}
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}
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/****************************************************************************
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* Function: stm32_rxindex
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*
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* Description:
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* Get the position of an RX descriptor in the ring. The descriptors of
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* the ring are the size of the union that also holds a TX descriptor,
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* not of struct eth_desc_s.
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*
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****************************************************************************/
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static inline int stm32_rxindex(struct stm32_ethmac_s *priv,
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struct eth_desc_s *rxdesc)
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{
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return (union stm32_desc_u *)rxdesc - (union stm32_desc_u *)priv->rxchbase;
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}
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/****************************************************************************
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* Function: stm32_freectxdesc
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*
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* Description:
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* Give a context descriptor back to the DMA. The DMA writes the
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* timestamp over the buffer address, so the address is restored from the
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* copy that the driver keeps.
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*
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* Parameters:
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* priv - Reference to the driver state structure
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* ctxdesc - The context descriptor
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*
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* Assumptions:
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* Global interrupts are disabled by interrupt handling logic.
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*
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****************************************************************************/
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static void stm32_freectxdesc(struct stm32_ethmac_s *priv,
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struct eth_desc_s *ctxdesc)
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{
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ctxdesc->des0 = priv->rxbuf[stm32_rxindex(priv, ctxdesc)];
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ctxdesc->des1 = 0;
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ctxdesc->des2 = 0;
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stm32_freesegment(priv, ctxdesc, 1);
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}
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#ifdef CONFIG_STM32_ETH_TIMESTAMP_RX
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/****************************************************************************
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* Function: stm32_rxtimestamp
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*
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* Description:
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* Get the hardware timestamp of a received frame, and put it in d_rxtime.
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* The timestamp is in the context descriptor that the DMA writes right
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* after the last descriptor of the frame. A frame without a timestamp
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* gets a time of zero.
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*
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* Parameters:
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* priv - Reference to the driver state structure
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* last - The last descriptor of the frame
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*
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* Returned Value:
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* The context descriptor, that the caller has to give back to the DMA
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* after the frame, or NULL if the frame has none. A context descriptor
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* that the DMA does not write in time is found later by the scan of the
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* descriptors, and dropped.
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*
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* Assumptions:
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* Global interrupts are disabled by interrupt handling logic.
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*
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****************************************************************************/
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static struct eth_desc_s *stm32_rxtimestamp(struct stm32_ethmac_s *priv,
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struct eth_desc_s *last)
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{
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struct net_driver_s *dev = &priv->dev;
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struct eth_desc_s *ctxdesc;
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int i;
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dev->d_rxtime.tv_sec = 0;
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dev->d_rxtime.tv_nsec = 0;
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if ((last->des3 & ETH_RDES3_WB_RS1V) == 0 ||
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(last->des1 & ETH_RDES1_WB_TSA) == 0)
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{
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return NULL;
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}
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ctxdesc = stm32_get_next_rxdesc(priv, last);
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for (i = 0; i < STM32_PTP_CTX_USTIMEOUT; i++)
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{
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up_invalidate_dcache((uintptr_t)ctxdesc,
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(uintptr_t)ctxdesc + sizeof(struct eth_desc_s));
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if ((ctxdesc->des3 & ETH_RDES3_WB_OWN) == 0)
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{
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break;
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}
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up_udelay(1);
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}
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if ((ctxdesc->des3 & ETH_RDES3_WB_OWN) != 0 ||
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(ctxdesc->des3 & ETH_RDES3_WB_CTXT) == 0)
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{
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return NULL;
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}
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/* The nanoseconds are in the first word and the seconds in the second,
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* and all ones is a timestamp that is not valid.
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*/
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if (ctxdesc->des0 != UINT32_MAX || ctxdesc->des1 != UINT32_MAX)
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{
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dev->d_rxtime.tv_sec = ctxdesc->des1;
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dev->d_rxtime.tv_nsec = ctxdesc->des0;
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}
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return ctxdesc;
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}
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#endif /* CONFIG_STM32_ETH_TIMESTAMP_RX */
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/****************************************************************************
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* Function: stm32_recvframe
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*
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@ -1787,6 +1916,9 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
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{
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struct eth_desc_s *rxdesc;
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struct eth_desc_s *rxcurr = NULL;
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#ifdef CONFIG_STM32_ETH_TIMESTAMP_RX
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struct eth_desc_s *ctxdesc;
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#endif
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uint8_t *buffer;
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int i;
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@ -1910,6 +2042,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
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DEBUGASSERT(dev->d_buf == NULL);
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dev->d_buf = (uint8_t *)rxcurr->des0;
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rxcurr->des0 = (uint32_t)buffer;
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priv->rxbuf[stm32_rxindex(priv, rxcurr)] =
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(uint32_t)buffer;
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/* Make sure that the modified RX descriptor is written
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* to physical memory.
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@ -1924,8 +2058,22 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
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*/
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priv->rxhead = stm32_get_next_rxdesc(priv, rxdesc);
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#ifdef CONFIG_STM32_ETH_TIMESTAMP_RX
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ctxdesc = stm32_rxtimestamp(priv, rxdesc);
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#endif
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stm32_freesegment(priv, rxcurr, priv->segments);
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#ifdef CONFIG_STM32_ETH_TIMESTAMP_RX
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if (ctxdesc != NULL)
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{
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priv->rxhead =
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stm32_get_next_rxdesc(priv, ctxdesc);
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stm32_freectxdesc(priv, ctxdesc);
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}
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#endif
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/* Force the completed RX DMA buffer to be re-read from
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* physical memory.
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*/
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@ -1960,8 +2108,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
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{
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/* Drop the context descriptors, we are not interested */
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DEBUGASSERT(rxcurr != NULL);
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stm32_freesegment(priv, rxcurr, 1);
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stm32_freectxdesc(priv, rxdesc);
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}
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/* Try the next descriptor */
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@ -3053,6 +3200,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv,
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/* Set Buffer1 address pointer */
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rxdesc->des0 = (uint32_t)&rxbuffer[i * ALIGNED_BUFSIZE];
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priv->rxbuf[i] = rxdesc->des0;
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/* Set Buffer1 address high bytes */
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@ -4044,6 +4192,16 @@ static int stm32_eth_ptp_init(void)
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*/
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tscr = ETH_MACTSCR_TSENA | ETH_MACTSCR_TSCFUPDT | ETH_MACTSCR_TSCTRLSSR;
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#ifdef CONFIG_STM32_ETH_TIMESTAMP_RX
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/* Timestamp the received PTP version 2 messages, over Ethernet and over
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* UDP, except for the announce, management and signaling messages.
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*/
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tscr |= ETH_MACTSCR_TSVER2ENA | ETH_MACTSCR_TSIPENA |
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ETH_MACTSCR_TSIPV4ENA | ETH_MACTSCR_TSIPV6ENA |
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ETH_MACTSCR_SNAPTYPSEL_1;
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#endif
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stm32_putreg(tscr, STM32_ETH_MACTSCR);
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/* Set the increment of the system time */
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@ -4831,6 +4989,10 @@ static inline int stm32_ethinitialize(int intf)
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stm32_ifdown(&priv->dev);
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#ifdef CONFIG_STM32_ETH_TIMESTAMP_RX
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priv->dev.d_features |= NETDEV_RX_STAMP;
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#endif
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/* Register the device with the OS so that socket IOCTLs can be performed */
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netdev_register(&priv->dev, NET_LL_ETHERNET);
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