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ARMv7-R: Add a configuration to support delayed memory initialization. This logic was already in place for SDRAM but is also required for some ECC memories as well.
This commit is contained in:
Gregory Nutt
parent
9364824a53
commit
c251fd7756
5 changed files with 39 additions and 20 deletions
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@ -5,6 +5,20 @@
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comment "ARMv7-A Configuration Options"
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config ARMV7R_MEMINIT
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bool
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default y if CONFIG_BOOT_SDRAM_DATA
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default n if !CONFIG_BOOT_SDRAM_DATA
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---help---
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If this configuration *not* selected, then it is assumed that all
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memory resources are initialized via arm_data_initialize() and
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available at power-up reset time. Other memories, such as SDRAM or
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some ECC SRAM memories, require some platform-specific
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initialization first. In that case, this option should be selected
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and the platform-specific implementation of arm_boot() must perform
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the memory initialization first, then explicitly call
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arm_data_initialize().
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config ARMV7R_HAVE_L2CC
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bool
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default n
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@ -115,9 +115,10 @@ extern "C"
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* Description:
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* Clear all of .bss to zero; set .data to the correct initial values.
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* This function is called automatically from ARMv7-R boot code *UNLESS*
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* executing from FLASH or SRAM with data is SDRAM (CONFIG_BOOT_SDRAM_DATA=y).
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* In that case, early board-specific logic must first initialize SDRAM
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* then call this function.
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* executing with data in some memory that requires platform-specific
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* initialization (such as SDRAM). That latter case is indicated with
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* CONFIG_ARMV7R_MEMINIT=y. In that case, early platform-specific logic
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* must first initialize then memory then call this function.
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*
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* Input Parameters:
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* None
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@ -319,19 +319,19 @@ __start:
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mcr CP15_ACTLR(r0) /* Write Auxiliary Control register */
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#endif
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#ifndef CONFIG_BOOT_SDRAM_DATA
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/* Initialize .bss and .data ONLY if .bss and .data lie in SRAM that is
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#ifndef CONFIG_ARMV7R_MEMINIT
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/* Initialize .bss and .data ONLY if .bss and .data lie in RAM that is
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* ready to use. Other memory, such as SDRAM, must be initialized before
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* it can be used. up_boot() will perform that memory initialization and
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* .bss and .data can be initialized after up_boot() returns.
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* it can be used. arm_boot() will perform that memory initialization and
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* .bss and .data can be initialized after arm_boot() returns.
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*/
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bl arm_data_initialize
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#endif
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/* Perform early C-level, platform-specific initialization. Logic
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* within arm_boot() must configure SDRAM and call arm_ram_initailize()
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* is CONFIG_BOOT_SDRAM_DATA=y.
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* within arm_boot() must configure SDRAM and call arm_data_initialize()
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* if CONFIG_ARMV7R_MEMINIT=y.
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*/
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bl arm_boot
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@ -362,7 +362,7 @@ __start:
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#ifdef CONFIG_STACK_COLORATION
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.type .Lstkinit, %object
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.Lstkinit:
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#ifdef CONFIG_BOOT_SDRAM_DATA
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#ifdef CONFIG_ARMV7R_MEMINIT
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.long IDLE_STACK_BASE /* Beginning of the IDLE stack, then words of IDLE stack */
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#else
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.long _ebss /* Beginning of the IDLE stack, then words of IDLE stack */
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@ -433,7 +433,7 @@ arm_data_initialize:
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.long _ebss
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.Lstackpointer:
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#ifdef CONFIG_BOOT_SDRAM_DATA
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#ifdef CONFIG_ARMV7R_MEMINIT
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.long IDLE_STACK_BASE+CONFIG_IDLETHREAD_STACKSIZE-4
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#else
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.long _ebss+CONFIG_IDLETHREAD_STACKSIZE-4
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@ -137,7 +137,7 @@
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/* Bits 3-4: Reserved */
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#define SCTLR_CCP15BEN (1 << 5) /* Bit 5: CP15 barrier enable */
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/* Bit 6: Reserved */
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#define SCTLR_B (1 << 7) /* Bit 7: Should be zero on ARMv7R */
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#define SCTLR_B (1 << 7) /* Bit 7: Should be zero on ARMv7-R */
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/* Bits 8-9: Reserved */
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#define SCTLR_SW (1 << 10) /* Bit 10: SWP/SWPB Enable bit */
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#define SCTLR_Z (1 << 11) /* Bit 11: Program flow prediction control */
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@ -159,7 +159,7 @@
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#define SCTLR_IE (1 << 31) /* Bit 31: Instruction endian-ness */
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/* Auxiliary Control Register (ACTLR): CRn=c1, opc1=0, CRm=c0, opc2=1
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* TODO: To be provided
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* Implementation defined
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*/
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/* Coprocessor Access Control Register (CPACR): CRn=c1, opc1=0, CRm=c0, opc2=2
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@ -167,7 +167,7 @@
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*/
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/* CP15 c2-c4 Registers *************************************************************/
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/* Not used on ARMv7R */
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/* Not used on ARMv7-R */
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/* CP15 c5 Registers ****************************************************************/
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/* Data Fault Status Register (DFSR): CRn=c5, opc1=0, CRm=c0, opc2=0
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@ -231,7 +231,7 @@
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/* See cp15_cacheops.h */
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/* CP15 c8 Registers ****************************************************************/
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/* Not used on ARMv7R */
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/* Not used on ARMv7-R */
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/* CP15 c9 Registers ****************************************************************/
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/* 32-bit Performance Monitors Control Register (PMCR): CRn=c9, opc1=0, CRm=c12, opc2=0
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@ -304,13 +304,13 @@
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*/
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/* CP15 c10 Registers ***************************************************************/
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/* Not used on ARMv7R */
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/* Not used on ARMv7-R */
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/* CP15 c11 Registers ***************************************************************/
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/* Reserved for implementation defined DMA functions */
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/* CP15 c12 Registers ***************************************************************/
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/* Not used on ARMv7R */
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/* Not used on ARMv7-R */
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/* CP15 c13 Registers ***************************************************************/
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@ -65,6 +65,10 @@
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* Pre-processor Definitions
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****************************************************************************/
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#ifndef CONFIG_ARMV7R_MEMINIT
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# error CONFIG_ARMV7R_MEMINIT is required by this architecture.
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#endif
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#define HIGH_VECTOR_ADDRESS 0xffff0000
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/****************************************************************************
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@ -199,7 +203,7 @@ static inline void tms570_event_export(void)
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* 1. The __start entry point in armv7-r/arm_head.S is invoked upon power-
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* on reset.
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* 2. __start prepares CPU for code execution.
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* 3a. If CONFIG_BOOT_SDRAM_DATA is not defined, then __start will prepare
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* 3a. If CONFIG_ARMV7R_MEMINIT is not defined, then __start will prepare
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* memory resources by calling arm_data_initialize() and will then
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* call this function.
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* 3b. Otherwise, this function will be called without having initialized
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@ -287,9 +291,9 @@ void arm_boot(void)
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tms570_board_initialize();
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#ifdef CONFIG_BOOT_SDRAM_DATA
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#ifdef CONFIG_ARMV7R_MEMINIT
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/* If .data and .bss reside in SDRAM, then initialize the data sections
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* now after SDRAM has been initialized.
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* now after RAM has been initialized.
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*/
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arm_data_initialize();
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