diff --git a/arch/arm/src/armv7-r/Kconfig b/arch/arm/src/armv7-r/Kconfig
index 1c0638a40e9..7319c4e5f40 100644
--- a/arch/arm/src/armv7-r/Kconfig
+++ b/arch/arm/src/armv7-r/Kconfig
@@ -5,6 +5,20 @@
 
 comment "ARMv7-A Configuration Options"
 
+config ARMV7R_MEMINIT
+	bool
+	default y if CONFIG_BOOT_SDRAM_DATA
+	default n if !CONFIG_BOOT_SDRAM_DATA
+	---help---
+		If this configuration *not* selected, then it is assumed that all
+		memory resources are initialized via arm_data_initialize() and
+		available at power-up reset time.  Other memories, such as SDRAM or
+		some ECC SRAM memories, require some platform-specific
+		initialization first.  In that case, this option should be selected
+		and the platform-specific implementation of arm_boot() must perform
+		the memory initialization first, then explicitly call
+		arm_data_initialize().
+
 config ARMV7R_HAVE_L2CC
 	bool
 	default n
diff --git a/arch/arm/src/armv7-r/arm.h b/arch/arm/src/armv7-r/arm.h
index 8ad3086836d..1c0155e4a31 100644
--- a/arch/arm/src/armv7-r/arm.h
+++ b/arch/arm/src/armv7-r/arm.h
@@ -115,9 +115,10 @@ extern "C"
  * Description:
  *   Clear all of .bss to zero; set .data to the correct initial values.
  *   This function is called automatically from ARMv7-R boot code *UNLESS*
- *   executing from FLASH or SRAM with data is SDRAM (CONFIG_BOOT_SDRAM_DATA=y).
- *   In that case, early board-specific logic must first initialize SDRAM
- *   then call this function.
+ *   executing with data in some memory that requires platform-specific
+ *   initialization (such as SDRAM).  That latter case is indicated with
+ *   CONFIG_ARMV7R_MEMINIT=y.  In that case, early platform-specific logic
+ *   must first initialize then memory then call this function.
  *
  * Input Parameters:
  *   None
diff --git a/arch/arm/src/armv7-r/arm_head.S b/arch/arm/src/armv7-r/arm_head.S
index e545fd301fc..854f38e1eb5 100644
--- a/arch/arm/src/armv7-r/arm_head.S
+++ b/arch/arm/src/armv7-r/arm_head.S
@@ -319,19 +319,19 @@ __start:
 	mcr		CP15_ACTLR(r0)			/* Write Auxiliary Control register */
 #endif
 
-#ifndef CONFIG_BOOT_SDRAM_DATA
-	/* Initialize .bss and .data ONLY if .bss and .data lie in SRAM that is
+#ifndef CONFIG_ARMV7R_MEMINIT
+	/* Initialize .bss and .data ONLY if .bss and .data lie in RAM that is
 	 * ready to use.  Other memory, such as SDRAM, must be initialized before
-	 * it can be used.  up_boot() will perform that memory initialization and
-	 * .bss and .data can be initialized after up_boot() returns.
+	 * it can be used.  arm_boot() will perform that memory initialization and
+	 * .bss and .data can be initialized after arm_boot() returns.
 	 */
 
 	bl		arm_data_initialize
 #endif
 
 	/* Perform early C-level, platform-specific initialization.  Logic
-	 * within arm_boot() must configure SDRAM and call arm_ram_initailize()
-	 * is CONFIG_BOOT_SDRAM_DATA=y.
+	 * within arm_boot() must configure SDRAM and call arm_data_initialize()
+	 * if CONFIG_ARMV7R_MEMINIT=y.
 	 */
 
 	bl		arm_boot
@@ -362,7 +362,7 @@ __start:
 #ifdef CONFIG_STACK_COLORATION
 	.type	.Lstkinit, %object
 .Lstkinit:
-#ifdef CONFIG_BOOT_SDRAM_DATA
+#ifdef CONFIG_ARMV7R_MEMINIT
 	.long	IDLE_STACK_BASE		/* Beginning of the IDLE stack, then words of IDLE stack */
 #else
 	.long	_ebss					/* Beginning of the IDLE stack, then words of IDLE stack */
@@ -433,7 +433,7 @@ arm_data_initialize:
 	.long	_ebss
 
 .Lstackpointer:
-#ifdef CONFIG_BOOT_SDRAM_DATA
+#ifdef CONFIG_ARMV7R_MEMINIT
 	.long	IDLE_STACK_BASE+CONFIG_IDLETHREAD_STACKSIZE-4
 #else
 	.long	_ebss+CONFIG_IDLETHREAD_STACKSIZE-4
diff --git a/arch/arm/src/armv7-r/sctlr.h b/arch/arm/src/armv7-r/sctlr.h
index 9ef79b1eb7d..572596aa17d 100644
--- a/arch/arm/src/armv7-r/sctlr.h
+++ b/arch/arm/src/armv7-r/sctlr.h
@@ -137,7 +137,7 @@
                                      /* Bits 3-4: Reserved */
 #define SCTLR_CCP15BEN     (1 << 5)  /* Bit 5:  CP15 barrier enable */
                                      /* Bit 6:  Reserved */
-#define SCTLR_B            (1 << 7)  /* Bit 7:  Should be zero on ARMv7R */
+#define SCTLR_B            (1 << 7)  /* Bit 7:  Should be zero on ARMv7-R */
                                      /* Bits 8-9: Reserved */
 #define SCTLR_SW           (1 << 10) /* Bit 10: SWP/SWPB Enable bit */
 #define SCTLR_Z            (1 << 11) /* Bit 11: Program flow prediction control */
@@ -159,7 +159,7 @@
 #define SCTLR_IE           (1 << 31) /* Bit 31: Instruction endian-ness */
 
 /* Auxiliary Control Register (ACTLR): CRn=c1, opc1=0, CRm=c0, opc2=1
- * TODO: To be provided
+ * Implementation defined
  */
 
 /* Coprocessor Access Control Register (CPACR): CRn=c1, opc1=0, CRm=c0, opc2=2
@@ -167,7 +167,7 @@
  */
 
 /* CP15 c2-c4 Registers *************************************************************/
-/* Not used on ARMv7R */
+/* Not used on ARMv7-R */
 
 /* CP15 c5 Registers ****************************************************************/
 /* Data Fault Status Register (DFSR): CRn=c5, opc1=0, CRm=c0, opc2=0
@@ -231,7 +231,7 @@
 /* See cp15_cacheops.h */
 
 /* CP15 c8 Registers ****************************************************************/
-/* Not used on ARMv7R */
+/* Not used on ARMv7-R */
 
 /* CP15 c9 Registers ****************************************************************/
 /* 32-bit Performance Monitors Control Register (PMCR): CRn=c9, opc1=0, CRm=c12, opc2=0
@@ -304,13 +304,13 @@
  */
 
 /* CP15 c10 Registers ***************************************************************/
-/* Not used on ARMv7R */
+/* Not used on ARMv7-R */
 
 /* CP15 c11 Registers ***************************************************************/
 /* Reserved for implementation defined DMA functions */
 
 /* CP15 c12 Registers ***************************************************************/
-/* Not used on ARMv7R */
+/* Not used on ARMv7-R */
 
 /* CP15 c13 Registers ***************************************************************/
 
diff --git a/arch/arm/src/tms570/tms570_boot.c b/arch/arm/src/tms570/tms570_boot.c
index 8aac5461883..3ad23ddbe00 100644
--- a/arch/arm/src/tms570/tms570_boot.c
+++ b/arch/arm/src/tms570/tms570_boot.c
@@ -65,6 +65,10 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
+#ifndef CONFIG_ARMV7R_MEMINIT
+#  error CONFIG_ARMV7R_MEMINIT is required by this architecture.
+#endif
+
 #define HIGH_VECTOR_ADDRESS   0xffff0000
 
 /****************************************************************************
@@ -199,7 +203,7 @@ static inline void tms570_event_export(void)
  *   1.  The __start entry point in armv7-r/arm_head.S is invoked upon power-
  *       on reset.
  *   2.  __start prepares CPU for code execution.
- *   3a. If CONFIG_BOOT_SDRAM_DATA is not defined, then __start will prepare
+ *   3a. If CONFIG_ARMV7R_MEMINIT is not defined, then __start will prepare
  *       memory resources by calling arm_data_initialize() and will then
  *       call this function.
  *   3b. Otherwise, this function will be called without having initialized
@@ -287,9 +291,9 @@ void arm_boot(void)
 
   tms570_board_initialize();
 
-#ifdef CONFIG_BOOT_SDRAM_DATA
+#ifdef CONFIG_ARMV7R_MEMINIT
   /* If .data and .bss reside in SDRAM, then initialize the data sections
-   * now after SDRAM has been initialized.
+   * now after RAM has been initialized.
    */
 
   arm_data_initialize();