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mpfs/emmcsd: Set 8-bit data width and DDR HS mode for eMMC

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This is not the correct way to do this, but it gives a nice perf. boost
This commit is contained in:
Ville Juven 2022-11-30 11:58:17 +02:00 • committed by Xiang Xiao
parent c36bdba3cb
commit c23babbcc7
1 changed files with 61 additions and 0 deletions
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61
arch/risc-v/src/mpfs/mpfs_emmcsd.c
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@ -1752,6 +1752,58 @@ static void mpfs_widebus(struct sdio_dev_s *dev, bool wide)
}
}
/****************************************************************************
* Name: mpfs_clock
*
****************************************************************************/
static void mpfs_set_hs_8bit(struct sdio_dev_s *dev)
{
struct mpfs_dev_s *priv = (struct mpfs_dev_s *)dev;
int ret;
uint32_t r1;
if ((ret = mpfs_sendcmd(dev, MMCSD_CMD6, 0x03b70000u | (6 << 8))) == OK)
{
if ((ret == mpfs_waitresponse(dev, MMCSD_CMD6)) == OK)
{
ret = mpfs_recvshortcrc(dev, MMCSD_CMD6, &r1);
}
}
if (ret < 0)
{
mcerr("Failed to set high speed mode\n");
goto err;
}
modifyreg32(MPFS_EMMCSD_HRS06, 0, priv->bus_mode);
if ((ret = mpfs_sendcmd(dev, MMCSD_CMD6, 0x03b70000u | (2 << 8))) == OK)
{
if ((ret == mpfs_waitresponse(dev, MMCSD_CMD6)) == OK)
{
ret = mpfs_recvshortcrc(dev, MMCSD_CMD6, &r1);
}
}
if (ret < 0)
{
mcerr("Failed to set 8-bit mode\n");
goto err;
}
modifyreg32(MPFS_EMMCSD_SRS10, 0, MPFS_EMMCSD_SRS10_EDTW);
return;
err:
/* Reset to 1-bit legacy mode */
modifyreg32(MPFS_EMMCSD_HRS06, 0, MPFS_EMMCSD_MODE_LEGACY);
modifyreg32(MPFS_EMMCSD_SRS10, MPFS_EMMCSD_SRS10_EDTW, 0);
}
/****************************************************************************
* Name: mpfs_clock
*
@ -1824,6 +1876,15 @@ static void mpfs_clock(struct sdio_dev_s *dev, enum sdio_clock_e rate)
/* Set the new clock frequency */
mpfs_setclkrate(priv, clckr);
/* REVISIT: This should really be a separate configuration procedure */
if (rate == CLOCK_MMC_TRANSFER)
{
/* eMMC: Set 8-bit data bus and correct bus mode */
mpfs_set_hs_8bit(dev);
}
}
/****************************************************************************