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Fix typos in comments and documentation (#750)
* Fix typos in comments and documentation
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54 changed files with 133 additions and 134 deletions
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@ -63,7 +63,7 @@
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* 528Mhz = (24Mhz * 22) / 1
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*
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* AHB_CLOCK_ROOT = PLL6fOut / IMXRT_AHB_PODF_DIVIDER
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* 1Hz to 500 Mhz = Mhz / IMXRT_ARM_CLOCK_DIVIDER
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* 1Hz to 500 MHz = MHz / IMXRT_ARM_CLOCK_DIVIDER
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* IMXRT_ARM_CLOCK_DIVIDER = 1
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* 500Mhz = 500Mhz / 1
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*
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@ -63,7 +63,7 @@
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* 600Mhz = (24Mhz * 100/2) / 2
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*
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* AHB_CLOCK_ROOT = PLL1fOut / IMXRT_AHB_PODF_DIVIDER
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* 1Hz to 600 Mhz = 600Mhz / IMXRT_ARM_CLOCK_DIVIDER
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* 1Hz to 600 MHz = 600Mhz / IMXRT_ARM_CLOCK_DIVIDER
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* IMXRT_ARM_CLOCK_DIVIDER = 1
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* 600Mhz = 600Mhz / 1
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*
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@ -63,7 +63,7 @@
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* 600Mhz = (24Mhz * 100/2) / 2
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*
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* AHB_CLOCK_ROOT = PLL1fOut / IMXRT_AHB_PODF_DIVIDER
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* 1Hz to 600 Mhz = 600Mhz / IMXRT_ARM_CLOCK_DIVIDER
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* 1Hz to 600 MHz = 600Mhz / IMXRT_ARM_CLOCK_DIVIDER
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* IMXRT_ARM_CLOCK_DIVIDER = 1
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* 600Mhz = 600Mhz / 1
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*
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@ -70,8 +70,8 @@
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* a KINETIS_MCG_PLL_REF_MIN >= PLLIN <= KINETIS_MCG_PLL_REF_MIN reference
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* clock to the PLL.
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*
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* PLL Input frequency: PLLIN = REFCLK / PRDIV = 50 Mhz / 20 = 2.5 MHz
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* PLL Output frequency: PLLOUT = PLLIN * VDIV = 2.5 Mhz * 48 = 120 MHz
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* PLL Input frequency: PLLIN = REFCLK / PRDIV = 50 MHz / 20 = 2.5 MHz
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* PLL Output frequency: PLLOUT = PLLIN * VDIV = 2.5 MHz * 48 = 120 MHz
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* MCG Frequency: PLLOUT = 120 MHz
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*
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* PRDIV register value is the divider minus KINETIS_MCG_C5_PRDIV_BASE.
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@ -74,9 +74,9 @@
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* KINETIS_MCG_PLL_REF_MIN >= PLLIN <=KINETIS_MCG_PLL_REF_MAX reference
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* clock to the PLL.
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*
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* PLL Input frequency: PLLIN = REFCLK / PRDIV = 12 Mhz / 1 = 12 MHz
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* PLL Output frequency: PLLOUT = PLLIN * VDIV = 12 Mhz * 30 = 360 MHz
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* MCG Frequency: PLLOUT = 180 Mhz = 360 MHz /
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* PLL Input frequency: PLLIN = REFCLK / PRDIV = 12 MHz / 1 = 12 MHz
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* PLL Output frequency: PLLOUT = PLLIN * VDIV = 12 MHz * 30 = 360 MHz
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* MCG Frequency: PLLOUT = 180 MHz = 360 MHz /
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* KINETIS_MCG_PLL_INTERNAL_DIVBY
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*
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* PRDIV register value is the divider minus KINETIS_MCG_C5_PRDIV_BASE.
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@ -114,7 +114,7 @@
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#define BOARD_SOPT2_PLLFLLSEL SIM_SOPT2_PLLFLLSEL_MCGPLLCLK
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#define BOARD_SOPT2_FREQ BOARD_MCG_FREQ
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/* N.B. The above BOARD_SOPT2_FREQ precludes use of USB with a 12 Mhz Xtal
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/* N.B. The above BOARD_SOPT2_FREQ precludes use of USB with a 12 MHz Xtal
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* Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ]
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* SIM_CLKDIV2_FREQ = BOARD_SOPT2_FREQ × [ (USBFRAC+1) / (USBDIV+1) ]
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* 48Mhz = 168Mhz X [(1 + 1) / (6 + 1)]
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@ -131,8 +131,8 @@
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/* Divider output clock = Divider input clock * ((PLLFLLFRAC+1)/(PLLFLLDIV+1))
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* SIM_CLKDIV3_FREQ = BOARD_SOPT2_FREQ × [ (PLLFLLFRAC+1) / (PLLFLLDIV+1)]
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* 90 Mhz = 180 Mhz X [(0 + 1) / (1 + 1)]
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* 90 Mhz = 180 Mhz / (1 + 1) * (0 + 1)
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* 90 MHz = 180 MHz X [(0 + 1) / (1 + 1)]
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* 90 MHz = 180 MHz / (1 + 1) * (0 + 1)
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*/
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#define BOARD_SIM_CLKDIV3_PLLFLLFRAC 1
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@ -92,7 +92,7 @@
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*
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* Board can be overclocked at 96MHz (per PJRC.com)
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* PLL Input frequency: PLLIN = REFCLK/PRDIV = 16MHz/8 = 2MHz
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* PLL Output frequency: PLLOUT = PLLIN*VDIV = Mhz*48 = 96MHz
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* PLL Output frequency: PLLOUT = PLLIN*VDIV = MHz*48 = 96MHz
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* MCG Frequency: PLLOUT = 96MHz
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*/
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@ -64,7 +64,7 @@
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*
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* PLL Input frequency: PLLIN = REFCLK/PRDIV = 50MHz/20 = 2.5 MHz
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* PLL Output frequency: PLLOUT = PLLIN*VDIV = 2.5Mhz*48 = 120MHz
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* MCG Frequency: PLLOUT = 120 Mhz
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* MCG Frequency: PLLOUT = 120 MHz
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*/
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#define BOARD_PRDIV 20 /* PLL External Reference Divider */
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@ -46,7 +46,7 @@ Olimex STR-P711
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- Power supply filtering capacitor
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- RESET circuit
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- RESET button
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- 4 Mhz crystal oscillator
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- 4 MHz crystal oscillator
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- 32768 Hz crystal and RTC
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Power Supply
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@ -58,7 +58,7 @@
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* - Power supply filtering capacitor
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* - RESET circuit
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* - RESET button
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* - 4 Mhz crystal oscillator
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* - 4 MHz crystal oscillator
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* - 32768 Hz crystal and RTC
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*
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****************************************************************************/
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