Fix typos in comments and documentation (#750)

* Fix typos in comments and documentation
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hartmannathan 2020-04-08 08:45:35 -04:00 • committed by GitHub
parent 9c7841aff1
commit bfc153ca27
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54 changed files with 133 additions and 134 deletions

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@ -63,7 +63,7 @@
* 528Mhz = (24Mhz * 22) / 1
*
* AHB_CLOCK_ROOT = PLL6fOut / IMXRT_AHB_PODF_DIVIDER
* 1Hz to 500 Mhz = Mhz / IMXRT_ARM_CLOCK_DIVIDER
* 1Hz to 500 MHz = MHz / IMXRT_ARM_CLOCK_DIVIDER
* IMXRT_ARM_CLOCK_DIVIDER = 1
* 500Mhz = 500Mhz / 1
*

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@ -63,7 +63,7 @@
* 600Mhz = (24Mhz * 100/2) / 2
*
* AHB_CLOCK_ROOT = PLL1fOut / IMXRT_AHB_PODF_DIVIDER
* 1Hz to 600 Mhz = 600Mhz / IMXRT_ARM_CLOCK_DIVIDER
* 1Hz to 600 MHz = 600Mhz / IMXRT_ARM_CLOCK_DIVIDER
* IMXRT_ARM_CLOCK_DIVIDER = 1
* 600Mhz = 600Mhz / 1
*

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@ -63,7 +63,7 @@
* 600Mhz = (24Mhz * 100/2) / 2
*
* AHB_CLOCK_ROOT = PLL1fOut / IMXRT_AHB_PODF_DIVIDER
* 1Hz to 600 Mhz = 600Mhz / IMXRT_ARM_CLOCK_DIVIDER
* 1Hz to 600 MHz = 600Mhz / IMXRT_ARM_CLOCK_DIVIDER
* IMXRT_ARM_CLOCK_DIVIDER = 1
* 600Mhz = 600Mhz / 1
*

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@ -70,8 +70,8 @@
* a KINETIS_MCG_PLL_REF_MIN >= PLLIN <= KINETIS_MCG_PLL_REF_MIN reference
* clock to the PLL.
*
* PLL Input frequency: PLLIN = REFCLK / PRDIV = 50 Mhz / 20 = 2.5 MHz
* PLL Output frequency: PLLOUT = PLLIN * VDIV = 2.5 Mhz * 48 = 120 MHz
* PLL Input frequency: PLLIN = REFCLK / PRDIV = 50 MHz / 20 = 2.5 MHz
* PLL Output frequency: PLLOUT = PLLIN * VDIV = 2.5 MHz * 48 = 120 MHz
* MCG Frequency: PLLOUT = 120 MHz
*
* PRDIV register value is the divider minus KINETIS_MCG_C5_PRDIV_BASE.

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@ -74,9 +74,9 @@
* KINETIS_MCG_PLL_REF_MIN >= PLLIN <=KINETIS_MCG_PLL_REF_MAX reference
* clock to the PLL.
*
* PLL Input frequency: PLLIN = REFCLK / PRDIV = 12 Mhz / 1 = 12 MHz
* PLL Output frequency: PLLOUT = PLLIN * VDIV = 12 Mhz * 30 = 360 MHz
* MCG Frequency: PLLOUT = 180 Mhz = 360 MHz /
* PLL Input frequency: PLLIN = REFCLK / PRDIV = 12 MHz / 1 = 12 MHz
* PLL Output frequency: PLLOUT = PLLIN * VDIV = 12 MHz * 30 = 360 MHz
* MCG Frequency: PLLOUT = 180 MHz = 360 MHz /
* KINETIS_MCG_PLL_INTERNAL_DIVBY
*
* PRDIV register value is the divider minus KINETIS_MCG_C5_PRDIV_BASE.
@ -114,7 +114,7 @@
#define BOARD_SOPT2_PLLFLLSEL SIM_SOPT2_PLLFLLSEL_MCGPLLCLK
#define BOARD_SOPT2_FREQ BOARD_MCG_FREQ
/* N.B. The above BOARD_SOPT2_FREQ precludes use of USB with a 12 Mhz Xtal
/* N.B. The above BOARD_SOPT2_FREQ precludes use of USB with a 12 MHz Xtal
* Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ]
* SIM_CLKDIV2_FREQ = BOARD_SOPT2_FREQ × [ (USBFRAC+1) / (USBDIV+1) ]
* 48Mhz = 168Mhz X [(1 + 1) / (6 + 1)]
@ -131,8 +131,8 @@
/* Divider output clock = Divider input clock * ((PLLFLLFRAC+1)/(PLLFLLDIV+1))
* SIM_CLKDIV3_FREQ = BOARD_SOPT2_FREQ × [ (PLLFLLFRAC+1) / (PLLFLLDIV+1)]
* 90 Mhz = 180 Mhz X [(0 + 1) / (1 + 1)]
* 90 Mhz = 180 Mhz / (1 + 1) * (0 + 1)
* 90 MHz = 180 MHz X [(0 + 1) / (1 + 1)]
* 90 MHz = 180 MHz / (1 + 1) * (0 + 1)
*/
#define BOARD_SIM_CLKDIV3_PLLFLLFRAC 1

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@ -92,7 +92,7 @@
*
* Board can be overclocked at 96MHz (per PJRC.com)
* PLL Input frequency: PLLIN = REFCLK/PRDIV = 16MHz/8 = 2MHz
* PLL Output frequency: PLLOUT = PLLIN*VDIV = Mhz*48 = 96MHz
* PLL Output frequency: PLLOUT = PLLIN*VDIV = MHz*48 = 96MHz
* MCG Frequency: PLLOUT = 96MHz
*/

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@ -64,7 +64,7 @@
*
* PLL Input frequency: PLLIN = REFCLK/PRDIV = 50MHz/20 = 2.5 MHz
* PLL Output frequency: PLLOUT = PLLIN*VDIV = 2.5Mhz*48 = 120MHz
* MCG Frequency: PLLOUT = 120 Mhz
* MCG Frequency: PLLOUT = 120 MHz
*/
#define BOARD_PRDIV 20 /* PLL External Reference Divider */

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@ -46,7 +46,7 @@ Olimex STR-P711
- Power supply filtering capacitor
- RESET circuit
- RESET button
- 4 Mhz crystal oscillator
- 4 MHz crystal oscillator
- 32768 Hz crystal and RTC
Power Supply

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@ -58,7 +58,7 @@
* - Power supply filtering capacitor
* - RESET circuit
* - RESET button
* - 4 Mhz crystal oscillator
* - 4 MHz crystal oscillator
* - 32768 Hz crystal and RTC
*
****************************************************************************/