Xtensa LX6 ESP32 Architectural Support. - Basic architectural support for Xtensa LX6 processors and the port for the Expressif ESP32 were added in NuttX-7.19. + Basic architectural support for Xtensa LX6 processors and the port for the Espressif ESP32 were added in NuttX-7.19. The basic ESP32 port is function in both single CPU and dual CPU SMP configurations.
- Expressif ESP32 Core v2 Board - The NuttX release includes support for Expressif ESP32 Core v2 board. + Espressif ESP32 Core v2 Board + The NuttX release includes support for Espressif ESP32 Core v2 board. There is an NSH configuration for each CPU configuration and an OS test configuration for verificatin of the port.
diff --git a/ReleaseNotes b/ReleaseNotes
index b7338843f53..6d58ee7c43e 100644
--- a/ReleaseNotes
+++ b/ReleaseNotes
@@ -12528,7 +12528,7 @@ Additional new features and extended functionality:
* Xtensa/ESP32
- Xtensa ESP32: Basic architectural support for Xtensa processors and
- the Expressif. ESP32 added.
+ the Espressif. ESP32 added.
- Xtensa ESP32: Add EXPERIMENTAL hooks to support lazy Xtensa
co-processor state restore in the future.
- Xtensa ESP32: Basic port is function in both single CPU and dual CPU
@@ -12540,7 +12540,7 @@ Additional new features and extended functionality:
* Xtensa/ESP32 Boards:
- - ESP32 Core v2: Basic support for Expressif ESP32 Core v2 board
+ - ESP32 Core v2: Basic support for Espressif ESP32 Core v2 board
added. The initial release includes an NSH and an SMP test
configuration.
- ESP32 Core v2: Add configuration to support linking NuttX for
@@ -13769,10 +13769,10 @@ Additional new features and extended functionality:
- STM32 L1: stm32l15xxx_rcc: configure medium performance voltage
range and zero wait-state when allowed by SYSCLK setting. Zero
wait-state for flash can be configured when: (1) Range 1 and
- SYSCLK <= 16 Mhz, (2) Range 2 and SYSCLK <= 8 Mhz, or (3) Range 3
- and SYSCLK <= 4.2 Mhz. Medium performance voltage range (1.5V)
- can be configured when SYSCLK is up to 16 Mhz and PLLVCO up to
- 48 Mhz. From Juha Niskanen.
+ SYSCLK <= 16 MHz, (2) Range 2 and SYSCLK <= 8 MHz, or (3) Range 3
+ and SYSCLK <= 4.2 MHz. Medium performance voltage range (1.5V)
+ can be configured when SYSCLK is up to 16 MHz and PLLVCO up to
+ 48 MHz. From Juha Niskanen.
- STM32 F0: Add basic support for STM32F0. From Alan Carvalho de
Assis.
- STM32 F0: Add basic support for STM32F07x family.
@@ -14778,7 +14778,7 @@ Additional new features and extended functionality:
- STM32 L4: Add support for the STM32L475 family.
- STM32 L4 RCC: Enable ADC clock source. From Juha Niskanen.
- - STM32: Allow clock frequencies > 168 Mhz on stm32f427/429. We need
+ - STM32: Allow clock frequencies > 168 MHz on stm32f427/429. We need
to enable the power overdrive for this case. This change allows the
required bits to be set in proper sequence. It also modifies the
local register access operations to allow more than 16-bit registers.
@@ -15297,7 +15297,7 @@ detailed bugfix information):
has not caused problems in the past, but seeing it set in the PC is
unnerving.
- * Expressif ESP32:
+ * Espressif ESP32:
- Fix ESP32 gpio enable reg and default UART pin. Modify default UART
pin for ESP-WROOM-32. Fix gpio enable reg. From Sungki Kim.
@@ -15349,8 +15349,8 @@ detailed bugfix information):
* NXP/Freescale Kinetis:
- Kinetis MPU: Disable MPU when not in protected mode. The hardware
- reset state of the the MPU precludes any bus masters other then DMA
- access to memory. Unfortunately USB and SDHC have there own DMA and
+ reset state of the the MPU precludes any bus masters other than DMA
+ access to memory. Unfortunately USB and SDHC have their own DMA and
will not have access to memory in the default reset state. This change
disabled the MPU if present on system startup. From David Sidrane.
- Kinetis MPU: Fixed warning for kinetis_mpudisable. Missing header
@@ -15957,7 +15957,7 @@ Additional new features and extended functionality:
drivers. The peripheral on STM32F7 and STM32L4 are identical except
for L4's 'wakeup from stop mode' flag and STM32F7's I2C driver is in
more 'ready to use' state. The I2C clock configuration is kept the
- same as before (I2CCLK = PCLK1 80 Mhz) instead of switching to
+ same as before (I2CCLK = PCLK1 80 MHz) instead of switching to
STM32F7 arch default that is I2CCLK=HSI. Further work would be to
add configuration option for choosing I2C clock source instead of
current hard-coded default. From Jussi Kivilinna.
@@ -22578,7 +22578,7 @@ detailed bugfix information):
Raised DEBUGASSERT in armv7-m/up_ramvec_initialize.c line: 144.
From Mateusz Szafoni.
- * Expressif ESP32 Drivers:
+ * Espressif ESP32 Drivers:
- ESP32 Timer ISR: Fix backward comparison. From Gregory Nutt.
- ESP32 Serial: Fix some backward arguments. Correct 2-stop bit
@@ -25894,7 +25894,7 @@ Additional new features and extended functionality:
- STM32 L4+ DMA: Add DMA support for STM32L4+ series. From Jussi
Kivilinna.
- STM32 L4 Clocking: Enable "Range 1 boost" mode if any PLL freq
- above 80 Mhz. From Jussi Kivilinna.
+ above 80 MHz. From Jussi Kivilinna.
- STM32 L4 LPTIM: Add support for LPTIM timers on the STM32L4 as PWM
outputs. From Matias N.
- STM32 H7 Progmem: Add FLASH progmem support. From David Sidrane.
diff --git a/arch/README.txt b/arch/README.txt
index 9568d7dd032..38ebe9df1c1 100644
--- a/arch/README.txt
+++ b/arch/README.txt
@@ -268,7 +268,7 @@ arch/xtensa
LX6 DPU support:
arch/xtensa/include/lx6 and arch/xtensa/xtensa/lx6
- Expressif ESP32 implementation of the LX6 DPU:
+ Espressif ESP32 implementation of the LX6 DPU:
arch/xtensa/include/esp32 and arch/xtensa/xtensa/esp32
arch/z16 - ZiLOG 16-bit processors
diff --git a/arch/arm/src/imxrt/imxrt_clockconfig.c b/arch/arm/src/imxrt/imxrt_clockconfig.c
index e883f984479..4a41f93ee81 100644
--- a/arch/arm/src/imxrt/imxrt_clockconfig.c
+++ b/arch/arm/src/imxrt/imxrt_clockconfig.c
@@ -605,7 +605,7 @@ void imxrt_clockconfig(void)
reg |= IMXRT_LPI2C_CLK_SELECT;
putreg32(reg, IMXRT_CCM_CSCDR2);
- /* Set LPI2C divider to 5 for 12 Mhz */
+ /* Set LPI2C divider to 5 for 12 MHz */
reg = getreg32(IMXRT_CCM_CSCDR2);
reg &= ~CCM_CSCDR2_LPI2C_CLK_PODF_MASK;
diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc176x_syscon.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc176x_syscon.h
index 9bec63ef559..537f42f07a7 100644
--- a/arch/arm/src/lpc17xx_40xx/hardware/lpc176x_syscon.h
+++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc176x_syscon.h
@@ -197,7 +197,7 @@
# define SYSCON_FLASHCFG_TIM_3 (2 << SYSCON_FLASHCFG_TIM_SHIFT) /* 3 CPU clock <= 60 MHz CPU clock */
# define SYSCON_FLASHCFG_TIM_4 (3 << SYSCON_FLASHCFG_TIM_SHIFT) /* 4 CPU clock <= 80 MHz CPU clock */
# define SYSCON_FLASHCFG_TIM_5 (4 << SYSCON_FLASHCFG_TIM_SHIFT) /* 5 CPU clock <= 100 MHz CPU clock
- * (Up to 120 Mhz for LPC1759/69 only */
+ * (Up to 120 MHz for LPC1759/69 only */
# define SYSCON_FLASHCFG_TIM_6 (5 << SYSCON_FLASHCFG_TIM_SHIFT) /* "safe" setting for any conditions */
/* Bits 16-31: Reserved */
diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_syscon.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_syscon.h
index 6c38abd4481..e767b7b6b81 100644
--- a/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_syscon.h
+++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_syscon.h
@@ -227,7 +227,7 @@
# define SYSCON_FLASHCFG_TIM_2 (2 << SYSCON_FLASHCFG_TIM_SHIFT) /* 3 CPU clock <= 60 MHz CPU clock */
# define SYSCON_FLASHCFG_TIM_3 (3 << SYSCON_FLASHCFG_TIM_SHIFT) /* 4 CPU clock <= 80 MHz CPU clock */
# define SYSCON_FLASHCFG_TIM_4 (4 << SYSCON_FLASHCFG_TIM_SHIFT) /* 5 CPU clock <= 100 MHz CPU clock
- * (Up to 120 Mhz for LPC1788x) */
+ * (Up to 120 MHz for LPC1788x) */
# define SYSCON_FLASHCFG_TIM_5 (5 << SYSCON_FLASHCFG_TIM_SHIFT) /* "safe" setting for any conditions */
/* Bits 16-31: Reserved */
/* Memory Mapping Control register (MEMMAP - 0x400F C040) */
diff --git a/arch/arm/src/lpc31xx/lpc31_cgu.h b/arch/arm/src/lpc31xx/lpc31_cgu.h
index 080f998b8fe..ea89d522676 100644
--- a/arch/arm/src/lpc31xx/lpc31_cgu.h
+++ b/arch/arm/src/lpc31xx/lpc31_cgu.h
@@ -1500,7 +1500,7 @@ Nandflash Controller */
#define CGU_HPFINSEL_SHIFT (0) /* Bits 0-3: Select input to high HPPLL0 */
#define CGU_HPFINSEL_MASK (15 << CGU_HPFINSEL_SHIFT)
-# define CGU_HPFINSEL_FFAST (CGU_FREQIN_FFAST << CGU_HPFINSEL_SHIFT) /* ffast (12 Mhz) */
+# define CGU_HPFINSEL_FFAST (CGU_FREQIN_FFAST << CGU_HPFINSEL_SHIFT) /* ffast (12 MHz) */
# define CGU_HPFINSEL_I2SRXBCK0 (CGU_FREQIN_I2SRXBCK0 << CGU_HPFINSEL_SHIFT) /* I2SRX_BCK0 */
# define CGU_HPFINSEL_I2SRXWS0 (CGU_FREQIN_I2SRXWS0 << CGU_HPFINSEL_SHIFT) /* I2SRX_WS0 */
# define CGU_HPFINSEL_I2SRXBCK1 (CGU_FREQIN_I2SRXBCK1 << CGU_HPFINSEL_SHIFT) /* I2SRX_BCK1 */
diff --git a/arch/arm/src/lpc43xx/spifi/inc/spifilib_dev.h b/arch/arm/src/lpc43xx/spifi/inc/spifilib_dev.h
index b33d0c7842e..b2a55b6d1e7 100644
--- a/arch/arm/src/lpc43xx/spifi/inc/spifilib_dev.h
+++ b/arch/arm/src/lpc43xx/spifi/inc/spifilib_dev.h
@@ -304,11 +304,11 @@ typedef struct SPIFI_DEVICE_DATA {
uint16_t subBlkSize; /**< size of sub-block */
uint16_t pageSize; /**< page size */
uint32_t maxReadSize; /**< max read allowed in one operation */
- uint8_t maxClkRate; /**< (in Mhz) maximum clock rate (max common speed) */
- uint8_t maxReadRate; /**< (in Mhz) max clock rate for read (driver may utilize fast read) */
- uint8_t maxHSReadRate; /**< (in Mhz) max clock rate for quad / dual read */
- uint8_t maxProgramRate; /**< (in Mhz) max clock rate for program */
- uint8_t maxHSProgramRate; /**< (in Mhz) max clock rate for quad program */
+ uint8_t maxClkRate; /**< (in MHz) maximum clock rate (max common speed) */
+ uint8_t maxReadRate; /**< (in MHz) max clock rate for read (driver may utilize fast read) */
+ uint8_t maxHSReadRate; /**< (in MHz) max clock rate for quad / dual read */
+ uint8_t maxProgramRate; /**< (in MHz) max clock rate for program */
+ uint8_t maxHSProgramRate; /**< (in MHz) max clock rate for quad program */
uint8_t initDeInitFxId; /**< init/DeInit fx_id */
uint8_t clearStatusFxId; /**< clearStatus fx_id */
uint8_t getStatusFxId; /**< getStatus fx_id */
diff --git a/arch/arm/src/lpc43xx/spifi/src/spifilib_fam_standard_cmd.c b/arch/arm/src/lpc43xx/spifi/src/spifilib_fam_standard_cmd.c
index d51cb3a67c7..d0f04930729 100644
--- a/arch/arm/src/lpc43xx/spifi/src/spifilib_fam_standard_cmd.c
+++ b/arch/arm/src/lpc43xx/spifi/src/spifilib_fam_standard_cmd.c
@@ -1352,7 +1352,7 @@ SPIFI_FAM_NODE_T *spifi_REG_FAMILY_CommonCommandSet(void)
0x1000, /* sub-block size */
0x100, /* page size */
MAX_SINGLE_READ, /* max single read bytes */
- 104, /* max clock rate in Mhz */
+ 104, /* max clock rate in MHz */
104, /* max read clock rate in MHz */
104, /* max high speed read clock rate in MHz */
104, /* max program clock rate in MHz */
diff --git a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.h b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.h
index dc2c7c8b3a0..6dcbd860845 100644
--- a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.h
+++ b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.h
@@ -177,8 +177,8 @@ enum scg_sosc_gain_e
enum scg_sosc_range_e
{
- SCG_SOSC_RANGE_MID = 2, /* Medium frequency range selected for the crystal OSC (4 Mhz to 8 Mhz). */
- SCG_SOSC_RANGE_HIGH = 3, /* High frequency range selected for the crystal OSC (8 Mhz to 40 Mhz). */
+ SCG_SOSC_RANGE_MID = 2, /* Medium frequency range selected for the crystal OSC (4 MHz to 8 MHz). */
+ SCG_SOSC_RANGE_HIGH = 3, /* High frequency range selected for the crystal OSC (8 MHz to 40 MHz). */
};
struct scg_sosc_config_s
diff --git a/arch/arm/src/sama5/sam_pmecc.c b/arch/arm/src/sama5/sam_pmecc.c
index cc2f17e2f0d..d756d6f30c0 100644
--- a/arch/arm/src/sama5/sam_pmecc.c
+++ b/arch/arm/src/sama5/sam_pmecc.c
@@ -1221,7 +1221,7 @@ int pmecc_configure(struct sam_nandcs_s *priv, bool protected)
* case, the ECC computation takes into account the whole spare area
* minus the ECC area in the ECC computation operation
*
- * NOTE: At 133 Mhz, the clkctrl field must be programmed with 2,
+ * NOTE: At 133 MHz, the clkctrl field must be programmed with 2,
* indicating that the setup time is 3 clock cycles.
*/
diff --git a/arch/arm/src/samv7/sam_clockconfig.c b/arch/arm/src/samv7/sam_clockconfig.c
index 5e28a267893..9557928b1cc 100644
--- a/arch/arm/src/samv7/sam_clockconfig.c
+++ b/arch/arm/src/samv7/sam_clockconfig.c
@@ -266,13 +266,13 @@ static inline void sam_pmcsetup(void)
if ((getreg32(SAM_PMC_MCKR) & PMC_MCKR_PLLADIV2) != 0)
{
- /* Divider = 480 Mhz / 2 / 48 Mhz = 5 */
+ /* Divider = 480 MHz / 2 / 48 MHz = 5 */
regval |= PMC_USB_USBDIV(4);
}
else
{
- /* Divider = 480 Mhz / 1 / 48 Mhz = 10 */
+ /* Divider = 480 MHz / 1 / 48 MHz = 10 */
regval |= PMC_USB_USBDIV(9);
}
diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig
index 0a8e8a346a3..ef98eed0b7d 100644
--- a/arch/arm/src/stm32/Kconfig
+++ b/arch/arm/src/stm32/Kconfig
@@ -9488,7 +9488,7 @@ config STM32_USB_ITRMP
The legacy USB in the F1 series shared interrupt lines with USB
device and CAN1. In the F3 series, a hardware options was added to
either retain the legacy F1 behavior or to map the USB interrupts to
- there own dedicated vectors. The option is available only for the
+ their own dedicated vectors. The option is available only for the
F3 family and selects the use of the dedicated USB interrupts.
menu "CAN driver configuration"
diff --git a/arch/arm/src/stm32/stm32f40xxx_rcc.c b/arch/arm/src/stm32/stm32f40xxx_rcc.c
index 257f6733985..957951a1726 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rcc.c
@@ -756,7 +756,7 @@ static void stm32_stdclockconfig(void)
#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F446) || \
defined(CONFIG_STM32_STM32F469)
- /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
+ /* Enable the Over-drive to extend the clock frequency to 180 MHz */
regval = getreg32(STM32_PWR_CR);
regval |= PWR_CR_ODEN;
diff --git a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c
index 08b7aa3e288..d8958c8a56f 100644
--- a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c
+++ b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c
@@ -806,9 +806,9 @@ static void stm32_stdclockconfig(void)
/* Over-drive is needed if
* - Voltage output scale 1 mode is selected and SYSCLK frequency is
- * over 180 Mhz.
+ * over 180 MHz.
* - Voltage output scale 2 mode is selected and SYSCLK frequence is
- * over 168 Mhz.
+ * over 168 MHz.
*/
if ((STM32_PWR_VOS_SCALE == PWR_CR1_VOS_SCALE_1 &&
@@ -817,7 +817,7 @@ static void stm32_stdclockconfig(void)
STM32_SYSCLK_FREQUENCY > 168000000))
{
/* Enable the Over-drive to extend the clock frequency up to
- * 216 Mhz.
+ * 216 MHz.
*/
regval = getreg32(STM32_PWR_CR1);
diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c
index ae553ab246c..397c6ce937f 100644
--- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c
+++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c
@@ -803,9 +803,9 @@ static void stm32_stdclockconfig(void)
/* Over-drive is needed if
* - Voltage output scale 1 mode is selected and SYSCLK frequency is
- * over 180 Mhz.
+ * over 180 MHz.
* - Voltage output scale 2 mode is selected and SYSCLK frequence is
- * over 168 Mhz.
+ * over 168 MHz.
*/
if ((STM32_PWR_VOS_SCALE == PWR_CR1_VOS_SCALE_1 &&
@@ -814,7 +814,7 @@ static void stm32_stdclockconfig(void)
STM32_SYSCLK_FREQUENCY > 168000000))
{
/* Enable the Over-drive to extend the clock frequency up to
- * 216 Mhz.
+ * 216 MHz.
*/
regval = getreg32(STM32_PWR_CR1);
diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c
index d78c3ddd89e..25d690f06d8 100644
--- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c
+++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c
@@ -820,9 +820,9 @@ static void stm32_stdclockconfig(void)
/* Over-drive is needed if
* - Voltage output scale 1 mode is selected and SYSCLK frequency is
- * over 180 Mhz.
+ * over 180 MHz.
* - Voltage output scale 2 mode is selected and SYSCLK frequence is
- * over 168 Mhz.
+ * over 168 MHz.
*/
if ((STM32_PWR_VOS_SCALE == PWR_CR1_VOS_SCALE_1 &&
@@ -831,7 +831,7 @@ static void stm32_stdclockconfig(void)
STM32_SYSCLK_FREQUENCY > 168000000))
{
/* Enable the Over-drive to extend the clock frequency up to
- * 216 Mhz.
+ * 216 MHz.
*/
regval = getreg32(STM32_PWR_CR1);
diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
index 274ee03807b..770607be446 100644
--- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
+++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
@@ -818,7 +818,7 @@ static void stm32_stdclockconfig(void)
/* Over-drive is needed if
* - Voltage output scale 1 mode is selected and SYSCLK frequency is
- * over 400 Mhz.
+ * over 400 MHz.
*/
if ((STM32_PWR_VOS_SCALE == PWR_D3CR_VOS_SCALE_1) &&
@@ -830,7 +830,7 @@ static void stm32_stdclockconfig(void)
regval |= RCC_APB4ENR_SYSCFGEN;
putreg32(regval, STM32_RCC_APB4ENR);
- /* Enable Overdrive to extend the clock frequency up to 480 Mhz. */
+ /* Enable Overdrive to extend the clock frequency up to 480 MHz. */
regval = getreg32(STM32_SYSCFG_PWRCR);
regval |= SYSCFG_PWRCR_ODEN;
diff --git a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c
index e15cfbe6c40..2b6a1c82fa9 100644
--- a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c
+++ b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c
@@ -814,7 +814,7 @@ static void stm32_stdclockconfig(void)
/* Over-drive is needed if
* - Voltage output scale 1 mode is selected and SYSCLK frequency is
- * over 400 Mhz.
+ * over 400 MHz.
*/
if ((STM32_PWR_VOS_SCALE == PWR_D3CR_VOS_SCALE_1) &&
@@ -826,7 +826,7 @@ static void stm32_stdclockconfig(void)
regval |= RCC_APB4ENR_SYSCFGEN;
putreg32(regval, STM32_RCC_APB4ENR);
- /* Enable Overdrive to extend the clock frequency up to 480 Mhz. */
+ /* Enable Overdrive to extend the clock frequency up to 480 MHz. */
regval = getreg32(STM32_SYSCFG_PWRCR);
regval |= SYSCFG_PWRCR_ODEN;
diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.c b/arch/arm/src/stm32l4/stm32l4_i2c.c
index 7dce6bc29df..5683fe9a3b9 100644
--- a/arch/arm/src/stm32l4/stm32l4_i2c.c
+++ b/arch/arm/src/stm32l4/stm32l4_i2c.c
@@ -79,7 +79,7 @@
* Fast-mode (up to 400 kHz)
* fI2CCLK clock source selection is based on RCC_CCIPR_I2CxSEL
* being set to PCLK and the calculations are based on PCLK frequency
- * of 80 Mhz
+ * of 80 MHz
*
* - Multiple instances (shared bus)
* - Interrupt based operation
@@ -100,7 +100,7 @@
* - Wakeup from Stop mode
* - More effective error reporting to higher layers
* - Slave operation
- * - Support of fI2CCLK frequencies other than 80 Mhz and other clock sources
+ * - Support of fI2CCLK frequencies other than 80 MHz and other clock sources
* - Polled operation (code present but untested)
* - SMBus support
* - Multi-master support
@@ -1349,7 +1349,7 @@ static void stm32l4_i2c_setclock(FAR struct stm32l4_i2c_priv_s *priv,
/* Default timing calculations from original STM32L4 driver: */
/* The Speed and timing calculation are based on the following
- * fI2CCLK = PCLK and is 80 Mhz
+ * fI2CCLK = PCLK and is 80 MHz
* Analog filter is on,
* Digital filter off
* Rise Time is 120 ns and fall is 10 ns
@@ -1400,7 +1400,7 @@ static void stm32l4_i2c_setclock(FAR struct stm32l4_i2c_priv_s *priv,
else if (i2cclk_mhz == 120)
{
/* The Speed and timing calculation are based on the following
- * fI2CCLK = PCLK and is 120 Mhz
+ * fI2CCLK = PCLK and is 120 MHz
* Analog filter is on,
* Digital filter off
* Rise Time is 120 ns and fall is 25 ns
@@ -2378,7 +2378,7 @@ static int stm32l4_i2c_init(FAR struct stm32l4_i2c_priv_s *priv)
/* TODO:
* - Provide means to set peripheral clock source via RCC_CCIPR_I2CxSEL
- * - Make clock source Kconfigurable (currently PCLK = 80 Mhz)
+ * - Make clock source Kconfigurable (currently PCLK = 80 MHz)
*/
/* Force a frequency update */
diff --git a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c
index 71caf84e47e..6126c880fc4 100644
--- a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c
+++ b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c
@@ -772,7 +772,7 @@ static void stm32l4_stdclockconfig(void)
/* Switch to Range 1 boost mode to support system frequencies up to
* 120 MHz.
- * If any PLL has output frequency higher than 80 Mhz, Range 1 boost
+ * If any PLL has output frequency higher than 80 MHz, Range 1 boost
* mode needs to be used (RM0432, "6.2.9 Clock source frequency versus
* voltage scaling").
* Range 2 is not supported.
diff --git a/arch/mips/src/pic32mx/pic32mx-ethernet.c b/arch/mips/src/pic32mx/pic32mx-ethernet.c
index 55f8e81107a..8f6df2bb275 100644
--- a/arch/mips/src/pic32mx/pic32mx-ethernet.c
+++ b/arch/mips/src/pic32mx/pic32mx-ethernet.c
@@ -2927,7 +2927,7 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv)
/* The RMII/MII of operation can be selected by strap options or register
* control (using the RBR register). For RMII mode, it is required to use
* the strap option, since it requires a 50 MHz clock instead of the normal
- * 25 Mhz.
+ * 25 MHz.
*/
#endif
diff --git a/arch/mips/src/pic32mz/pic32mz-ethernet.c b/arch/mips/src/pic32mz/pic32mz-ethernet.c
index 14a177c3a34..2d4692d8239 100644
--- a/arch/mips/src/pic32mz/pic32mz-ethernet.c
+++ b/arch/mips/src/pic32mz/pic32mz-ethernet.c
@@ -3094,7 +3094,7 @@ static inline int pic32mz_phyinit(struct pic32mz_driver_s *priv)
/* The RMII/MII of operation can be selected by strap options or register
* control (using the RBR register). For RMII mode, it is required to use
* the strap option, since it requires a 50 MHz clock instead of the normal
- * 25 Mhz.
+ * 25 MHz.
*/
#endif
diff --git a/arch/mips/src/pic32mz/pic32mz-lowinit.c b/arch/mips/src/pic32mz/pic32mz-lowinit.c
index bd0f85cc128..c0a73edc2e1 100644
--- a/arch/mips/src/pic32mz/pic32mz-lowinit.c
+++ b/arch/mips/src/pic32mz/pic32mz-lowinit.c
@@ -217,7 +217,7 @@ static inline void pic32mz_prefetch(void)
}
else
{
- /* For devices with 252 Mhz SYSCLK */
+ /* For devices with 252 MHz SYSCLK */
nwaits = 4;
regval = PRECON_PREFEN_CPUID;
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 5569e1b2500..59f7c40148d 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -10,7 +10,7 @@ choice
default ARCH_CHIP_ESP32
config ARCH_CHIP_ESP32
- bool "Expressif ESP32"
+ bool "Espressif ESP32"
select ARCH_FAMILY_LX6
select XTENSA_HAVE_INTERRUPTS
select ARCH_HAVE_MULTICPU
@@ -18,7 +18,7 @@ config ARCH_CHIP_ESP32
select ARCH_TOOLCHAIN_GNU
select ARCH_GLOBAL_IRQDISABLE
---help---
- The ESP32 is a dual-core system from Expressif with two Harvard
+ The ESP32 is a dual-core system from Espressif with two Harvard
architecture Xtensa LX6 CPUs. All embedded memory, external memory
and peripherals are located on the data bus and/or the instruction
bus of these CPUs. With some minor exceptions, the address mapping
diff --git a/arch/xtensa/src/esp32/esp32_clockconfig.c b/arch/xtensa/src/esp32/esp32_clockconfig.c
index 42a2cfd26ab..59c5fb1d05c 100644
--- a/arch/xtensa/src/esp32/esp32_clockconfig.c
+++ b/arch/xtensa/src/esp32/esp32_clockconfig.c
@@ -6,7 +6,7 @@
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt