mirror of
https://github.com/apache/nuttx.git
synced 2026-09-08 18:06:33 +00:00
Fix typos in comments and documentation (#750)
* Fix typos in comments and documentation
This commit is contained in:
hartmannathan
GitHub
parent
9c7841aff1
commit
bfc153ca27
54 changed files with 133 additions and 134 deletions
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@ -268,7 +268,7 @@ arch/xtensa
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LX6 DPU support:
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arch/xtensa/include/lx6 and arch/xtensa/xtensa/lx6
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Expressif ESP32 implementation of the LX6 DPU:
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Espressif ESP32 implementation of the LX6 DPU:
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arch/xtensa/include/esp32 and arch/xtensa/xtensa/esp32
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arch/z16 - ZiLOG 16-bit processors
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@ -605,7 +605,7 @@ void imxrt_clockconfig(void)
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reg |= IMXRT_LPI2C_CLK_SELECT;
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putreg32(reg, IMXRT_CCM_CSCDR2);
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/* Set LPI2C divider to 5 for 12 Mhz */
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/* Set LPI2C divider to 5 for 12 MHz */
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reg = getreg32(IMXRT_CCM_CSCDR2);
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reg &= ~CCM_CSCDR2_LPI2C_CLK_PODF_MASK;
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@ -197,7 +197,7 @@
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# define SYSCON_FLASHCFG_TIM_3 (2 << SYSCON_FLASHCFG_TIM_SHIFT) /* 3 CPU clock <= 60 MHz CPU clock */
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# define SYSCON_FLASHCFG_TIM_4 (3 << SYSCON_FLASHCFG_TIM_SHIFT) /* 4 CPU clock <= 80 MHz CPU clock */
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# define SYSCON_FLASHCFG_TIM_5 (4 << SYSCON_FLASHCFG_TIM_SHIFT) /* 5 CPU clock <= 100 MHz CPU clock
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* (Up to 120 Mhz for LPC1759/69 only */
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* (Up to 120 MHz for LPC1759/69 only */
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# define SYSCON_FLASHCFG_TIM_6 (5 << SYSCON_FLASHCFG_TIM_SHIFT) /* "safe" setting for any conditions */
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/* Bits 16-31: Reserved */
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@ -227,7 +227,7 @@
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# define SYSCON_FLASHCFG_TIM_2 (2 << SYSCON_FLASHCFG_TIM_SHIFT) /* 3 CPU clock <= 60 MHz CPU clock */
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# define SYSCON_FLASHCFG_TIM_3 (3 << SYSCON_FLASHCFG_TIM_SHIFT) /* 4 CPU clock <= 80 MHz CPU clock */
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# define SYSCON_FLASHCFG_TIM_4 (4 << SYSCON_FLASHCFG_TIM_SHIFT) /* 5 CPU clock <= 100 MHz CPU clock
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* (Up to 120 Mhz for LPC1788x) */
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* (Up to 120 MHz for LPC1788x) */
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# define SYSCON_FLASHCFG_TIM_5 (5 << SYSCON_FLASHCFG_TIM_SHIFT) /* "safe" setting for any conditions */
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/* Bits 16-31: Reserved */
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/* Memory Mapping Control register (MEMMAP - 0x400F C040) */
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@ -1500,7 +1500,7 @@ Nandflash Controller */
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#define CGU_HPFINSEL_SHIFT (0) /* Bits 0-3: Select input to high HPPLL0 */
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#define CGU_HPFINSEL_MASK (15 << CGU_HPFINSEL_SHIFT)
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# define CGU_HPFINSEL_FFAST (CGU_FREQIN_FFAST << CGU_HPFINSEL_SHIFT) /* ffast (12 Mhz) */
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# define CGU_HPFINSEL_FFAST (CGU_FREQIN_FFAST << CGU_HPFINSEL_SHIFT) /* ffast (12 MHz) */
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# define CGU_HPFINSEL_I2SRXBCK0 (CGU_FREQIN_I2SRXBCK0 << CGU_HPFINSEL_SHIFT) /* I2SRX_BCK0 */
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# define CGU_HPFINSEL_I2SRXWS0 (CGU_FREQIN_I2SRXWS0 << CGU_HPFINSEL_SHIFT) /* I2SRX_WS0 */
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# define CGU_HPFINSEL_I2SRXBCK1 (CGU_FREQIN_I2SRXBCK1 << CGU_HPFINSEL_SHIFT) /* I2SRX_BCK1 */
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@ -304,11 +304,11 @@ typedef struct SPIFI_DEVICE_DATA {
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uint16_t subBlkSize; /**< size of sub-block */
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uint16_t pageSize; /**< page size */
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uint32_t maxReadSize; /**< max read allowed in one operation */
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uint8_t maxClkRate; /**< (in Mhz) maximum clock rate (max common speed) */
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uint8_t maxReadRate; /**< (in Mhz) max clock rate for read (driver may utilize fast read) */
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uint8_t maxHSReadRate; /**< (in Mhz) max clock rate for quad / dual read */
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uint8_t maxProgramRate; /**< (in Mhz) max clock rate for program */
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uint8_t maxHSProgramRate; /**< (in Mhz) max clock rate for quad program */
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uint8_t maxClkRate; /**< (in MHz) maximum clock rate (max common speed) */
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uint8_t maxReadRate; /**< (in MHz) max clock rate for read (driver may utilize fast read) */
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uint8_t maxHSReadRate; /**< (in MHz) max clock rate for quad / dual read */
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uint8_t maxProgramRate; /**< (in MHz) max clock rate for program */
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uint8_t maxHSProgramRate; /**< (in MHz) max clock rate for quad program */
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uint8_t initDeInitFxId; /**< init/DeInit fx_id */
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uint8_t clearStatusFxId; /**< clearStatus fx_id */
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uint8_t getStatusFxId; /**< getStatus fx_id */
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@ -1352,7 +1352,7 @@ SPIFI_FAM_NODE_T *spifi_REG_FAMILY_CommonCommandSet(void)
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0x1000, /* sub-block size */
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0x100, /* page size */
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MAX_SINGLE_READ, /* max single read bytes */
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104, /* max clock rate in Mhz */
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104, /* max clock rate in MHz */
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104, /* max read clock rate in MHz */
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104, /* max high speed read clock rate in MHz */
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104, /* max program clock rate in MHz */
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@ -177,8 +177,8 @@ enum scg_sosc_gain_e
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enum scg_sosc_range_e
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{
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SCG_SOSC_RANGE_MID = 2, /* Medium frequency range selected for the crystal OSC (4 Mhz to 8 Mhz). */
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SCG_SOSC_RANGE_HIGH = 3, /* High frequency range selected for the crystal OSC (8 Mhz to 40 Mhz). */
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SCG_SOSC_RANGE_MID = 2, /* Medium frequency range selected for the crystal OSC (4 MHz to 8 MHz). */
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SCG_SOSC_RANGE_HIGH = 3, /* High frequency range selected for the crystal OSC (8 MHz to 40 MHz). */
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};
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struct scg_sosc_config_s
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@ -1221,7 +1221,7 @@ int pmecc_configure(struct sam_nandcs_s *priv, bool protected)
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* case, the ECC computation takes into account the whole spare area
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* minus the ECC area in the ECC computation operation
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*
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* NOTE: At 133 Mhz, the clkctrl field must be programmed with 2,
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* NOTE: At 133 MHz, the clkctrl field must be programmed with 2,
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* indicating that the setup time is 3 clock cycles.
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*/
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@ -266,13 +266,13 @@ static inline void sam_pmcsetup(void)
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if ((getreg32(SAM_PMC_MCKR) & PMC_MCKR_PLLADIV2) != 0)
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{
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/* Divider = 480 Mhz / 2 / 48 Mhz = 5 */
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/* Divider = 480 MHz / 2 / 48 MHz = 5 */
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regval |= PMC_USB_USBDIV(4);
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}
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else
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{
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/* Divider = 480 Mhz / 1 / 48 Mhz = 10 */
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/* Divider = 480 MHz / 1 / 48 MHz = 10 */
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regval |= PMC_USB_USBDIV(9);
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}
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@ -9488,7 +9488,7 @@ config STM32_USB_ITRMP
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The legacy USB in the F1 series shared interrupt lines with USB
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device and CAN1. In the F3 series, a hardware options was added to
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either retain the legacy F1 behavior or to map the USB interrupts to
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there own dedicated vectors. The option is available only for the
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their own dedicated vectors. The option is available only for the
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F3 family and selects the use of the dedicated USB interrupts.
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menu "CAN driver configuration"
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@ -756,7 +756,7 @@ static void stm32_stdclockconfig(void)
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#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F446) || \
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defined(CONFIG_STM32_STM32F469)
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/* Enable the Over-drive to extend the clock frequency to 180 Mhz */
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/* Enable the Over-drive to extend the clock frequency to 180 MHz */
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regval = getreg32(STM32_PWR_CR);
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regval |= PWR_CR_ODEN;
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@ -806,9 +806,9 @@ static void stm32_stdclockconfig(void)
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/* Over-drive is needed if
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* - Voltage output scale 1 mode is selected and SYSCLK frequency is
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* over 180 Mhz.
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* over 180 MHz.
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* - Voltage output scale 2 mode is selected and SYSCLK frequence is
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* over 168 Mhz.
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* over 168 MHz.
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*/
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if ((STM32_PWR_VOS_SCALE == PWR_CR1_VOS_SCALE_1 &&
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@ -817,7 +817,7 @@ static void stm32_stdclockconfig(void)
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STM32_SYSCLK_FREQUENCY > 168000000))
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{
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/* Enable the Over-drive to extend the clock frequency up to
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* 216 Mhz.
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* 216 MHz.
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*/
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regval = getreg32(STM32_PWR_CR1);
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@ -803,9 +803,9 @@ static void stm32_stdclockconfig(void)
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/* Over-drive is needed if
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* - Voltage output scale 1 mode is selected and SYSCLK frequency is
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* over 180 Mhz.
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* over 180 MHz.
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* - Voltage output scale 2 mode is selected and SYSCLK frequence is
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* over 168 Mhz.
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* over 168 MHz.
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*/
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if ((STM32_PWR_VOS_SCALE == PWR_CR1_VOS_SCALE_1 &&
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@ -814,7 +814,7 @@ static void stm32_stdclockconfig(void)
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STM32_SYSCLK_FREQUENCY > 168000000))
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{
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/* Enable the Over-drive to extend the clock frequency up to
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* 216 Mhz.
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* 216 MHz.
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*/
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regval = getreg32(STM32_PWR_CR1);
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@ -820,9 +820,9 @@ static void stm32_stdclockconfig(void)
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/* Over-drive is needed if
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* - Voltage output scale 1 mode is selected and SYSCLK frequency is
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* over 180 Mhz.
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* over 180 MHz.
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* - Voltage output scale 2 mode is selected and SYSCLK frequence is
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* over 168 Mhz.
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* over 168 MHz.
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*/
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if ((STM32_PWR_VOS_SCALE == PWR_CR1_VOS_SCALE_1 &&
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@ -831,7 +831,7 @@ static void stm32_stdclockconfig(void)
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STM32_SYSCLK_FREQUENCY > 168000000))
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{
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/* Enable the Over-drive to extend the clock frequency up to
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* 216 Mhz.
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* 216 MHz.
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*/
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regval = getreg32(STM32_PWR_CR1);
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@ -818,7 +818,7 @@ static void stm32_stdclockconfig(void)
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/* Over-drive is needed if
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* - Voltage output scale 1 mode is selected and SYSCLK frequency is
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* over 400 Mhz.
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* over 400 MHz.
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*/
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if ((STM32_PWR_VOS_SCALE == PWR_D3CR_VOS_SCALE_1) &&
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@ -830,7 +830,7 @@ static void stm32_stdclockconfig(void)
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regval |= RCC_APB4ENR_SYSCFGEN;
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putreg32(regval, STM32_RCC_APB4ENR);
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/* Enable Overdrive to extend the clock frequency up to 480 Mhz. */
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/* Enable Overdrive to extend the clock frequency up to 480 MHz. */
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regval = getreg32(STM32_SYSCFG_PWRCR);
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regval |= SYSCFG_PWRCR_ODEN;
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@ -814,7 +814,7 @@ static void stm32_stdclockconfig(void)
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/* Over-drive is needed if
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* - Voltage output scale 1 mode is selected and SYSCLK frequency is
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* over 400 Mhz.
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* over 400 MHz.
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*/
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if ((STM32_PWR_VOS_SCALE == PWR_D3CR_VOS_SCALE_1) &&
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@ -826,7 +826,7 @@ static void stm32_stdclockconfig(void)
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regval |= RCC_APB4ENR_SYSCFGEN;
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putreg32(regval, STM32_RCC_APB4ENR);
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/* Enable Overdrive to extend the clock frequency up to 480 Mhz. */
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/* Enable Overdrive to extend the clock frequency up to 480 MHz. */
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regval = getreg32(STM32_SYSCFG_PWRCR);
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regval |= SYSCFG_PWRCR_ODEN;
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@ -79,7 +79,7 @@
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* Fast-mode (up to 400 kHz)
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* fI2CCLK clock source selection is based on RCC_CCIPR_I2CxSEL
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* being set to PCLK and the calculations are based on PCLK frequency
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* of 80 Mhz
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* of 80 MHz
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*
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* - Multiple instances (shared bus)
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* - Interrupt based operation
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@ -100,7 +100,7 @@
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* - Wakeup from Stop mode
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* - More effective error reporting to higher layers
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* - Slave operation
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* - Support of fI2CCLK frequencies other than 80 Mhz and other clock sources
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* - Support of fI2CCLK frequencies other than 80 MHz and other clock sources
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* - Polled operation (code present but untested)
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* - SMBus support
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* - Multi-master support
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@ -1349,7 +1349,7 @@ static void stm32l4_i2c_setclock(FAR struct stm32l4_i2c_priv_s *priv,
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/* Default timing calculations from original STM32L4 driver: */
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/* The Speed and timing calculation are based on the following
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* fI2CCLK = PCLK and is 80 Mhz
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* fI2CCLK = PCLK and is 80 MHz
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* Analog filter is on,
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* Digital filter off
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* Rise Time is 120 ns and fall is 10 ns
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@ -1400,7 +1400,7 @@ static void stm32l4_i2c_setclock(FAR struct stm32l4_i2c_priv_s *priv,
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else if (i2cclk_mhz == 120)
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{
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/* The Speed and timing calculation are based on the following
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* fI2CCLK = PCLK and is 120 Mhz
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* fI2CCLK = PCLK and is 120 MHz
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* Analog filter is on,
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* Digital filter off
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* Rise Time is 120 ns and fall is 25 ns
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@ -2378,7 +2378,7 @@ static int stm32l4_i2c_init(FAR struct stm32l4_i2c_priv_s *priv)
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/* TODO:
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* - Provide means to set peripheral clock source via RCC_CCIPR_I2CxSEL
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* - Make clock source Kconfigurable (currently PCLK = 80 Mhz)
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* - Make clock source Kconfigurable (currently PCLK = 80 MHz)
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*/
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/* Force a frequency update */
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@ -772,7 +772,7 @@ static void stm32l4_stdclockconfig(void)
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/* Switch to Range 1 boost mode to support system frequencies up to
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* 120 MHz.
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* If any PLL has output frequency higher than 80 Mhz, Range 1 boost
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* If any PLL has output frequency higher than 80 MHz, Range 1 boost
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* mode needs to be used (RM0432, "6.2.9 Clock source frequency versus
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* voltage scaling").
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* Range 2 is not supported.
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@ -2927,7 +2927,7 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv)
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/* The RMII/MII of operation can be selected by strap options or register
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* control (using the RBR register). For RMII mode, it is required to use
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* the strap option, since it requires a 50 MHz clock instead of the normal
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* 25 Mhz.
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* 25 MHz.
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*/
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#endif
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@ -3094,7 +3094,7 @@ static inline int pic32mz_phyinit(struct pic32mz_driver_s *priv)
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/* The RMII/MII of operation can be selected by strap options or register
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* control (using the RBR register). For RMII mode, it is required to use
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* the strap option, since it requires a 50 MHz clock instead of the normal
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* 25 Mhz.
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* 25 MHz.
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*/
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#endif
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@ -217,7 +217,7 @@ static inline void pic32mz_prefetch(void)
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}
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else
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{
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/* For devices with 252 Mhz SYSCLK */
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/* For devices with 252 MHz SYSCLK */
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nwaits = 4;
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regval = PRECON_PREFEN_CPUID;
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@ -10,7 +10,7 @@ choice
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default ARCH_CHIP_ESP32
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config ARCH_CHIP_ESP32
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bool "Expressif ESP32"
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bool "Espressif ESP32"
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select ARCH_FAMILY_LX6
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select XTENSA_HAVE_INTERRUPTS
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select ARCH_HAVE_MULTICPU
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@ -18,7 +18,7 @@ config ARCH_CHIP_ESP32
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select ARCH_TOOLCHAIN_GNU
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select ARCH_GLOBAL_IRQDISABLE
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---help---
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The ESP32 is a dual-core system from Expressif with two Harvard
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The ESP32 is a dual-core system from Espressif with two Harvard
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architecture Xtensa LX6 CPUs. All embedded memory, external memory
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and peripherals are located on the data bus and/or the instruction
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bus of these CPUs. With some minor exceptions, the address mapping
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@ -6,7 +6,7 @@
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Derives from software originally provided by Expressif Systems:
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* Derives from software originally provided by Espressif Systems:
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*
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* Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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*
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@ -6,7 +6,7 @@
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Derives from software originally provided by Expressif Systems:
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* Derives from software originally provided by Espressif Systems:
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*
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* Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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*
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@ -6,7 +6,7 @@
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Derivies from sample code provided by Expressif Systems:
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* Derives from sample code provided by Espressif Systems:
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*
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* Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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*
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|
@ -6,7 +6,7 @@
|
|||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Derivies in part from sample code provided by Expressif Systems:
|
||||
* Derives in part from sample code provided by Espressif Systems:
|
||||
*
|
||||
* Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
*
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Derivies from sample code provided by Expressif Systems:
|
||||
* Derives from sample code provided by Espressif Systems:
|
||||
*
|
||||
* Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
*
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Derivies from sample code provided by Expressif Systems:
|
||||
* Derives from sample code provided by Espressif Systems:
|
||||
*
|
||||
* Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
*
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue