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!arch/stm32: move common sources to common/stm32

Browse source 
BREAKING CHANGE: Common STM32 source and private header files moved to
arch/arm/src/common/stm32. Out-of-tree code that references family-local
common source paths must update includes, build rules, and source paths
to the new common STM32 location.

Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl 2026-05-28 20:50:38 +02:00 • committed by Xiang Xiao
parent 2754c26a9b
commit bf30992c2c
333 changed files with 5163 additions and 4414 deletions
Download patch file Download diff file Expand all files Collapse all files

2
Documentation/implementation/nuttx_initialization_sequence.rst
View file

@ -378,7 +378,7 @@ file and in that case those operations are not performed:
* ``note_register()`` - Registers the standard ``/dev/note``.
* ``arm_serialinit()`` - Initialize the **standard** serial driver
(found at ``nuttx/arch/arm/src/stm32/stm32_serial.c`` STM32 F4).
(found at ``nuttx/arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c`` STM32 F4).
* ``arm_netinitialize()`` - Initialize the network. For the STM32 F4,
this function is in ``nuttx/arch/arm/src/stm32/stm32_eth.c``.

504
arch/arm/src/common/stm32/CMakeLists.txt Normal file
View file

@ -0,0 +1,504 @@
# ##############################################################################
# arch/arm/src/common/stm32/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
target_include_directories(arch BEFORE PUBLIC ${CMAKE_CURRENT_LIST_DIR})
if(CONFIG_BUILD_PROTECTED)
target_include_directories(arch_interface BEFORE
PUBLIC ${CMAKE_CURRENT_LIST_DIR})
endif()
set(SRCS)
if(CONFIG_STM32_COMMON_LEGACY)
list(
APPEND
SRCS
stm32_allocateheap_m3m4_v1.c
stm32_start_m3m4_v1.c
stm32_lse_m3m4_v1.c
stm32_lsi_m3m4_v1.c
stm32_irq_m3m4_v1.c
stm32_waste_m3m4_v1.c
stm32_capture_m3m4_v1.c)
if(CONFIG_STM32_HAVE_IP_GPIO_M3M4_V1)
list(APPEND SRCS stm32_gpio_m3m4_v1v2.c)
endif()
if(CONFIG_STM32_HAVE_IP_EXTI_V1 OR CONFIG_STM32_HAVE_IP_EXTI_V2)
list(APPEND SRCS stm32_exti_gpio_m3m4_v1v2.c)
endif()
if(CONFIG_STM32_HAVE_IP_SPI_V1
OR CONFIG_STM32_HAVE_IP_SPI_V2
OR CONFIG_STM32_HAVE_IP_SPI_V3
OR CONFIG_STM32_HAVE_IP_SPI_V4)
list(APPEND SRCS stm32_spi_m3m4_v2v3v4.c)
endif()
if(CONFIG_STM32_HAVE_IP_I2S_M3M4_V1)
list(APPEND SRCS stm32_i2s_m3m4_v1.c)
endif()
if(CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1)
list(APPEND SRCS stm32_sdio_m3m4_v1.c)
endif()
if(CONFIG_STM32_HAVE_IP_TIMERS)
list(APPEND SRCS stm32_tim_m3m4_v1v2v3.c)
endif()
if(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1)
list(APPEND SRCS stm32_ccm_m3m4_v1.c)
endif()
if(CONFIG_STM32_HAVE_IP_UID_M3M4_V1)
list(APPEND SRCS stm32_uid_m3m4_v1v2.c)
endif()
if(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1)
list(APPEND SRCS stm32_dfumode_m3m4_v1.c)
endif()
if(CONFIG_STM32_HAVE_IP_USART_V1
OR CONFIG_STM32_HAVE_IP_USART_V2
OR CONFIG_STM32_HAVE_IP_USART_V3
OR CONFIG_STM32_HAVE_IP_USART_V4)
list(APPEND SRCS stm32_lowputc_usart_m3m4_v1v2v3v4.c)
endif()
if(CONFIG_STM32_HAVE_IP_FLASH_M3M4_L1)
list(APPEND SRCS stm32_flash_m3m4_l1.c)
elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F1F3)
list(APPEND SRCS stm32_flash_m3m4_f1f3.c)
elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4)
list(APPEND SRCS stm32_flash_m3m4_f2f4.c)
elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_G4)
list(APPEND SRCS stm32_flash_m3m4_g4.c)
endif()
if(CONFIG_STM32_TICKLESS_TIMER)
list(APPEND SRCS stm32_tickless_m3m4_v1.c)
elseif(CONFIG_ARCH_ARMV6M)
list(APPEND SRCS stm32_timerisr_armv6m.c)
else()
list(APPEND SRCS stm32_timerisr_armv7m.c)
endif()
if(CONFIG_BUILD_PROTECTED)
list(APPEND SRCS stm32_userspace_m3m4_v1.c stm32_mpuinit_m3m4_v1.c)
endif()
if(NOT CONFIG_ARCH_IDLE_CUSTOM)
list(APPEND SRCS stm32_idle_m3m4_v1.c)
endif()
list(APPEND SRCS stm32_pmstop_m3m4_v1.c stm32_pmstandby_m3m4_v1.c
stm32_pmsleep_m3m4_v1.c)
if(NOT CONFIG_ARCH_CUSTOM_PMINIT)
list(APPEND SRCS stm32_pminitialize_m3m4_v1.c)
endif()
if(CONFIG_STM32_USART)
if(CONFIG_STM32_HAVE_IP_USART_V1
OR CONFIG_STM32_HAVE_IP_USART_V2
OR CONFIG_STM32_HAVE_IP_USART_V3
OR CONFIG_STM32_HAVE_IP_USART_V4)
list(APPEND SRCS stm32_serial_m3m4_v1v2v3v4.c)
endif()
endif()
if(CONFIG_STM32_DMA)
if(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX)
list(APPEND SRCS stm32_dma_m0_v1_7ch_dmamux.c)
elseif(CONFIG_STM32_HAVE_IP_DMA_V1_7CH)
list(APPEND SRCS stm32_dma_m0_v1_7ch.c)
elseif(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX)
list(APPEND SRCS stm32_dma_m3m4_v1_8ch_dmamux.c)
elseif(CONFIG_STM32_HAVE_IP_DMA_V1_8CH)
list(APPEND SRCS stm32_dma_m3m4_v1_8ch.c)
elseif(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM)
list(APPEND SRCS stm32_dma_m3m4_v2_stream.c)
endif()
endif()
if(CONFIG_TIMER AND CONFIG_STM32_HAVE_IP_TIMERS)
list(APPEND SRCS stm32_tim_m3m4_v1v2v3_lowerhalf.c)
endif()
if(CONFIG_STM32_ONESHOT)
list(APPEND SRCS stm32_oneshot_m3m4_v1.c stm32_oneshot_m3m4_v1_lowerhalf.c)
endif()
if(CONFIG_STM32_FREERUN)
list(APPEND SRCS stm32_freerun_m3m4_v1.c)
endif()
if(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1)
if(CONFIG_STM32_I2C_ALT)
list(APPEND SRCS stm32_i2c_m3m4_v1_alt.c)
elseif(CONFIG_STM32_STM32F4XXX)
list(APPEND SRCS stm32_i2c_m3m4_v1_f40xxx.c)
else()
list(APPEND SRCS stm32_i2c_m3m4_v1.c)
endif()
elseif(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2)
list(APPEND SRCS stm32_i2c_m3m4_v2.c)
if(CONFIG_STM32_I2C_SLAVE)
list(APPEND SRCS stm32_i2c_m3m4_v2_slave.c)
endif()
endif()
if(CONFIG_USBDEV)
if(CONFIG_STM32_USB AND CONFIG_STM32_HAVE_IP_USBDEV_M3M4_V1)
list(APPEND SRCS stm32_usbdev_m3m4_v1.c)
endif()
if(CONFIG_STM32_USBFS AND CONFIG_STM32_HAVE_IP_USBFS_M3M4_V1)
list(APPEND SRCS stm32_usbfs_m3m4_v1.c)
endif()
if(CONFIG_STM32_OTGFS AND CONFIG_STM32_HAVE_IP_OTGFS_M3M4_V1)
list(APPEND SRCS stm32_otgfsdev_m3m4_v1.c)
endif()
if(CONFIG_STM32_OTGHS AND CONFIG_STM32_HAVE_IP_OTGHS_M3M4_V1)
list(APPEND SRCS stm32_otghsdev_m3m4_v1.c)
endif()
endif()
if(CONFIG_STM32_USBHOST)
if(CONFIG_STM32_OTGFS AND CONFIG_STM32_HAVE_IP_OTGFS_M3M4_V1)
list(APPEND SRCS stm32_otgfshost_m3m4_v1.c)
endif()
if(CONFIG_STM32_OTGHS AND CONFIG_STM32_HAVE_IP_OTGHS_M3M4_V1)
list(APPEND SRCS stm32_otghshost_m3m4_v1.c)
endif()
if(CONFIG_STM32_HAVE_COMMON_USBHOST_DEBUG AND (CONFIG_USBHOST_TRACE
OR CONFIG_DEBUG_USB))
list(APPEND SRCS stm32_usbhost_m3m4_v1.c)
endif()
endif()
if(CONFIG_STM32_ETHMAC AND CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1)
list(APPEND SRCS stm32_eth_m3m4_v1.c)
endif()
if(CONFIG_STM32_PWR AND CONFIG_STM32_HAVE_IP_PWR_M3M4_V1)
list(APPEND SRCS stm32_pwr_m3m4_v1.c stm32_exti_pwr_m3m4_v1.c)
endif()
if(CONFIG_STM32_RTC)
if(CONFIG_STM32_HAVE_IP_RTC_COUNTER_M3M4_V1)
list(APPEND SRCS stm32_rtcounter_m3m4_v1.c)
elseif(CONFIG_STM32_HAVE_IP_RTCC_M3M4_L1)
list(APPEND SRCS stm32_rtcc_m3m4_l1.c)
elseif(CONFIG_STM32_HAVE_IP_RTCC_M3M4_F4)
list(APPEND SRCS stm32_rtcc_m3m4_f4.c)
elseif(CONFIG_STM32_HAVE_IP_RTCC_M3M4_V1)
list(APPEND SRCS stm32_rtcc_m3m4_v1.c)
endif()
if(CONFIG_RTC_ALARM)
list(APPEND SRCS stm32_exti_alarm_m3m4_v1.c)
endif()
if(CONFIG_RTC_PERIODIC)
list(APPEND SRCS stm32_exti_wakeup_m3m4_v1.c)
endif()
if(CONFIG_RTC_DRIVER AND CONFIG_STM32_HAVE_IP_RTC_M3M4_V1)
list(APPEND SRCS stm32_rtc_m3m4_v1_lowerhalf.c)
endif()
endif()
if(CONFIG_STM32_ADC
AND (CONFIG_STM32_HAVE_IP_ADC_M3M4_V1
OR CONFIG_STM32_HAVE_IP_ADC_M3M4_V2))
list(APPEND SRCS stm32_adc_m3m4_v1v2.c)
endif()
if(CONFIG_STM32_SDADC AND CONFIG_STM32_HAVE_IP_SDADC_M3M4_V1)
list(APPEND SRCS stm32_sdadc_m3m4_v1.c)
endif()
if(CONFIG_STM32_DAC
AND (CONFIG_STM32_HAVE_IP_DAC_M3M4_V1
OR CONFIG_STM32_HAVE_IP_DAC_M3M4_V2))
list(APPEND SRCS stm32_dac_m3m4_v1.c)
endif()
if(CONFIG_STM32_COMP)
if(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1)
list(APPEND SRCS stm32_comp_m3m4_v1.c)
elseif(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2)
list(APPEND SRCS stm32_comp_m3m4_v2.c)
endif()
endif()
if(CONFIG_STM32_OPAMP AND CONFIG_STM32_HAVE_IP_OPAMP_M3M4_V1)
list(APPEND SRCS stm32_opamp_m3m4_v1.c)
endif()
if(CONFIG_STM32_HRTIM AND CONFIG_STM32_HAVE_IP_HRTIM_M3M4_V1)
list(APPEND SRCS stm32_hrtim_m3m4_v1.c)
endif()
if(CONFIG_STM32_1WIREDRIVER)
list(APPEND SRCS stm32_1wire_m3m4_v1.c)
endif()
if(CONFIG_STM32_HCIUART)
list(APPEND SRCS stm32_hciuart_m3m4_v1.c)
endif()
if(CONFIG_STM32_RNG AND CONFIG_STM32_HAVE_IP_RNG_M3M4_V1)
list(APPEND SRCS stm32_rng_m3m4_v1.c)
endif()
if(CONFIG_STM32_LTDC AND CONFIG_STM32_HAVE_IP_LTDC_M3M4_V1)
list(APPEND SRCS stm32_ltdc_m3m4_v1.c)
endif()
if(CONFIG_STM32_DMA2D AND CONFIG_STM32_HAVE_IP_DMA2D_M3M4_V1)
list(APPEND SRCS stm32_dma2d_m3m4_v1.c)
endif()
if(CONFIG_STM32_PWM)
list(APPEND SRCS stm32_pwm_m3m4_v1v2v3.c)
endif()
if(CONFIG_STM32_PULSECOUNT)
list(APPEND SRCS stm32_pulsecount_m3m4_v1v2v3.c)
endif()
if(CONFIG_STM32_CAP)
list(APPEND SRCS stm32_capture_m3m4_v1_lowerhalf.c)
endif()
if(CONFIG_SENSORS_QENCODER AND CONFIG_STM32_QE)
list(APPEND SRCS stm32_qencoder_m3m4_v1v2v3.c)
endif()
if(CONFIG_STM32_CAN AND CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1)
if(CONFIG_STM32_CAN_CHARDRIVER)
list(APPEND SRCS stm32_can_m3m4_v1.c)
endif()
if(CONFIG_STM32_CAN_SOCKET)
list(APPEND SRCS stm32_can_m3m4_v1_sock.c)
endif()
endif()
if(CONFIG_STM32_FDCAN AND CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1)
if(CONFIG_STM32_FDCAN_CHARDRIVER)
list(APPEND SRCS stm32_fdcan_m3m4_v1.c)
endif()
if(CONFIG_STM32_FDCAN_SOCKET)
list(APPEND SRCS stm32_fdcan_m3m4_v1_sock.c)
endif()
endif()
if(CONFIG_STM32_IWDG AND CONFIG_STM32_HAVE_IP_WDG_M3M4_V1)
list(APPEND SRCS stm32_iwdg_m3m4_v1.c)
endif()
if(CONFIG_STM32_WWDG AND CONFIG_STM32_HAVE_IP_WDG_M3M4_V1)
list(APPEND SRCS stm32_wwdg_m3m4_v1.c)
endif()
if(CONFIG_DEBUG_FEATURES
AND (CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1
OR CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2
OR CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3))
list(APPEND SRCS stm32_dumpgpio_m3m4_v1.c)
endif()
if(CONFIG_STM32_AES AND CONFIG_STM32_HAVE_IP_AES_M3M4_V1)
list(APPEND SRCS stm32_aes_m3m4_v1.c)
endif()
if(CONFIG_CRYPTO_CRYPTODEV_HARDWARE AND CONFIG_STM32_HAVE_IP_CRYPTO_M3M4_V1)
list(APPEND SRCS stm32_crypto_m3m4_v1.c)
endif()
if(CONFIG_STM32_BBSRAM AND CONFIG_STM32_HAVE_IP_BBSRAM_M3M4_V1)
list(APPEND SRCS stm32_bbsram_m3m4_v1.c)
endif()
if(CONFIG_STM32_FMC AND CONFIG_STM32_HAVE_IP_FMC_M3M4_V1)
list(APPEND SRCS stm32_fmc_m3m4_v1.c)
endif()
if(CONFIG_STM32_FSMC AND CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1)
list(APPEND SRCS stm32_fsmc_m3m4_v1.c)
endif()
if(CONFIG_STM32_FOC)
list(APPEND SRCS stm32_foc_m3m4_v1.c)
endif()
if(CONFIG_STM32_CORDIC AND CONFIG_STM32_HAVE_IP_CORDIC_M3M4_V1)
list(APPEND SRCS stm32_cordic_m3m4_v1.c)
endif()
endif()
if(CONFIG_ARCH_CORTEXM0)
list(
APPEND
SRCS
stm32_irq_m0_v1.c
stm32_start_m0_v1.c
stm32_lsi_m0_v1.c)
if(CONFIG_STM32_HAVE_IP_GPIO_M0_V1)
list(APPEND SRCS stm32_gpio_m0_v1.c)
endif()
if(CONFIG_STM32_HAVE_IP_EXTI_V1 OR CONFIG_STM32_HAVE_IP_EXTI_V2)
list(APPEND SRCS stm32_exti_gpio_m0_v1.c)
endif()
if(CONFIG_STM32_HAVE_IP_UID_M0_V1)
list(APPEND SRCS stm32_uid_m0_v1.c)
endif()
if(CONFIG_STM32_HAVE_IP_USART_V3)
list(APPEND SRCS stm32_lowputc_usart_m0_v3.c stm32_serial_m0_v3.c)
elseif(CONFIG_STM32_HAVE_IP_USART_V4)
list(APPEND SRCS stm32_lowputc_usart_m0_v4.c stm32_serial_m0_v4.c)
endif()
if(CONFIG_STM32_RTC_LSECLOCK OR CONFIG_LCD_LSECLOCK)
list(APPEND SRCS stm32_lse_m0_v1.c)
endif()
if(NOT CONFIG_ARCH_IDLE_CUSTOM)
list(APPEND SRCS stm32_idle_m0_v1.c)
endif()
if(NOT CONFIG_SCHED_TICKLESS)
if(CONFIG_ARCH_ARMV6M)
list(APPEND SRCS stm32_timerisr_armv6m.c)
else()
list(APPEND SRCS stm32_timerisr_armv7m.c)
endif()
endif()
if(CONFIG_STM32_PWR)
if(CONFIG_STM32_HAVE_IP_PWR_M0_V1)
list(APPEND SRCS stm32_pwr_m0_v1.c)
elseif(CONFIG_STM32_HAVE_IP_PWR_G0)
list(APPEND SRCS stm32_pwr_m0_g0.c)
endif()
endif()
if(CONFIG_STM32_DMA)
if(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX)
list(APPEND SRCS stm32_dma_m0_v1_7ch_dmamux.c)
elseif(CONFIG_STM32_HAVE_IP_DMA_V1_7CH)
list(APPEND SRCS stm32_dma_m0_v1_7ch.c)
elseif(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX)
list(APPEND SRCS stm32_dma_m3m4_v1_8ch_dmamux.c)
elseif(CONFIG_STM32_HAVE_IP_DMA_V1_8CH)
list(APPEND SRCS stm32_dma_m3m4_v1_8ch.c)
elseif(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM)
list(APPEND SRCS stm32_dma_m3m4_v2_stream.c)
endif()
endif()
if(CONFIG_STM32_PROGMEM)
if(CONFIG_STM32_HAVE_IP_FLASH_M0_G0C0)
list(APPEND SRCS stm32_flash_m0_g0c0.c)
elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_L1)
list(APPEND SRCS stm32_flash_m3m4_l1.c)
elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F1F3)
list(APPEND SRCS stm32_flash_m3m4_f1f3.c)
elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4)
list(APPEND SRCS stm32_flash_m3m4_f2f4.c)
elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_G4)
list(APPEND SRCS stm32_flash_m3m4_g4.c)
endif()
endif()
if(CONFIG_STM32_HAVE_HSI48)
list(APPEND SRCS stm32_hsi48_m0_v1.c)
endif()
if(CONFIG_STM32_USB AND CONFIG_STM32_HAVE_IP_USBDEV_M0_V1)
list(APPEND SRCS stm32_usbdev_m0_v1.c)
endif()
if(CONFIG_STM32_I2C)
list(APPEND SRCS stm32_i2c_m0_v1.c)
endif()
if(CONFIG_STM32_SPI)
list(APPEND SRCS stm32_spi_m0_v1.c)
endif()
if(CONFIG_STM32_PWM)
list(APPEND SRCS stm32_pwm_m0_v1.c)
endif()
if(CONFIG_PULSECOUNT AND CONFIG_STM32_TIM1_PULSECOUNT)
list(APPEND SRCS stm32_pulsecount_m0_v1.c)
endif()
if(CONFIG_STM32_ADC AND CONFIG_STM32_HAVE_IP_ADC_M0_V1)
list(APPEND SRCS stm32_adc_m0_v1.c)
endif()
if(CONFIG_STM32_AES AND CONFIG_STM32_HAVE_IP_AES_M0_V1)
list(APPEND SRCS stm32_aes_m0_v1.c)
endif()
if(CONFIG_STM32_RNG AND CONFIG_STM32_HAVE_IP_RNG_M0_V1)
list(APPEND SRCS stm32_rng_m0_v1.c)
endif()
if(CONFIG_STM32_TIM AND CONFIG_STM32_HAVE_IP_TIMERS_M0_V1)
list(APPEND SRCS stm32_tim_m0_v1.c stm32_tim_m0_v1_lowerhalf.c)
endif()
if(CONFIG_STM32_IWDG AND CONFIG_STM32_HAVE_IP_WDG_M0_V1)
list(APPEND SRCS stm32_iwdg_m0_v1.c)
endif()
if(CONFIG_STM32_WWDG AND CONFIG_STM32_HAVE_IP_WDG_M0_V1)
list(APPEND SRCS stm32_wwdg_m0_v1.c)
endif()
if(CONFIG_STM32_FDCAN AND CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M0_V1)
if(CONFIG_STM32_FDCAN_CHARDRIVER)
list(APPEND SRCS stm32_fdcan_m0_v1.c)
endif()
if(CONFIG_STM32_FDCAN_SOCKET)
list(APPEND SRCS stm32_fdcan_m0_v1_sock.c)
endif()
endif()
if(CONFIG_SENSORS_QENCODER)
list(APPEND SRCS stm32_qencoder_m0_v1.c)
endif()
endif()
if(CONFIG_SENSORS_HALL3PHASE)
list(APPEND SRCS stm32_hall3ph.c)
endif()
target_sources(arch PRIVATE ${SRCS})

549
arch/arm/src/common/stm32/Make.defs Normal file
View file

@ -0,0 +1,549 @@
############################################################################
# arch/arm/src/common/stm32/Make.defs
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
STM32_COMMON_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32
VPATH += common$(DELIM)stm32
INCLUDES += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR)
ARCHINCLUDES += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR)
ARCHXXINCLUDES += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR)
# IP-core driver selection notes (see arch/arm/src/common/stm32/Kconfig.have):
# - Some peripherals use a "register-set" symbol that picks the hardware header
# plus a "driver-variant" symbol that picks the .c file below (e.g. FLASH:
# STM32_HAVE_IP_FLASH_M3M4_V1 header + STM32_HAVE_IP_FLASH_M3M4_F2F4 driver).
# - This file is split into a legacy Cortex-M3/M4 block (the F1/F2/F3/F4/G4/L1
# families, STM32_COMMON_LEGACY) and a Cortex-M0 block (F0/L0/G0/C0,
# ARCH_CORTEXM0). STM32_COMMON_LEGACY -- not a plain Cortex symbol -- gates
# the M3/M4 block because the other Cortex-M4 families (L4/WB/WL5) include
# this file too but provide their own implementation.
ifeq ($(CONFIG_STM32_COMMON_LEGACY),y)
CHIP_CSRCS += stm32_allocateheap_m3m4_v1.c
CHIP_CSRCS += stm32_start_m3m4_v1.c
CHIP_CSRCS += stm32_lse_m3m4_v1.c
CHIP_CSRCS += stm32_lsi_m3m4_v1.c
CHIP_CSRCS += stm32_irq_m3m4_v1.c
ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_USART_V1) \
$(CONFIG_STM32_HAVE_IP_USART_V2) \
$(CONFIG_STM32_HAVE_IP_USART_V3) \
$(CONFIG_STM32_HAVE_IP_USART_V4)),)
CHIP_CSRCS += stm32_lowputc_usart_m3m4_v1v2v3v4.c
endif
ifeq ($(CONFIG_STM32_HAVE_IP_GPIO_M3M4_V1),y)
CHIP_CSRCS += stm32_gpio_m3m4_v1v2.c
endif
ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_EXTI_V1) \
$(CONFIG_STM32_HAVE_IP_EXTI_V2)),)
CHIP_CSRCS += stm32_exti_gpio_m3m4_v1v2.c
endif
ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_L1),y)
CHIP_CSRCS += stm32_flash_m3m4_l1.c
else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F1F3),y)
CHIP_CSRCS += stm32_flash_m3m4_f1f3.c
else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4),y)
CHIP_CSRCS += stm32_flash_m3m4_f2f4.c
else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_G4),y)
CHIP_CSRCS += stm32_flash_m3m4_g4.c
endif
ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_SPI_V1) \
$(CONFIG_STM32_HAVE_IP_SPI_V2) \
$(CONFIG_STM32_HAVE_IP_SPI_V3) \
$(CONFIG_STM32_HAVE_IP_SPI_V4)),)
CHIP_CSRCS += stm32_spi_m3m4_v2v3v4.c
endif
ifeq ($(CONFIG_STM32_HAVE_IP_I2S_M3M4_V1),y)
CHIP_CSRCS += stm32_i2s_m3m4_v1.c
endif
ifeq ($(CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1),y)
CHIP_CSRCS += stm32_sdio_m3m4_v1.c
endif
ifeq ($(CONFIG_STM32_HAVE_IP_TIMERS),y)
CHIP_CSRCS += stm32_tim_m3m4_v1v2v3.c
endif
CHIP_CSRCS += stm32_waste_m3m4_v1.c
ifeq ($(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1),y)
CHIP_CSRCS += stm32_ccm_m3m4_v1.c
endif
ifeq ($(CONFIG_STM32_HAVE_IP_UID_M3M4_V1),y)
CHIP_CSRCS += stm32_uid_m3m4_v1v2.c
endif
CHIP_CSRCS += stm32_capture_m3m4_v1.c
ifeq ($(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1),y)
CHIP_CSRCS += stm32_dfumode_m3m4_v1.c
endif
ifdef CONFIG_STM32_TICKLESS_TIMER
CHIP_CSRCS += stm32_tickless_m3m4_v1.c
else
ifeq ($(CONFIG_ARCH_ARMV6M),y)
CHIP_CSRCS += stm32_timerisr_armv6m.c
else
CHIP_CSRCS += stm32_timerisr_armv7m.c
endif
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += stm32_userspace_m3m4_v1.c
CHIP_CSRCS += stm32_mpuinit_m3m4_v1.c
endif
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CHIP_CSRCS += stm32_idle_m3m4_v1.c
endif
CHIP_CSRCS += stm32_pmstop_m3m4_v1.c
CHIP_CSRCS += stm32_pmstandby_m3m4_v1.c
CHIP_CSRCS += stm32_pmsleep_m3m4_v1.c
ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y)
CHIP_CSRCS += stm32_pminitialize_m3m4_v1.c
endif
ifeq ($(CONFIG_STM32_USART),y)
ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_USART_V1) \
$(CONFIG_STM32_HAVE_IP_USART_V2) \
$(CONFIG_STM32_HAVE_IP_USART_V3) \
$(CONFIG_STM32_HAVE_IP_USART_V4)),)
CHIP_CSRCS += stm32_serial_m3m4_v1v2v3v4.c
endif
endif
ifeq ($(CONFIG_STM32_DMA),y)
ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX),y)
CHIP_CSRCS += stm32_dma_m0_v1_7ch_dmamux.c
else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_7CH),y)
CHIP_CSRCS += stm32_dma_m0_v1_7ch.c
else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX),y)
CHIP_CSRCS += stm32_dma_m3m4_v1_8ch_dmamux.c
else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_8CH),y)
CHIP_CSRCS += stm32_dma_m3m4_v1_8ch.c
else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM),y)
CHIP_CSRCS += stm32_dma_m3m4_v2_stream.c
endif
endif
ifeq ($(CONFIG_TIMER)$(CONFIG_STM32_HAVE_IP_TIMERS),yy)
CHIP_CSRCS += stm32_tim_m3m4_v1v2v3_lowerhalf.c
endif
ifeq ($(CONFIG_STM32_ONESHOT),y)
CHIP_CSRCS += stm32_oneshot_m3m4_v1.c
CHIP_CSRCS += stm32_oneshot_m3m4_v1_lowerhalf.c
endif
ifeq ($(CONFIG_STM32_FREERUN),y)
CHIP_CSRCS += stm32_freerun_m3m4_v1.c
endif
ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1),y)
ifeq ($(CONFIG_STM32_I2C_ALT),y)
CHIP_CSRCS += stm32_i2c_m3m4_v1_alt.c
else ifeq ($(CONFIG_STM32_STM32F4XXX),y)
CHIP_CSRCS += stm32_i2c_m3m4_v1_f40xxx.c
else
CHIP_CSRCS += stm32_i2c_m3m4_v1.c
endif
else ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2),y)
CHIP_CSRCS += stm32_i2c_m3m4_v2.c
ifeq ($(CONFIG_STM32_I2C_SLAVE),y)
CHIP_CSRCS += stm32_i2c_m3m4_v2_slave.c
endif
endif
ifeq ($(CONFIG_USBDEV),y)
ifeq ($(CONFIG_STM32_USB),y)
ifeq ($(CONFIG_STM32_HAVE_IP_USBDEV_M3M4_V1),y)
CHIP_CSRCS += stm32_usbdev_m3m4_v1.c
endif
endif
ifeq ($(CONFIG_STM32_USBFS),y)
ifeq ($(CONFIG_STM32_HAVE_IP_USBFS_M3M4_V1),y)
CHIP_CSRCS += stm32_usbfs_m3m4_v1.c
endif
endif
ifeq ($(CONFIG_STM32_OTGFS),y)
ifeq ($(CONFIG_STM32_HAVE_IP_OTGFS_M3M4_V1),y)
CHIP_CSRCS += stm32_otgfsdev_m3m4_v1.c
endif
endif
ifeq ($(CONFIG_STM32_OTGHS),y)
ifeq ($(CONFIG_STM32_HAVE_IP_OTGHS_M3M4_V1),y)
CHIP_CSRCS += stm32_otghsdev_m3m4_v1.c
endif
endif
endif
ifeq ($(CONFIG_STM32_USBHOST),y)
ifeq ($(CONFIG_STM32_OTGFS),y)
ifeq ($(CONFIG_STM32_HAVE_IP_OTGFS_M3M4_V1),y)
CHIP_CSRCS += stm32_otgfshost_m3m4_v1.c
endif
endif
ifeq ($(CONFIG_STM32_OTGHS),y)
ifeq ($(CONFIG_STM32_HAVE_IP_OTGHS_M3M4_V1),y)
CHIP_CSRCS += stm32_otghshost_m3m4_v1.c
endif
endif
ifeq ($(CONFIG_STM32_HAVE_COMMON_USBHOST_DEBUG),y)
ifeq ($(CONFIG_USBHOST_TRACE),y)
CHIP_CSRCS += stm32_usbhost_m3m4_v1.c
else
ifeq ($(CONFIG_DEBUG_USB),y)
CHIP_CSRCS += stm32_usbhost_m3m4_v1.c
endif
endif
endif
endif
ifeq ($(CONFIG_STM32_ETHMAC),y)
ifeq ($(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1),y)
CHIP_CSRCS += stm32_eth_m3m4_v1.c
endif
endif
ifeq ($(CONFIG_STM32_PWR)$(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1),yy)
CHIP_CSRCS += stm32_pwr_m3m4_v1.c stm32_exti_pwr_m3m4_v1.c
endif
ifeq ($(CONFIG_STM32_RTC),y)
ifeq ($(CONFIG_STM32_HAVE_IP_RTC_COUNTER_M3M4_V1),y)
CHIP_CSRCS += stm32_rtcounter_m3m4_v1.c
else ifeq ($(CONFIG_STM32_HAVE_IP_RTCC_M3M4_L1),y)
CHIP_CSRCS += stm32_rtcc_m3m4_l1.c
else ifeq ($(CONFIG_STM32_HAVE_IP_RTCC_M3M4_F4),y)
CHIP_CSRCS += stm32_rtcc_m3m4_f4.c
else ifeq ($(CONFIG_STM32_HAVE_IP_RTCC_M3M4_V1),y)
CHIP_CSRCS += stm32_rtcc_m3m4_v1.c
endif
ifeq ($(CONFIG_RTC_ALARM),y)
CHIP_CSRCS += stm32_exti_alarm_m3m4_v1.c
endif
ifeq ($(CONFIG_RTC_PERIODIC),y)
CHIP_CSRCS += stm32_exti_wakeup_m3m4_v1.c
endif
ifeq ($(CONFIG_RTC_DRIVER)$(CONFIG_STM32_HAVE_IP_RTC_M3M4_V1),yy)
CHIP_CSRCS += stm32_rtc_m3m4_v1_lowerhalf.c
endif
endif
ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) \
$(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)),)
ifeq ($(CONFIG_STM32_ADC),y)
CHIP_CSRCS += stm32_adc_m3m4_v1v2.c
endif
endif
ifeq ($(CONFIG_STM32_SDADC),y)
ifeq ($(CONFIG_STM32_HAVE_IP_SDADC_M3M4_V1),y)
CHIP_CSRCS += stm32_sdadc_m3m4_v1.c
endif
endif
ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) \
$(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)),)
ifeq ($(CONFIG_STM32_DAC),y)
CHIP_CSRCS += stm32_dac_m3m4_v1.c
endif
endif
ifeq ($(CONFIG_STM32_COMP),y)
ifeq ($(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1),y)
CHIP_CSRCS += stm32_comp_m3m4_v1.c
else ifeq ($(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2),y)
CHIP_CSRCS += stm32_comp_m3m4_v2.c
endif
endif
ifeq ($(CONFIG_STM32_OPAMP)$(CONFIG_STM32_HAVE_IP_OPAMP_M3M4_V1),yy)
CHIP_CSRCS += stm32_opamp_m3m4_v1.c
endif
ifeq ($(CONFIG_STM32_HRTIM),y)
ifeq ($(CONFIG_STM32_HAVE_IP_HRTIM_M3M4_V1),y)
CHIP_CSRCS += stm32_hrtim_m3m4_v1.c
endif
endif
ifeq ($(CONFIG_STM32_1WIREDRIVER),y)
CHIP_CSRCS += stm32_1wire_m3m4_v1.c
endif
ifeq ($(CONFIG_STM32_HCIUART),y)
CHIP_CSRCS += stm32_hciuart_m3m4_v1.c
endif
ifeq ($(CONFIG_STM32_RNG)$(CONFIG_STM32_HAVE_IP_RNG_M3M4_V1),yy)
CHIP_CSRCS += stm32_rng_m3m4_v1.c
endif
ifeq ($(CONFIG_STM32_LTDC),y)
ifeq ($(CONFIG_STM32_HAVE_IP_LTDC_M3M4_V1),y)
CHIP_CSRCS += stm32_ltdc_m3m4_v1.c
endif
endif
ifeq ($(CONFIG_STM32_DMA2D),y)
ifeq ($(CONFIG_STM32_HAVE_IP_DMA2D_M3M4_V1),y)
CHIP_CSRCS += stm32_dma2d_m3m4_v1.c
endif
endif
ifeq ($(CONFIG_STM32_PWM),y)
CHIP_CSRCS += stm32_pwm_m3m4_v1v2v3.c
endif
ifeq ($(CONFIG_STM32_PULSECOUNT),y)
CHIP_CSRCS += stm32_pulsecount_m3m4_v1v2v3.c
endif
ifeq ($(CONFIG_STM32_CAP),y)
CHIP_CSRCS += stm32_capture_m3m4_v1_lowerhalf.c
endif
ifeq ($(CONFIG_SENSORS_QENCODER)$(CONFIG_STM32_QE),yy)
CHIP_CSRCS += stm32_qencoder_m3m4_v1v2v3.c
endif
ifeq ($(CONFIG_STM32_CAN)$(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1),yy)
ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y)
CHIP_CSRCS += stm32_can_m3m4_v1.c
endif
ifeq ($(CONFIG_STM32_CAN_SOCKET),y)
CHIP_CSRCS += stm32_can_m3m4_v1_sock.c
endif
endif
ifeq ($(CONFIG_STM32_FDCAN),y)
ifeq ($(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1),y)
ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y)
CHIP_CSRCS += stm32_fdcan_m3m4_v1.c
endif
ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y)
CHIP_CSRCS += stm32_fdcan_m3m4_v1_sock.c
endif
endif
endif
ifeq ($(CONFIG_STM32_IWDG)$(CONFIG_STM32_HAVE_IP_WDG_M3M4_V1),yy)
CHIP_CSRCS += stm32_iwdg_m3m4_v1.c
endif
ifeq ($(CONFIG_STM32_WWDG)$(CONFIG_STM32_HAVE_IP_WDG_M3M4_V1),yy)
CHIP_CSRCS += stm32_wwdg_m3m4_v1.c
endif
ifeq ($(CONFIG_DEBUG_FEATURES),y)
ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) \
$(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) \
$(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3)),)
CHIP_CSRCS += stm32_dumpgpio_m3m4_v1.c
endif
endif
ifeq ($(CONFIG_STM32_AES)$(CONFIG_STM32_HAVE_IP_AES_M3M4_V1),yy)
CHIP_CSRCS += stm32_aes_m3m4_v1.c
endif
ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE)$(CONFIG_STM32_HAVE_IP_CRYPTO_M3M4_V1),yy)
CHIP_CSRCS += stm32_crypto_m3m4_v1.c
endif
ifeq ($(CONFIG_STM32_BBSRAM),y)
ifeq ($(CONFIG_STM32_HAVE_IP_BBSRAM_M3M4_V1),y)
CHIP_CSRCS += stm32_bbsram_m3m4_v1.c
endif
endif
ifeq ($(CONFIG_STM32_FMC),y)
ifeq ($(CONFIG_STM32_HAVE_IP_FMC_M3M4_V1),y)
CHIP_CSRCS += stm32_fmc_m3m4_v1.c
endif
endif
ifeq ($(CONFIG_STM32_FSMC),y)
ifeq ($(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1),y)
CHIP_CSRCS += stm32_fsmc_m3m4_v1.c
endif
endif
ifeq ($(CONFIG_STM32_FOC),y)
CHIP_CSRCS += stm32_foc_m3m4_v1.c
endif
ifeq ($(CONFIG_STM32_CORDIC)$(CONFIG_STM32_HAVE_IP_CORDIC_M3M4_V1),yy)
CHIP_CSRCS += stm32_cordic_m3m4_v1.c
endif
endif
ifeq ($(CONFIG_ARCH_CORTEXM0),y)
CHIP_CSRCS += stm32_irq_m0_v1.c
ifeq ($(CONFIG_STM32_HAVE_IP_USART_V3),y)
CHIP_CSRCS += stm32_lowputc_usart_m0_v3.c
else ifeq ($(CONFIG_STM32_HAVE_IP_USART_V4),y)
CHIP_CSRCS += stm32_lowputc_usart_m0_v4.c
endif
CHIP_CSRCS += stm32_start_m0_v1.c
CHIP_CSRCS += stm32_lsi_m0_v1.c
ifeq ($(CONFIG_STM32_HAVE_IP_GPIO_M0_V1),y)
CHIP_CSRCS += stm32_gpio_m0_v1.c
endif
ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_EXTI_V1) \
$(CONFIG_STM32_HAVE_IP_EXTI_V2)),)
CHIP_CSRCS += stm32_exti_gpio_m0_v1.c
endif
ifeq ($(CONFIG_STM32_HAVE_IP_USART_V3),y)
CHIP_CSRCS += stm32_serial_m0_v3.c
else ifeq ($(CONFIG_STM32_HAVE_IP_USART_V4),y)
CHIP_CSRCS += stm32_serial_m0_v4.c
endif
ifeq ($(CONFIG_STM32_HAVE_IP_UID_M0_V1),y)
CHIP_CSRCS += stm32_uid_m0_v1.c
endif
ifneq ($(CONFIG_STM32_RTC_LSECLOCK)$(CONFIG_LCD_LSECLOCK),)
CHIP_CSRCS += stm32_lse_m0_v1.c
endif
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CHIP_CSRCS += stm32_idle_m0_v1.c
endif
ifneq ($(CONFIG_SCHED_TICKLESS),y)
ifeq ($(CONFIG_ARCH_ARMV6M),y)
CHIP_CSRCS += stm32_timerisr_armv6m.c
else
CHIP_CSRCS += stm32_timerisr_armv7m.c
endif
endif
ifeq ($(CONFIG_STM32_PWR),y)
ifeq ($(CONFIG_STM32_HAVE_IP_PWR_M0_V1),y)
CHIP_CSRCS += stm32_pwr_m0_v1.c
else ifeq ($(CONFIG_STM32_HAVE_IP_PWR_G0),y)
CHIP_CSRCS += stm32_pwr_m0_g0.c
endif
endif
ifeq ($(CONFIG_STM32_DMA),y)
ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX),y)
CHIP_CSRCS += stm32_dma_m0_v1_7ch_dmamux.c
else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_7CH),y)
CHIP_CSRCS += stm32_dma_m0_v1_7ch.c
else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX),y)
CHIP_CSRCS += stm32_dma_m3m4_v1_8ch_dmamux.c
else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_8CH),y)
CHIP_CSRCS += stm32_dma_m3m4_v1_8ch.c
else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM),y)
CHIP_CSRCS += stm32_dma_m3m4_v2_stream.c
endif
endif
ifeq ($(CONFIG_STM32_PROGMEM),y)
ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M0_G0C0),y)
CHIP_CSRCS += stm32_flash_m0_g0c0.c
else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_L1),y)
CHIP_CSRCS += stm32_flash_m3m4_l1.c
else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F1F3),y)
CHIP_CSRCS += stm32_flash_m3m4_f1f3.c
else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4),y)
CHIP_CSRCS += stm32_flash_m3m4_f2f4.c
else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_G4),y)
CHIP_CSRCS += stm32_flash_m3m4_g4.c
endif
endif
ifeq ($(CONFIG_STM32_HAVE_HSI48),y)
CHIP_CSRCS += stm32_hsi48_m0_v1.c
endif
ifeq ($(CONFIG_STM32_USB),y)
ifeq ($(CONFIG_STM32_HAVE_IP_USBDEV_M0_V1),y)
CHIP_CSRCS += stm32_usbdev_m0_v1.c
endif
endif
ifeq ($(CONFIG_STM32_I2C),y)
CHIP_CSRCS += stm32_i2c_m0_v1.c
endif
ifeq ($(CONFIG_STM32_SPI),y)
CHIP_CSRCS += stm32_spi_m0_v1.c
endif
ifeq ($(CONFIG_STM32_PWM),y)
CHIP_CSRCS += stm32_pwm_m0_v1.c
endif
ifeq ($(CONFIG_PULSECOUNT),y)
ifeq ($(CONFIG_STM32_TIM1_PULSECOUNT),y)
CHIP_CSRCS += stm32_pulsecount_m0_v1.c
endif
endif
ifeq ($(CONFIG_STM32_ADC)$(CONFIG_STM32_HAVE_IP_ADC_M0_V1),yy)
CHIP_CSRCS += stm32_adc_m0_v1.c
endif
ifeq ($(CONFIG_STM32_AES)$(CONFIG_STM32_HAVE_IP_AES_M0_V1),yy)
CHIP_CSRCS += stm32_aes_m0_v1.c
endif
ifeq ($(CONFIG_STM32_RNG)$(CONFIG_STM32_HAVE_IP_RNG_M0_V1),yy)
CHIP_CSRCS += stm32_rng_m0_v1.c
endif
ifeq ($(CONFIG_STM32_TIM)$(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1),yy)
CHIP_CSRCS += stm32_tim_m0_v1.c stm32_tim_m0_v1_lowerhalf.c
endif
ifeq ($(CONFIG_STM32_IWDG)$(CONFIG_STM32_HAVE_IP_WDG_M0_V1),yy)
CHIP_CSRCS += stm32_iwdg_m0_v1.c
endif
ifeq ($(CONFIG_STM32_WWDG)$(CONFIG_STM32_HAVE_IP_WDG_M0_V1),yy)
CHIP_CSRCS += stm32_wwdg_m0_v1.c
endif
ifeq ($(CONFIG_STM32_FDCAN),y)
ifeq ($(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M0_V1),y)
ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y)
CHIP_CSRCS += stm32_fdcan_m0_v1.c
endif
ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y)
CHIP_CSRCS += stm32_fdcan_m0_v1_sock.c
endif
endif
endif
ifeq ($(CONFIG_SENSORS_QENCODER),y)
CHIP_CSRCS += stm32_qencoder_m0_v1.c
endif
endif
ifeq ($(CONFIG_SENSORS_HALL3PHASE),y)
CHIP_CSRCS += stm32_hall3ph.c
endif

36
arch/arm/src/stm32/hardware/stm32_adc.h → arch/arm/src/common/stm32/hardware/stm32_adc.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_adc.h
* arch/arm/src/common/stm32/hardware/stm32_adc.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,31 +20,16 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/* There are 2 main types of ADC IP cores among STM32 chips:
* 1. STM32 ADC IPv1:
* a) basic version for F1 and F37x
* b) extended version for F2, F4, F7, L1:
* 2. STM32 ADC IPv2:
* a) basic version for F0 and L0
* b) extended version for F3 (without F37x), G4, H7, L4, L4+
*
* We also distinguish these variants:
* 1. The modified STM32 ADC IPv1 core for the L1 family, which differs
* too much to keep it in the same file as ADC IPv1.
* 2. The modified STM32 ADC IPv2 core for the G4 family, which differs
* too much to keep it in the same file as ADC IPv2.
*/
#if defined(CONFIG_STM32_HAVE_IP_ADC_M0_V1)
# include "hardware/stm32_adc_v2_m0.h"
#elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) || defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)
#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) && \
defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)
@ -53,18 +38,21 @@
#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1)
# if defined(CONFIG_STM32_STM32L15XX)
# include "stm32_adc_v1l1.h" /* Special case for L1 */
# include "stm32_adc_v1l1.h"
# else
# include "stm32_adc_v1.h"
# endif
#elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)
# if defined(CONFIG_STM32_STM32G4XXX)
# include "stm32_adc_v2g4.h" /* Special case for G4 */
# include "stm32_adc_v2g4.h"
# else
# include "stm32_adc_v2.h"
# endif
#else
# error "STM32 ADC IP version not specified"
#endif
#else
# error "Unsupported STM32 ADC"
#endif
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_H */

8
arch/arm/src/stm32/hardware/stm32_adc_v1.h → arch/arm/src/common/stm32/hardware/stm32_adc_v1.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_adc_v1.h
* arch/arm/src/common/stm32/hardware/stm32_adc_v1.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1_H
/****************************************************************************
* Included Files
@ -637,4 +637,4 @@
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1_H */

8
arch/arm/src/stm32/hardware/stm32_adc_v1l1.h → arch/arm/src/common/stm32/hardware/stm32_adc_v1l1.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_adc_v1l1.h
* arch/arm/src/common/stm32/hardware/stm32_adc_v1l1.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1L1_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1L1_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1L1_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1L1_H
/****************************************************************************
* Included Files
@ -568,4 +568,4 @@
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1L1_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1L1_H */

8
arch/arm/src/stm32/hardware/stm32_adc_v2.h → arch/arm/src/common/stm32/hardware/stm32_adc_v2.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_adc_v2.h
* arch/arm/src/common/stm32/hardware/stm32_adc_v2.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_H
/****************************************************************************
* Included Files
@ -732,4 +732,4 @@
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h → arch/arm/src/common/stm32/hardware/stm32_adc_v2_m0.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h
* arch/arm/src/common/stm32/hardware/stm32_adc_v2_m0.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_M0_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_M0_H
/****************************************************************************
* Included Files
@ -323,4 +323,4 @@
#define ADC_CCR_VLCDEN (1 << 24) /* Bit 24: VLCD enable */
#define ADC_CCR_LFMEN (1 << 25) /* Bit 25: Low Frequency Mode enable */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_M0_H */

8
arch/arm/src/stm32/hardware/stm32_adc_v2g4.h → arch/arm/src/common/stm32/hardware/stm32_adc_v2g4.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_adc_v2g4.h
* arch/arm/src/common/stm32/hardware/stm32_adc_v2g4.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2G4_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2G4_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2G4_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2G4_H
/****************************************************************************
* Included Files
@ -866,4 +866,4 @@
#define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data of the Slave ADC */
#define ADC_CDR_RDATA_SLV_MASK (0xffff << ADC_CDR_RDATA_SLV_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2G4_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2G4_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h → arch/arm/src/common/stm32/hardware/stm32_aes.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h
* arch/arm/src/common/stm32/hardware/stm32_aes.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_AES_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_AES_H
/****************************************************************************
* Included Files
@ -98,4 +98,4 @@
#define AES_SR_RDERR (1 << 1) /* Read Error Flag */
#define AES_SR_WRERR (1 << 2) /* Write Error Flag */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_AES_H */

8
arch/arm/src/stm32/hardware/stm32_bkp.h → arch/arm/src/common/stm32/hardware/stm32_bkp.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_bkp.h
* arch/arm/src/common/stm32/hardware/stm32_bkp.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_BKP_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_BKP_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_BKP_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_BKP_H
/****************************************************************************
* Pre-processor Definitions
@ -174,4 +174,4 @@
#define BKP_DR_SHIFT (0) /* Bits 1510: Backup data */
#define BKP_DR_MASK (0xffff << BKP_DR_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_BKP_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_BKP_H */

43
arch/arm/src/common/stm32/hardware/stm32_can.h Normal file
View file

@ -0,0 +1,43 @@
/****************************************************************************
* arch/arm/src/common/stm32/hardware/stm32_can.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_H
/****************************************************************************
* Included Files
****************************************************************************/
#if (defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M0_V1) + \
defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1)) > 1
# error Only one STM32 CAN IP version must be selected
#endif
#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M0_V1)
# include "hardware/stm32_can_bxcan_m0.h"
#elif defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1)
# include "hardware/stm32_can_bxcan.h"
#else
# error "Unsupported STM32 CAN"
#endif
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_H */

18
arch/arm/src/stm32/hardware/stm32_can.h → arch/arm/src/common/stm32/hardware/stm32_can_bxcan.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_can.h
* arch/arm/src/common/stm32/hardware/stm32_can_bxcan.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_CAN_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_CAN_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_H
/****************************************************************************
* Included Files
@ -437,14 +437,14 @@
/* CAN filter master register */
#define CAN_FMR_FINIT (1 << 0) /* Bit 0: Filter Init Mode */
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1)
# define CAN_FMR_CAN2SB_SHIFT (8) /* Bits 13-8: CAN2 start bank */
# define CAN_FMR_CAN2SB_MASK (0x3f << CAN_FMR_CAN2SB_SHIFT)
#endif
/* CAN filter mode register */
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1)
# define CAN_FM1R_FBM_SHIFT (0) /* Bits 13:0: Filter Mode */
# define CAN_FM1R_FBM_MASK (0x3fff << CAN_FM1R_FBM_SHIFT)
#else
@ -454,7 +454,7 @@
/* CAN filter scale register */
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1)
# define CAN_FS1R_FSC_SHIFT (0) /* Bits 13:0: Filter Scale Configuration */
# define CAN_FS1R_FSC_MASK (0x3fff << CAN_FS1R_FSC_SHIFT)
#else
@ -464,7 +464,7 @@
/* CAN filter FIFO assignment register */
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1)
# define CAN_FFA1R_FFA_SHIFT (0) /* Bits 13:0: Filter FIFO Assignment */
# define CAN_FFA1R_FFA_MASK (0x3fff << CAN_FFA1R_FFA_SHIFT)
#else
@ -474,7 +474,7 @@
/* CAN filter activation register */
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1)
# define CAN_FA1R_FACT_SHIFT (0) /* Bits 13:0: Filter Active */
# define CAN_FA1R_FACT_MASK (0x3fff << CAN_FA1R_FACT_SHIFT)
#else
@ -494,4 +494,4 @@
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_CAN_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_can.h → arch/arm/src/common/stm32/hardware/stm32_can_bxcan_m0.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_can.h
* arch/arm/src/common/stm32/hardware/stm32_can_bxcan_m0.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_M0_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_M0_H
/****************************************************************************
* Included Files
@ -453,4 +453,4 @@
#define CAN_FA1R_FACT_SHIFT (0) /* Bits 13:0: Filter Active */
#define CAN_FA1R_FACT_MASK (0x3fff << CAN_FA1R_FACT_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_M0_H */

45
arch/arm/src/common/stm32/hardware/stm32_comp.h Normal file
View file

@ -0,0 +1,45 @@
/****************************************************************************
* arch/arm/src/common/stm32/hardware/stm32_comp.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_H
/****************************************************************************
* Included Files
****************************************************************************/
#if (defined(CONFIG_STM32_HAVE_IP_COMP_M0_V1) + \
defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) + \
defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2)) > 1
# error Only one STM32 COMP IP version must be selected
#endif
#if defined(CONFIG_STM32_HAVE_IP_COMP_M0_V1)
# include "hardware/stm32_comp_m0.h"
#elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) || \
defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2)
# include "hardware/stm32_comp_v1v2.h"
#else
# error "Unsupported STM32 COMP"
#endif
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h → arch/arm/src/common/stm32/hardware/stm32_comp_m0.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h
* arch/arm/src/common/stm32/hardware/stm32_comp_m0.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_M0_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_M0_H
/****************************************************************************
* Included Files
@ -121,4 +121,4 @@
#define COMP_CSR_COMP2OUT (1 << 14) /* Bit 14: Comparator 1 output */
#define COMP_CSR_COMP2LOCK (1 << 15) /* Bit 15: Comparator 1 lock */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_M0_H */

12
arch/arm/src/stm32/hardware/stm32_comp.h → arch/arm/src/common/stm32/hardware/stm32_comp_v1v2.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_comp.h
* arch/arm/src/common/stm32/hardware/stm32_comp_v1v2.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_V1V2_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_V1V2_H
/****************************************************************************
* Included Files
@ -41,13 +41,13 @@
#if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1)
# if defined(CONFIG_STM32_STM32F33XX)
# include "stm32f33xxx_comp.h"
# include "hardware/stm32f33xxx_comp.h"
# else
# error "Device not supported."
# endif
#elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2)
# if defined(CONFIG_STM32_STM32G4XXX)
# include "stm32g4xxxx_comp.h"
# include "hardware/stm32g4xxxx_comp.h"
# else
# error "Device not supported."
# endif
@ -57,4 +57,4 @@
#endif /* CONFIG_STM32_COMP */
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_V1V2_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h → arch/arm/src/common/stm32/hardware/stm32_crc.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h
* arch/arm/src/common/stm32/hardware/stm32_crc.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRC_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRC_H
/****************************************************************************
* Included Files
@ -79,4 +79,4 @@
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRC_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h → arch/arm/src/common/stm32/hardware/stm32_crs.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h
* arch/arm/src/common/stm32/hardware/stm32_crs.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRS_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRS_H
/****************************************************************************
* Pre-processor Definitions
@ -100,4 +100,4 @@
#define CRS_ICR_ERRC (1 << 2) /* Bit 2: Error clear flag */
#define CRS_ICR_ESYNCC (1 << 3) /* Bit 3: Expected SYNC clear flag */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRS_H */

45
arch/arm/src/common/stm32/hardware/stm32_dac.h Normal file
View file

@ -0,0 +1,45 @@
/****************************************************************************
* arch/arm/src/common/stm32/hardware/stm32_dac.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_H
/****************************************************************************
* Included Files
****************************************************************************/
#if (defined(CONFIG_STM32_HAVE_IP_DAC_M0_V1) + \
defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) + \
defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)) > 1
# error Only one STM32 DAC IP version must be selected
#endif
#if defined(CONFIG_STM32_HAVE_IP_DAC_M0_V1)
# include "hardware/stm32_dac_m0.h"
#elif defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) || \
defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)
# include "hardware/stm32_dac_v1v2.h"
#else
# error "Unsupported STM32 DAC"
#endif
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h → arch/arm/src/common/stm32/hardware/stm32_dac_m0.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h
* arch/arm/src/common/stm32/hardware/stm32_dac_m0.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_M0_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_M0_H
/****************************************************************************
* Included Files
@ -208,4 +208,4 @@
#define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */
#define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_M0_H */

8
arch/arm/src/stm32/hardware/stm32_dac_v1.h → arch/arm/src/common/stm32/hardware/stm32_dac_v1.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_dac_v1.h
* arch/arm/src/common/stm32/hardware/stm32_dac_v1.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_V1_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_V1_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1_H
/****************************************************************************
* Included Files
@ -312,4 +312,4 @@
#define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */
#define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_V1_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1_H */

8
arch/arm/src/stm32/hardware/stm32_dac.h → arch/arm/src/common/stm32/hardware/stm32_dac_v1v2.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_dac.h
* arch/arm/src/common/stm32/hardware/stm32_dac_v1v2.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1V2_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1V2_H
/****************************************************************************
* Included Files
@ -53,4 +53,4 @@
# error "STM32 DAC IP version not specified"
#endif
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1V2_H */

47
arch/arm/src/common/stm32/hardware/stm32_dbgmcu.h Normal file
View file

@ -0,0 +1,47 @@
/****************************************************************************
* arch/arm/src/common/stm32/hardware/stm32_dbgmcu.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_H
/****************************************************************************
* Included Files
****************************************************************************/
#if (defined(CONFIG_STM32_HAVE_IP_DBGMCU_M0_V1) + \
defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) + \
defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) + \
defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3)) > 1
# error Only one STM32 DBGMCU IP version must be selected
#endif
#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M0_V1)
# include "hardware/stm32_dbgmcu_m0.h"
#elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) || \
defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \
defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3)
# include "hardware/stm32_dbgmcu_v1.h"
#else
# error "Unsupported STM32 DBGMCU"
#endif
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h → arch/arm/src/common/stm32/hardware/stm32_dbgmcu_m0.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h
* arch/arm/src/common/stm32/hardware/stm32_dbgmcu_m0.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DBGMCU_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DBGMCU_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_M0_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_M0_H
/****************************************************************************
* Included Files
@ -77,4 +77,4 @@
# define DBGMCU_APB1_TIM17STOP (1 << 18) /* Bit 16: TIM17 stopped when core is halted */
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DBGMCU_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_M0_H */

12
arch/arm/src/stm32/hardware/stm32_dbgmcu.h → arch/arm/src/common/stm32/hardware/stm32_dbgmcu_v1.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_dbgmcu.h
* arch/arm/src/common/stm32/hardware/stm32_dbgmcu_v1.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DBGMCU_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DBGMCU_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_V1_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_V1_H
/****************************************************************************
* Included Files
@ -93,7 +93,7 @@
/* Debug MCU APB1 freeze register */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2)
# define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */
# define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */
# define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */
@ -130,7 +130,7 @@
/* Debug MCU APB2 freeze register */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2)
# define DBGMCU_APB2_TIM1STOP (1 << 0) /* Bit 0: TIM1 stopped when core is halted */
# define DBGMCU_APB2_TIM8STOP (1 << 1) /* Bit 1: TIM8 stopped when core is halted */
# define DBGMCU_APB2_TIM9STOP (1 << 16) /* Bit 16: TIM9 stopped when core is halted */
@ -194,4 +194,4 @@
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DBGMCU_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_V1_H */

15
arch/arm/src/stm32/hardware/stm32_dma.h → arch/arm/src/common/stm32/hardware/stm32_dma.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_dma.h
* arch/arm/src/common/stm32/hardware/stm32_dma.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_H
/****************************************************************************
* Included Files
@ -41,12 +41,15 @@
# error Only one STM32 DMA IP version must be selected
#endif
#if defined(CONFIG_STM32_HAVE_IP_DMA_V1)
#if defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH) || \
defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) || \
defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH) || \
defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX)
# include "stm32_dma_v1.h"
#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2)
#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM)
# include "stm32_dma_v2.h"
#else
# error "STM32 DMA IP version not specified"
#endif
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_H */

8
arch/arm/src/stm32/hardware/stm32_dma2d.h → arch/arm/src/common/stm32/hardware/stm32_dma2d.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_dma2d.h
* arch/arm/src/common/stm32/hardware/stm32_dma2d.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA2D_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA2D_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA2D_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA2D_H
/****************************************************************************
* Included Files
@ -234,4 +234,4 @@
* Public Types
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA2D_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA2D_H */

25
arch/arm/src/stm32/hardware/stm32_i2c.h → arch/arm/src/common/stm32/hardware/stm32_dma_v1.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_i2c.h
* arch/arm/src/common/stm32/hardware/stm32_dma_v1.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,24 +20,21 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_H
/****************************************************************************
* Included Files
****************************************************************************/
/* There are 2 main types of I2C IP cores among STM32 chips:
* 1. STM32 I2C IPv1 - F1, F2, F4 and L1
* 2. STM32 I2C IPv2 - F0, F3, F7, G0, G4, H7, L0 and L4
*/
#if defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1)
# include "stm32_i2c_v1.h"
#elif defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2)
# include "stm32_i2c_v2.h"
#if defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH) || \
defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX)
# include "hardware/stm32_dma_v1_7ch.h"
#elif defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH) || \
defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX)
# include "hardware/stm32_dma_v1_8ch.h"
#else
# error STM32 I2C IP version not specified
# error "Unsupported STM32 DMA v1"
#endif
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h → arch/arm/src/common/stm32/hardware/stm32_dma_v1_7ch.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h
* arch/arm/src/common/stm32/hardware/stm32_dma_v1_7ch.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_7CH_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_7CH_H
/****************************************************************************
* Pre-processor Definitions
@ -545,4 +545,4 @@
# error "Unknown DMA channel assignments"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_7CH_H */

32
arch/arm/src/stm32/hardware/stm32_dma_v1.h → arch/arm/src/common/stm32/hardware/stm32_dma_v1_8ch.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_dma_v1.h
* arch/arm/src/common/stm32/hardware/stm32_dma_v1_8ch.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V1_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V1_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_8CH_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_8CH_H
/****************************************************************************
* Pre-processor Definitions
@ -139,7 +139,7 @@
#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET)
#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET)
#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET)
#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8)
#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8)
# define STM32_DMA1_CCR8 (STM32_DMA1_BASE+STM32_DMA_CCR8_OFFSET)
#endif
@ -151,7 +151,7 @@
#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET)
#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET)
#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET)
#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8)
#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8)
# define STM32_DMA1_CNDTR8 (STM32_DMA1_BASE+STM32_DMA_CNDTR8_OFFSET)
#endif
@ -163,7 +163,7 @@
#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET)
#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET)
#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET)
#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8)
#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8)
# define STM32_DMA1_CPAR8 (STM32_DMA1_BASE+STM32_DMA_CPAR8_OFFSET)
#endif
@ -175,7 +175,7 @@
#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET)
#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET)
#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET)
#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8)
#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8)
# define STM32_DMA1_CMAR8 (STM32_DMA1_BASE+STM32_DMA_CMAR8_OFFSET)
#endif
@ -188,7 +188,7 @@
#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET)
#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET)
#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET)
#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678)
#if defined(CONFIG_STM32_DMA2_HAVE_CHAN678)
# define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET)
# define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET)
# define STM32_DMA2_CCR8 (STM32_DMA2_BASE+STM32_DMA_CCR8_OFFSET)
@ -200,7 +200,7 @@
#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET)
#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET)
#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET)
#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678)
#if defined(CONFIG_STM32_DMA2_HAVE_CHAN678)
# define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET)
# define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET)
# define STM32_DMA2_CNDTR8 (STM32_DMA2_BASE+STM32_DMA_CNDTR8_OFFSET)
@ -212,7 +212,7 @@
#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET)
#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET)
#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET)
#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678)
#if defined(CONFIG_STM32_DMA2_HAVE_CHAN678)
# define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET)
# define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET)
# define STM32_DMA2_CPAR8 (STM32_DMA2_BASE+STM32_DMA_CPAR8_OFFSET)
@ -224,7 +224,7 @@
#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET)
#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET)
#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET)
#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678)
#if defined(CONFIG_STM32_DMA2_HAVE_CHAN678)
# define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET)
# define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET)
# define STM32_DMA2_CMAR8 (STM32_DMA2_BASE+STM32_DMA_CMAR8_OFFSET)
@ -286,7 +286,7 @@
#define DMA_IFCR_CHAN8_SHIFT (28) /* Bits 31-28: DMA Channel 8 interrupt flag clear */
#define DMA_IFCR_CHAN8_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN8_SHIFT)
#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) || defined(CONFIG_STM32_HAVE_DMA2_CHAN678)
#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) || defined(CONFIG_STM32_DMA2_HAVE_CHAN678)
# define DMA_IFCR_ALLCHANNELS (0xffffffff)
#else
# define DMA_IFCR_ALLCHANNELS (0x0fffffff)
@ -350,14 +350,14 @@
#define STM32_DMA1_CHAN5 (4)
#define STM32_DMA1_CHAN6 (5)
#define STM32_DMA1_CHAN7 (6)
#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8)
#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8)
# define STM32_DMA1_CHAN8 (7)
# define STM32_DMA2_CHAN1 (8)
# define STM32_DMA2_CHAN2 (9)
# define STM32_DMA2_CHAN3 (10)
# define STM32_DMA2_CHAN4 (11)
# define STM32_DMA2_CHAN5 (12)
# if defined(CONFIG_STM32_HAVE_DMA2_CHAN678)
# if defined(CONFIG_STM32_DMA2_HAVE_CHAN678)
# define STM32_DMA2_CHAN6 (13)
# define STM32_DMA2_CHAN7 (14)
# define STM32_DMA2_CHAN8 (15)
@ -368,7 +368,7 @@
# define STM32_DMA2_CHAN3 (9)
# define STM32_DMA2_CHAN4 (10)
# define STM32_DMA2_CHAN5 (11)
# if defined(CONFIG_STM32_HAVE_DMA2_CHAN678)
# if defined(CONFIG_STM32_DMA2_HAVE_CHAN678)
# define STM32_DMA2_CHAN6 (12)
# define STM32_DMA2_CHAN7 (13)
# define STM32_DMA2_CHAN8 (14)
@ -770,4 +770,4 @@
# error "Unknown DMA channel assignments"
#endif
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V1_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_8CH_H */

8
arch/arm/src/stm32/hardware/stm32_dma_v2.h → arch/arm/src/common/stm32/hardware/stm32_dma_v2.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_dma_v2.h
* arch/arm/src/common/stm32/hardware/stm32_dma_v2.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V2_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V2_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V2_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V2_H
/****************************************************************************
* Pre-processor Definitions
@ -558,4 +558,4 @@
#define DMAMAP_TIM8_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
#define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V2_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V2_H */

19
arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h → arch/arm/src/common/stm32/hardware/stm32_dmamux.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h
* arch/arm/src/common/stm32/hardware/stm32_dmamux.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,22 +20,21 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32_HAVE_IP_USART_V1)
# include "hardware/stm32_uart_v1.h"
#elif defined(CONFIG_STM32_HAVE_IP_USART_V2)
# include "hardware/stm32_uart_v2.h"
#if defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX)
# include "hardware/stm32_dmamux_7ch.h"
#elif defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX)
# include "hardware/stm32_dmamux_16ch.h"
#else
# error "Unsupported STM32 M0 USART"
# error "Unsupported STM32 DMAMUX"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_H */

8
arch/arm/src/stm32/hardware/stm32_dmamux.h → arch/arm/src/common/stm32/hardware/stm32_dmamux_16ch.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_dmamux.h
* arch/arm/src/common/stm32/hardware/stm32_dmamux_16ch.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMAMUX_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMAMUX_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_16CH_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_16CH_H
/****************************************************************************
* Included Files
@ -176,4 +176,4 @@
# error "Unsupported STM32 sub family"
#endif
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMAMUX_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_16CH_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h → arch/arm/src/common/stm32/hardware/stm32_dmamux_7ch.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h
* arch/arm/src/common/stm32/hardware/stm32_dmamux_7ch.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_7CH_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_7CH_H
/****************************************************************************
* Included Files
@ -159,4 +159,4 @@
# error "Unsupported STM32 M0 sub family"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_7CH_H */

24
arch/arm/src/stm32/hardware/stm32_eth.h → arch/arm/src/common/stm32/hardware/stm32_eth.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_eth.h
* arch/arm/src/common/stm32/hardware/stm32_eth.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ETH_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ETH_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ETH_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ETH_H
/****************************************************************************
* Included Files
@ -51,7 +51,7 @@
#define STM32_ETH_MACVLANTR_OFFSET 0x001c /* Ethernet MAC VLAN tag register */
#define STM32_ETH_MACRWUFFR_OFFSET 0x0028 /* Ethernet MAC remote wakeup frame filter reg */
#define STM32_ETH_MACPMTCSR_OFFSET 0x002c /* Ethernet MAC PMT control and status register */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1)
# define STM32_ETH_MACDBGR_OFFSET 0x0034 /* Ethernet MAC debug register */
#endif
#define STM32_ETH_MACSR_OFFSET 0x0038 /* Ethernet MAC interrupt status register */
@ -124,7 +124,7 @@
#define STM32_ETH_MACVLANTR (STM32_ETHERNET_BASE+STM32_ETH_MACVLANTR_OFFSET)
#define STM32_ETH_MACRWUFFR (STM32_ETHERNET_BASE+STM32_ETH_MACRWUFFR_OFFSET)
#define STM32_ETH_MACPMTCSR (STM32_ETHERNET_BASE+STM32_ETH_MACPMTCSR_OFFSET)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1)
# define STM32_ETH_MACDBGR (STM32_ETHERNET_BASE+STM32_ETH_MACDBGR_OFFSET)
#endif
#define STM32_ETH_MACSR (STM32_ETHERNET_BASE+STM32_ETH_MACSR_OFFSET)
@ -213,7 +213,7 @@
#define ETH_MACCR_JD (1 << 22) /* Bit 22: Jabber disable */
#define ETH_MACCR_WD (1 << 23) /* Bit 23: Watchdog disable */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1)
# define ETH_MACCR_CSTF (1 << 25) /* Bits 25: CRC stripping for Type frames */
#endif
@ -304,7 +304,7 @@
/* Ethernet MAC debug register */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1)
#define ETH_MACDBGR_MMRPEA (1 << 0) /* Bit 0: MAC MII receive protocol engine active */
#define ETH_MACDBGR_MSFRWCS_SHIFT (1) /* Bits 1-2: MAC small FIFO read / write controllers status */
@ -432,7 +432,7 @@
#define ETH_MMCCR_ROR (1 << 2) /* Bit 2: Reset on read */
#define ETH_MMCCR_MCF (1 << 3) /* Bit 3: MMC counter freeze */
#define ETH_MMCCR_MCP (1 << 4) /* Bit 4: MMC counter preset */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1)
# define ETH_MMCCR_MCFHP (1 << 5) /* Bit 5: MMC counter Full-Half preset */
#endif
@ -469,7 +469,7 @@
#define ETH_PTPTSCR_TSITE (1 << 4) /* Bit 4: Time stamp interrupt trigger enable */
#define ETH_PTPTSCR_TSARU (1 << 5) /* Bit 5: Time stamp addend register update */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1)
#define ETH_PTPTSCR_TSSARFE (1 << 8) /* Bit 8: Time stamp snapshot for all received frames enable */
#define ETH_PTPTSCR_TSSSR (1 << 9) /* Bit 9: Time stamp subsecond rollover: digital or binary rollover control */
#define ETH_PTPTSCR_TSPTPPSV2E (1 << 10) /* Bit 10: Time stamp PTP packet snooping for version2 format enable */
@ -568,7 +568,7 @@
#define ETH_DMABMR_USP (1 << 23) /* Bit 23: Use separate PBL */
#define ETH_DMABMR_FPM (1 << 24) /* Bit 24: 4xPBL mode */
#define ETH_DMABMR_AAB (1 << 25) /* Bit 25: Address-aligned beats */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1)
# define ETH_DMABMR_MB (1 << 26) /* Bit 26: Mixed burst */
#endif
@ -743,7 +743,7 @@
/* RDES0: Receive descriptor Word0 */
#define ETH_RDES0_PCE (1 << 0) /* Bit 0: Payload checksum error */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1)
# define ETH_RDES0_ESA (1 << 0) /* Bit 0: Extended status available */
#endif
#define ETH_RDES0_CE (1 << 1) /* Bit 1: CRC error */
@ -874,4 +874,4 @@ struct eth_rxdesc_s
#endif /* __ASSEMBLY__ */
#endif /* STM32_NETHERNET > 0 */
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ETH_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ETH_H */

49
arch/arm/src/common/stm32/hardware/stm32_exti.h Normal file
View file

@ -0,0 +1,49 @@
/****************************************************************************
* arch/arm/src/common/stm32/hardware/stm32_exti.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_H
/****************************************************************************
* Included Files
****************************************************************************/
/* The EXTI IP version (V1/V2) is independent of the CPU core. The M0 and
* M3/M4 ports currently keep separate register headers, so the file is
* chosen by the standard NuttX core symbol (CONFIG_ARCH_CORTEXM0) while the
* version is core-agnostic.
*/
#if (defined(CONFIG_STM32_HAVE_IP_EXTI_V1) + \
defined(CONFIG_STM32_HAVE_IP_EXTI_V2)) > 1
# error Only one STM32 EXTI IP version must be selected
#endif
#if !(defined(CONFIG_STM32_HAVE_IP_EXTI_V1) || defined(CONFIG_STM32_HAVE_IP_EXTI_V2))
# error "Unsupported STM32 EXTI"
#elif defined(CONFIG_ARCH_CORTEXM0)
# include "hardware/stm32_exti_v1v2_m0.h"
#else
# include "hardware/stm32_exti_v1v2.h"
#endif
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_H */

12
arch/arm/src/stm32/hardware/stm32_exti.h → arch/arm/src/common/stm32/hardware/stm32_exti_v1v2.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_exti.h
* arch/arm/src/common/stm32/hardware/stm32_exti_v1v2.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_EXTI_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_EXTI_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_H
/****************************************************************************
* Included Files
@ -55,7 +55,7 @@
# define STM32_EXTI1_MASK 0xffffffff
# define STM32_NEXTI2 4
# define STM32_EXTI2_MASK 0x0000000f
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V1)
# define STM32_NEXTI 23
# define STM32_EXTI_MASK 0x007fffff
#endif
@ -132,7 +132,7 @@
# define EXTI_COMP1 (1 << 21) /* EXTI line 21 is connected to the Comparator 1 wakeup event */
# define EXTI_COMP2 (1 << 22) /* EXTI line 22 is connected to the Comparator 2 wakeup event */
# define EXTI_RTC_ACQUIRE (1 << 23) /* EXTI line 23 is connected to the channel acquisition interrupt */
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V1)
# define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */
# define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */
# define EXTI_OTGFS_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB OTG FS Wakeup event */
@ -228,4 +228,4 @@
# define STM32_EXTI_PR STM32_EXTI1_PR
#endif
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_EXTI_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h → arch/arm/src/common/stm32/hardware/stm32_exti_v1v2_m0.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h
* arch/arm/src/common/stm32/hardware/stm32_exti_v1v2_m0.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_M0_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_M0_H
/****************************************************************************
* Included Files
@ -42,4 +42,4 @@
# error "Unrecognized STM32 M0 EXTI"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_M0_H */

43
arch/arm/src/common/stm32/hardware/stm32_fdcan.h Normal file
View file

@ -0,0 +1,43 @@
/****************************************************************************
* arch/arm/src/common/stm32/hardware/stm32_fdcan.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_H
/****************************************************************************
* Included Files
****************************************************************************/
#if (defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M0_V1) + \
defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1)) > 1
# error Only one STM32 FDCAN IP version must be selected
#endif
#if defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M0_V1)
# include "hardware/stm32_fdcan_mcan_m0.h"
#elif defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1)
# include "hardware/stm32_fdcan_mcan.h"
#else
# error "Unsupported STM32 FDCAN"
#endif
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_H */

8
arch/arm/src/stm32/hardware/stm32_fdcan.h → arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_fdcan.h
* arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FDCAN_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FDCAN_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_H
/****************************************************************************
* Included Files
@ -585,4 +585,4 @@
# define EXTFILTER_F1_EFT_CLASSIC (2 << EXTFILTER_F1_EFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */
# define EXTFILTER_F1_EFT_NOXIDAM (3 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from EF1ID to EF2ID, no XIDAM */
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FDCAN_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_fdcan.h → arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan_m0.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_fdcan.h
* arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan_m0.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FDCAN_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FDCAN_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_M0_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_M0_H
/****************************************************************************
* Included Files
@ -579,4 +579,4 @@
# define EXTFILTER_F1_EFT_CLASSIC (2 << EXTFILTER_F1_EFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */
# define EXTFILTER_F1_EFT_NOXIDAM (3 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from EF1ID to EF2ID, no XIDAM */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FDCAN_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_M0_H */

43
arch/arm/src/common/stm32/hardware/stm32_flash.h Normal file
View file

@ -0,0 +1,43 @@
/****************************************************************************
* arch/arm/src/common/stm32/hardware/stm32_flash.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_H
/****************************************************************************
* Included Files
****************************************************************************/
#if (defined(CONFIG_STM32_HAVE_IP_FLASH_M0_V1) + \
defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_V1)) > 1
# error Only one STM32 flash IP version must be selected
#endif
#if defined(CONFIG_STM32_HAVE_IP_FLASH_M0_V1)
# include "hardware/stm32_flash_m0.h"
#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_V1)
# include "hardware/stm32_flash_v1v2.h"
#else
# error "Unsupported STM32 flash"
#endif
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h → arch/arm/src/common/stm32/hardware/stm32_flash_m0.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h
* arch/arm/src/common/stm32/hardware/stm32_flash_m0.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_M0_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_M0_H
/****************************************************************************
* Included Files
@ -42,4 +42,4 @@
# error "Unsupported STM32 M0 FLASH"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_M0_H */

28
arch/arm/src/stm32/hardware/stm32_flash.h → arch/arm/src/common/stm32/hardware/stm32_flash_v1v2.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_flash.h
* arch/arm/src/common/stm32/hardware/stm32_flash_v1v2.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FLASH_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FLASH_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_V1V2_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_V1V2_H
/****************************************************************************
* Pre-processor Definitions
@ -45,7 +45,7 @@
#if defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT)
# if defined(CONFIG_STM32_STM32L15XX)
# if defined(CONFIG_STM32_HIGHDENSITY)
# if defined(CONFIG_STM32L1_HIGHDENSITY)
/* Different STM32L1xxx MCU version are now called by different 'categories'
* instead of 'densities'. Cat.5 MCU can have up to 512KB of FLASH.
@ -102,7 +102,7 @@
# define STM32_FLASH_NPAGES 128
# define STM32_FLASH_PAGESIZE 2048
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4)
# define STM32_FLASH_NPAGES 8
# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (3 * 128))
# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \
@ -125,7 +125,7 @@
/* Define the Valid Configuration the F2 and F4 */
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# if defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4)
# if defined(CONFIG_STM32_FLASH_CONFIG_B)
# define STM32_FLASH_NPAGES 5
@ -308,7 +308,7 @@
# define STM32_FLASH_AR_OFFSET 0x0014
# define STM32_FLASH_OBR_OFFSET 0x001c
# define STM32_FLASH_WRPR_OFFSET 0x0020
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4)
# define STM32_FLASH_OPTCR_OFFSET 0x0014
# endif
#endif
@ -372,7 +372,7 @@
# define STM32_FLASH_AR (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET)
# define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET)
# define STM32_FLASH_WRPR (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET)
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4)
# define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET)
# endif
# if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
@ -447,7 +447,7 @@
defined(CONFIG_STM32_STM32F37XX)
# define FLASH_ACR_PRFTBS (1 << 5) /* Bit 5: FLASH prefetch buffer status */
# endif
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4)
# define FLASH_ACR_PRFTEN (1 << 8) /* FLASH prefetch enable */
# define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */
# define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */
@ -464,7 +464,7 @@
# define FLASH_SR_PGERR (1 << 2) /* Programming Error */
# define FLASH_SR_WRPRT_ERR (1 << 4) /* Write Protection Error */
# define FLASH_SR_EOP (1 << 5) /* End of Operation */
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4)
# define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */
# define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */
# define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */
@ -533,7 +533,7 @@
defined(CONFIG_STM32_STM32F37XX)
# define FLASH_CR_OBL_LAUNCH (1 << 13) /* Bit 13: Force option byte loading */
# endif
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4)
# define FLASH_CR_PG (1 << 0) /* Bit 0: Programming */
# define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */
# define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */
@ -610,7 +610,7 @@
/* Flash Option Control Register (OPTCR) */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#if defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4)
# define FLASH_OPTCR_OPTLOCK (1 << 0) /* Bit 0: Option lock */
# define FLASH_OPTCR_OPTSTRT (1 << 1) /* Bit 1: Option start */
# define FLASH_OPTCR_BORLEV_SHIFT (2) /* Bits 2-3: BOR reset Level */
@ -786,8 +786,8 @@
int stm32_flash_lock(void);
int stm32_flash_unlock(void);
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#if defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4)
int stm32_flash_writeprotect(size_t page, bool enabled);
#endif
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FLASH_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_V1V2_H */

8
arch/arm/src/stm32/hardware/stm32_fmc.h → arch/arm/src/common/stm32/hardware/stm32_fmc.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_fmc.h
* arch/arm/src/common/stm32/hardware/stm32_fmc.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMC_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMC_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FMC_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FMC_H
/****************************************************************************
* Included Files
@ -389,4 +389,4 @@
#define FMC_SDSR_MODES2_SELF_REFRESH (1 << 3)
#define FMC_SDSR_MODES2_POWER_DOWN (2 << 3)
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMC_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FMC_H */

10
arch/arm/src/stm32/hardware/stm32_fsmc.h → arch/arm/src/common/stm32/hardware/stm32_fsmc.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_fsmc.h
* arch/arm/src/common/stm32/hardware/stm32_fsmc.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMSC_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMSC_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FSMC_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FSMC_H
/****************************************************************************
* Included Files
@ -150,7 +150,7 @@
#define FSMC_BCR_WREN (1 << 12) /* Write enable bit */
#define FSMC_BCR_WAITEN (1 << 13) /* Wait enable bit */
#define FSMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#if defined(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1)
# define FSMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */
#endif
#define FSMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */
@ -298,4 +298,4 @@
#define FSMC_PIO4_IOHIZ_MASK (255 << FSMC_PIO4_IOHIZ_SHIFT)
# define FSMC_PIO4_IOHIZ(n) ((n) << FSMC_PIO4_IOHIZ_SHIFT) /* (n)xHCLK n=0..255 */
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMSC_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FSMC_H */

36
arch/arm/src/stm32/hardware/stm32_memorymap.h → arch/arm/src/common/stm32/hardware/stm32_gpio.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_memorymap.h
* arch/arm/src/common/stm32/hardware/stm32_gpio.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,34 +20,30 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_MEMORYMAP_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32_STM32L15XX)
# include "hardware/stm32l15xxx_memorymap.h"
#if defined(CONFIG_STM32_HAVE_IP_GPIO_M0_V1)
# include "hardware/stm32_gpio_v2_m0.h"
#elif defined(CONFIG_STM32_STM32L15XX)
# include "hardware/stm32l15xxx_gpio.h"
#elif defined(CONFIG_STM32_STM32F10XX)
# include "hardware/stm32f10xxx_memorymap.h"
# include "hardware/stm32f10xxx_gpio.h"
#elif defined(CONFIG_STM32_STM32F20XX)
# include "hardware/stm32f20xxx_memorymap.h"
#elif defined(CONFIG_STM32_STM32F30XX)
# include "hardware/stm32f30xxx_memorymap.h"
#elif defined(CONFIG_STM32_STM32F33XX)
# include "hardware/stm32f33xxx_memorymap.h"
#elif defined(CONFIG_STM32_STM32F37XX)
# include "hardware/stm32f37xxx_memorymap.h"
# include "hardware/stm32f20xxx_gpio.h"
#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
defined(CONFIG_STM32_STM32F37XX)
# include "hardware/stm32f30xxx_gpio.h"
#elif defined(CONFIG_STM32_STM32F4XXX)
# include "hardware/stm32f40xxx_memorymap.h"
# include "hardware/stm32f40xxx_gpio.h"
#elif defined(CONFIG_STM32_STM32G4XXX)
# include "hardware/stm32g4xxxx_memorymap.h"
# include "hardware/stm32g4xxxx_gpio.h"
#else
# error "Unsupported STM32 memory map"
# error "Unsupported STM32 GPIO"
#endif
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_MEMORYMAP_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h → arch/arm/src/common/stm32/hardware/stm32_gpio_v2_m0.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h
* arch/arm/src/common/stm32/hardware/stm32_gpio_v2_m0.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_V2_M0_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_V2_M0_H
/****************************************************************************
* Pre-processor Definitions
@ -344,4 +344,4 @@
#define GPIO_BRR(n) (1 << (n))
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_V2_M0_H */

51
arch/arm/src/common/stm32/hardware/stm32_i2c.h Normal file
View file

@ -0,0 +1,51 @@
/****************************************************************************
* arch/arm/src/common/stm32/hardware/stm32_i2c.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_H
/****************************************************************************
* Included Files
****************************************************************************/
#if (defined(CONFIG_STM32_HAVE_IP_I2C_M0_V1) + \
defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) + \
defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2)) > 1
# error Only one STM32 I2C IP version must be selected
#endif
#if defined(CONFIG_STM32_HAVE_IP_I2C_M0_V1)
# include "hardware/stm32_i2c_v2_m0.h"
#elif defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) || defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2)
#if defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1)
# include "stm32_i2c_v1.h"
#elif defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2)
# include "stm32_i2c_v2.h"
#else
# error STM32 I2C IP version not specified
#endif
#else
# error "Unsupported STM32 I2C"
#endif
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_H */

8
arch/arm/src/stm32/hardware/stm32_i2c_v1.h → arch/arm/src/common/stm32/hardware/stm32_i2c_v1.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_i2c_v1.h
* arch/arm/src/common/stm32/hardware/stm32_i2c_v1.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V1_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V1_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V1_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V1_H
/* This file provide definitions for the STM32 I2C IP core 1
*(F1, F2, F4 and L1)
@ -200,4 +200,4 @@
# define I2C_FLTR_DNF_MASK (0xf << I2C_FLTR_DNF_SHIFT)
#endif
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V1_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V1_H */

8
arch/arm/src/stm32/hardware/stm32_i2c_v2.h → arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_i2c_v2.h
* arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V2_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V2_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_H
/* This file provide definitions for the STM32 I2C IP core 2 (F0, F3, F7, G0,
* G4, H7, L0 and L4).
@ -238,4 +238,4 @@
#define I2C_TXDR_MASK (0xff)
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V2_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h → arch/arm/src/common/stm32/hardware/stm32_i2c_v2_m0.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h
* arch/arm/src/common/stm32/hardware/stm32_i2c_v2_m0.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_M0_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_M0_H
/****************************************************************************
* Pre-processor Definitions
@ -224,4 +224,4 @@
#define I2C_TXDR_MASK (0xff)
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_M0_H */

8
arch/arm/src/stm32/hardware/stm32_lcd.h → arch/arm/src/common/stm32/hardware/stm32_lcd.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_lcd.h
* arch/arm/src/common/stm32/hardware/stm32_lcd.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LCD_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LCD_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LCD_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LCD_H
/****************************************************************************
* Included Files
@ -206,4 +206,4 @@
#define LCD_RAMH_S(n) (1 << ((n)-32))
#endif /* STM32_NLCD */
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LCD_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LCD_H */

8
arch/arm/src/stm32/hardware/stm32_ltdc.h → arch/arm/src/common/stm32/hardware/stm32_ltdc.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_ltdc.h
* arch/arm/src/common/stm32/hardware/stm32_ltdc.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LTDC_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LTDC_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LTDC_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LTDC_H
/****************************************************************************
* Included Files
@ -365,4 +365,4 @@
* Public Types
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LTDC_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LTDC_H */

8
arch/arm/src/stm32/hardware/stm32_otghs.h → arch/arm/src/common/stm32/hardware/stm32_otghs.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_otghs.h
* arch/arm/src/common/stm32/hardware/stm32_otghs.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OTGHS_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OTGHS_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_OTGHS_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_OTGHS_H
/****************************************************************************
* Included Files
@ -1108,4 +1108,4 @@
#define OTGHS_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */
/* Bits 5-31: Reserved, must be kept at reset value */
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OTGHS_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_OTGHS_H */

45
arch/arm/src/common/stm32/hardware/stm32_pwr.h Normal file
View file

@ -0,0 +1,45 @@
/****************************************************************************
* arch/arm/src/common/stm32/hardware/stm32_pwr.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_H
/****************************************************************************
* Included Files
****************************************************************************/
#if (defined(CONFIG_STM32_HAVE_IP_PWR_M0_V1) + \
defined(CONFIG_STM32_HAVE_IP_PWR_G0) + \
defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1)) > 1
# error Only one STM32 PWR IP version must be selected
#endif
#if defined(CONFIG_STM32_HAVE_IP_PWR_M0_V1) || \
defined(CONFIG_STM32_HAVE_IP_PWR_G0)
# include "hardware/stm32_pwr_v1_m0_g0.h"
#elif defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1)
# include "hardware/stm32_pwr_v1.h"
#else
# error "Unsupported STM32 PWR"
#endif
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_H */

12
arch/arm/src/stm32/hardware/stm32_pwr.h → arch/arm/src/common/stm32/hardware/stm32_pwr_v1.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_pwr.h
* arch/arm/src/common/stm32/hardware/stm32_pwr_v1.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PWR_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PWR_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_H
/****************************************************************************
* Included Files
@ -77,7 +77,7 @@
# endif
#define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#if defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1)
# define PWR_CR_FPDS (1 << 9) /* Bit 9: Flash power down in Stop mode */
# if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) || \
@ -151,7 +151,7 @@
# define PWR_CSR_EWUP (1 << 8) /* Bit 8: Enable WKUP pin */
#endif
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#if defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1)
# define PWR_CSR_BRE (1 << 9) /* Bit 9: Backup regulator enable */
# define PWR_CSR_VOSRDY (1 << 14) /* Bit 14: Regulator voltage scaling output selection ready bite */
#endif
@ -162,4 +162,4 @@
# define PWR_CSR_ODSWRDY (1 << 17) /* Bit 17: Over Drive Switch ready */
#endif
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PWR_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h → arch/arm/src/common/stm32/hardware/stm32_pwr_v1_m0_g0.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h
* arch/arm/src/common/stm32/hardware/stm32_pwr_v1_m0_g0.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_M0_G0_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_M0_G0_H
/****************************************************************************
* Included Files
@ -42,4 +42,4 @@
# error "Unsupported STM32 M0 PWR"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_M0_G0_H */

69
arch/arm/src/common/stm32/hardware/stm32_rcc.h Normal file
View file

@ -0,0 +1,69 @@
/****************************************************************************
* arch/arm/src/common/stm32/hardware/stm32_rcc.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RCC_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RCC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_ARCH_CHIP_STM32F0)
# include "hardware/stm32f0_rcc.h"
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
# include "hardware/stm32l0_rcc.h"
#elif defined(CONFIG_ARCH_CHIP_STM32G0)
# include "hardware/stm32g0_rcc.h"
#elif defined(CONFIG_ARCH_CHIP_STM32C0)
# include "hardware/stm32c0_rcc.h"
#elif defined(CONFIG_ARCH_CHIP_STM32F1)
# include "hardware/stm32f10xxx_rcc.h"
#elif defined(CONFIG_ARCH_CHIP_STM32F2)
# include "hardware/stm32f20xxx_rcc.h"
#elif defined(CONFIG_ARCH_CHIP_STM32F3)
# if defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F302X8) || \
defined(CONFIG_STM32_STM32F302XC) || \
defined(CONFIG_STM32_STM32F303XC) || \
defined(CONFIG_STM32_STM32F303XE)
# include "hardware/stm32f30xxx_rcc.h"
# elif defined(CONFIG_STM32_STM32F33XX)
# include "hardware/stm32f33xxx_rcc.h"
# elif defined(CONFIG_STM32_STM32F37XX)
# include "hardware/stm32f37xxx_rcc.h"
# else
# error "Unsupported STM32F3 RCC"
# endif
#elif defined(CONFIG_ARCH_CHIP_STM32F4)
# include "hardware/stm32f40xxx_rcc.h"
#elif defined(CONFIG_ARCH_CHIP_STM32G4)
# include "hardware/stm32g4xxxx_rcc.h"
#elif defined(CONFIG_ARCH_CHIP_STM32L1)
# include "hardware/stm32l15xxx_rcc.h"
#else
# error "Unsupported STM32 RCC"
#endif
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RCC_H */

43
arch/arm/src/common/stm32/hardware/stm32_rng.h Normal file
View file

@ -0,0 +1,43 @@
/****************************************************************************
* arch/arm/src/common/stm32/hardware/stm32_rng.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_H
/****************************************************************************
* Included Files
****************************************************************************/
#if (defined(CONFIG_STM32_HAVE_IP_RNG_M0_V1) + \
defined(CONFIG_STM32_HAVE_IP_RNG_M3M4_V1)) > 1
# error Only one STM32 RNG IP version must be selected
#endif
#if defined(CONFIG_STM32_HAVE_IP_RNG_M0_V1)
# include "hardware/stm32_rng_m0.h"
#elif defined(CONFIG_STM32_HAVE_IP_RNG_M3M4_V1)
# include "hardware/stm32_rng_v1.h"
#else
# error "Unsupported STM32 RNG"
#endif
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h → arch/arm/src/common/stm32/hardware/stm32_rng_m0.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h
* arch/arm/src/common/stm32/hardware/stm32_rng_m0.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_M0_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_M0_H
/****************************************************************************
* Included Files
@ -62,4 +62,4 @@
#define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */
#define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_M0_H */

8
arch/arm/src/stm32/hardware/stm32_rng.h → arch/arm/src/common/stm32/hardware/stm32_rng_v1.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_rng.h
* arch/arm/src/common/stm32/hardware/stm32_rng_v1.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_V1_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_V1_H
/****************************************************************************
* Included Files
@ -61,4 +61,4 @@
#define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */
#define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_V1_H */

8
arch/arm/src/stm32/hardware/stm32_rtc.h → arch/arm/src/common/stm32/hardware/stm32_rtc.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_rtc.h
* arch/arm/src/common/stm32/hardware/stm32_rtc.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTC_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTC_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_H
/****************************************************************************
* Pre-processor Definitions
@ -80,4 +80,4 @@
#define RTC_DIVH_RTC_DIV_SHIFT (0) /* Bits 3-0: RTC Clock Divider High */
#define RTC_DIVH_RTC_DIV_MASK (0x0f << RTC_DIVH_RTC_DIV_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTC_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_H */

47
arch/arm/src/common/stm32/hardware/stm32_rtcc.h Normal file
View file

@ -0,0 +1,47 @@
/****************************************************************************
* arch/arm/src/common/stm32/hardware/stm32_rtcc.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_H
/****************************************************************************
* Included Files
****************************************************************************/
#if (defined(CONFIG_STM32_HAVE_IP_RTCC_M0_V1) + \
defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_V1) + \
defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_L1) + \
defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_F4)) > 1
# error Only one STM32 RTCC IP version must be selected
#endif
#if defined(CONFIG_STM32_HAVE_IP_RTCC_M0_V1)
# include "hardware/stm32_rtcc_m0.h"
#elif defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_V1) || \
defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_L1) || \
defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_F4)
# include "hardware/stm32_rtcc_v1.h"
#else
# error "Unsupported STM32 RTCC"
#endif
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h → arch/arm/src/common/stm32/hardware/stm32_rtcc_m0.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h
* arch/arm/src/common/stm32/hardware/stm32_rtcc_m0.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_M0_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_M0_H
/****************************************************************************
* Pre-processor Definitions
@ -311,4 +311,4 @@
#define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */
#define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_M0_H */

8
arch/arm/src/stm32/hardware/stm32_rtcc.h → arch/arm/src/common/stm32/hardware/stm32_rtcc_v1.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_rtcc.h
* arch/arm/src/common/stm32/hardware/stm32_rtcc_v1.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTCC_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTCC_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_V1C_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_V1C_H
/****************************************************************************
* Pre-processor Definitions
@ -405,4 +405,4 @@
#define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */
#define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTCC_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_V1C_H */

8
arch/arm/src/stm32/hardware/stm32_sdio.h → arch/arm/src/common/stm32/hardware/stm32_sdio.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_sdio.h
* arch/arm/src/common/stm32/hardware/stm32_sdio.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SDIO_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SDIO_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SDIO_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SDIO_H
/****************************************************************************
* Pre-processor Definitions
@ -276,4 +276,4 @@
#define SDIO_FIFOCNT_SHIFT (0)
#define SDIO_FIFOCNT_MASK (0x01ffffff << SDIO_FIFOCNT_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SDIO_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SDIO_H */

54
arch/arm/src/common/stm32/hardware/stm32_spi.h Normal file
View file

@ -0,0 +1,54 @@
/****************************************************************************
* arch/arm/src/common/stm32/hardware/stm32_spi.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_H
/****************************************************************************
* Included Files
****************************************************************************/
/* The SPI IP version (V1..V4) is independent of the CPU core. The register
* layout is the same, but the M0 and M3/M4 ports currently keep separate
* register headers, so the file is chosen by the standard NuttX core symbol
* (CONFIG_ARCH_CORTEXM0) while the version is core-agnostic.
*/
#if (defined(CONFIG_STM32_HAVE_IP_SPI_V1) + \
defined(CONFIG_STM32_HAVE_IP_SPI_V2) + \
defined(CONFIG_STM32_HAVE_IP_SPI_V3) + \
defined(CONFIG_STM32_HAVE_IP_SPI_V4)) > 1
# error Only one STM32 SPI IP version must be selected
#endif
#if !(defined(CONFIG_STM32_HAVE_IP_SPI_V1) || \
defined(CONFIG_STM32_HAVE_IP_SPI_V2) || \
defined(CONFIG_STM32_HAVE_IP_SPI_V3) || \
defined(CONFIG_STM32_HAVE_IP_SPI_V4))
# error "Unsupported STM32 SPI"
#elif defined(CONFIG_ARCH_CORTEXM0)
# include "hardware/stm32_spi_v1v2_m0.h"
#else
# include "hardware/stm32_spi_v2v3v4.h"
#endif
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_H */

16
arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h → arch/arm/src/common/stm32/hardware/stm32_spi_v1v2_m0.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h
* arch/arm/src/common/stm32/hardware/stm32_spi_v1v2_m0.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V1V2_M0_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V1V2_M0_H
/****************************************************************************
* Included Files
@ -32,14 +32,12 @@
/* Select STM32 SPI IP core */
#if defined(CONFIG_STM32_STM32F0) || \
defined(CONFIG_STM32_STM32G0) || \
defined(CONFIG_STM32_STM32C0)
#if defined(CONFIG_STM32_HAVE_IP_SPI_V2)
# define HAVE_IP_SPI_V2
#elif defined(CONFIG_STM32_STM32L0)
#elif defined(CONFIG_STM32_HAVE_IP_SPI_V1)
# define HAVE_IP_SPI_V1
#else
# error Unsupported family
# error Unsupported STM32 F0/L0/G0/C0 SPI IP
#endif
/****************************************************************************
@ -229,4 +227,4 @@
#define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */
#define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V1V2_M0_H */

14
arch/arm/src/stm32/hardware/stm32_spi.h → arch/arm/src/common/stm32/hardware/stm32_spi_v2v3v4.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_spi.h
* arch/arm/src/common/stm32/hardware/stm32_spi_v2v3v4.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SPI_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SPI_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V2V3V4_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V2V3V4_H
/****************************************************************************
* Included Files
@ -45,7 +45,7 @@
#undef HAVE_SPI_FIFOS /* No Tx/Rx FIFOs */
#undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */
#if defined(STM32_HAVE_IP_SPI_V2)
#if defined(CONFIG_STM32_HAVE_IP_SPI_V2)
# define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */
# undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */
# define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */
@ -54,7 +54,7 @@
# undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */
#endif
#if defined(STM32_HAVE_IP_SPI_V3)
#if defined(CONFIG_STM32_HAVE_IP_SPI_V3)
# define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */
# undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */
# define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */
@ -63,7 +63,7 @@
# undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */
#endif
#if defined(STM32_HAVE_IP_SPI_V4)
#if defined(CONFIG_STM32_HAVE_IP_SPI_V4)
# define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */
# define HAVE_SPI_I2S_ASTRT /* Supports I2S asynchronous start capability */
# define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */
@ -280,4 +280,4 @@
# define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */
#endif
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SPI_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V2V3V4_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h → arch/arm/src/common/stm32/hardware/stm32_syscfg.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h
* arch/arm/src/common/stm32/hardware/stm32_syscfg.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SYSCFG_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SYSCFG_H
/****************************************************************************
* Included Files
@ -40,4 +40,4 @@
# error "Unsupported STM32 M0 SYSCFG"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SYSCFG_H */

24
arch/arm/src/stm32/hardware/stm32_tim.h → arch/arm/src/common/stm32/hardware/stm32_tim.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_tim.h
* arch/arm/src/common/stm32/hardware/stm32_tim.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,13 +20,26 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_H
/****************************************************************************
* Included Files
****************************************************************************/
#if (defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) + \
defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) + \
defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) + \
defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3)) > 1
# error Only one STM32 TIMER IP version must be selected
#endif
#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1)
# include "hardware/stm32_tim_v3_m0.h"
#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \
defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) || \
defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3)
#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \
defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2)
# include "stm32_tim_v1v2.h"
@ -35,5 +48,8 @@
#else
# error "STM32 TIMER IP version not specified"
#endif
#else
# error "Unsupported STM32 TIM"
#endif
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_H */

8
arch/arm/src/stm32/hardware/stm32_tim_v1v2.h → arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_tim_v1v2.h
* arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V1V2_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V1V2_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V1V2_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V1V2_H
/****************************************************************************
* Pre-processor Definitions
@ -1304,4 +1304,4 @@
#define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V1V2_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V1V2_H */

8
arch/arm/src/stm32/hardware/stm32_tim_v3.h → arch/arm/src/common/stm32/hardware/stm32_tim_v3.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_tim_v3.h
* arch/arm/src/common/stm32/hardware/stm32_tim_v3.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V3_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V3_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_H
/****************************************************************************
* Included Files
@ -1437,4 +1437,4 @@
#define BTIM_ARR_MASK_16 (0xffff << BTIM_ARR_SHIFT) /* Bits 0-15: Auto reload register */
#define BTIM_ARR_MASK_20 (0xfffff << BTIM_ARR_SHIFT) /* Bits 0-19: Auto reload register when BTIM_CR1_DITHEN */
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V3_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h → arch/arm/src/common/stm32/hardware/stm32_tim_v3_m0.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h
* arch/arm/src/common/stm32/hardware/stm32_tim_v3_m0.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_M0_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_M0_H
/****************************************************************************
* Included Files
@ -1148,4 +1148,4 @@
#define BTIM_CNT_UIFCPY (1 << 31) /* Bit 31: UIF copy */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_M0_H */

38
arch/arm/src/stm32f0l0g0/stm32_serial.c → arch/arm/src/common/stm32/hardware/stm32_uart.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/stm32_serial.c
* arch/arm/src/common/stm32/hardware/stm32_uart.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,6 +20,9 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_H
/****************************************************************************
* Included Files
****************************************************************************/
@ -27,20 +30,23 @@
#include <nuttx/config.h>
#include "chip.h"
/* This file is only a thin shell that includes the correct serial
* implementation for the selected STM32 IP core:
* - STM32 UART IP version 1 - F0, L0
* - STM32 UART IP version 2 - G0
*/
#if defined(CONFIG_STM32_HAVE_IP_USART_V1)
# include "stm32_serial_v1.c"
#elif defined(CONFIG_STM32_HAVE_IP_USART_V2)
# include "stm32_serial_v2.c"
#else
# error "Unsupported STM32 M0 serial"
#if (defined(CONFIG_STM32_HAVE_IP_USART_V1) + \
defined(CONFIG_STM32_HAVE_IP_USART_V2) + \
defined(CONFIG_STM32_HAVE_IP_USART_V3) + \
defined(CONFIG_STM32_HAVE_IP_USART_V4)) > 1
# error Only one STM32 USART IP version must be selected
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
#if defined(CONFIG_STM32_HAVE_IP_USART_V1)
# include "hardware/stm32_uart_v1.h"
#elif defined(CONFIG_STM32_HAVE_IP_USART_V2)
# include "hardware/stm32_uart_v2.h"
#elif defined(CONFIG_STM32_HAVE_IP_USART_V3)
# include "hardware/stm32_uart_v3.h"
#elif defined(CONFIG_STM32_HAVE_IP_USART_V4)
# include "hardware/stm32_uart_v4.h"
#else
# error "Unsupported STM32 USART core"
#endif
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_H */

206
arch/arm/src/common/stm32/hardware/stm32_uart_v1.h Normal file
View file

@ -0,0 +1,206 @@
/****************************************************************************
* arch/arm/src/common/stm32/hardware/stm32_uart_v1.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V1_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V1_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */
#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */
#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */
#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */
#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */
#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */
#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */
/* Register Addresses *******************************************************/
#if STM32_NUSART > 0
# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
#endif
#if STM32_NUSART > 1
# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
#endif
#if STM32_NUSART > 2
# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
#endif
#if STM32_NUSART > 3
# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET)
# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET)
# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
#endif
#if STM32_NUSART > 4
# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET)
# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET)
# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
#endif
/* Register Bitfield Definitions ********************************************/
/* Status register */
#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */
#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */
#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */
#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */
#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */
#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */
#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */
#define USART_SR_ALLBITS (0x03ff)
#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */
/* Data register */
#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */
#define USART_DR_MASK (0xff << USART_DR_SHIFT)
/* Baud Rate Register */
#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
/* Control register 1 */
#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */
#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
#define USART_CR1_M (1 << 12) /* Bit 12: word length */
#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */
#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE)
/* Control register 2 */
#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */
#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT)
#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
/* Control register 3 */
#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
/* Guard time and prescaler register */
#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
/* Compatibility definitions ************************************************/
/* F3 Transmit/Read registers */
#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */
#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V1_H */

236
arch/arm/src/common/stm32/hardware/stm32_uart_v2.h Normal file
View file

@ -0,0 +1,236 @@
/****************************************************************************
* arch/arm/src/common/stm32/hardware/stm32_uart_v2.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V2_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V2_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */
#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */
#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */
#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */
#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */
#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */
#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */
/* Register Addresses *******************************************************/
#if STM32_NUSART > 0
# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
#endif
#if STM32_NUSART > 1
# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
#endif
#if STM32_NUSART > 2
# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
#endif
#if STM32_NUSART > 3
# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET)
# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET)
# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
#endif
#if STM32_NUSART > 4
# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET)
# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET)
# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
#endif
#if STM32_NUSART > 5
# define STM32_USART6_SR (STM32_USART6_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART6_DR (STM32_USART6_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART6_BRR (STM32_USART6_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET)
# define STM32_USART6_GTPR (STM32_USART6_BASE+STM32_USART_GTPR_OFFSET)
#endif
#if STM32_NUSART > 6
# define STM32_UART7_SR (STM32_UART7_BASE+STM32_USART_SR_OFFSET)
# define STM32_UART7_DR (STM32_UART7_BASE+STM32_USART_DR_OFFSET)
# define STM32_UART7_BRR (STM32_UART7_BASE+STM32_USART_BRR_OFFSET)
# define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET)
# define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET)
# define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET)
#endif
#if STM32_NUSART > 7
# define STM32_UART8_SR (STM32_UART8_BASE+STM32_USART_SR_OFFSET)
# define STM32_UART8_DR (STM32_UART8_BASE+STM32_USART_DR_OFFSET)
# define STM32_UART8_BRR (STM32_UART8_BASE+STM32_USART_BRR_OFFSET)
# define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET)
# define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET)
# define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET)
#endif
/* Register Bitfield Definitions ********************************************/
/* Status register */
#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */
#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */
#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */
#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */
#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */
#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */
#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */
#define USART_SR_ALLBITS (0x03ff)
#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */
/* Data register */
#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */
#define USART_DR_MASK (0xff << USART_DR_SHIFT)
/* Baud Rate Register */
#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
/* Control register 1 */
#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */
#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
#define USART_CR1_M (1 << 12) /* Bit 12: word length */
#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */
#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE)
/* Control register 2 */
#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */
#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT)
#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
/* Control register 3 */
#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */
/* Guard time and prescaler register */
#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
/* Compatibility definitions ************************************************/
/* F3 Transmit/Read registers */
#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */
#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V2_H */

36
arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h → arch/arm/src/common/stm32/hardware/stm32_uart_v3.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h
* arch/arm/src/common/stm32/hardware/stm32_uart_v3.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V1_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V1_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V3_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V3_H
/****************************************************************************
* Included Files
@ -192,6 +192,8 @@
#define USART_CR2_ADD_SHIFT (24) /* Bits 24-31: Address of the USART node */
#define USART_CR2_ADD_MASK (0xff << USART_CR2_ADD_SHIFT)
#define USART_CR2_ADD8_SHIFT USART_CR2_ADD_SHIFT /* F1/F2/F4-compatible name */
#define USART_CR2_ADD8_MASK USART_CR2_ADD_MASK
/* Control register 3 */
@ -275,6 +277,8 @@
#define USART_ISR_TEACK (1 << 21) /* Bit 20: Transmit enable acknowledge Flag */
#define USART_ISR_REACK (1 << 22) /* Bit 21: Receive enable acknowledge Flag */
#define USART_ISR_ALLBITS (0x007fdfff)
/* ICR */
#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */
@ -300,4 +304,28 @@
#define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */
#define USART_TDR_MASK (0xff << USART_TDR_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V1_H */
/* Compatibility definitions ************************************************/
/* Compatibility with F1/F2/F4 Status Register names. This USART IP replaces
* the SR register with separate ISR/ICR registers; alias the legacy SR names
* so the shared M3/M4 serial driver keeps working on these parts.
*/
#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET
#define USART_SR_PE USART_ISR_PE /* Parity Error */
#define USART_SR_FE USART_ISR_FE /* Framing error */
#define USART_SR_NE USART_ISR_NF /* Noise detected flag */
#define USART_SR_ORE USART_ISR_ORE /* Overrun error */
#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */
#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */
#define USART_SR_TC USART_ISR_TC /* Transmission Complete */
#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */
#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */
#define USART_SR_CTS USART_ISR_CTS /* CTS Flag */
#define USART_SR_ALLBITS USART_ISR_ALLBITS
#define USART_CR1_M USART_CR1_M0
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V3_H */

46
arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h → arch/arm/src/common/stm32/hardware/stm32_uart_v4.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h
* arch/arm/src/common/stm32/hardware/stm32_uart_v4.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V2_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V2_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V4_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V4_H
/****************************************************************************
* Included Files
@ -153,6 +153,14 @@
USART_CR1_PEIE | USART_CR1_CMIE |USART_CR1_RTOIE | USART_CR1_EOBIE |\
USART_CR1_TXFEIE | USART_CR1_RXFFIE)
/* LPUART shares the USART CR1 layout but has no receiver-timeout or
* end-of-block interrupts.
*/
#define LPUART_CR1_ALLINTS \
(USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | USART_CR1_TXEIE |\
USART_CR1_PEIE | USART_CR1_CMIE | USART_CR1_TXFEIE | USART_CR1_RXFFIE)
/* Control register 2 */
#define USART_CR2_SLVEN (1 << 0) /* Bit 0: Synchronous Slave mode enable */
@ -216,6 +224,12 @@
#define USART_CR3_SCARCNT_SHIFT (17) /* Bit 17-19: Smartcard auto-retry count */
#define USART_CR3_SCARCNT_MASK (7 << USART_CR3_SCARCNT_SHIFT)
# define USART_CR3_SCARCNT(n) ((uint32_t)(n) << USART_CR3_SCARCNT_SHIFT)
#define USART_CR3_WUS_SHIFT (20) /* Bit 20-21: Wakeup interrupt flag selection */
#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT)
# define USART_CR3_WUS_ADDR (0 << USART_CR3_WUS_SHIFT)
# define USART_CR3_WUS_STARTBIT (2 << USART_CR3_WUS_SHIFT)
# define USART_CR3_WUS_RXFNE (3 << USART_CR3_WUS_SHIFT)
#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup interrupt enable */
#define USART_CR3_RXFTCFG_SHIFT (25) /* Bit 25-27: Receive FIFO threshold configuration */
#define USART_CR3_RXFTCFG_MASK (7 << USART_CR3_RXFTCFG_SHIFT)
# define USART_CR3_RXFTCFG(n) ((uint32_t)(n) << USART_CR3_RXFTCFG_SHIFT)
@ -349,4 +363,28 @@
# define USART_PRESC_DIV128 (10 << USART_PRESC_SHIFT) /* Input clock divided by 128 */
# define USART_PRESC_DIV256 (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V2_H */
/* Compatibility definitions ************************************************/
/* Compatibility with F1/F2/F4 Status Register names. This USART IP replaces
* the SR register with separate ISR/ICR registers; alias the legacy SR names
* so the shared M3/M4 serial driver keeps working on these parts.
*/
#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET
#define USART_SR_PE USART_ISR_PE /* Parity Error */
#define USART_SR_FE USART_ISR_FE /* Framing error */
#define USART_SR_NE USART_ISR_NE /* Noise detected flag */
#define USART_SR_ORE USART_ISR_ORE /* Overrun error */
#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */
#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */
#define USART_SR_TC USART_ISR_TC /* Transmission Complete */
#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */
#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */
#define USART_SR_CTS USART_ISR_CTS /* CTS Flag */
#define USART_SR_ALLBITS USART_ISR_ALLBITS
#define USART_CR1_M USART_CR1_M0
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V4_H */

43
arch/arm/src/common/stm32/hardware/stm32_usbdev.h Normal file
View file

@ -0,0 +1,43 @@
/****************************************************************************
* arch/arm/src/common/stm32/hardware/stm32_usbdev.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_H
/****************************************************************************
* Included Files
****************************************************************************/
#if (defined(CONFIG_STM32_HAVE_IP_USBDEV_M0_V1) + \
defined(CONFIG_STM32_HAVE_IP_USBDEV_M3M4_V1)) > 1
# error Only one STM32 USB device IP version must be selected
#endif
#if defined(CONFIG_STM32_HAVE_IP_USBDEV_M0_V1)
# include "hardware/stm32_usbdev_m0.h"
#elif defined(CONFIG_STM32_HAVE_IP_USBDEV_M3M4_V1)
# include "hardware/stm32_usbdev_v1.h"
#else
# error "Unsupported STM32 USB device"
#endif
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h → arch/arm/src/common/stm32/hardware/stm32_usbdev_m0.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h
* arch/arm/src/common/stm32/hardware/stm32_usbdev_m0.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_M0_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_M0_H
/****************************************************************************
* Included Files
@ -252,4 +252,4 @@
#define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT)
#endif /* CONFIG_STM32_HAVE_USBDEV */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_M0_H */

8
arch/arm/src/stm32/hardware/stm32_usbdev.h → arch/arm/src/common/stm32/hardware/stm32_usbdev_v1.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_usbdev.h
* arch/arm/src/common/stm32/hardware/stm32_usbdev_v1.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBDEV_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBDEV_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_V1_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_V1_H
/****************************************************************************
* Included Files
@ -224,4 +224,4 @@
#define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT)
#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F37XX */
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBDEV_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_V1_H */

8
arch/arm/src/stm32/hardware/stm32_usbfs.h → arch/arm/src/common/stm32/hardware/stm32_usbfs.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_usbfs.h
* arch/arm/src/common/stm32/hardware/stm32_usbfs.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBFS_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBFS_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBFS_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBFS_H
/****************************************************************************
* Included Files
@ -247,4 +247,4 @@
#define USB_BCDR_DPPU (1 << 15) /* Bit 15: DP pull-up control */
#endif /* CONFIG_STM32_USBFS */
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBFS_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBFS_H */

43
arch/arm/src/common/stm32/hardware/stm32_wdg.h Normal file
View file

@ -0,0 +1,43 @@
/****************************************************************************
* arch/arm/src/common/stm32/hardware/stm32_wdg.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_H
/****************************************************************************
* Included Files
****************************************************************************/
#if (defined(CONFIG_STM32_HAVE_IP_WDG_M0_V1) + \
defined(CONFIG_STM32_HAVE_IP_WDG_M3M4_V1)) > 1
# error Only one STM32 WDG IP version must be selected
#endif
#if defined(CONFIG_STM32_HAVE_IP_WDG_M0_V1)
# include "hardware/stm32_wdg_m0.h"
#elif defined(CONFIG_STM32_HAVE_IP_WDG_M3M4_V1)
# include "hardware/stm32_wdg_v1v2.h"
#else
# error "Unsupported STM32 WDG"
#endif
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h → arch/arm/src/common/stm32/hardware/stm32_wdg_m0.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h
* arch/arm/src/common/stm32/hardware/stm32_wdg_m0.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_M0_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_M0_H
/****************************************************************************
* Included Files
@ -138,4 +138,4 @@
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_M0_H */

8
arch/arm/src/stm32/hardware/stm32_wdg.h → arch/arm/src/common/stm32/hardware/stm32_wdg_v1v2.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_wdg.h
* arch/arm/src/common/stm32/hardware/stm32_wdg_v1v2.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_WDG_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_WDG_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_V1V2_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_V1V2_H
/****************************************************************************
* Included Files
@ -147,4 +147,4 @@
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_WDG_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_V1V2_H */

8
arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h → arch/arm/src/common/stm32/hardware/stm32_wdt.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h
* arch/arm/src/common/stm32/hardware/stm32_wdt.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDT_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDT_H
/****************************************************************************
* Included Files
@ -126,4 +126,4 @@
#define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDT_H */

8
arch/arm/src/stm32/hardware/stm32fxxxxx_otgfs.h → arch/arm/src/common/stm32/hardware/stm32fxxxxx_otgfs.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32fxxxxx_otgfs.h
* arch/arm/src/common/stm32/hardware/stm32fxxxxx_otgfs.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32FXXXXX_OTGFS_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32FXXXXX_OTGFS_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32FXXXXX_OTGFS_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32FXXXXX_OTGFS_H
/****************************************************************************
* Included Files
@ -1112,4 +1112,4 @@
#define OTGFS_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */
/* Bits 5-31: Reserved, must be kept at reset value */
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32FXXXXX_OTGFS_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32FXXXXX_OTGFS_H */

8
arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h → arch/arm/src/common/stm32/hardware/stm32gxxxxx_dac.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h
* arch/arm/src/common/stm32/hardware/stm32gxxxxx_dac.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32GXXXXX_DAC_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32GXXXXX_DAC_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32GXXXXX_DAC_H
#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32GXXXXX_DAC_H
/****************************************************************************
* Included Files
@ -522,4 +522,4 @@
#define DAC_STR_STINCDATA_SHIFT (16) /* DAC channel 1 Sawtooth increment value (12.4 bit format) */
#define DAC_STR_STINCDATA_MASK (0xffff << DAC_STR_STINCDATA_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32GXXXXX_DAC_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32GXXXXX_DAC_H */

10
arch/arm/src/stm32/stm32_1wire.h → arch/arm/src/common/stm32/stm32_1wire.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_1wire.h
* arch/arm/src/common/stm32/stm32_1wire.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_STM32_1WIRE_H
#define __ARCH_ARM_SRC_STM32_STM32_1WIRE_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_1WIRE_H
#define __ARCH_ARM_SRC_COMMON_STM32_STM32_1WIRE_H
/****************************************************************************
* Included Files
@ -29,6 +29,8 @@
#include <nuttx/config.h>
#include <nuttx/1wire/1wire.h>
#include "stm32_uart.h"
/****************************************************************************
@ -71,4 +73,4 @@ struct onewire_dev_s *stm32_1wireinitialize(int port);
int stm32_1wireuninitialize(struct onewire_dev_s *dev);
#endif /* __ARCH_ARM_SRC_STM32_STM32_1WIRE_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_1WIRE_H */

3
arch/arm/src/stm32/stm32_1wire.c → arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_1wire.c
* arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c
*
* SPDX-License-Identifier: Apache-2.0
*
@ -52,6 +52,7 @@
#include "arm_internal.h"
#include "stm32_rcc.h"
#include "stm32_1wire.h"
#include "stm32_rcc.h"
#ifdef HAVE_1WIREDRIVER

20
arch/arm/src/stm32f0l0g0/stm32_lowputc.c → arch/arm/src/common/stm32/stm32_adc.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/stm32_lowputc.c
* arch/arm/src/common/stm32/stm32_adc.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,21 +20,21 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_ADC_H
#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_ADC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32_HAVE_IP_USART_V1)
# include "stm32_lowputc_v1.c"
#elif defined(CONFIG_STM32_HAVE_IP_USART_V2)
# include "stm32_lowputc_v2.c"
#if defined(CONFIG_STM32_HAVE_IP_ADC_M0_V1)
# include "stm32_adc_m0_v1.h"
#elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) || defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)
# include "stm32_adc_m3m4_v1v2.h"
#else
# error "Unsupported STM32 M0 serial"
# error "Unsupported STM32 ADC"
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_ADC_H */

2
arch/arm/src/stm32f0l0g0/stm32_adc.c → arch/arm/src/common/stm32/stm32_adc_m0_v1.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/stm32_adc.c
* arch/arm/src/common/stm32/stm32_adc_m0_v1.c
*
* SPDX-License-Identifier: Apache-2.0
*

10
arch/arm/src/stm32f0l0g0/stm32_adc.h → arch/arm/src/common/stm32/stm32_adc_m0_v1.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0l0g0/stm32_adc.h
* arch/arm/src/common/stm32/stm32_adc_m0_v1.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H
#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V2_M0_H
#define __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V2_M0_H
/****************************************************************************
* Included Files
@ -165,7 +165,7 @@
/* TRG5 and TRG6 reserved */
# define ADC1_EXTSEL_EXTI11 ADC12_CFGR1_EXTSEL_TRG7
#else
# error
# error "Unrecognized STM32 M0 sub-family for ADC EXTSEL"
#endif
/* EXTSEL configuration *****************************************************/
@ -445,4 +445,4 @@ const struct stm32_adc_ops_s
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32_ADC1 */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V2_M0_H */

2
arch/arm/src/stm32/stm32_adc.c → arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_adc.c
* arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c
*
* SPDX-License-Identifier: Apache-2.0
*

10
arch/arm/src/stm32/stm32_adc.h → arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_adc.h
* arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_STM32_ADC_H
#define __ARCH_ARM_SRC_STM32_STM32_ADC_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V1V2_H
#define __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V1V2_H
/****************************************************************************
* Included Files
@ -134,7 +134,7 @@
# undef CONFIG_STM32_TIM4_ADC4
#endif
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1)
# ifndef CONFIG_STM32_TIM5
# undef CONFIG_STM32_TIM5_ADC
# undef CONFIG_STM32_TIM5_ADC1
@ -2342,4 +2342,4 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist,
#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 ||
* CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4
*/
#endif /* __ARCH_ARM_SRC_STM32_STM32_ADC_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V1V2_H */

24
arch/arm/src/stm32/stm32_aes.h → arch/arm/src/common/stm32/stm32_aes.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_aes.h
* arch/arm/src/common/stm32/stm32_aes.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_STM32_AES_H
#define __ARCH_ARM_SRC_STM32_STM32_AES_H
#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_AES_H
#define __ARCH_ARM_SRC_COMMON_STM32_STM32_AES_H
/****************************************************************************
* Included Files
@ -33,14 +33,14 @@
#include "chip.h"
/* Only the STM32L162 devices have AES, but we don't bother with exact macros
* for simplicity.
*/
#ifdef CONFIG_STM32_STM32L15XX
# include "hardware/stm32l15xxx_aes.h"
#else
# error "Unknown chip for AES"
#if defined(CONFIG_STM32_HAVE_IP_AES_M0_V1)
# include "hardware/stm32_aes.h"
#elif defined(CONFIG_STM32_HAVE_IP_AES_M3M4_V1)
# ifdef CONFIG_STM32_STM32L15XX
# include "hardware/stm32l15xxx_aes.h"
# else
# error "Unknown chip for AES"
# endif
#endif
/****************************************************************************
@ -55,4 +55,4 @@
* Inline Functions
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32_STM32_AES_H */
#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_AES_H */

4
arch/arm/src/stm32/stm32_aes.c → arch/arm/src/common/stm32/stm32_aes_m0_v1.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_aes.c
* arch/arm/src/common/stm32/stm32_aes_m0_v1.c
*
* SPDX-License-Identifier: Apache-2.0
*
@ -36,7 +36,7 @@
#include <nuttx/crypto/crypto.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/semaphore.h>
#include <nuttx/mutex.h>
#include <arch/board/board.h>
#include "arm_internal.h"

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