diff --git a/Documentation/implementation/nuttx_initialization_sequence.rst b/Documentation/implementation/nuttx_initialization_sequence.rst index d3255a5e8ca..2538e7d3a4b 100644 --- a/Documentation/implementation/nuttx_initialization_sequence.rst +++ b/Documentation/implementation/nuttx_initialization_sequence.rst @@ -378,7 +378,7 @@ file and in that case those operations are not performed: * ``note_register()`` - Registers the standard ``/dev/note``. * ``arm_serialinit()`` - Initialize the **standard** serial driver - (found at ``nuttx/arch/arm/src/stm32/stm32_serial.c`` STM32 F4). + (found at ``nuttx/arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c`` STM32 F4). * ``arm_netinitialize()`` - Initialize the network. For the STM32 F4, this function is in ``nuttx/arch/arm/src/stm32/stm32_eth.c``. diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt new file mode 100644 index 00000000000..f7b24554c0f --- /dev/null +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -0,0 +1,504 @@ +# ############################################################################## +# arch/arm/src/common/stm32/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +target_include_directories(arch BEFORE PUBLIC ${CMAKE_CURRENT_LIST_DIR}) + +if(CONFIG_BUILD_PROTECTED) + target_include_directories(arch_interface BEFORE + PUBLIC ${CMAKE_CURRENT_LIST_DIR}) +endif() + +set(SRCS) + +if(CONFIG_STM32_COMMON_LEGACY) + list( + APPEND + SRCS + stm32_allocateheap_m3m4_v1.c + stm32_start_m3m4_v1.c + stm32_lse_m3m4_v1.c + stm32_lsi_m3m4_v1.c + stm32_irq_m3m4_v1.c + stm32_waste_m3m4_v1.c + stm32_capture_m3m4_v1.c) + + if(CONFIG_STM32_HAVE_IP_GPIO_M3M4_V1) + list(APPEND SRCS stm32_gpio_m3m4_v1v2.c) + endif() + + if(CONFIG_STM32_HAVE_IP_EXTI_V1 OR CONFIG_STM32_HAVE_IP_EXTI_V2) + list(APPEND SRCS stm32_exti_gpio_m3m4_v1v2.c) + endif() + + if(CONFIG_STM32_HAVE_IP_SPI_V1 + OR CONFIG_STM32_HAVE_IP_SPI_V2 + OR CONFIG_STM32_HAVE_IP_SPI_V3 + OR CONFIG_STM32_HAVE_IP_SPI_V4) + list(APPEND SRCS stm32_spi_m3m4_v2v3v4.c) + endif() + + if(CONFIG_STM32_HAVE_IP_I2S_M3M4_V1) + list(APPEND SRCS stm32_i2s_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1) + list(APPEND SRCS stm32_sdio_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_TIMERS) + list(APPEND SRCS stm32_tim_m3m4_v1v2v3.c) + endif() + + if(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1) + list(APPEND SRCS stm32_ccm_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_UID_M3M4_V1) + list(APPEND SRCS stm32_uid_m3m4_v1v2.c) + endif() + + if(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1) + list(APPEND SRCS stm32_dfumode_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_USART_V1 + OR CONFIG_STM32_HAVE_IP_USART_V2 + OR CONFIG_STM32_HAVE_IP_USART_V3 + OR CONFIG_STM32_HAVE_IP_USART_V4) + list(APPEND SRCS stm32_lowputc_usart_m3m4_v1v2v3v4.c) + endif() + + if(CONFIG_STM32_HAVE_IP_FLASH_M3M4_L1) + list(APPEND SRCS stm32_flash_m3m4_l1.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F1F3) + list(APPEND SRCS stm32_flash_m3m4_f1f3.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) + list(APPEND SRCS stm32_flash_m3m4_f2f4.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_G4) + list(APPEND SRCS stm32_flash_m3m4_g4.c) + endif() + + if(CONFIG_STM32_TICKLESS_TIMER) + list(APPEND SRCS stm32_tickless_m3m4_v1.c) + elseif(CONFIG_ARCH_ARMV6M) + list(APPEND SRCS stm32_timerisr_armv6m.c) + else() + list(APPEND SRCS stm32_timerisr_armv7m.c) + endif() + + if(CONFIG_BUILD_PROTECTED) + list(APPEND SRCS stm32_userspace_m3m4_v1.c stm32_mpuinit_m3m4_v1.c) + endif() + + if(NOT CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS stm32_idle_m3m4_v1.c) + endif() + + list(APPEND SRCS stm32_pmstop_m3m4_v1.c stm32_pmstandby_m3m4_v1.c + stm32_pmsleep_m3m4_v1.c) + + if(NOT CONFIG_ARCH_CUSTOM_PMINIT) + list(APPEND SRCS stm32_pminitialize_m3m4_v1.c) + endif() + + if(CONFIG_STM32_USART) + if(CONFIG_STM32_HAVE_IP_USART_V1 + OR CONFIG_STM32_HAVE_IP_USART_V2 + OR CONFIG_STM32_HAVE_IP_USART_V3 + OR CONFIG_STM32_HAVE_IP_USART_V4) + list(APPEND SRCS stm32_serial_m3m4_v1v2v3v4.c) + endif() + endif() + + if(CONFIG_STM32_DMA) + if(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) + list(APPEND SRCS stm32_dma_m0_v1_7ch_dmamux.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_7CH) + list(APPEND SRCS stm32_dma_m0_v1_7ch.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX) + list(APPEND SRCS stm32_dma_m3m4_v1_8ch_dmamux.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_8CH) + list(APPEND SRCS stm32_dma_m3m4_v1_8ch.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM) + list(APPEND SRCS stm32_dma_m3m4_v2_stream.c) + endif() + endif() + + if(CONFIG_TIMER AND CONFIG_STM32_HAVE_IP_TIMERS) + list(APPEND SRCS stm32_tim_m3m4_v1v2v3_lowerhalf.c) + endif() + + if(CONFIG_STM32_ONESHOT) + list(APPEND SRCS stm32_oneshot_m3m4_v1.c stm32_oneshot_m3m4_v1_lowerhalf.c) + endif() + + if(CONFIG_STM32_FREERUN) + list(APPEND SRCS stm32_freerun_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) + if(CONFIG_STM32_I2C_ALT) + list(APPEND SRCS stm32_i2c_m3m4_v1_alt.c) + elseif(CONFIG_STM32_STM32F4XXX) + list(APPEND SRCS stm32_i2c_m3m4_v1_f40xxx.c) + else() + list(APPEND SRCS stm32_i2c_m3m4_v1.c) + endif() + elseif(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) + list(APPEND SRCS stm32_i2c_m3m4_v2.c) + if(CONFIG_STM32_I2C_SLAVE) + list(APPEND SRCS stm32_i2c_m3m4_v2_slave.c) + endif() + endif() + + if(CONFIG_USBDEV) + if(CONFIG_STM32_USB AND CONFIG_STM32_HAVE_IP_USBDEV_M3M4_V1) + list(APPEND SRCS stm32_usbdev_m3m4_v1.c) + endif() + if(CONFIG_STM32_USBFS AND CONFIG_STM32_HAVE_IP_USBFS_M3M4_V1) + list(APPEND SRCS stm32_usbfs_m3m4_v1.c) + endif() + if(CONFIG_STM32_OTGFS AND CONFIG_STM32_HAVE_IP_OTGFS_M3M4_V1) + list(APPEND SRCS stm32_otgfsdev_m3m4_v1.c) + endif() + if(CONFIG_STM32_OTGHS AND CONFIG_STM32_HAVE_IP_OTGHS_M3M4_V1) + list(APPEND SRCS stm32_otghsdev_m3m4_v1.c) + endif() + endif() + + if(CONFIG_STM32_USBHOST) + if(CONFIG_STM32_OTGFS AND CONFIG_STM32_HAVE_IP_OTGFS_M3M4_V1) + list(APPEND SRCS stm32_otgfshost_m3m4_v1.c) + endif() + if(CONFIG_STM32_OTGHS AND CONFIG_STM32_HAVE_IP_OTGHS_M3M4_V1) + list(APPEND SRCS stm32_otghshost_m3m4_v1.c) + endif() + if(CONFIG_STM32_HAVE_COMMON_USBHOST_DEBUG AND (CONFIG_USBHOST_TRACE + OR CONFIG_DEBUG_USB)) + list(APPEND SRCS stm32_usbhost_m3m4_v1.c) + endif() + endif() + + if(CONFIG_STM32_ETHMAC AND CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) + list(APPEND SRCS stm32_eth_m3m4_v1.c) + endif() + + if(CONFIG_STM32_PWR AND CONFIG_STM32_HAVE_IP_PWR_M3M4_V1) + list(APPEND SRCS stm32_pwr_m3m4_v1.c stm32_exti_pwr_m3m4_v1.c) + endif() + + if(CONFIG_STM32_RTC) + if(CONFIG_STM32_HAVE_IP_RTC_COUNTER_M3M4_V1) + list(APPEND SRCS stm32_rtcounter_m3m4_v1.c) + elseif(CONFIG_STM32_HAVE_IP_RTCC_M3M4_L1) + list(APPEND SRCS stm32_rtcc_m3m4_l1.c) + elseif(CONFIG_STM32_HAVE_IP_RTCC_M3M4_F4) + list(APPEND SRCS stm32_rtcc_m3m4_f4.c) + elseif(CONFIG_STM32_HAVE_IP_RTCC_M3M4_V1) + list(APPEND SRCS stm32_rtcc_m3m4_v1.c) + endif() + if(CONFIG_RTC_ALARM) + list(APPEND SRCS stm32_exti_alarm_m3m4_v1.c) + endif() + if(CONFIG_RTC_PERIODIC) + list(APPEND SRCS stm32_exti_wakeup_m3m4_v1.c) + endif() + if(CONFIG_RTC_DRIVER AND CONFIG_STM32_HAVE_IP_RTC_M3M4_V1) + list(APPEND SRCS stm32_rtc_m3m4_v1_lowerhalf.c) + endif() + endif() + + if(CONFIG_STM32_ADC + AND (CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 + OR CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)) + list(APPEND SRCS stm32_adc_m3m4_v1v2.c) + endif() + + if(CONFIG_STM32_SDADC AND CONFIG_STM32_HAVE_IP_SDADC_M3M4_V1) + list(APPEND SRCS stm32_sdadc_m3m4_v1.c) + endif() + + if(CONFIG_STM32_DAC + AND (CONFIG_STM32_HAVE_IP_DAC_M3M4_V1 + OR CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)) + list(APPEND SRCS stm32_dac_m3m4_v1.c) + endif() + + if(CONFIG_STM32_COMP) + if(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) + list(APPEND SRCS stm32_comp_m3m4_v1.c) + elseif(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) + list(APPEND SRCS stm32_comp_m3m4_v2.c) + endif() + endif() + + if(CONFIG_STM32_OPAMP AND CONFIG_STM32_HAVE_IP_OPAMP_M3M4_V1) + list(APPEND SRCS stm32_opamp_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HRTIM AND CONFIG_STM32_HAVE_IP_HRTIM_M3M4_V1) + list(APPEND SRCS stm32_hrtim_m3m4_v1.c) + endif() + + if(CONFIG_STM32_1WIREDRIVER) + list(APPEND SRCS stm32_1wire_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HCIUART) + list(APPEND SRCS stm32_hciuart_m3m4_v1.c) + endif() + + if(CONFIG_STM32_RNG AND CONFIG_STM32_HAVE_IP_RNG_M3M4_V1) + list(APPEND SRCS stm32_rng_m3m4_v1.c) + endif() + + if(CONFIG_STM32_LTDC AND CONFIG_STM32_HAVE_IP_LTDC_M3M4_V1) + list(APPEND SRCS stm32_ltdc_m3m4_v1.c) + endif() + + if(CONFIG_STM32_DMA2D AND CONFIG_STM32_HAVE_IP_DMA2D_M3M4_V1) + list(APPEND SRCS stm32_dma2d_m3m4_v1.c) + endif() + + if(CONFIG_STM32_PWM) + list(APPEND SRCS stm32_pwm_m3m4_v1v2v3.c) + endif() + + if(CONFIG_STM32_PULSECOUNT) + list(APPEND SRCS stm32_pulsecount_m3m4_v1v2v3.c) + endif() + + if(CONFIG_STM32_CAP) + list(APPEND SRCS stm32_capture_m3m4_v1_lowerhalf.c) + endif() + + if(CONFIG_SENSORS_QENCODER AND CONFIG_STM32_QE) + list(APPEND SRCS stm32_qencoder_m3m4_v1v2v3.c) + endif() + + if(CONFIG_STM32_CAN AND CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) + if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can_m3m4_v1.c) + endif() + if(CONFIG_STM32_CAN_SOCKET) + list(APPEND SRCS stm32_can_m3m4_v1_sock.c) + endif() + endif() + + if(CONFIG_STM32_FDCAN AND CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1) + if(CONFIG_STM32_FDCAN_CHARDRIVER) + list(APPEND SRCS stm32_fdcan_m3m4_v1.c) + endif() + if(CONFIG_STM32_FDCAN_SOCKET) + list(APPEND SRCS stm32_fdcan_m3m4_v1_sock.c) + endif() + endif() + + if(CONFIG_STM32_IWDG AND CONFIG_STM32_HAVE_IP_WDG_M3M4_V1) + list(APPEND SRCS stm32_iwdg_m3m4_v1.c) + endif() + + if(CONFIG_STM32_WWDG AND CONFIG_STM32_HAVE_IP_WDG_M3M4_V1) + list(APPEND SRCS stm32_wwdg_m3m4_v1.c) + endif() + + if(CONFIG_DEBUG_FEATURES + AND (CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1 + OR CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2 + OR CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3)) + list(APPEND SRCS stm32_dumpgpio_m3m4_v1.c) + endif() + + if(CONFIG_STM32_AES AND CONFIG_STM32_HAVE_IP_AES_M3M4_V1) + list(APPEND SRCS stm32_aes_m3m4_v1.c) + endif() + + if(CONFIG_CRYPTO_CRYPTODEV_HARDWARE AND CONFIG_STM32_HAVE_IP_CRYPTO_M3M4_V1) + list(APPEND SRCS stm32_crypto_m3m4_v1.c) + endif() + + if(CONFIG_STM32_BBSRAM AND CONFIG_STM32_HAVE_IP_BBSRAM_M3M4_V1) + list(APPEND SRCS stm32_bbsram_m3m4_v1.c) + endif() + + if(CONFIG_STM32_FMC AND CONFIG_STM32_HAVE_IP_FMC_M3M4_V1) + list(APPEND SRCS stm32_fmc_m3m4_v1.c) + endif() + + if(CONFIG_STM32_FSMC AND CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) + list(APPEND SRCS stm32_fsmc_m3m4_v1.c) + endif() + + if(CONFIG_STM32_FOC) + list(APPEND SRCS stm32_foc_m3m4_v1.c) + endif() + + if(CONFIG_STM32_CORDIC AND CONFIG_STM32_HAVE_IP_CORDIC_M3M4_V1) + list(APPEND SRCS stm32_cordic_m3m4_v1.c) + endif() +endif() + +if(CONFIG_ARCH_CORTEXM0) + list( + APPEND + SRCS + stm32_irq_m0_v1.c + stm32_start_m0_v1.c + stm32_lsi_m0_v1.c) + + if(CONFIG_STM32_HAVE_IP_GPIO_M0_V1) + list(APPEND SRCS stm32_gpio_m0_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_EXTI_V1 OR CONFIG_STM32_HAVE_IP_EXTI_V2) + list(APPEND SRCS stm32_exti_gpio_m0_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_UID_M0_V1) + list(APPEND SRCS stm32_uid_m0_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_USART_V3) + list(APPEND SRCS stm32_lowputc_usart_m0_v3.c stm32_serial_m0_v3.c) + elseif(CONFIG_STM32_HAVE_IP_USART_V4) + list(APPEND SRCS stm32_lowputc_usart_m0_v4.c stm32_serial_m0_v4.c) + endif() + + if(CONFIG_STM32_RTC_LSECLOCK OR CONFIG_LCD_LSECLOCK) + list(APPEND SRCS stm32_lse_m0_v1.c) + endif() + + if(NOT CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS stm32_idle_m0_v1.c) + endif() + + if(NOT CONFIG_SCHED_TICKLESS) + if(CONFIG_ARCH_ARMV6M) + list(APPEND SRCS stm32_timerisr_armv6m.c) + else() + list(APPEND SRCS stm32_timerisr_armv7m.c) + endif() + endif() + + if(CONFIG_STM32_PWR) + if(CONFIG_STM32_HAVE_IP_PWR_M0_V1) + list(APPEND SRCS stm32_pwr_m0_v1.c) + elseif(CONFIG_STM32_HAVE_IP_PWR_G0) + list(APPEND SRCS stm32_pwr_m0_g0.c) + endif() + endif() + + if(CONFIG_STM32_DMA) + if(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) + list(APPEND SRCS stm32_dma_m0_v1_7ch_dmamux.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_7CH) + list(APPEND SRCS stm32_dma_m0_v1_7ch.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX) + list(APPEND SRCS stm32_dma_m3m4_v1_8ch_dmamux.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_8CH) + list(APPEND SRCS stm32_dma_m3m4_v1_8ch.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM) + list(APPEND SRCS stm32_dma_m3m4_v2_stream.c) + endif() + endif() + + if(CONFIG_STM32_PROGMEM) + if(CONFIG_STM32_HAVE_IP_FLASH_M0_G0C0) + list(APPEND SRCS stm32_flash_m0_g0c0.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_L1) + list(APPEND SRCS stm32_flash_m3m4_l1.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F1F3) + list(APPEND SRCS stm32_flash_m3m4_f1f3.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) + list(APPEND SRCS stm32_flash_m3m4_f2f4.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_G4) + list(APPEND SRCS stm32_flash_m3m4_g4.c) + endif() + endif() + + if(CONFIG_STM32_HAVE_HSI48) + list(APPEND SRCS stm32_hsi48_m0_v1.c) + endif() + + if(CONFIG_STM32_USB AND CONFIG_STM32_HAVE_IP_USBDEV_M0_V1) + list(APPEND SRCS stm32_usbdev_m0_v1.c) + endif() + + if(CONFIG_STM32_I2C) + list(APPEND SRCS stm32_i2c_m0_v1.c) + endif() + + if(CONFIG_STM32_SPI) + list(APPEND SRCS stm32_spi_m0_v1.c) + endif() + + if(CONFIG_STM32_PWM) + list(APPEND SRCS stm32_pwm_m0_v1.c) + endif() + + if(CONFIG_PULSECOUNT AND CONFIG_STM32_TIM1_PULSECOUNT) + list(APPEND SRCS stm32_pulsecount_m0_v1.c) + endif() + + if(CONFIG_STM32_ADC AND CONFIG_STM32_HAVE_IP_ADC_M0_V1) + list(APPEND SRCS stm32_adc_m0_v1.c) + endif() + + if(CONFIG_STM32_AES AND CONFIG_STM32_HAVE_IP_AES_M0_V1) + list(APPEND SRCS stm32_aes_m0_v1.c) + endif() + + if(CONFIG_STM32_RNG AND CONFIG_STM32_HAVE_IP_RNG_M0_V1) + list(APPEND SRCS stm32_rng_m0_v1.c) + endif() + + if(CONFIG_STM32_TIM AND CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) + list(APPEND SRCS stm32_tim_m0_v1.c stm32_tim_m0_v1_lowerhalf.c) + endif() + + if(CONFIG_STM32_IWDG AND CONFIG_STM32_HAVE_IP_WDG_M0_V1) + list(APPEND SRCS stm32_iwdg_m0_v1.c) + endif() + + if(CONFIG_STM32_WWDG AND CONFIG_STM32_HAVE_IP_WDG_M0_V1) + list(APPEND SRCS stm32_wwdg_m0_v1.c) + endif() + + if(CONFIG_STM32_FDCAN AND CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M0_V1) + if(CONFIG_STM32_FDCAN_CHARDRIVER) + list(APPEND SRCS stm32_fdcan_m0_v1.c) + endif() + if(CONFIG_STM32_FDCAN_SOCKET) + list(APPEND SRCS stm32_fdcan_m0_v1_sock.c) + endif() + endif() + + if(CONFIG_SENSORS_QENCODER) + list(APPEND SRCS stm32_qencoder_m0_v1.c) + endif() +endif() + +if(CONFIG_SENSORS_HALL3PHASE) + list(APPEND SRCS stm32_hall3ph.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs new file mode 100644 index 00000000000..1e51e181755 --- /dev/null +++ b/arch/arm/src/common/stm32/Make.defs @@ -0,0 +1,549 @@ +############################################################################ +# arch/arm/src/common/stm32/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +STM32_COMMON_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +VPATH += common$(DELIM)stm32 +INCLUDES += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +ARCHINCLUDES += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +ARCHXXINCLUDES += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) + +# IP-core driver selection notes (see arch/arm/src/common/stm32/Kconfig.have): +# - Some peripherals use a "register-set" symbol that picks the hardware header +# plus a "driver-variant" symbol that picks the .c file below (e.g. FLASH: +# STM32_HAVE_IP_FLASH_M3M4_V1 header + STM32_HAVE_IP_FLASH_M3M4_F2F4 driver). +# - This file is split into a legacy Cortex-M3/M4 block (the F1/F2/F3/F4/G4/L1 +# families, STM32_COMMON_LEGACY) and a Cortex-M0 block (F0/L0/G0/C0, +# ARCH_CORTEXM0). STM32_COMMON_LEGACY -- not a plain Cortex symbol -- gates +# the M3/M4 block because the other Cortex-M4 families (L4/WB/WL5) include +# this file too but provide their own implementation. + +ifeq ($(CONFIG_STM32_COMMON_LEGACY),y) + +CHIP_CSRCS += stm32_allocateheap_m3m4_v1.c +CHIP_CSRCS += stm32_start_m3m4_v1.c +CHIP_CSRCS += stm32_lse_m3m4_v1.c +CHIP_CSRCS += stm32_lsi_m3m4_v1.c +CHIP_CSRCS += stm32_irq_m3m4_v1.c +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_USART_V1) \ + $(CONFIG_STM32_HAVE_IP_USART_V2) \ + $(CONFIG_STM32_HAVE_IP_USART_V3) \ + $(CONFIG_STM32_HAVE_IP_USART_V4)),) +CHIP_CSRCS += stm32_lowputc_usart_m3m4_v1v2v3v4.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_GPIO_M3M4_V1),y) +CHIP_CSRCS += stm32_gpio_m3m4_v1v2.c +endif +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_EXTI_V1) \ + $(CONFIG_STM32_HAVE_IP_EXTI_V2)),) +CHIP_CSRCS += stm32_exti_gpio_m3m4_v1v2.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_L1),y) +CHIP_CSRCS += stm32_flash_m3m4_l1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F1F3),y) +CHIP_CSRCS += stm32_flash_m3m4_f1f3.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4),y) +CHIP_CSRCS += stm32_flash_m3m4_f2f4.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_G4),y) +CHIP_CSRCS += stm32_flash_m3m4_g4.c +endif +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_SPI_V1) \ + $(CONFIG_STM32_HAVE_IP_SPI_V2) \ + $(CONFIG_STM32_HAVE_IP_SPI_V3) \ + $(CONFIG_STM32_HAVE_IP_SPI_V4)),) +CHIP_CSRCS += stm32_spi_m3m4_v2v3v4.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_I2S_M3M4_V1),y) +CHIP_CSRCS += stm32_i2s_m3m4_v1.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1),y) +CHIP_CSRCS += stm32_sdio_m3m4_v1.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_TIMERS),y) +CHIP_CSRCS += stm32_tim_m3m4_v1v2v3.c +endif +CHIP_CSRCS += stm32_waste_m3m4_v1.c +ifeq ($(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1),y) +CHIP_CSRCS += stm32_ccm_m3m4_v1.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_UID_M3M4_V1),y) +CHIP_CSRCS += stm32_uid_m3m4_v1v2.c +endif +CHIP_CSRCS += stm32_capture_m3m4_v1.c +ifeq ($(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1),y) +CHIP_CSRCS += stm32_dfumode_m3m4_v1.c +endif + +ifdef CONFIG_STM32_TICKLESS_TIMER +CHIP_CSRCS += stm32_tickless_m3m4_v1.c +else +ifeq ($(CONFIG_ARCH_ARMV6M),y) +CHIP_CSRCS += stm32_timerisr_armv6m.c +else +CHIP_CSRCS += stm32_timerisr_armv7m.c +endif +endif + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += stm32_userspace_m3m4_v1.c +CHIP_CSRCS += stm32_mpuinit_m3m4_v1.c +endif + +ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CHIP_CSRCS += stm32_idle_m3m4_v1.c +endif + +CHIP_CSRCS += stm32_pmstop_m3m4_v1.c +CHIP_CSRCS += stm32_pmstandby_m3m4_v1.c +CHIP_CSRCS += stm32_pmsleep_m3m4_v1.c + +ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) +CHIP_CSRCS += stm32_pminitialize_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_USART),y) +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_USART_V1) \ + $(CONFIG_STM32_HAVE_IP_USART_V2) \ + $(CONFIG_STM32_HAVE_IP_USART_V3) \ + $(CONFIG_STM32_HAVE_IP_USART_V4)),) +CHIP_CSRCS += stm32_serial_m3m4_v1v2v3v4.c +endif +endif + +ifeq ($(CONFIG_STM32_DMA),y) +ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX),y) +CHIP_CSRCS += stm32_dma_m0_v1_7ch_dmamux.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_7CH),y) +CHIP_CSRCS += stm32_dma_m0_v1_7ch.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX),y) +CHIP_CSRCS += stm32_dma_m3m4_v1_8ch_dmamux.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_8CH),y) +CHIP_CSRCS += stm32_dma_m3m4_v1_8ch.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM),y) +CHIP_CSRCS += stm32_dma_m3m4_v2_stream.c +endif +endif + +ifeq ($(CONFIG_TIMER)$(CONFIG_STM32_HAVE_IP_TIMERS),yy) +CHIP_CSRCS += stm32_tim_m3m4_v1v2v3_lowerhalf.c +endif + +ifeq ($(CONFIG_STM32_ONESHOT),y) +CHIP_CSRCS += stm32_oneshot_m3m4_v1.c +CHIP_CSRCS += stm32_oneshot_m3m4_v1_lowerhalf.c +endif + +ifeq ($(CONFIG_STM32_FREERUN),y) +CHIP_CSRCS += stm32_freerun_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1),y) +ifeq ($(CONFIG_STM32_I2C_ALT),y) +CHIP_CSRCS += stm32_i2c_m3m4_v1_alt.c +else ifeq ($(CONFIG_STM32_STM32F4XXX),y) +CHIP_CSRCS += stm32_i2c_m3m4_v1_f40xxx.c +else +CHIP_CSRCS += stm32_i2c_m3m4_v1.c +endif +else ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2),y) +CHIP_CSRCS += stm32_i2c_m3m4_v2.c +ifeq ($(CONFIG_STM32_I2C_SLAVE),y) +CHIP_CSRCS += stm32_i2c_m3m4_v2_slave.c +endif +endif + +ifeq ($(CONFIG_USBDEV),y) +ifeq ($(CONFIG_STM32_USB),y) +ifeq ($(CONFIG_STM32_HAVE_IP_USBDEV_M3M4_V1),y) +CHIP_CSRCS += stm32_usbdev_m3m4_v1.c +endif +endif +ifeq ($(CONFIG_STM32_USBFS),y) +ifeq ($(CONFIG_STM32_HAVE_IP_USBFS_M3M4_V1),y) +CHIP_CSRCS += stm32_usbfs_m3m4_v1.c +endif +endif +ifeq ($(CONFIG_STM32_OTGFS),y) +ifeq ($(CONFIG_STM32_HAVE_IP_OTGFS_M3M4_V1),y) +CHIP_CSRCS += stm32_otgfsdev_m3m4_v1.c +endif +endif +ifeq ($(CONFIG_STM32_OTGHS),y) +ifeq ($(CONFIG_STM32_HAVE_IP_OTGHS_M3M4_V1),y) +CHIP_CSRCS += stm32_otghsdev_m3m4_v1.c +endif +endif +endif + +ifeq ($(CONFIG_STM32_USBHOST),y) +ifeq ($(CONFIG_STM32_OTGFS),y) +ifeq ($(CONFIG_STM32_HAVE_IP_OTGFS_M3M4_V1),y) +CHIP_CSRCS += stm32_otgfshost_m3m4_v1.c +endif +endif +ifeq ($(CONFIG_STM32_OTGHS),y) +ifeq ($(CONFIG_STM32_HAVE_IP_OTGHS_M3M4_V1),y) +CHIP_CSRCS += stm32_otghshost_m3m4_v1.c +endif +endif +ifeq ($(CONFIG_STM32_HAVE_COMMON_USBHOST_DEBUG),y) +ifeq ($(CONFIG_USBHOST_TRACE),y) +CHIP_CSRCS += stm32_usbhost_m3m4_v1.c +else +ifeq ($(CONFIG_DEBUG_USB),y) +CHIP_CSRCS += stm32_usbhost_m3m4_v1.c +endif +endif +endif +endif + +ifeq ($(CONFIG_STM32_ETHMAC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1),y) +CHIP_CSRCS += stm32_eth_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_PWR)$(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1),yy) +CHIP_CSRCS += stm32_pwr_m3m4_v1.c stm32_exti_pwr_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_RTC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_RTC_COUNTER_M3M4_V1),y) +CHIP_CSRCS += stm32_rtcounter_m3m4_v1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_RTCC_M3M4_L1),y) +CHIP_CSRCS += stm32_rtcc_m3m4_l1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_RTCC_M3M4_F4),y) +CHIP_CSRCS += stm32_rtcc_m3m4_f4.c +else ifeq ($(CONFIG_STM32_HAVE_IP_RTCC_M3M4_V1),y) +CHIP_CSRCS += stm32_rtcc_m3m4_v1.c +endif +ifeq ($(CONFIG_RTC_ALARM),y) +CHIP_CSRCS += stm32_exti_alarm_m3m4_v1.c +endif +ifeq ($(CONFIG_RTC_PERIODIC),y) +CHIP_CSRCS += stm32_exti_wakeup_m3m4_v1.c +endif +ifeq ($(CONFIG_RTC_DRIVER)$(CONFIG_STM32_HAVE_IP_RTC_M3M4_V1),yy) +CHIP_CSRCS += stm32_rtc_m3m4_v1_lowerhalf.c +endif +endif + +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) \ + $(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)),) +ifeq ($(CONFIG_STM32_ADC),y) +CHIP_CSRCS += stm32_adc_m3m4_v1v2.c +endif +endif + +ifeq ($(CONFIG_STM32_SDADC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_SDADC_M3M4_V1),y) +CHIP_CSRCS += stm32_sdadc_m3m4_v1.c +endif +endif + +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) \ + $(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)),) +ifeq ($(CONFIG_STM32_DAC),y) +CHIP_CSRCS += stm32_dac_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_COMP),y) +ifeq ($(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1),y) +CHIP_CSRCS += stm32_comp_m3m4_v1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2),y) +CHIP_CSRCS += stm32_comp_m3m4_v2.c +endif +endif + +ifeq ($(CONFIG_STM32_OPAMP)$(CONFIG_STM32_HAVE_IP_OPAMP_M3M4_V1),yy) +CHIP_CSRCS += stm32_opamp_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_HRTIM),y) +ifeq ($(CONFIG_STM32_HAVE_IP_HRTIM_M3M4_V1),y) +CHIP_CSRCS += stm32_hrtim_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_1WIREDRIVER),y) +CHIP_CSRCS += stm32_1wire_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_HCIUART),y) +CHIP_CSRCS += stm32_hciuart_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_RNG)$(CONFIG_STM32_HAVE_IP_RNG_M3M4_V1),yy) +CHIP_CSRCS += stm32_rng_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_LTDC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_LTDC_M3M4_V1),y) +CHIP_CSRCS += stm32_ltdc_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_DMA2D),y) +ifeq ($(CONFIG_STM32_HAVE_IP_DMA2D_M3M4_V1),y) +CHIP_CSRCS += stm32_dma2d_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_PWM),y) +CHIP_CSRCS += stm32_pwm_m3m4_v1v2v3.c +endif + +ifeq ($(CONFIG_STM32_PULSECOUNT),y) +CHIP_CSRCS += stm32_pulsecount_m3m4_v1v2v3.c +endif + +ifeq ($(CONFIG_STM32_CAP),y) +CHIP_CSRCS += stm32_capture_m3m4_v1_lowerhalf.c +endif + +ifeq ($(CONFIG_SENSORS_QENCODER)$(CONFIG_STM32_QE),yy) +CHIP_CSRCS += stm32_qencoder_m3m4_v1v2v3.c +endif + +ifeq ($(CONFIG_STM32_CAN)$(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1),yy) +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CHIP_CSRCS += stm32_can_m3m4_v1.c +endif +ifeq ($(CONFIG_STM32_CAN_SOCKET),y) +CHIP_CSRCS += stm32_can_m3m4_v1_sock.c +endif +endif + +ifeq ($(CONFIG_STM32_FDCAN),y) +ifeq ($(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1),y) +ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) +CHIP_CSRCS += stm32_fdcan_m3m4_v1.c +endif +ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) +CHIP_CSRCS += stm32_fdcan_m3m4_v1_sock.c +endif +endif +endif + +ifeq ($(CONFIG_STM32_IWDG)$(CONFIG_STM32_HAVE_IP_WDG_M3M4_V1),yy) +CHIP_CSRCS += stm32_iwdg_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_WWDG)$(CONFIG_STM32_HAVE_IP_WDG_M3M4_V1),yy) +CHIP_CSRCS += stm32_wwdg_m3m4_v1.c +endif + +ifeq ($(CONFIG_DEBUG_FEATURES),y) +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) \ + $(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) \ + $(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3)),) +CHIP_CSRCS += stm32_dumpgpio_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_AES)$(CONFIG_STM32_HAVE_IP_AES_M3M4_V1),yy) +CHIP_CSRCS += stm32_aes_m3m4_v1.c +endif + +ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE)$(CONFIG_STM32_HAVE_IP_CRYPTO_M3M4_V1),yy) +CHIP_CSRCS += stm32_crypto_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_BBSRAM),y) +ifeq ($(CONFIG_STM32_HAVE_IP_BBSRAM_M3M4_V1),y) +CHIP_CSRCS += stm32_bbsram_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_FMC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_FMC_M3M4_V1),y) +CHIP_CSRCS += stm32_fmc_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_FSMC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1),y) +CHIP_CSRCS += stm32_fsmc_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_FOC),y) +CHIP_CSRCS += stm32_foc_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_CORDIC)$(CONFIG_STM32_HAVE_IP_CORDIC_M3M4_V1),yy) +CHIP_CSRCS += stm32_cordic_m3m4_v1.c +endif + +endif + +ifeq ($(CONFIG_ARCH_CORTEXM0),y) + +CHIP_CSRCS += stm32_irq_m0_v1.c +ifeq ($(CONFIG_STM32_HAVE_IP_USART_V3),y) +CHIP_CSRCS += stm32_lowputc_usart_m0_v3.c +else ifeq ($(CONFIG_STM32_HAVE_IP_USART_V4),y) +CHIP_CSRCS += stm32_lowputc_usart_m0_v4.c +endif +CHIP_CSRCS += stm32_start_m0_v1.c +CHIP_CSRCS += stm32_lsi_m0_v1.c +ifeq ($(CONFIG_STM32_HAVE_IP_GPIO_M0_V1),y) +CHIP_CSRCS += stm32_gpio_m0_v1.c +endif +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_EXTI_V1) \ + $(CONFIG_STM32_HAVE_IP_EXTI_V2)),) +CHIP_CSRCS += stm32_exti_gpio_m0_v1.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_USART_V3),y) +CHIP_CSRCS += stm32_serial_m0_v3.c +else ifeq ($(CONFIG_STM32_HAVE_IP_USART_V4),y) +CHIP_CSRCS += stm32_serial_m0_v4.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_UID_M0_V1),y) +CHIP_CSRCS += stm32_uid_m0_v1.c +endif + +ifneq ($(CONFIG_STM32_RTC_LSECLOCK)$(CONFIG_LCD_LSECLOCK),) +CHIP_CSRCS += stm32_lse_m0_v1.c +endif + +ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CHIP_CSRCS += stm32_idle_m0_v1.c +endif + +ifneq ($(CONFIG_SCHED_TICKLESS),y) +ifeq ($(CONFIG_ARCH_ARMV6M),y) +CHIP_CSRCS += stm32_timerisr_armv6m.c +else +CHIP_CSRCS += stm32_timerisr_armv7m.c +endif +endif + +ifeq ($(CONFIG_STM32_PWR),y) +ifeq ($(CONFIG_STM32_HAVE_IP_PWR_M0_V1),y) +CHIP_CSRCS += stm32_pwr_m0_v1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_PWR_G0),y) +CHIP_CSRCS += stm32_pwr_m0_g0.c +endif +endif + +ifeq ($(CONFIG_STM32_DMA),y) +ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX),y) +CHIP_CSRCS += stm32_dma_m0_v1_7ch_dmamux.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_7CH),y) +CHIP_CSRCS += stm32_dma_m0_v1_7ch.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX),y) +CHIP_CSRCS += stm32_dma_m3m4_v1_8ch_dmamux.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_8CH),y) +CHIP_CSRCS += stm32_dma_m3m4_v1_8ch.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM),y) +CHIP_CSRCS += stm32_dma_m3m4_v2_stream.c +endif +endif + +ifeq ($(CONFIG_STM32_PROGMEM),y) +ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M0_G0C0),y) +CHIP_CSRCS += stm32_flash_m0_g0c0.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_L1),y) +CHIP_CSRCS += stm32_flash_m3m4_l1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F1F3),y) +CHIP_CSRCS += stm32_flash_m3m4_f1f3.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4),y) +CHIP_CSRCS += stm32_flash_m3m4_f2f4.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_G4),y) +CHIP_CSRCS += stm32_flash_m3m4_g4.c +endif +endif + +ifeq ($(CONFIG_STM32_HAVE_HSI48),y) +CHIP_CSRCS += stm32_hsi48_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_USB),y) +ifeq ($(CONFIG_STM32_HAVE_IP_USBDEV_M0_V1),y) +CHIP_CSRCS += stm32_usbdev_m0_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_I2C),y) +CHIP_CSRCS += stm32_i2c_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_SPI),y) +CHIP_CSRCS += stm32_spi_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_PWM),y) +CHIP_CSRCS += stm32_pwm_m0_v1.c +endif + +ifeq ($(CONFIG_PULSECOUNT),y) +ifeq ($(CONFIG_STM32_TIM1_PULSECOUNT),y) +CHIP_CSRCS += stm32_pulsecount_m0_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_ADC)$(CONFIG_STM32_HAVE_IP_ADC_M0_V1),yy) +CHIP_CSRCS += stm32_adc_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_AES)$(CONFIG_STM32_HAVE_IP_AES_M0_V1),yy) +CHIP_CSRCS += stm32_aes_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_RNG)$(CONFIG_STM32_HAVE_IP_RNG_M0_V1),yy) +CHIP_CSRCS += stm32_rng_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_TIM)$(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1),yy) +CHIP_CSRCS += stm32_tim_m0_v1.c stm32_tim_m0_v1_lowerhalf.c +endif + +ifeq ($(CONFIG_STM32_IWDG)$(CONFIG_STM32_HAVE_IP_WDG_M0_V1),yy) +CHIP_CSRCS += stm32_iwdg_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_WWDG)$(CONFIG_STM32_HAVE_IP_WDG_M0_V1),yy) +CHIP_CSRCS += stm32_wwdg_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_FDCAN),y) +ifeq ($(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M0_V1),y) +ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) +CHIP_CSRCS += stm32_fdcan_m0_v1.c +endif +ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) +CHIP_CSRCS += stm32_fdcan_m0_v1_sock.c +endif +endif +endif + +ifeq ($(CONFIG_SENSORS_QENCODER),y) +CHIP_CSRCS += stm32_qencoder_m0_v1.c +endif + +endif + +ifeq ($(CONFIG_SENSORS_HALL3PHASE),y) +CHIP_CSRCS += stm32_hall3ph.c +endif diff --git a/arch/arm/src/stm32/hardware/stm32_adc.h b/arch/arm/src/common/stm32/hardware/stm32_adc.h similarity index 63% rename from arch/arm/src/stm32/hardware/stm32_adc.h rename to arch/arm/src/common/stm32/hardware/stm32_adc.h index 49df6093b60..9ad1291ad40 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_adc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_adc.h + * arch/arm/src/common/stm32/hardware/stm32_adc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,31 +20,16 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_H /**************************************************************************** * Included Files ****************************************************************************/ -#include - -#include "chip.h" - -/* There are 2 main types of ADC IP cores among STM32 chips: - * 1. STM32 ADC IPv1: - * a) basic version for F1 and F37x - * b) extended version for F2, F4, F7, L1: - * 2. STM32 ADC IPv2: - * a) basic version for F0 and L0 - * b) extended version for F3 (without F37x), G4, H7, L4, L4+ - * - * We also distinguish these variants: - * 1. The modified STM32 ADC IPv1 core for the L1 family, which differs - * too much to keep it in the same file as ADC IPv1. - * 2. The modified STM32 ADC IPv2 core for the G4 family, which differs - * too much to keep it in the same file as ADC IPv2. - */ +#if defined(CONFIG_STM32_HAVE_IP_ADC_M0_V1) +# include "hardware/stm32_adc_v2_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) || defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) #if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) && \ defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) @@ -53,18 +38,21 @@ #if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) # if defined(CONFIG_STM32_STM32L15XX) -# include "stm32_adc_v1l1.h" /* Special case for L1 */ +# include "stm32_adc_v1l1.h" # else # include "stm32_adc_v1.h" # endif #elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) # if defined(CONFIG_STM32_STM32G4XXX) -# include "stm32_adc_v2g4.h" /* Special case for G4 */ +# include "stm32_adc_v2g4.h" # else # include "stm32_adc_v2.h" # endif #else # error "STM32 ADC IP version not specified" #endif +#else +# error "Unsupported STM32 ADC" +#endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v1.h b/arch/arm/src/common/stm32/hardware/stm32_adc_v1.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_adc_v1.h rename to arch/arm/src/common/stm32/hardware/stm32_adc_v1.h index d1ba76649c3..ef09aabbac8 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc_v1.h +++ b/arch/arm/src/common/stm32/hardware/stm32_adc_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_adc_v1.h + * arch/arm/src/common/stm32/hardware/stm32_adc_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1_H /**************************************************************************** * Included Files @@ -637,4 +637,4 @@ * Public Function Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v1l1.h b/arch/arm/src/common/stm32/hardware/stm32_adc_v1l1.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_adc_v1l1.h rename to arch/arm/src/common/stm32/hardware/stm32_adc_v1l1.h index 68b5beacd86..919c9f57919 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc_v1l1.h +++ b/arch/arm/src/common/stm32/hardware/stm32_adc_v1l1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_adc_v1l1.h + * arch/arm/src/common/stm32/hardware/stm32_adc_v1l1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1L1_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1L1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1L1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1L1_H /**************************************************************************** * Included Files @@ -568,4 +568,4 @@ * Public Function Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1L1_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1L1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v2.h b/arch/arm/src/common/stm32/hardware/stm32_adc_v2.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_adc_v2.h rename to arch/arm/src/common/stm32/hardware/stm32_adc_v2.h index 6e62bb59a74..e8629afef80 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc_v2.h +++ b/arch/arm/src/common/stm32/hardware/stm32_adc_v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_adc_v2.h + * arch/arm/src/common/stm32/hardware/stm32_adc_v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_H /**************************************************************************** * Included Files @@ -732,4 +732,4 @@ * Public Function Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h b/arch/arm/src/common/stm32/hardware/stm32_adc_v2_m0.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h rename to arch/arm/src/common/stm32/hardware/stm32_adc_v2_m0.h index f074647fe54..645174f4637 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_adc_v2_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h + * arch/arm/src/common/stm32/hardware/stm32_adc_v2_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_M0_H /**************************************************************************** * Included Files @@ -323,4 +323,4 @@ #define ADC_CCR_VLCDEN (1 << 24) /* Bit 24: VLCD enable */ #define ADC_CCR_LFMEN (1 << 25) /* Bit 25: Low Frequency Mode enable */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v2g4.h b/arch/arm/src/common/stm32/hardware/stm32_adc_v2g4.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_adc_v2g4.h rename to arch/arm/src/common/stm32/hardware/stm32_adc_v2g4.h index 211bff7fe43..314244086db 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc_v2g4.h +++ b/arch/arm/src/common/stm32/hardware/stm32_adc_v2g4.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_adc_v2g4.h + * arch/arm/src/common/stm32/hardware/stm32_adc_v2g4.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2G4_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2G4_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2G4_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2G4_H /**************************************************************************** * Included Files @@ -866,4 +866,4 @@ #define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data of the Slave ADC */ #define ADC_CDR_RDATA_SLV_MASK (0xffff << ADC_CDR_RDATA_SLV_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2G4_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2G4_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h b/arch/arm/src/common/stm32/hardware/stm32_aes.h similarity index 95% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h rename to arch/arm/src/common/stm32/hardware/stm32_aes.h index d49e402abba..2f1342a7492 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h +++ b/arch/arm/src/common/stm32/hardware/stm32_aes.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h + * arch/arm/src/common/stm32/hardware/stm32_aes.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_AES_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_AES_H /**************************************************************************** * Included Files @@ -98,4 +98,4 @@ #define AES_SR_RDERR (1 << 1) /* Read Error Flag */ #define AES_SR_WRERR (1 << 2) /* Write Error Flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_AES_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_bkp.h b/arch/arm/src/common/stm32/hardware/stm32_bkp.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_bkp.h rename to arch/arm/src/common/stm32/hardware/stm32_bkp.h index a06ed4085dc..f37ffd14f16 100644 --- a/arch/arm/src/stm32/hardware/stm32_bkp.h +++ b/arch/arm/src/common/stm32/hardware/stm32_bkp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_bkp.h + * arch/arm/src/common/stm32/hardware/stm32_bkp.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_BKP_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_BKP_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_BKP_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_BKP_H /**************************************************************************** * Pre-processor Definitions @@ -174,4 +174,4 @@ #define BKP_DR_SHIFT (0) /* Bits 1510: Backup data */ #define BKP_DR_MASK (0xffff << BKP_DR_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_BKP_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_BKP_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_can.h b/arch/arm/src/common/stm32/hardware/stm32_can.h new file mode 100644 index 00000000000..6f8bdc2d273 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_can.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_can.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1)) > 1 +# error Only one STM32 CAN IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M0_V1) +# include "hardware/stm32_can_bxcan_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) +# include "hardware/stm32_can_bxcan.h" +#else +# error "Unsupported STM32 CAN" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_can.h b/arch/arm/src/common/stm32/hardware/stm32_can_bxcan.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_can.h rename to arch/arm/src/common/stm32/hardware/stm32_can_bxcan.h index f1c0fa67523..0de8ea6e5be 100644 --- a/arch/arm/src/stm32/hardware/stm32_can.h +++ b/arch/arm/src/common/stm32/hardware/stm32_can_bxcan.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_can.h + * arch/arm/src/common/stm32/hardware/stm32_can_bxcan.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_CAN_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_CAN_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_H /**************************************************************************** * Included Files @@ -437,14 +437,14 @@ /* CAN filter master register */ #define CAN_FMR_FINIT (1 << 0) /* Bit 0: Filter Init Mode */ -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) # define CAN_FMR_CAN2SB_SHIFT (8) /* Bits 13-8: CAN2 start bank */ # define CAN_FMR_CAN2SB_MASK (0x3f << CAN_FMR_CAN2SB_SHIFT) #endif /* CAN filter mode register */ -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) # define CAN_FM1R_FBM_SHIFT (0) /* Bits 13:0: Filter Mode */ # define CAN_FM1R_FBM_MASK (0x3fff << CAN_FM1R_FBM_SHIFT) #else @@ -454,7 +454,7 @@ /* CAN filter scale register */ -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) # define CAN_FS1R_FSC_SHIFT (0) /* Bits 13:0: Filter Scale Configuration */ # define CAN_FS1R_FSC_MASK (0x3fff << CAN_FS1R_FSC_SHIFT) #else @@ -464,7 +464,7 @@ /* CAN filter FIFO assignment register */ -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) # define CAN_FFA1R_FFA_SHIFT (0) /* Bits 13:0: Filter FIFO Assignment */ # define CAN_FFA1R_FFA_MASK (0x3fff << CAN_FFA1R_FFA_SHIFT) #else @@ -474,7 +474,7 @@ /* CAN filter activation register */ -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) # define CAN_FA1R_FACT_SHIFT (0) /* Bits 13:0: Filter Active */ # define CAN_FA1R_FACT_MASK (0x3fff << CAN_FA1R_FACT_SHIFT) #else @@ -494,4 +494,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_CAN_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_can.h b/arch/arm/src/common/stm32/hardware/stm32_can_bxcan_m0.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_can.h rename to arch/arm/src/common/stm32/hardware/stm32_can_bxcan_m0.h index 774855c7f8f..378e5a03df5 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_can.h +++ b/arch/arm/src/common/stm32/hardware/stm32_can_bxcan_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_can.h + * arch/arm/src/common/stm32/hardware/stm32_can_bxcan_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_M0_H /**************************************************************************** * Included Files @@ -453,4 +453,4 @@ #define CAN_FA1R_FACT_SHIFT (0) /* Bits 13:0: Filter Active */ #define CAN_FA1R_FACT_MASK (0x3fff << CAN_FA1R_FACT_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_comp.h b/arch/arm/src/common/stm32/hardware/stm32_comp.h new file mode 100644 index 00000000000..364b1f8a418 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_comp.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_comp.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_COMP_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2)) > 1 +# error Only one STM32 COMP IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_COMP_M0_V1) +# include "hardware/stm32_comp_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) +# include "hardware/stm32_comp_v1v2.h" +#else +# error "Unsupported STM32 COMP" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h b/arch/arm/src/common/stm32/hardware/stm32_comp_m0.h similarity index 97% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h rename to arch/arm/src/common/stm32/hardware/stm32_comp_m0.h index 5d96fe86f47..06672e2ff1d 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h +++ b/arch/arm/src/common/stm32/hardware/stm32_comp_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h + * arch/arm/src/common/stm32/hardware/stm32_comp_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_M0_H /**************************************************************************** * Included Files @@ -121,4 +121,4 @@ #define COMP_CSR_COMP2OUT (1 << 14) /* Bit 14: Comparator 1 output */ #define COMP_CSR_COMP2LOCK (1 << 15) /* Bit 15: Comparator 1 lock */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_comp.h b/arch/arm/src/common/stm32/hardware/stm32_comp_v1v2.h similarity index 84% rename from arch/arm/src/stm32/hardware/stm32_comp.h rename to arch/arm/src/common/stm32/hardware/stm32_comp_v1v2.h index b950d622b07..94c93d429ba 100644 --- a/arch/arm/src/stm32/hardware/stm32_comp.h +++ b/arch/arm/src/common/stm32/hardware/stm32_comp_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_comp.h + * arch/arm/src/common/stm32/hardware/stm32_comp_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_V1V2_H /**************************************************************************** * Included Files @@ -41,13 +41,13 @@ #if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) # if defined(CONFIG_STM32_STM32F33XX) -# include "stm32f33xxx_comp.h" +# include "hardware/stm32f33xxx_comp.h" # else # error "Device not supported." # endif #elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) # if defined(CONFIG_STM32_STM32G4XXX) -# include "stm32g4xxxx_comp.h" +# include "hardware/stm32g4xxxx_comp.h" # else # error "Device not supported." # endif @@ -57,4 +57,4 @@ #endif /* CONFIG_STM32_COMP */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_V1V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h b/arch/arm/src/common/stm32/hardware/stm32_crc.h similarity index 94% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h rename to arch/arm/src/common/stm32/hardware/stm32_crc.h index 8aa180ded0e..6b51ac8e12b 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_crc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h + * arch/arm/src/common/stm32/hardware/stm32_crc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRC_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h b/arch/arm/src/common/stm32/hardware/stm32_crs.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h rename to arch/arm/src/common/stm32/hardware/stm32_crs.h index 00e007a49cd..b544f9728c8 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h +++ b/arch/arm/src/common/stm32/hardware/stm32_crs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h + * arch/arm/src/common/stm32/hardware/stm32_crs.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRS_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRS_H /**************************************************************************** * Pre-processor Definitions @@ -100,4 +100,4 @@ #define CRS_ICR_ERRC (1 << 2) /* Bit 2: Error clear flag */ #define CRS_ICR_ESYNCC (1 << 3) /* Bit 3: Expected SYNC clear flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRS_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dac.h b/arch/arm/src/common/stm32/hardware/stm32_dac.h new file mode 100644 index 00000000000..dd8df7ed9b1 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dac.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dac.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_DAC_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)) > 1 +# error Only one STM32 DAC IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_DAC_M0_V1) +# include "hardware/stm32_dac_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2) +# include "hardware/stm32_dac_v1v2.h" +#else +# error "Unsupported STM32 DAC" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h b/arch/arm/src/common/stm32/hardware/stm32_dac_m0.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h rename to arch/arm/src/common/stm32/hardware/stm32_dac_m0.h index 7b5262432c0..f95f33e87c2 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dac_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h + * arch/arm/src/common/stm32/hardware/stm32_dac_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_M0_H /**************************************************************************** * Included Files @@ -208,4 +208,4 @@ #define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */ #define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dac_v1.h b/arch/arm/src/common/stm32/hardware/stm32_dac_v1.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_dac_v1.h rename to arch/arm/src/common/stm32/hardware/stm32_dac_v1.h index 74742ac2781..8e213a40b05 100644 --- a/arch/arm/src/stm32/hardware/stm32_dac_v1.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dac_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dac_v1.h + * arch/arm/src/common/stm32/hardware/stm32_dac_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_V1_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_V1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1_H /**************************************************************************** * Included Files @@ -312,4 +312,4 @@ #define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */ #define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_V1_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dac.h b/arch/arm/src/common/stm32/hardware/stm32_dac_v1v2.h similarity index 88% rename from arch/arm/src/stm32/hardware/stm32_dac.h rename to arch/arm/src/common/stm32/hardware/stm32_dac_v1v2.h index 34aa92ce260..9c8587dd4af 100644 --- a/arch/arm/src/stm32/hardware/stm32_dac.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dac_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dac.h + * arch/arm/src/common/stm32/hardware/stm32_dac_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1V2_H /**************************************************************************** * Included Files @@ -53,4 +53,4 @@ # error "STM32 DAC IP version not specified" #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1V2_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dbgmcu.h b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu.h new file mode 100644 index 00000000000..23ef2b1fd8d --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu.h @@ -0,0 +1,47 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dbgmcu.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_DBGMCU_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) + \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3)) > 1 +# error Only one STM32 DBGMCU IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M0_V1) +# include "hardware/stm32_dbgmcu_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3) +# include "hardware/stm32_dbgmcu_v1.h" +#else +# error "Unsupported STM32 DBGMCU" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu_m0.h similarity index 93% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h rename to arch/arm/src/common/stm32/hardware/stm32_dbgmcu_m0.h index 0e5efadeaf7..d310e7c1ac7 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h + * arch/arm/src/common/stm32/hardware/stm32_dbgmcu_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DBGMCU_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DBGMCU_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_M0_H /**************************************************************************** * Included Files @@ -77,4 +77,4 @@ # define DBGMCU_APB1_TIM17STOP (1 << 18) /* Bit 16: TIM17 stopped when core is halted */ #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DBGMCU_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dbgmcu.h b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu_v1.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_dbgmcu.h rename to arch/arm/src/common/stm32/hardware/stm32_dbgmcu_v1.h index ce905d218d7..12628ae6ed6 100644 --- a/arch/arm/src/stm32/hardware/stm32_dbgmcu.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dbgmcu.h + * arch/arm/src/common/stm32/hardware/stm32_dbgmcu_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DBGMCU_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DBGMCU_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_V1_H /**************************************************************************** * Included Files @@ -93,7 +93,7 @@ /* Debug MCU APB1 freeze register */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) # define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */ # define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */ # define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */ @@ -130,7 +130,7 @@ /* Debug MCU APB2 freeze register */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) # define DBGMCU_APB2_TIM1STOP (1 << 0) /* Bit 0: TIM1 stopped when core is halted */ # define DBGMCU_APB2_TIM8STOP (1 << 1) /* Bit 1: TIM8 stopped when core is halted */ # define DBGMCU_APB2_TIM9STOP (1 << 16) /* Bit 16: TIM9 stopped when core is halted */ @@ -194,4 +194,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DBGMCU_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_V1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dma.h b/arch/arm/src/common/stm32/hardware/stm32_dma.h similarity index 77% rename from arch/arm/src/stm32/hardware/stm32_dma.h rename to arch/arm/src/common/stm32/hardware/stm32_dma.h index a34478f9029..ee43743cd57 100644 --- a/arch/arm/src/stm32/hardware/stm32_dma.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dma.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dma.h + * arch/arm/src/common/stm32/hardware/stm32_dma.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_H /**************************************************************************** * Included Files @@ -41,12 +41,15 @@ # error Only one STM32 DMA IP version must be selected #endif -#if defined(CONFIG_STM32_HAVE_IP_DMA_V1) +#if defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX) # include "stm32_dma_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM) # include "stm32_dma_v2.h" #else # error "STM32 DMA IP version not specified" #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dma2d.h b/arch/arm/src/common/stm32/hardware/stm32_dma2d.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_dma2d.h rename to arch/arm/src/common/stm32/hardware/stm32_dma2d.h index 5f885095e2e..35abefb0915 100644 --- a/arch/arm/src/stm32/hardware/stm32_dma2d.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dma2d.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dma2d.h + * arch/arm/src/common/stm32/hardware/stm32_dma2d.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA2D_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA2D_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA2D_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA2D_H /**************************************************************************** * Included Files @@ -234,4 +234,4 @@ * Public Types ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA2D_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA2D_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_i2c.h b/arch/arm/src/common/stm32/hardware/stm32_dma_v1.h similarity index 67% rename from arch/arm/src/stm32/hardware/stm32_i2c.h rename to arch/arm/src/common/stm32/hardware/stm32_dma_v1.h index dd0a6f68872..1ddb8dcc46e 100644 --- a/arch/arm/src/stm32/hardware/stm32_i2c.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dma_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_i2c.h + * arch/arm/src/common/stm32/hardware/stm32_dma_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,24 +20,21 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_H /**************************************************************************** * Included Files ****************************************************************************/ -/* There are 2 main types of I2C IP cores among STM32 chips: - * 1. STM32 I2C IPv1 - F1, F2, F4 and L1 - * 2. STM32 I2C IPv2 - F0, F3, F7, G0, G4, H7, L0 and L4 - */ - -#if defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) -# include "stm32_i2c_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) -# include "stm32_i2c_v2.h" +#if defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) +# include "hardware/stm32_dma_v1_7ch.h" +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX) +# include "hardware/stm32_dma_v1_8ch.h" #else -# error STM32 I2C IP version not specified +# error "Unsupported STM32 DMA v1" #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h b/arch/arm/src/common/stm32/hardware/stm32_dma_v1_7ch.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h rename to arch/arm/src/common/stm32/hardware/stm32_dma_v1_7ch.h index cdae49a53ee..6b3860db903 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dma_v1_7ch.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h + * arch/arm/src/common/stm32/hardware/stm32_dma_v1_7ch.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_7CH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_7CH_H /**************************************************************************** * Pre-processor Definitions @@ -545,4 +545,4 @@ # error "Unknown DMA channel assignments" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_7CH_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dma_v1.h b/arch/arm/src/common/stm32/hardware/stm32_dma_v1_8ch.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_dma_v1.h rename to arch/arm/src/common/stm32/hardware/stm32_dma_v1_8ch.h index 0f73d267096..4d4cb3ed4e6 100644 --- a/arch/arm/src/stm32/hardware/stm32_dma_v1.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dma_v1_8ch.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dma_v1.h + * arch/arm/src/common/stm32/hardware/stm32_dma_v1_8ch.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V1_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_8CH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_8CH_H /**************************************************************************** * Pre-processor Definitions @@ -139,7 +139,7 @@ #define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) #define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) #define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) # define STM32_DMA1_CCR8 (STM32_DMA1_BASE+STM32_DMA_CCR8_OFFSET) #endif @@ -151,7 +151,7 @@ #define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) #define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) #define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) # define STM32_DMA1_CNDTR8 (STM32_DMA1_BASE+STM32_DMA_CNDTR8_OFFSET) #endif @@ -163,7 +163,7 @@ #define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) #define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) #define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) # define STM32_DMA1_CPAR8 (STM32_DMA1_BASE+STM32_DMA_CPAR8_OFFSET) #endif @@ -175,7 +175,7 @@ #define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) #define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) #define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) # define STM32_DMA1_CMAR8 (STM32_DMA1_BASE+STM32_DMA_CMAR8_OFFSET) #endif @@ -188,7 +188,7 @@ #define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) #define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) #define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +#if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET) # define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET) # define STM32_DMA2_CCR8 (STM32_DMA2_BASE+STM32_DMA_CCR8_OFFSET) @@ -200,7 +200,7 @@ #define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) #define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) #define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +#if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET) # define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET) # define STM32_DMA2_CNDTR8 (STM32_DMA2_BASE+STM32_DMA_CNDTR8_OFFSET) @@ -212,7 +212,7 @@ #define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) #define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) #define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +#if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET) # define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET) # define STM32_DMA2_CPAR8 (STM32_DMA2_BASE+STM32_DMA_CPAR8_OFFSET) @@ -224,7 +224,7 @@ #define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) #define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) #define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +#if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET) # define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET) # define STM32_DMA2_CMAR8 (STM32_DMA2_BASE+STM32_DMA_CMAR8_OFFSET) @@ -286,7 +286,7 @@ #define DMA_IFCR_CHAN8_SHIFT (28) /* Bits 31-28: DMA Channel 8 interrupt flag clear */ #define DMA_IFCR_CHAN8_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN8_SHIFT) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) || defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) || defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define DMA_IFCR_ALLCHANNELS (0xffffffff) #else # define DMA_IFCR_ALLCHANNELS (0x0fffffff) @@ -350,14 +350,14 @@ #define STM32_DMA1_CHAN5 (4) #define STM32_DMA1_CHAN6 (5) #define STM32_DMA1_CHAN7 (6) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) # define STM32_DMA1_CHAN8 (7) # define STM32_DMA2_CHAN1 (8) # define STM32_DMA2_CHAN2 (9) # define STM32_DMA2_CHAN3 (10) # define STM32_DMA2_CHAN4 (11) # define STM32_DMA2_CHAN5 (12) -# if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +# if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define STM32_DMA2_CHAN6 (13) # define STM32_DMA2_CHAN7 (14) # define STM32_DMA2_CHAN8 (15) @@ -368,7 +368,7 @@ # define STM32_DMA2_CHAN3 (9) # define STM32_DMA2_CHAN4 (10) # define STM32_DMA2_CHAN5 (11) -# if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +# if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define STM32_DMA2_CHAN6 (12) # define STM32_DMA2_CHAN7 (13) # define STM32_DMA2_CHAN8 (14) @@ -770,4 +770,4 @@ # error "Unknown DMA channel assignments" #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V1_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_8CH_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dma_v2.h b/arch/arm/src/common/stm32/hardware/stm32_dma_v2.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_dma_v2.h rename to arch/arm/src/common/stm32/hardware/stm32_dma_v2.h index 916ddc13804..cff6393fb12 100644 --- a/arch/arm/src/stm32/hardware/stm32_dma_v2.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dma_v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dma_v2.h + * arch/arm/src/common/stm32/hardware/stm32_dma_v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V2_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V2_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V2_H /**************************************************************************** * Pre-processor Definitions @@ -558,4 +558,4 @@ #define DMAMAP_TIM8_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) #define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V2_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h b/arch/arm/src/common/stm32/hardware/stm32_dmamux.h similarity index 72% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h rename to arch/arm/src/common/stm32/hardware/stm32_dmamux.h index 1a03d8f4dcd..1531e37123a 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dmamux.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h + * arch/arm/src/common/stm32/hardware/stm32_dmamux.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,22 +20,21 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_H /**************************************************************************** * Included Files ****************************************************************************/ #include -#include "chip.h" -#if defined(CONFIG_STM32_HAVE_IP_USART_V1) -# include "hardware/stm32_uart_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_USART_V2) -# include "hardware/stm32_uart_v2.h" +#if defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) +# include "hardware/stm32_dmamux_7ch.h" +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX) +# include "hardware/stm32_dmamux_16ch.h" #else -# error "Unsupported STM32 M0 USART" +# error "Unsupported STM32 DMAMUX" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dmamux.h b/arch/arm/src/common/stm32/hardware/stm32_dmamux_16ch.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_dmamux.h rename to arch/arm/src/common/stm32/hardware/stm32_dmamux_16ch.h index 18fd66b1498..bc0cc2d6832 100644 --- a/arch/arm/src/stm32/hardware/stm32_dmamux.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dmamux_16ch.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dmamux.h + * arch/arm/src/common/stm32/hardware/stm32_dmamux_16ch.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMAMUX_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMAMUX_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_16CH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_16CH_H /**************************************************************************** * Included Files @@ -176,4 +176,4 @@ # error "Unsupported STM32 sub family" #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMAMUX_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_16CH_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h b/arch/arm/src/common/stm32/hardware/stm32_dmamux_7ch.h similarity index 97% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h rename to arch/arm/src/common/stm32/hardware/stm32_dmamux_7ch.h index ccab2c6f14a..b7c36335c0a 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dmamux_7ch.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h + * arch/arm/src/common/stm32/hardware/stm32_dmamux_7ch.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_7CH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_7CH_H /**************************************************************************** * Included Files @@ -159,4 +159,4 @@ # error "Unsupported STM32 M0 sub family" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_7CH_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_eth.h b/arch/arm/src/common/stm32/hardware/stm32_eth.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_eth.h rename to arch/arm/src/common/stm32/hardware/stm32_eth.h index d95a6441c49..1d02920541c 100644 --- a/arch/arm/src/stm32/hardware/stm32_eth.h +++ b/arch/arm/src/common/stm32/hardware/stm32_eth.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_eth.h + * arch/arm/src/common/stm32/hardware/stm32_eth.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ETH_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ETH_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ETH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ETH_H /**************************************************************************** * Included Files @@ -51,7 +51,7 @@ #define STM32_ETH_MACVLANTR_OFFSET 0x001c /* Ethernet MAC VLAN tag register */ #define STM32_ETH_MACRWUFFR_OFFSET 0x0028 /* Ethernet MAC remote wakeup frame filter reg */ #define STM32_ETH_MACPMTCSR_OFFSET 0x002c /* Ethernet MAC PMT control and status register */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) # define STM32_ETH_MACDBGR_OFFSET 0x0034 /* Ethernet MAC debug register */ #endif #define STM32_ETH_MACSR_OFFSET 0x0038 /* Ethernet MAC interrupt status register */ @@ -124,7 +124,7 @@ #define STM32_ETH_MACVLANTR (STM32_ETHERNET_BASE+STM32_ETH_MACVLANTR_OFFSET) #define STM32_ETH_MACRWUFFR (STM32_ETHERNET_BASE+STM32_ETH_MACRWUFFR_OFFSET) #define STM32_ETH_MACPMTCSR (STM32_ETHERNET_BASE+STM32_ETH_MACPMTCSR_OFFSET) -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) # define STM32_ETH_MACDBGR (STM32_ETHERNET_BASE+STM32_ETH_MACDBGR_OFFSET) #endif #define STM32_ETH_MACSR (STM32_ETHERNET_BASE+STM32_ETH_MACSR_OFFSET) @@ -213,7 +213,7 @@ #define ETH_MACCR_JD (1 << 22) /* Bit 22: Jabber disable */ #define ETH_MACCR_WD (1 << 23) /* Bit 23: Watchdog disable */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) # define ETH_MACCR_CSTF (1 << 25) /* Bits 25: CRC stripping for Type frames */ #endif @@ -304,7 +304,7 @@ /* Ethernet MAC debug register */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) #define ETH_MACDBGR_MMRPEA (1 << 0) /* Bit 0: MAC MII receive protocol engine active */ #define ETH_MACDBGR_MSFRWCS_SHIFT (1) /* Bits 1-2: MAC small FIFO read / write controllers status */ @@ -432,7 +432,7 @@ #define ETH_MMCCR_ROR (1 << 2) /* Bit 2: Reset on read */ #define ETH_MMCCR_MCF (1 << 3) /* Bit 3: MMC counter freeze */ #define ETH_MMCCR_MCP (1 << 4) /* Bit 4: MMC counter preset */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) # define ETH_MMCCR_MCFHP (1 << 5) /* Bit 5: MMC counter Full-Half preset */ #endif @@ -469,7 +469,7 @@ #define ETH_PTPTSCR_TSITE (1 << 4) /* Bit 4: Time stamp interrupt trigger enable */ #define ETH_PTPTSCR_TSARU (1 << 5) /* Bit 5: Time stamp addend register update */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) #define ETH_PTPTSCR_TSSARFE (1 << 8) /* Bit 8: Time stamp snapshot for all received frames enable */ #define ETH_PTPTSCR_TSSSR (1 << 9) /* Bit 9: Time stamp subsecond rollover: digital or binary rollover control */ #define ETH_PTPTSCR_TSPTPPSV2E (1 << 10) /* Bit 10: Time stamp PTP packet snooping for version2 format enable */ @@ -568,7 +568,7 @@ #define ETH_DMABMR_USP (1 << 23) /* Bit 23: Use separate PBL */ #define ETH_DMABMR_FPM (1 << 24) /* Bit 24: 4xPBL mode */ #define ETH_DMABMR_AAB (1 << 25) /* Bit 25: Address-aligned beats */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) # define ETH_DMABMR_MB (1 << 26) /* Bit 26: Mixed burst */ #endif @@ -743,7 +743,7 @@ /* RDES0: Receive descriptor Word0 */ #define ETH_RDES0_PCE (1 << 0) /* Bit 0: Payload checksum error */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) # define ETH_RDES0_ESA (1 << 0) /* Bit 0: Extended status available */ #endif #define ETH_RDES0_CE (1 << 1) /* Bit 1: CRC error */ @@ -874,4 +874,4 @@ struct eth_rxdesc_s #endif /* __ASSEMBLY__ */ #endif /* STM32_NETHERNET > 0 */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ETH_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ETH_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_exti.h b/arch/arm/src/common/stm32/hardware/stm32_exti.h new file mode 100644 index 00000000000..8b22f1abf70 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_exti.h @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_exti.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* The EXTI IP version (V1/V2) is independent of the CPU core. The M0 and + * M3/M4 ports currently keep separate register headers, so the file is + * chosen by the standard NuttX core symbol (CONFIG_ARCH_CORTEXM0) while the + * version is core-agnostic. + */ + +#if (defined(CONFIG_STM32_HAVE_IP_EXTI_V1) + \ + defined(CONFIG_STM32_HAVE_IP_EXTI_V2)) > 1 +# error Only one STM32 EXTI IP version must be selected +#endif + +#if !(defined(CONFIG_STM32_HAVE_IP_EXTI_V1) || defined(CONFIG_STM32_HAVE_IP_EXTI_V2)) +# error "Unsupported STM32 EXTI" +#elif defined(CONFIG_ARCH_CORTEXM0) +# include "hardware/stm32_exti_v1v2_m0.h" +#else +# include "hardware/stm32_exti_v1v2.h" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_exti.h b/arch/arm/src/common/stm32/hardware/stm32_exti_v1v2.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_exti.h rename to arch/arm/src/common/stm32/hardware/stm32_exti_v1v2.h index 80d2d9c4bce..66af0a47a61 100644 --- a/arch/arm/src/stm32/hardware/stm32_exti.h +++ b/arch/arm/src/common/stm32/hardware/stm32_exti_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_exti.h + * arch/arm/src/common/stm32/hardware/stm32_exti_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_EXTI_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_EXTI_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_H /**************************************************************************** * Included Files @@ -55,7 +55,7 @@ # define STM32_EXTI1_MASK 0xffffffff # define STM32_NEXTI2 4 # define STM32_EXTI2_MASK 0x0000000f -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V1) # define STM32_NEXTI 23 # define STM32_EXTI_MASK 0x007fffff #endif @@ -132,7 +132,7 @@ # define EXTI_COMP1 (1 << 21) /* EXTI line 21 is connected to the Comparator 1 wakeup event */ # define EXTI_COMP2 (1 << 22) /* EXTI line 22 is connected to the Comparator 2 wakeup event */ # define EXTI_RTC_ACQUIRE (1 << 23) /* EXTI line 23 is connected to the channel acquisition interrupt */ -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V1) # define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */ # define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */ # define EXTI_OTGFS_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB OTG FS Wakeup event */ @@ -228,4 +228,4 @@ # define STM32_EXTI_PR STM32_EXTI1_PR #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_EXTI_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h b/arch/arm/src/common/stm32/hardware/stm32_exti_v1v2_m0.h similarity index 85% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h rename to arch/arm/src/common/stm32/hardware/stm32_exti_v1v2_m0.h index 82e7cff363d..3f147d2a17f 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h +++ b/arch/arm/src/common/stm32/hardware/stm32_exti_v1v2_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h + * arch/arm/src/common/stm32/hardware/stm32_exti_v1v2_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_M0_H /**************************************************************************** * Included Files @@ -42,4 +42,4 @@ # error "Unrecognized STM32 M0 EXTI" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_fdcan.h b/arch/arm/src/common/stm32/hardware/stm32_fdcan.h new file mode 100644 index 00000000000..6ce5e34f2aa --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_fdcan.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_fdcan.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1)) > 1 +# error Only one STM32 FDCAN IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M0_V1) +# include "hardware/stm32_fdcan_mcan_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1) +# include "hardware/stm32_fdcan_mcan.h" +#else +# error "Unsupported STM32 FDCAN" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_fdcan.h b/arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_fdcan.h rename to arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan.h index 11885bc6b57..be1f77a5d3a 100644 --- a/arch/arm/src/stm32/hardware/stm32_fdcan.h +++ b/arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_fdcan.h + * arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FDCAN_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FDCAN_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_H /**************************************************************************** * Included Files @@ -585,4 +585,4 @@ # define EXTFILTER_F1_EFT_CLASSIC (2 << EXTFILTER_F1_EFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */ # define EXTFILTER_F1_EFT_NOXIDAM (3 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from EF1ID to EF2ID, no XIDAM */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FDCAN_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_fdcan.h b/arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan_m0.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_fdcan.h rename to arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan_m0.h index fa93956fc69..c8a0eba38e3 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_fdcan.h +++ b/arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_fdcan.h + * arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FDCAN_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FDCAN_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_M0_H /**************************************************************************** * Included Files @@ -579,4 +579,4 @@ # define EXTFILTER_F1_EFT_CLASSIC (2 << EXTFILTER_F1_EFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */ # define EXTFILTER_F1_EFT_NOXIDAM (3 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from EF1ID to EF2ID, no XIDAM */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FDCAN_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_flash.h b/arch/arm/src/common/stm32/hardware/stm32_flash.h new file mode 100644 index 00000000000..acfe2f89b92 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_flash.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_flash.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_FLASH_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_V1)) > 1 +# error Only one STM32 flash IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_FLASH_M0_V1) +# include "hardware/stm32_flash_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_V1) +# include "hardware/stm32_flash_v1v2.h" +#else +# error "Unsupported STM32 flash" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h b/arch/arm/src/common/stm32/hardware/stm32_flash_m0.h similarity index 86% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h rename to arch/arm/src/common/stm32/hardware/stm32_flash_m0.h index 57193fbe896..17f642f71e6 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h +++ b/arch/arm/src/common/stm32/hardware/stm32_flash_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h + * arch/arm/src/common/stm32/hardware/stm32_flash_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_M0_H /**************************************************************************** * Included Files @@ -42,4 +42,4 @@ # error "Unsupported STM32 M0 FLASH" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_flash.h b/arch/arm/src/common/stm32/hardware/stm32_flash_v1v2.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_flash.h rename to arch/arm/src/common/stm32/hardware/stm32_flash_v1v2.h index 2da31815084..3a3a5c796b1 100644 --- a/arch/arm/src/stm32/hardware/stm32_flash.h +++ b/arch/arm/src/common/stm32/hardware/stm32_flash_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_flash.h + * arch/arm/src/common/stm32/hardware/stm32_flash_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FLASH_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FLASH_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_V1V2_H /**************************************************************************** * Pre-processor Definitions @@ -45,7 +45,7 @@ #if defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) # if defined(CONFIG_STM32_STM32L15XX) -# if defined(CONFIG_STM32_HIGHDENSITY) +# if defined(CONFIG_STM32L1_HIGHDENSITY) /* Different STM32L1xxx MCU version are now called by different 'categories' * instead of 'densities'. Cat.5 MCU can have up to 512KB of FLASH. @@ -102,7 +102,7 @@ # define STM32_FLASH_NPAGES 128 # define STM32_FLASH_PAGESIZE 2048 -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # define STM32_FLASH_NPAGES 8 # define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (3 * 128)) # define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ @@ -125,7 +125,7 @@ /* Define the Valid Configuration the F2 and F4 */ -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# if defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # if defined(CONFIG_STM32_FLASH_CONFIG_B) # define STM32_FLASH_NPAGES 5 @@ -308,7 +308,7 @@ # define STM32_FLASH_AR_OFFSET 0x0014 # define STM32_FLASH_OBR_OFFSET 0x001c # define STM32_FLASH_WRPR_OFFSET 0x0020 -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # define STM32_FLASH_OPTCR_OFFSET 0x0014 # endif #endif @@ -372,7 +372,7 @@ # define STM32_FLASH_AR (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET) # define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET) # define STM32_FLASH_WRPR (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET) -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET) # endif # if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ @@ -447,7 +447,7 @@ defined(CONFIG_STM32_STM32F37XX) # define FLASH_ACR_PRFTBS (1 << 5) /* Bit 5: FLASH prefetch buffer status */ # endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # define FLASH_ACR_PRFTEN (1 << 8) /* FLASH prefetch enable */ # define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */ # define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */ @@ -464,7 +464,7 @@ # define FLASH_SR_PGERR (1 << 2) /* Programming Error */ # define FLASH_SR_WRPRT_ERR (1 << 4) /* Write Protection Error */ # define FLASH_SR_EOP (1 << 5) /* End of Operation */ -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */ # define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */ # define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */ @@ -533,7 +533,7 @@ defined(CONFIG_STM32_STM32F37XX) # define FLASH_CR_OBL_LAUNCH (1 << 13) /* Bit 13: Force option byte loading */ # endif -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # define FLASH_CR_PG (1 << 0) /* Bit 0: Programming */ # define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */ # define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */ @@ -610,7 +610,7 @@ /* Flash Option Control Register (OPTCR) */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # define FLASH_OPTCR_OPTLOCK (1 << 0) /* Bit 0: Option lock */ # define FLASH_OPTCR_OPTSTRT (1 << 1) /* Bit 1: Option start */ # define FLASH_OPTCR_BORLEV_SHIFT (2) /* Bits 2-3: BOR reset Level */ @@ -786,8 +786,8 @@ int stm32_flash_lock(void); int stm32_flash_unlock(void); -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) int stm32_flash_writeprotect(size_t page, bool enabled); #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FLASH_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_V1V2_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_fmc.h b/arch/arm/src/common/stm32/hardware/stm32_fmc.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_fmc.h rename to arch/arm/src/common/stm32/hardware/stm32_fmc.h index 149b3ab6de9..4b72c82856e 100644 --- a/arch/arm/src/stm32/hardware/stm32_fmc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_fmc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_fmc.h + * arch/arm/src/common/stm32/hardware/stm32_fmc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FMC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FMC_H /**************************************************************************** * Included Files @@ -389,4 +389,4 @@ #define FMC_SDSR_MODES2_SELF_REFRESH (1 << 3) #define FMC_SDSR_MODES2_POWER_DOWN (2 << 3) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FMC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_fsmc.h b/arch/arm/src/common/stm32/hardware/stm32_fsmc.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_fsmc.h rename to arch/arm/src/common/stm32/hardware/stm32_fsmc.h index b53230f351c..703dbb1ab7f 100644 --- a/arch/arm/src/stm32/hardware/stm32_fsmc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_fsmc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_fsmc.h + * arch/arm/src/common/stm32/hardware/stm32_fsmc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMSC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMSC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FSMC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FSMC_H /**************************************************************************** * Included Files @@ -150,7 +150,7 @@ #define FSMC_BCR_WREN (1 << 12) /* Write enable bit */ #define FSMC_BCR_WAITEN (1 << 13) /* Wait enable bit */ #define FSMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) # define FSMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */ #endif #define FSMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */ @@ -298,4 +298,4 @@ #define FSMC_PIO4_IOHIZ_MASK (255 << FSMC_PIO4_IOHIZ_SHIFT) # define FSMC_PIO4_IOHIZ(n) ((n) << FSMC_PIO4_IOHIZ_SHIFT) /* (n)xHCLK n=0..255 */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMSC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FSMC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_memorymap.h b/arch/arm/src/common/stm32/hardware/stm32_gpio.h similarity index 61% rename from arch/arm/src/stm32/hardware/stm32_memorymap.h rename to arch/arm/src/common/stm32/hardware/stm32_gpio.h index 5fd8733f4f6..ea028b5b223 100644 --- a/arch/arm/src/stm32/hardware/stm32_memorymap.h +++ b/arch/arm/src/common/stm32/hardware/stm32_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_memorymap.h + * arch/arm/src/common/stm32/hardware/stm32_gpio.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,34 +20,30 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_H /**************************************************************************** * Included Files ****************************************************************************/ -#include -#include "chip.h" - -#if defined(CONFIG_STM32_STM32L15XX) -# include "hardware/stm32l15xxx_memorymap.h" +#if defined(CONFIG_STM32_HAVE_IP_GPIO_M0_V1) +# include "hardware/stm32_gpio_v2_m0.h" +#elif defined(CONFIG_STM32_STM32L15XX) +# include "hardware/stm32l15xxx_gpio.h" #elif defined(CONFIG_STM32_STM32F10XX) -# include "hardware/stm32f10xxx_memorymap.h" +# include "hardware/stm32f10xxx_gpio.h" #elif defined(CONFIG_STM32_STM32F20XX) -# include "hardware/stm32f20xxx_memorymap.h" -#elif defined(CONFIG_STM32_STM32F30XX) -# include "hardware/stm32f30xxx_memorymap.h" -#elif defined(CONFIG_STM32_STM32F33XX) -# include "hardware/stm32f33xxx_memorymap.h" -#elif defined(CONFIG_STM32_STM32F37XX) -# include "hardware/stm32f37xxx_memorymap.h" +# include "hardware/stm32f20xxx_gpio.h" +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) +# include "hardware/stm32f30xxx_gpio.h" #elif defined(CONFIG_STM32_STM32F4XXX) -# include "hardware/stm32f40xxx_memorymap.h" +# include "hardware/stm32f40xxx_gpio.h" #elif defined(CONFIG_STM32_STM32G4XXX) -# include "hardware/stm32g4xxxx_memorymap.h" +# include "hardware/stm32g4xxxx_gpio.h" #else -# error "Unsupported STM32 memory map" +# error "Unsupported STM32 GPIO" #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h b/arch/arm/src/common/stm32/hardware/stm32_gpio_v2_m0.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h rename to arch/arm/src/common/stm32/hardware/stm32_gpio_v2_m0.h index 11ecd42a32d..94637dfc7a1 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h +++ b/arch/arm/src/common/stm32/hardware/stm32_gpio_v2_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h + * arch/arm/src/common/stm32/hardware/stm32_gpio_v2_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_V2_M0_H /**************************************************************************** * Pre-processor Definitions @@ -344,4 +344,4 @@ #define GPIO_BRR(n) (1 << (n)) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_V2_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_i2c.h b/arch/arm/src/common/stm32/hardware/stm32_i2c.h new file mode 100644 index 00000000000..879ec20a764 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_i2c.h @@ -0,0 +1,51 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_i2c.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_I2C_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2)) > 1 +# error Only one STM32 I2C IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_I2C_M0_V1) +# include "hardware/stm32_i2c_v2_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) || defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) + +#if defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) +# include "stm32_i2c_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) +# include "stm32_i2c_v2.h" +#else +# error STM32 I2C IP version not specified +#endif +#else +# error "Unsupported STM32 I2C" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_i2c_v1.h b/arch/arm/src/common/stm32/hardware/stm32_i2c_v1.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_i2c_v1.h rename to arch/arm/src/common/stm32/hardware/stm32_i2c_v1.h index 85ef897b18c..9f3bbda52a4 100644 --- a/arch/arm/src/stm32/hardware/stm32_i2c_v1.h +++ b/arch/arm/src/common/stm32/hardware/stm32_i2c_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_i2c_v1.h + * arch/arm/src/common/stm32/hardware/stm32_i2c_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V1_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V1_H /* This file provide definitions for the STM32 I2C IP core 1 *(F1, F2, F4 and L1) @@ -200,4 +200,4 @@ # define I2C_FLTR_DNF_MASK (0xf << I2C_FLTR_DNF_SHIFT) #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V1_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_i2c_v2.h b/arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_i2c_v2.h rename to arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h index e1cf7490982..5f3212b26c3 100644 --- a/arch/arm/src/stm32/hardware/stm32_i2c_v2.h +++ b/arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_i2c_v2.h + * arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V2_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V2_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_H /* This file provide definitions for the STM32 I2C IP core 2 (F0, F3, F7, G0, * G4, H7, L0 and L4). @@ -238,4 +238,4 @@ #define I2C_TXDR_MASK (0xff) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V2_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h b/arch/arm/src/common/stm32/hardware/stm32_i2c_v2_m0.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h rename to arch/arm/src/common/stm32/hardware/stm32_i2c_v2_m0.h index aa10265f4a9..2f8d29fd1f9 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h +++ b/arch/arm/src/common/stm32/hardware/stm32_i2c_v2_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h + * arch/arm/src/common/stm32/hardware/stm32_i2c_v2_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_M0_H /**************************************************************************** * Pre-processor Definitions @@ -224,4 +224,4 @@ #define I2C_TXDR_MASK (0xff) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_lcd.h b/arch/arm/src/common/stm32/hardware/stm32_lcd.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_lcd.h rename to arch/arm/src/common/stm32/hardware/stm32_lcd.h index 806fbe38b5a..d23ab4d41e7 100644 --- a/arch/arm/src/stm32/hardware/stm32_lcd.h +++ b/arch/arm/src/common/stm32/hardware/stm32_lcd.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_lcd.h + * arch/arm/src/common/stm32/hardware/stm32_lcd.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LCD_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LCD_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LCD_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LCD_H /**************************************************************************** * Included Files @@ -206,4 +206,4 @@ #define LCD_RAMH_S(n) (1 << ((n)-32)) #endif /* STM32_NLCD */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LCD_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LCD_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_ltdc.h b/arch/arm/src/common/stm32/hardware/stm32_ltdc.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_ltdc.h rename to arch/arm/src/common/stm32/hardware/stm32_ltdc.h index 3d7b9fd3d02..9d7be41f439 100644 --- a/arch/arm/src/stm32/hardware/stm32_ltdc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_ltdc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_ltdc.h + * arch/arm/src/common/stm32/hardware/stm32_ltdc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LTDC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LTDC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LTDC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LTDC_H /**************************************************************************** * Included Files @@ -365,4 +365,4 @@ * Public Types ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LTDC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LTDC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_otghs.h b/arch/arm/src/common/stm32/hardware/stm32_otghs.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_otghs.h rename to arch/arm/src/common/stm32/hardware/stm32_otghs.h index 59583ad9699..42e0fdab7c6 100644 --- a/arch/arm/src/stm32/hardware/stm32_otghs.h +++ b/arch/arm/src/common/stm32/hardware/stm32_otghs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_otghs.h + * arch/arm/src/common/stm32/hardware/stm32_otghs.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OTGHS_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OTGHS_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_OTGHS_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_OTGHS_H /**************************************************************************** * Included Files @@ -1108,4 +1108,4 @@ #define OTGHS_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */ /* Bits 5-31: Reserved, must be kept at reset value */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OTGHS_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_OTGHS_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_pwr.h b/arch/arm/src/common/stm32/hardware/stm32_pwr.h new file mode 100644 index 00000000000..cbd743564b8 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_pwr.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_pwr.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_PWR_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_PWR_G0) + \ + defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1)) > 1 +# error Only one STM32 PWR IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_PWR_M0_V1) || \ + defined(CONFIG_STM32_HAVE_IP_PWR_G0) +# include "hardware/stm32_pwr_v1_m0_g0.h" +#elif defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1) +# include "hardware/stm32_pwr_v1.h" +#else +# error "Unsupported STM32 PWR" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_pwr.h b/arch/arm/src/common/stm32/hardware/stm32_pwr_v1.h similarity index 95% rename from arch/arm/src/stm32/hardware/stm32_pwr.h rename to arch/arm/src/common/stm32/hardware/stm32_pwr_v1.h index 18598c77167..e2fc5e05621 100644 --- a/arch/arm/src/stm32/hardware/stm32_pwr.h +++ b/arch/arm/src/common/stm32/hardware/stm32_pwr_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_pwr.h + * arch/arm/src/common/stm32/hardware/stm32_pwr_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PWR_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PWR_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_H /**************************************************************************** * Included Files @@ -77,7 +77,7 @@ # endif #define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1) # define PWR_CR_FPDS (1 << 9) /* Bit 9: Flash power down in Stop mode */ # if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) || \ @@ -151,7 +151,7 @@ # define PWR_CSR_EWUP (1 << 8) /* Bit 8: Enable WKUP pin */ #endif -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1) # define PWR_CSR_BRE (1 << 9) /* Bit 9: Backup regulator enable */ # define PWR_CSR_VOSRDY (1 << 14) /* Bit 14: Regulator voltage scaling output selection ready bite */ #endif @@ -162,4 +162,4 @@ # define PWR_CSR_ODSWRDY (1 << 17) /* Bit 17: Over Drive Switch ready */ #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PWR_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h b/arch/arm/src/common/stm32/hardware/stm32_pwr_v1_m0_g0.h similarity index 85% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h rename to arch/arm/src/common/stm32/hardware/stm32_pwr_v1_m0_g0.h index bdb173a17cb..66a345f6d82 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h +++ b/arch/arm/src/common/stm32/hardware/stm32_pwr_v1_m0_g0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h + * arch/arm/src/common/stm32/hardware/stm32_pwr_v1_m0_g0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_M0_G0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_M0_G0_H /**************************************************************************** * Included Files @@ -42,4 +42,4 @@ # error "Unsupported STM32 M0 PWR" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_M0_G0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_rcc.h b/arch/arm/src/common/stm32/hardware/stm32_rcc.h new file mode 100644 index 00000000000..308cd4d9df9 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_rcc.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_rcc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RCC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_ARCH_CHIP_STM32F0) +# include "hardware/stm32f0_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32L0) +# include "hardware/stm32l0_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32G0) +# include "hardware/stm32g0_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32C0) +# include "hardware/stm32c0_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F1) +# include "hardware/stm32f10xxx_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F2) +# include "hardware/stm32f20xxx_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F3) +# if defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F302X8) || \ + defined(CONFIG_STM32_STM32F302XC) || \ + defined(CONFIG_STM32_STM32F303XC) || \ + defined(CONFIG_STM32_STM32F303XE) +# include "hardware/stm32f30xxx_rcc.h" +# elif defined(CONFIG_STM32_STM32F33XX) +# include "hardware/stm32f33xxx_rcc.h" +# elif defined(CONFIG_STM32_STM32F37XX) +# include "hardware/stm32f37xxx_rcc.h" +# else +# error "Unsupported STM32F3 RCC" +# endif +#elif defined(CONFIG_ARCH_CHIP_STM32F4) +# include "hardware/stm32f40xxx_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32G4) +# include "hardware/stm32g4xxxx_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32L1) +# include "hardware/stm32l15xxx_rcc.h" +#else +# error "Unsupported STM32 RCC" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_rng.h b/arch/arm/src/common/stm32/hardware/stm32_rng.h new file mode 100644 index 00000000000..5b81e5116b6 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_rng.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_rng.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_RNG_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_RNG_M3M4_V1)) > 1 +# error Only one STM32 RNG IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_RNG_M0_V1) +# include "hardware/stm32_rng_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_RNG_M3M4_V1) +# include "hardware/stm32_rng_v1.h" +#else +# error "Unsupported STM32 RNG" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h b/arch/arm/src/common/stm32/hardware/stm32_rng_m0.h similarity index 92% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h rename to arch/arm/src/common/stm32/hardware/stm32_rng_m0.h index 7155e947581..1fc3c863998 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h +++ b/arch/arm/src/common/stm32/hardware/stm32_rng_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h + * arch/arm/src/common/stm32/hardware/stm32_rng_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_M0_H /**************************************************************************** * Included Files @@ -62,4 +62,4 @@ #define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */ #define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_rng.h b/arch/arm/src/common/stm32/hardware/stm32_rng_v1.h similarity index 91% rename from arch/arm/src/stm32/hardware/stm32_rng.h rename to arch/arm/src/common/stm32/hardware/stm32_rng_v1.h index 645994e2f66..51a829ed5dc 100644 --- a/arch/arm/src/stm32/hardware/stm32_rng.h +++ b/arch/arm/src/common/stm32/hardware/stm32_rng_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_rng.h + * arch/arm/src/common/stm32/hardware/stm32_rng_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_V1_H /**************************************************************************** * Included Files @@ -61,4 +61,4 @@ #define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */ #define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_V1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_rtc.h b/arch/arm/src/common/stm32/hardware/stm32_rtc.h similarity index 94% rename from arch/arm/src/stm32/hardware/stm32_rtc.h rename to arch/arm/src/common/stm32/hardware/stm32_rtc.h index fc768d7aa02..b80f73f118f 100644 --- a/arch/arm/src/stm32/hardware/stm32_rtc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_rtc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_rtc.h + * arch/arm/src/common/stm32/hardware/stm32_rtc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_H /**************************************************************************** * Pre-processor Definitions @@ -80,4 +80,4 @@ #define RTC_DIVH_RTC_DIV_SHIFT (0) /* Bits 3-0: RTC Clock Divider High */ #define RTC_DIVH_RTC_DIV_MASK (0x0f << RTC_DIVH_RTC_DIV_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_rtcc.h b/arch/arm/src/common/stm32/hardware/stm32_rtcc.h new file mode 100644 index 00000000000..7431435f80f --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_rtcc.h @@ -0,0 +1,47 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_rtcc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_RTCC_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_L1) + \ + defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_F4)) > 1 +# error Only one STM32 RTCC IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_RTCC_M0_V1) +# include "hardware/stm32_rtcc_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_L1) || \ + defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_F4) +# include "hardware/stm32_rtcc_v1.h" +#else +# error "Unsupported STM32 RTCC" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h b/arch/arm/src/common/stm32/hardware/stm32_rtcc_m0.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h rename to arch/arm/src/common/stm32/hardware/stm32_rtcc_m0.h index 78145ffc5ca..e90b3270896 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_rtcc_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h + * arch/arm/src/common/stm32/hardware/stm32_rtcc_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_M0_H /**************************************************************************** * Pre-processor Definitions @@ -311,4 +311,4 @@ #define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */ #define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_rtcc.h b/arch/arm/src/common/stm32/hardware/stm32_rtcc_v1.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_rtcc.h rename to arch/arm/src/common/stm32/hardware/stm32_rtcc_v1.h index e939a1214ea..278f432ecd8 100644 --- a/arch/arm/src/stm32/hardware/stm32_rtcc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_rtcc_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_rtcc.h + * arch/arm/src/common/stm32/hardware/stm32_rtcc_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTCC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTCC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_V1C_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_V1C_H /**************************************************************************** * Pre-processor Definitions @@ -405,4 +405,4 @@ #define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */ #define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTCC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_V1C_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_sdio.h b/arch/arm/src/common/stm32/hardware/stm32_sdio.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_sdio.h rename to arch/arm/src/common/stm32/hardware/stm32_sdio.h index 4c732893275..d9c18c5b7d5 100644 --- a/arch/arm/src/stm32/hardware/stm32_sdio.h +++ b/arch/arm/src/common/stm32/hardware/stm32_sdio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_sdio.h + * arch/arm/src/common/stm32/hardware/stm32_sdio.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SDIO_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SDIO_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SDIO_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SDIO_H /**************************************************************************** * Pre-processor Definitions @@ -276,4 +276,4 @@ #define SDIO_FIFOCNT_SHIFT (0) #define SDIO_FIFOCNT_MASK (0x01ffffff << SDIO_FIFOCNT_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SDIO_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SDIO_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_spi.h b/arch/arm/src/common/stm32/hardware/stm32_spi.h new file mode 100644 index 00000000000..2d9836336ef --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_spi.h @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_spi.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* The SPI IP version (V1..V4) is independent of the CPU core. The register + * layout is the same, but the M0 and M3/M4 ports currently keep separate + * register headers, so the file is chosen by the standard NuttX core symbol + * (CONFIG_ARCH_CORTEXM0) while the version is core-agnostic. + */ + +#if (defined(CONFIG_STM32_HAVE_IP_SPI_V1) + \ + defined(CONFIG_STM32_HAVE_IP_SPI_V2) + \ + defined(CONFIG_STM32_HAVE_IP_SPI_V3) + \ + defined(CONFIG_STM32_HAVE_IP_SPI_V4)) > 1 +# error Only one STM32 SPI IP version must be selected +#endif + +#if !(defined(CONFIG_STM32_HAVE_IP_SPI_V1) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V2) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V3) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V4)) +# error "Unsupported STM32 SPI" +#elif defined(CONFIG_ARCH_CORTEXM0) +# include "hardware/stm32_spi_v1v2_m0.h" +#else +# include "hardware/stm32_spi_v2v3v4.h" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h b/arch/arm/src/common/stm32/hardware/stm32_spi_v1v2_m0.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h rename to arch/arm/src/common/stm32/hardware/stm32_spi_v1v2_m0.h index fd63397093e..8d730e7b21f 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h +++ b/arch/arm/src/common/stm32/hardware/stm32_spi_v1v2_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h + * arch/arm/src/common/stm32/hardware/stm32_spi_v1v2_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V1V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V1V2_M0_H /**************************************************************************** * Included Files @@ -32,14 +32,12 @@ /* Select STM32 SPI IP core */ -#if defined(CONFIG_STM32_STM32F0) || \ - defined(CONFIG_STM32_STM32G0) || \ - defined(CONFIG_STM32_STM32C0) +#if defined(CONFIG_STM32_HAVE_IP_SPI_V2) # define HAVE_IP_SPI_V2 -#elif defined(CONFIG_STM32_STM32L0) +#elif defined(CONFIG_STM32_HAVE_IP_SPI_V1) # define HAVE_IP_SPI_V1 #else -# error Unsupported family +# error Unsupported STM32 F0/L0/G0/C0 SPI IP #endif /**************************************************************************** @@ -229,4 +227,4 @@ #define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */ #define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V1V2_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_spi.h b/arch/arm/src/common/stm32/hardware/stm32_spi_v2v3v4.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_spi.h rename to arch/arm/src/common/stm32/hardware/stm32_spi_v2v3v4.h index b52e278e380..187df078bf5 100644 --- a/arch/arm/src/stm32/hardware/stm32_spi.h +++ b/arch/arm/src/common/stm32/hardware/stm32_spi_v2v3v4.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_spi.h + * arch/arm/src/common/stm32/hardware/stm32_spi_v2v3v4.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SPI_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SPI_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V2V3V4_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V2V3V4_H /**************************************************************************** * Included Files @@ -45,7 +45,7 @@ #undef HAVE_SPI_FIFOS /* No Tx/Rx FIFOs */ #undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ -#if defined(STM32_HAVE_IP_SPI_V2) +#if defined(CONFIG_STM32_HAVE_IP_SPI_V2) # define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ # undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ # define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ @@ -54,7 +54,7 @@ # undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ #endif -#if defined(STM32_HAVE_IP_SPI_V3) +#if defined(CONFIG_STM32_HAVE_IP_SPI_V3) # define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ # undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ # define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ @@ -63,7 +63,7 @@ # undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ #endif -#if defined(STM32_HAVE_IP_SPI_V4) +#if defined(CONFIG_STM32_HAVE_IP_SPI_V4) # define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ # define HAVE_SPI_I2S_ASTRT /* Supports I2S asynchronous start capability */ # define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ @@ -280,4 +280,4 @@ # define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */ #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SPI_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V2V3V4_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h b/arch/arm/src/common/stm32/hardware/stm32_syscfg.h similarity index 86% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h rename to arch/arm/src/common/stm32/hardware/stm32_syscfg.h index f8966bbbcb3..7ed634e52b2 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h +++ b/arch/arm/src/common/stm32/hardware/stm32_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h + * arch/arm/src/common/stm32/hardware/stm32_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SYSCFG_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SYSCFG_H /**************************************************************************** * Included Files @@ -40,4 +40,4 @@ # error "Unsupported STM32 M0 SYSCFG" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SYSCFG_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_tim.h b/arch/arm/src/common/stm32/hardware/stm32_tim.h similarity index 64% rename from arch/arm/src/stm32/hardware/stm32_tim.h rename to arch/arm/src/common/stm32/hardware/stm32_tim.h index 3815bf402db..4db3706e889 100644 --- a/arch/arm/src/stm32/hardware/stm32_tim.h +++ b/arch/arm/src/common/stm32/hardware/stm32_tim.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_tim.h + * arch/arm/src/common/stm32/hardware/stm32_tim.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,13 +20,26 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_H /**************************************************************************** * Included Files ****************************************************************************/ +#if (defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) + \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3)) > 1 +# error Only one STM32 TIMER IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) +# include "hardware/stm32_tim_v3_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) + #if defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) # include "stm32_tim_v1v2.h" @@ -35,5 +48,8 @@ #else # error "STM32 TIMER IP version not specified" #endif +#else +# error "Unsupported STM32 TIM" +#endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h b/arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_tim_v1v2.h rename to arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h index 44b35d1140f..d519a4df68e 100644 --- a/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h +++ b/arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_tim_v1v2.h + * arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V1V2_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V1V2_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V1V2_H /**************************************************************************** * Pre-processor Definitions @@ -1304,4 +1304,4 @@ #define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V1V2_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V1V2_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_tim_v3.h b/arch/arm/src/common/stm32/hardware/stm32_tim_v3.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_tim_v3.h rename to arch/arm/src/common/stm32/hardware/stm32_tim_v3.h index eb6e5421394..d4bd858b591 100644 --- a/arch/arm/src/stm32/hardware/stm32_tim_v3.h +++ b/arch/arm/src/common/stm32/hardware/stm32_tim_v3.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_tim_v3.h + * arch/arm/src/common/stm32/hardware/stm32_tim_v3.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V3_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V3_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_H /**************************************************************************** * Included Files @@ -1437,4 +1437,4 @@ #define BTIM_ARR_MASK_16 (0xffff << BTIM_ARR_SHIFT) /* Bits 0-15: Auto reload register */ #define BTIM_ARR_MASK_20 (0xfffff << BTIM_ARR_SHIFT) /* Bits 0-19: Auto reload register when BTIM_CR1_DITHEN */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V3_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h b/arch/arm/src/common/stm32/hardware/stm32_tim_v3_m0.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h rename to arch/arm/src/common/stm32/hardware/stm32_tim_v3_m0.h index 7149293388a..211e43f7d51 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h +++ b/arch/arm/src/common/stm32/hardware/stm32_tim_v3_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h + * arch/arm/src/common/stm32/hardware/stm32_tim_v3_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_M0_H /**************************************************************************** * Included Files @@ -1148,4 +1148,4 @@ #define BTIM_CNT_UIFCPY (1 << 31) /* Bit 31: UIF copy */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_M0_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial.c b/arch/arm/src/common/stm32/hardware/stm32_uart.h similarity index 63% rename from arch/arm/src/stm32f0l0g0/stm32_serial.c rename to arch/arm/src/common/stm32/hardware/stm32_uart.h index 5edb01036ef..471eb707aef 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial.c +++ b/arch/arm/src/common/stm32/hardware/stm32_uart.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_serial.c + * arch/arm/src/common/stm32/hardware/stm32_uart.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,6 +20,9 @@ * ****************************************************************************/ +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_H + /**************************************************************************** * Included Files ****************************************************************************/ @@ -27,20 +30,23 @@ #include #include "chip.h" -/* This file is only a thin shell that includes the correct serial - * implementation for the selected STM32 IP core: - * - STM32 UART IP version 1 - F0, L0 - * - STM32 UART IP version 2 - G0 - */ - -#if defined(CONFIG_STM32_HAVE_IP_USART_V1) -# include "stm32_serial_v1.c" -#elif defined(CONFIG_STM32_HAVE_IP_USART_V2) -# include "stm32_serial_v2.c" -#else -# error "Unsupported STM32 M0 serial" +#if (defined(CONFIG_STM32_HAVE_IP_USART_V1) + \ + defined(CONFIG_STM32_HAVE_IP_USART_V2) + \ + defined(CONFIG_STM32_HAVE_IP_USART_V3) + \ + defined(CONFIG_STM32_HAVE_IP_USART_V4)) > 1 +# error Only one STM32 USART IP version must be selected #endif -/**************************************************************************** - * Public Functions - ****************************************************************************/ +#if defined(CONFIG_STM32_HAVE_IP_USART_V1) +# include "hardware/stm32_uart_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_USART_V2) +# include "hardware/stm32_uart_v2.h" +#elif defined(CONFIG_STM32_HAVE_IP_USART_V3) +# include "hardware/stm32_uart_v3.h" +#elif defined(CONFIG_STM32_HAVE_IP_USART_V4) +# include "hardware/stm32_uart_v4.h" +#else +# error "Unsupported STM32 USART core" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_uart_v1.h b/arch/arm/src/common/stm32/hardware/stm32_uart_v1.h new file mode 100644 index 00000000000..3938a7f13fd --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_uart_v1.h @@ -0,0 +1,206 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_uart_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V1_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ +#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ +#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ +#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ +#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ +#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ +#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ + +/* Register Addresses *******************************************************/ + +#if STM32_NUSART > 0 +# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 1 +# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 2 +# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 3 +# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) +#endif + +#if STM32_NUSART > 4 +# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* Status register */ + +#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ +#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ +#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ +#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ +#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ +#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ +#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ +#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ +#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ +#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ + +#define USART_SR_ALLBITS (0x03ff) +#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ + +/* Data register */ + +#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ +#define USART_DR_MASK (0xff << USART_DR_SHIFT) + +/* Baud Rate Register */ + +#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ +#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) +#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ +#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) + +/* Control register 1 */ + +#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ +#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ +#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ +#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ +#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ +#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ +#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ +#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ +#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ +#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ +#define USART_CR1_M (1 << 12) /* Bit 12: word length */ +#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ + +#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) + +/* Control register 2 */ + +#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ +#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) +#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ +#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ +#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ +#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ +#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ +#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ +#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) +# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ +# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ +# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ +# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ + +#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ + +/* Control register 3 */ + +#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ +#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ +#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ +#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ +#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ +#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ +#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ +#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ +#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ +#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ +#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ + +/* Guard time and prescaler register */ + +#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ +#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) +#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ +#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) + +/* Compatibility definitions ************************************************/ + +/* F3 Transmit/Read registers */ + +#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ +#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V1_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_uart_v2.h b/arch/arm/src/common/stm32/hardware/stm32_uart_v2.h new file mode 100644 index 00000000000..02f3811c221 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_uart_v2.h @@ -0,0 +1,236 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_uart_v2.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V2_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ +#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ +#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ +#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ +#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ +#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ +#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ + +/* Register Addresses *******************************************************/ + +#if STM32_NUSART > 0 +# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 1 +# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 2 +# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 3 +# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) +#endif + +#if STM32_NUSART > 4 +# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) +#endif + +#if STM32_NUSART > 5 +# define STM32_USART6_SR (STM32_USART6_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART6_DR (STM32_USART6_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART6_BRR (STM32_USART6_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART6_GTPR (STM32_USART6_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 6 +# define STM32_UART7_SR (STM32_UART7_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART7_DR (STM32_UART7_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART7_BRR (STM32_UART7_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET) +#endif + +#if STM32_NUSART > 7 +# define STM32_UART8_SR (STM32_UART8_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART8_DR (STM32_UART8_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART8_BRR (STM32_UART8_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* Status register */ + +#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ +#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ +#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ +#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ +#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ +#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ +#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ +#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ +#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ +#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ + +#define USART_SR_ALLBITS (0x03ff) +#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ + +/* Data register */ + +#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ +#define USART_DR_MASK (0xff << USART_DR_SHIFT) + +/* Baud Rate Register */ + +#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ +#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) +#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ +#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) + +/* Control register 1 */ + +#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ +#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ +#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ +#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ +#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ +#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ +#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ +#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ +#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ +#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ +#define USART_CR1_M (1 << 12) /* Bit 12: word length */ +#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ +#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ + +#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) + +/* Control register 2 */ + +#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ +#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) +#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ +#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ +#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ +#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ +#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ +#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ +#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) +# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ +# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ +# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ +# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ + +#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ + +/* Control register 3 */ + +#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ +#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ +#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ +#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ +#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ +#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ +#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ +#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ +#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ +#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ +#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ +#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ + +/* Guard time and prescaler register */ + +#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ +#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) +#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ +#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) + +/* Compatibility definitions ************************************************/ + +/* F3 Transmit/Read registers */ + +#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ +#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h b/arch/arm/src/common/stm32/hardware/stm32_uart_v3.h similarity index 91% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h rename to arch/arm/src/common/stm32/hardware/stm32_uart_v3.h index 41bc90b3ae5..be5e3970c92 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h +++ b/arch/arm/src/common/stm32/hardware/stm32_uart_v3.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h + * arch/arm/src/common/stm32/hardware/stm32_uart_v3.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V1_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V3_H /**************************************************************************** * Included Files @@ -192,6 +192,8 @@ #define USART_CR2_ADD_SHIFT (24) /* Bits 24-31: Address of the USART node */ #define USART_CR2_ADD_MASK (0xff << USART_CR2_ADD_SHIFT) +#define USART_CR2_ADD8_SHIFT USART_CR2_ADD_SHIFT /* F1/F2/F4-compatible name */ +#define USART_CR2_ADD8_MASK USART_CR2_ADD_MASK /* Control register 3 */ @@ -275,6 +277,8 @@ #define USART_ISR_TEACK (1 << 21) /* Bit 20: Transmit enable acknowledge Flag */ #define USART_ISR_REACK (1 << 22) /* Bit 21: Receive enable acknowledge Flag */ +#define USART_ISR_ALLBITS (0x007fdfff) + /* ICR */ #define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */ @@ -300,4 +304,28 @@ #define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */ #define USART_TDR_MASK (0xff << USART_TDR_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V1_H */ +/* Compatibility definitions ************************************************/ + +/* Compatibility with F1/F2/F4 Status Register names. This USART IP replaces + * the SR register with separate ISR/ICR registers; alias the legacy SR names + * so the shared M3/M4 serial driver keeps working on these parts. + */ + +#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET + +#define USART_SR_PE USART_ISR_PE /* Parity Error */ +#define USART_SR_FE USART_ISR_FE /* Framing error */ +#define USART_SR_NE USART_ISR_NF /* Noise detected flag */ +#define USART_SR_ORE USART_ISR_ORE /* Overrun error */ +#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */ +#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */ +#define USART_SR_TC USART_ISR_TC /* Transmission Complete */ +#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */ +#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */ +#define USART_SR_CTS USART_ISR_CTS /* CTS Flag */ + +#define USART_SR_ALLBITS USART_ISR_ALLBITS + +#define USART_CR1_M USART_CR1_M0 + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V3_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h b/arch/arm/src/common/stm32/hardware/stm32_uart_v4.h similarity index 91% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h rename to arch/arm/src/common/stm32/hardware/stm32_uart_v4.h index 82dbcfdcc2f..8f8f0900c93 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h +++ b/arch/arm/src/common/stm32/hardware/stm32_uart_v4.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h + * arch/arm/src/common/stm32/hardware/stm32_uart_v4.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V2_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V2_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V4_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V4_H /**************************************************************************** * Included Files @@ -153,6 +153,14 @@ USART_CR1_PEIE | USART_CR1_CMIE |USART_CR1_RTOIE | USART_CR1_EOBIE |\ USART_CR1_TXFEIE | USART_CR1_RXFFIE) +/* LPUART shares the USART CR1 layout but has no receiver-timeout or + * end-of-block interrupts. + */ + +#define LPUART_CR1_ALLINTS \ + (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | USART_CR1_TXEIE |\ + USART_CR1_PEIE | USART_CR1_CMIE | USART_CR1_TXFEIE | USART_CR1_RXFFIE) + /* Control register 2 */ #define USART_CR2_SLVEN (1 << 0) /* Bit 0: Synchronous Slave mode enable */ @@ -216,6 +224,12 @@ #define USART_CR3_SCARCNT_SHIFT (17) /* Bit 17-19: Smartcard auto-retry count */ #define USART_CR3_SCARCNT_MASK (7 << USART_CR3_SCARCNT_SHIFT) # define USART_CR3_SCARCNT(n) ((uint32_t)(n) << USART_CR3_SCARCNT_SHIFT) +#define USART_CR3_WUS_SHIFT (20) /* Bit 20-21: Wakeup interrupt flag selection */ +#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT) +# define USART_CR3_WUS_ADDR (0 << USART_CR3_WUS_SHIFT) +# define USART_CR3_WUS_STARTBIT (2 << USART_CR3_WUS_SHIFT) +# define USART_CR3_WUS_RXFNE (3 << USART_CR3_WUS_SHIFT) +#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup interrupt enable */ #define USART_CR3_RXFTCFG_SHIFT (25) /* Bit 25-27: Receive FIFO threshold configuration */ #define USART_CR3_RXFTCFG_MASK (7 << USART_CR3_RXFTCFG_SHIFT) # define USART_CR3_RXFTCFG(n) ((uint32_t)(n) << USART_CR3_RXFTCFG_SHIFT) @@ -349,4 +363,28 @@ # define USART_PRESC_DIV128 (10 << USART_PRESC_SHIFT) /* Input clock divided by 128 */ # define USART_PRESC_DIV256 (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V2_H */ +/* Compatibility definitions ************************************************/ + +/* Compatibility with F1/F2/F4 Status Register names. This USART IP replaces + * the SR register with separate ISR/ICR registers; alias the legacy SR names + * so the shared M3/M4 serial driver keeps working on these parts. + */ + +#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET + +#define USART_SR_PE USART_ISR_PE /* Parity Error */ +#define USART_SR_FE USART_ISR_FE /* Framing error */ +#define USART_SR_NE USART_ISR_NE /* Noise detected flag */ +#define USART_SR_ORE USART_ISR_ORE /* Overrun error */ +#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */ +#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */ +#define USART_SR_TC USART_ISR_TC /* Transmission Complete */ +#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */ +#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */ +#define USART_SR_CTS USART_ISR_CTS /* CTS Flag */ + +#define USART_SR_ALLBITS USART_ISR_ALLBITS + +#define USART_CR1_M USART_CR1_M0 + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V4_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_usbdev.h b/arch/arm/src/common/stm32/hardware/stm32_usbdev.h new file mode 100644 index 00000000000..ae78216c98a --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_usbdev.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_usbdev.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_USBDEV_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_USBDEV_M3M4_V1)) > 1 +# error Only one STM32 USB device IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_USBDEV_M0_V1) +# include "hardware/stm32_usbdev_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_USBDEV_M3M4_V1) +# include "hardware/stm32_usbdev_v1.h" +#else +# error "Unsupported STM32 USB device" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h b/arch/arm/src/common/stm32/hardware/stm32_usbdev_m0.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h rename to arch/arm/src/common/stm32/hardware/stm32_usbdev_m0.h index 52f0df5aef2..d40fb53b23a 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h +++ b/arch/arm/src/common/stm32/hardware/stm32_usbdev_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h + * arch/arm/src/common/stm32/hardware/stm32_usbdev_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_M0_H /**************************************************************************** * Included Files @@ -252,4 +252,4 @@ #define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT) #endif /* CONFIG_STM32_HAVE_USBDEV */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_usbdev.h b/arch/arm/src/common/stm32/hardware/stm32_usbdev_v1.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_usbdev.h rename to arch/arm/src/common/stm32/hardware/stm32_usbdev_v1.h index a2c0e400294..2a7b97f4936 100644 --- a/arch/arm/src/stm32/hardware/stm32_usbdev.h +++ b/arch/arm/src/common/stm32/hardware/stm32_usbdev_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_usbdev.h + * arch/arm/src/common/stm32/hardware/stm32_usbdev_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBDEV_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBDEV_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_V1_H /**************************************************************************** * Included Files @@ -224,4 +224,4 @@ #define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT) #endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F37XX */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBDEV_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_V1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_usbfs.h b/arch/arm/src/common/stm32/hardware/stm32_usbfs.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_usbfs.h rename to arch/arm/src/common/stm32/hardware/stm32_usbfs.h index 1d83a91e3f0..cd0fc280184 100644 --- a/arch/arm/src/stm32/hardware/stm32_usbfs.h +++ b/arch/arm/src/common/stm32/hardware/stm32_usbfs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_usbfs.h + * arch/arm/src/common/stm32/hardware/stm32_usbfs.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBFS_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBFS_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBFS_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBFS_H /**************************************************************************** * Included Files @@ -247,4 +247,4 @@ #define USB_BCDR_DPPU (1 << 15) /* Bit 15: DP pull-up control */ #endif /* CONFIG_STM32_USBFS */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBFS_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBFS_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_wdg.h b/arch/arm/src/common/stm32/hardware/stm32_wdg.h new file mode 100644 index 00000000000..2a24642f307 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_wdg.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_wdg.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_WDG_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_WDG_M3M4_V1)) > 1 +# error Only one STM32 WDG IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_WDG_M0_V1) +# include "hardware/stm32_wdg_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_WDG_M3M4_V1) +# include "hardware/stm32_wdg_v1v2.h" +#else +# error "Unsupported STM32 WDG" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h b/arch/arm/src/common/stm32/hardware/stm32_wdg_m0.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h rename to arch/arm/src/common/stm32/hardware/stm32_wdg_m0.h index 824bf9c6a7d..eb366fccc37 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h +++ b/arch/arm/src/common/stm32/hardware/stm32_wdg_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h + * arch/arm/src/common/stm32/hardware/stm32_wdg_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_M0_H /**************************************************************************** * Included Files @@ -138,4 +138,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_wdg.h b/arch/arm/src/common/stm32/hardware/stm32_wdg_v1v2.h similarity index 96% rename from arch/arm/src/stm32/hardware/stm32_wdg.h rename to arch/arm/src/common/stm32/hardware/stm32_wdg_v1v2.h index 55ac57d3b64..8febf5740cb 100644 --- a/arch/arm/src/stm32/hardware/stm32_wdg.h +++ b/arch/arm/src/common/stm32/hardware/stm32_wdg_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_wdg.h + * arch/arm/src/common/stm32/hardware/stm32_wdg_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_WDG_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_WDG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_V1V2_H /**************************************************************************** * Included Files @@ -147,4 +147,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_WDG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_V1V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h b/arch/arm/src/common/stm32/hardware/stm32_wdt.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h rename to arch/arm/src/common/stm32/hardware/stm32_wdt.h index 54c6a345b3a..d99695aa858 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h +++ b/arch/arm/src/common/stm32/hardware/stm32_wdt.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h + * arch/arm/src/common/stm32/hardware/stm32_wdt.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDT_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDT_H /**************************************************************************** * Included Files @@ -126,4 +126,4 @@ #define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDT_H */ diff --git a/arch/arm/src/stm32/hardware/stm32fxxxxx_otgfs.h b/arch/arm/src/common/stm32/hardware/stm32fxxxxx_otgfs.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32fxxxxx_otgfs.h rename to arch/arm/src/common/stm32/hardware/stm32fxxxxx_otgfs.h index 199b4098af4..610531a01d8 100644 --- a/arch/arm/src/stm32/hardware/stm32fxxxxx_otgfs.h +++ b/arch/arm/src/common/stm32/hardware/stm32fxxxxx_otgfs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32fxxxxx_otgfs.h + * arch/arm/src/common/stm32/hardware/stm32fxxxxx_otgfs.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32FXXXXX_OTGFS_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32FXXXXX_OTGFS_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32FXXXXX_OTGFS_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32FXXXXX_OTGFS_H /**************************************************************************** * Included Files @@ -1112,4 +1112,4 @@ #define OTGFS_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */ /* Bits 5-31: Reserved, must be kept at reset value */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32FXXXXX_OTGFS_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32FXXXXX_OTGFS_H */ diff --git a/arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h b/arch/arm/src/common/stm32/hardware/stm32gxxxxx_dac.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h rename to arch/arm/src/common/stm32/hardware/stm32gxxxxx_dac.h index 0b412885c97..d48838484d9 100644 --- a/arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h +++ b/arch/arm/src/common/stm32/hardware/stm32gxxxxx_dac.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h + * arch/arm/src/common/stm32/hardware/stm32gxxxxx_dac.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32GXXXXX_DAC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32GXXXXX_DAC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32GXXXXX_DAC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32GXXXXX_DAC_H /**************************************************************************** * Included Files @@ -522,4 +522,4 @@ #define DAC_STR_STINCDATA_SHIFT (16) /* DAC channel 1 Sawtooth increment value (12.4 bit format) */ #define DAC_STR_STINCDATA_MASK (0xffff << DAC_STR_STINCDATA_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32GXXXXX_DAC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32GXXXXX_DAC_H */ diff --git a/arch/arm/src/stm32/stm32_1wire.h b/arch/arm/src/common/stm32/stm32_1wire.h similarity index 92% rename from arch/arm/src/stm32/stm32_1wire.h rename to arch/arm/src/common/stm32/stm32_1wire.h index dbd2ed588d7..79f9f6d47e4 100644 --- a/arch/arm/src/stm32/stm32_1wire.h +++ b/arch/arm/src/common/stm32/stm32_1wire.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_1wire.h + * arch/arm/src/common/stm32/stm32_1wire.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_1WIRE_H -#define __ARCH_ARM_SRC_STM32_STM32_1WIRE_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_1WIRE_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_1WIRE_H /**************************************************************************** * Included Files @@ -29,6 +29,8 @@ #include +#include + #include "stm32_uart.h" /**************************************************************************** @@ -71,4 +73,4 @@ struct onewire_dev_s *stm32_1wireinitialize(int port); int stm32_1wireuninitialize(struct onewire_dev_s *dev); -#endif /* __ARCH_ARM_SRC_STM32_STM32_1WIRE_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_1WIRE_H */ diff --git a/arch/arm/src/stm32/stm32_1wire.c b/arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_1wire.c rename to arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c index e3c27f32354..595136c6c65 100644 --- a/arch/arm/src/stm32/stm32_1wire.c +++ b/arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_1wire.c + * arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -52,6 +52,7 @@ #include "arm_internal.h" #include "stm32_rcc.h" #include "stm32_1wire.h" +#include "stm32_rcc.h" #ifdef HAVE_1WIREDRIVER diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc.c b/arch/arm/src/common/stm32/stm32_adc.h similarity index 73% rename from arch/arm/src/stm32f0l0g0/stm32_lowputc.c rename to arch/arm/src/common/stm32/stm32_adc.h index 91bd0cfbeae..fce412ef2ef 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lowputc.c +++ b/arch/arm/src/common/stm32/stm32_adc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lowputc.c + * arch/arm/src/common/stm32/stm32_adc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,21 +20,21 @@ * ****************************************************************************/ +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_ADC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_ADC_H + /**************************************************************************** * Included Files ****************************************************************************/ #include -#include "chip.h" -#if defined(CONFIG_STM32_HAVE_IP_USART_V1) -# include "stm32_lowputc_v1.c" -#elif defined(CONFIG_STM32_HAVE_IP_USART_V2) -# include "stm32_lowputc_v2.c" +#if defined(CONFIG_STM32_HAVE_IP_ADC_M0_V1) +# include "stm32_adc_m0_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) || defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) +# include "stm32_adc_m3m4_v1v2.h" #else -# error "Unsupported STM32 M0 serial" +# error "Unsupported STM32 ADC" #endif -/**************************************************************************** - * Public Functions - ****************************************************************************/ +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_ADC_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_adc.c b/arch/arm/src/common/stm32/stm32_adc_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_adc.c rename to arch/arm/src/common/stm32/stm32_adc_m0_v1.c index 6366eb0ed32..cfa4e5c8cf1 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_adc.c +++ b/arch/arm/src/common/stm32/stm32_adc_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_adc.c + * arch/arm/src/common/stm32/stm32_adc_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_adc.h b/arch/arm/src/common/stm32/stm32_adc_m0_v1.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_adc.h rename to arch/arm/src/common/stm32/stm32_adc_m0_v1.h index 579d1ffc21c..1cd50f60f7c 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_adc.h +++ b/arch/arm/src/common/stm32/stm32_adc_m0_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_adc.h + * arch/arm/src/common/stm32/stm32_adc_m0_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V2_M0_H /**************************************************************************** * Included Files @@ -165,7 +165,7 @@ /* TRG5 and TRG6 reserved */ # define ADC1_EXTSEL_EXTI11 ADC12_CFGR1_EXTSEL_TRG7 #else -# error +# error "Unrecognized STM32 M0 sub-family for ADC EXTSEL" #endif /* EXTSEL configuration *****************************************************/ @@ -445,4 +445,4 @@ const struct stm32_adc_ops_s #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_ADC1 */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V2_M0_H */ diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c similarity index 99% rename from arch/arm/src/stm32/stm32_adc.c rename to arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c index 331b4f1b795..b53e2b6a071 100644 --- a/arch/arm/src/stm32/stm32_adc.c +++ b/arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_adc.c + * arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_adc.h b/arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h similarity index 99% rename from arch/arm/src/stm32/stm32_adc.h rename to arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h index 05c5bdf4801..b6317b5e32d 100644 --- a/arch/arm/src/stm32/stm32_adc.h +++ b/arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_adc.h + * arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_ADC_H -#define __ARCH_ARM_SRC_STM32_STM32_ADC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V1V2_H /**************************************************************************** * Included Files @@ -134,7 +134,7 @@ # undef CONFIG_STM32_TIM4_ADC4 #endif -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) # ifndef CONFIG_STM32_TIM5 # undef CONFIG_STM32_TIM5_ADC # undef CONFIG_STM32_TIM5_ADC1 @@ -2342,4 +2342,4 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, #endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || * CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4 */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_ADC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V1V2_H */ diff --git a/arch/arm/src/stm32/stm32_aes.h b/arch/arm/src/common/stm32/stm32_aes.h similarity index 80% rename from arch/arm/src/stm32/stm32_aes.h rename to arch/arm/src/common/stm32/stm32_aes.h index f0de4f59720..8e0a90c4424 100644 --- a/arch/arm/src/stm32/stm32_aes.h +++ b/arch/arm/src/common/stm32/stm32_aes.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_aes.h + * arch/arm/src/common/stm32/stm32_aes.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_AES_H -#define __ARCH_ARM_SRC_STM32_STM32_AES_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_AES_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_AES_H /**************************************************************************** * Included Files @@ -33,14 +33,14 @@ #include "chip.h" -/* Only the STM32L162 devices have AES, but we don't bother with exact macros - * for simplicity. - */ - -#ifdef CONFIG_STM32_STM32L15XX -# include "hardware/stm32l15xxx_aes.h" -#else -# error "Unknown chip for AES" +#if defined(CONFIG_STM32_HAVE_IP_AES_M0_V1) +# include "hardware/stm32_aes.h" +#elif defined(CONFIG_STM32_HAVE_IP_AES_M3M4_V1) +# ifdef CONFIG_STM32_STM32L15XX +# include "hardware/stm32l15xxx_aes.h" +# else +# error "Unknown chip for AES" +# endif #endif /**************************************************************************** @@ -55,4 +55,4 @@ * Inline Functions ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_STM32_AES_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_AES_H */ diff --git a/arch/arm/src/stm32/stm32_aes.c b/arch/arm/src/common/stm32/stm32_aes_m0_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_aes.c rename to arch/arm/src/common/stm32/stm32_aes_m0_v1.c index ae58ed82c17..4348d1c4f0b 100644 --- a/arch/arm/src/stm32/stm32_aes.c +++ b/arch/arm/src/common/stm32/stm32_aes_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_aes.c + * arch/arm/src/common/stm32/stm32_aes_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -36,7 +36,7 @@ #include #include #include -#include +#include #include #include "arm_internal.h" diff --git a/arch/arm/src/stm32f0l0g0/stm32_aes.c b/arch/arm/src/common/stm32/stm32_aes_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_aes.c rename to arch/arm/src/common/stm32/stm32_aes_m3m4_v1.c index 746047df3d7..96ff3b7cbf6 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_aes.c +++ b/arch/arm/src/common/stm32/stm32_aes_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_aes.c + * arch/arm/src/common/stm32/stm32_aes_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -71,7 +71,7 @@ static int stm32aes_setup_cr(int mode, int encrypt); ****************************************************************************/ static mutex_t g_stm32aes_lock = NXMUTEX_INITIALIZER; -static bool g_stm32aes_initdone; +static bool g_stm32aes_initdone = false; /**************************************************************************** * Public Data diff --git a/arch/arm/src/stm32/stm32_alarm.h b/arch/arm/src/common/stm32/stm32_alarm.h similarity index 94% rename from arch/arm/src/stm32/stm32_alarm.h rename to arch/arm/src/common/stm32/stm32_alarm.h index 2660dfd8a05..0d192e8e847 100644 --- a/arch/arm/src/stm32/stm32_alarm.h +++ b/arch/arm/src/common/stm32/stm32_alarm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_alarm.h + * arch/arm/src/common/stm32/stm32_alarm.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_ALARM_H -#define __ARCH_ARM_SRC_STM32_STM32_ALARM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_ALARM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_ALARM_H /**************************************************************************** * Included Files @@ -121,4 +121,4 @@ int stm32_rtc_rdalarm(FAR struct alm_rdalarm_s *alminfo); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_RTC_ALARM */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_ALARM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_ALARM_H */ diff --git a/arch/arm/src/stm32/stm32_allocateheap.c b/arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_allocateheap.c rename to arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c index 69d5a18bb7b..010ede1eeb3 100644 --- a/arch/arm/src/stm32/stm32_allocateheap.c +++ b/arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_allocateheap.c + * arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -342,7 +342,7 @@ * In addition, external FSMC SRAM may be available. */ -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) /* The STM32 F2 and the STM32 F401/F411/F412 have no CCM SRAM */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma.c b/arch/arm/src/common/stm32/stm32_bbsram.h similarity index 78% rename from arch/arm/src/stm32f0l0g0/stm32_dma.c rename to arch/arm/src/common/stm32/stm32_bbsram.h index 3e3b9af30ea..8c8658f963f 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_dma.c +++ b/arch/arm/src/common/stm32/stm32_bbsram.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_dma.c + * arch/arm/src/common/stm32/stm32_bbsram.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,20 +20,19 @@ * ****************************************************************************/ +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32BBSRAM_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32BBSRAM_H + /**************************************************************************** * Included Files ****************************************************************************/ #include -#include "chip.h" - -#if defined(CONFIG_STM32_HAVE_DMAMUX) -# include "stm32_dma_v1mux.c" +#if defined(CONFIG_STM32_HAVE_IP_BBSRAM_M3M4_V1) +# include "stm32_bbsram_m3m4_v1.h" #else -# include "stm32_dma_v1.c" +# error "Unsupported STM32 stm32_bbsram" #endif -/**************************************************************************** - * Private Functions - ****************************************************************************/ +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32BBSRAM_H */ diff --git a/arch/arm/src/stm32/stm32_bbsram.c b/arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_bbsram.c rename to arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.c index b595b377611..14c132dc8ea 100644 --- a/arch/arm/src/stm32/stm32_bbsram.c +++ b/arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_bbsram.c + * arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -46,7 +46,7 @@ #include #include -#include "stm32_bbsram.h" +#include "stm32_bbsram_m3m4_v1.h" #include "chip.h" #include "stm32_pwr.h" #include "stm32_rtc.h" diff --git a/arch/arm/src/stm32/stm32_bbsram.h b/arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.h similarity index 95% rename from arch/arm/src/stm32/stm32_bbsram.h rename to arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.h index bca2251088f..3f8abefa83e 100644 --- a/arch/arm/src/stm32/stm32_bbsram.h +++ b/arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_bbsram.h + * arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_BBSRAM_H -#define __ARCH_ARM_SRC_STM32_STM32_BBSRAM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_BBSRAM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_BBSRAM_H /**************************************************************************** * The purpose of this driver is to add battery backup file to the file @@ -45,7 +45,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_BBSRAM_M3M4_V1) # define STM32_BBSRAM_SIZE 4096 #else # error No backup SRAM on this STM32 @@ -149,4 +149,4 @@ int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length); } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_BBSRAM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_BBSRAM_H */ diff --git a/arch/arm/src/stm32/stm32_bkp.h b/arch/arm/src/common/stm32/stm32_bkp.h similarity index 90% rename from arch/arm/src/stm32/stm32_bkp.h rename to arch/arm/src/common/stm32/stm32_bkp.h index 1d2c3cc858d..ab84719310e 100644 --- a/arch/arm/src/stm32/stm32_bkp.h +++ b/arch/arm/src/common/stm32/stm32_bkp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_bkp.h + * arch/arm/src/common/stm32/stm32_bkp.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_BKP_H -#define __ARCH_ARM_SRC_STM32_STM32_BKP_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_BKP_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_BKP_H /**************************************************************************** * Included Files @@ -47,4 +47,4 @@ * Pre-processor Definitions ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_STM32_BKP_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_BKP_H */ diff --git a/arch/arm/src/stm32/stm32_can.h b/arch/arm/src/common/stm32/stm32_can.h similarity index 71% rename from arch/arm/src/stm32/stm32_can.h rename to arch/arm/src/common/stm32/stm32_can.h index e9f906a92e1..ef931423e57 100644 --- a/arch/arm/src/stm32/stm32_can.h +++ b/arch/arm/src/common/stm32/stm32_can.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_can.h + * arch/arm/src/common/stm32/stm32_can.h * * SPDX-License-Identifier: Apache-2.0 * @@ -23,16 +23,18 @@ #ifndef __ARCH_ARM_SRC_STM32_STM32_CAN_H #define __ARCH_ARM_SRC_STM32_STM32_CAN_H +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) + /**************************************************************************** * Included Files ****************************************************************************/ -#include +# include -#include "chip.h" -#include "hardware/stm32_can.h" +# include "chip.h" +# include "hardware/stm32_can.h" -#include +# include /**************************************************************************** * Pre-processor Definitions @@ -42,23 +44,23 @@ /* Up to 2 CAN interfaces are supported */ -#if STM32_NCAN < 2 -# undef CONFIG_STM32_CAN2 -#endif +# if STM32_NCAN < 2 +# undef CONFIG_STM32_CAN2 +# endif -#if STM32_NCAN < 1 -# undef CONFIG_STM32_CAN1 -#endif +# if STM32_NCAN < 1 +# undef CONFIG_STM32_CAN1 +# endif /* CAN BAUD */ -#if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_BAUD) -# error "CONFIG_STM32_CAN1_BAUD is not defined" -#endif +# if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_BAUD) +# error "CONFIG_STM32_CAN1_BAUD is not defined" +# endif -#if defined(CONFIG_STM32_CAN2) && !defined(CONFIG_STM32_CAN2_BAUD) -# error "CONFIG_STM32_CAN2_BAUD is not defined" -#endif +# if defined(CONFIG_STM32_CAN2) && !defined(CONFIG_STM32_CAN2_BAUD) +# error "CONFIG_STM32_CAN2_BAUD is not defined" +# endif /* User-defined TSEG1 and TSEG2 settings may be used. * @@ -67,46 +69,46 @@ * CAN_BIT_QUANTA = The number of CAN time quanta in on bit time */ -#ifndef CONFIG_STM32_CAN_TSEG1 -# define CONFIG_STM32_CAN_TSEG1 6 -#endif +# ifndef CONFIG_STM32_CAN_TSEG1 +# define CONFIG_STM32_CAN_TSEG1 6 +# endif -#if CONFIG_STM32_CAN_TSEG1 < 1 || CONFIG_STM32_CAN_TSEG1 > CAN_BTR_TSEG1_MAX -# error "CONFIG_STM32_CAN_TSEG1 is out of range" -#endif +# if CONFIG_STM32_CAN_TSEG1 < 1 || CONFIG_STM32_CAN_TSEG1 > CAN_BTR_TSEG1_MAX +# error "CONFIG_STM32_CAN_TSEG1 is out of range" +# endif -#ifndef CONFIG_STM32_CAN_TSEG2 -# define CONFIG_STM32_CAN_TSEG2 7 -#endif +# ifndef CONFIG_STM32_CAN_TSEG2 +# define CONFIG_STM32_CAN_TSEG2 7 +# endif -#if CONFIG_STM32_CAN_TSEG2 < 1 || CONFIG_STM32_CAN_TSEG2 > CAN_BTR_TSEG2_MAX -# error "CONFIG_STM32_CAN_TSEG2 is out of range" -#endif +# if CONFIG_STM32_CAN_TSEG2 < 1 || CONFIG_STM32_CAN_TSEG2 > CAN_BTR_TSEG2_MAX +# error "CONFIG_STM32_CAN_TSEG2 is out of range" +# endif /**************************************************************************** * Public Types ****************************************************************************/ -#ifndef __ASSEMBLY__ +# ifndef __ASSEMBLY__ /**************************************************************************** * Public Data ****************************************************************************/ -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" +# undef EXTERN +# if defined(__cplusplus) +# define EXTERN extern "C" extern "C" { -#else -#define EXTERN extern -#endif +# else +# define EXTERN extern +# endif /**************************************************************************** * Public Function Prototypes ****************************************************************************/ -#ifdef CONFIG_STM32_CAN_CHARDRIVER +# ifdef CONFIG_STM32_CAN_CHARDRIVER /**************************************************************************** * Name: stm32_caninitialize @@ -124,9 +126,9 @@ extern "C" struct can_dev_s; struct can_dev_s *stm32_caninitialize(int port); -#endif +# endif -#ifdef CONFIG_STM32_CAN_SOCKET +# ifdef CONFIG_STM32_CAN_SOCKET /**************************************************************************** * Name: stm32_cansockinitialize @@ -143,12 +145,14 @@ struct can_dev_s *stm32_caninitialize(int port); ****************************************************************************/ int stm32_cansockinitialize(int port); -#endif +# endif -#undef EXTERN -#if defined(__cplusplus) +# undef EXTERN +# if defined(__cplusplus) } +# endif + +# endif /* __ASSEMBLY__ */ #endif -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_STM32_STM32_CAN_H */ diff --git a/arch/arm/src/stm32/stm32_can.c b/arch/arm/src/common/stm32/stm32_can_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_can.c rename to arch/arm/src/common/stm32/stm32_can_m3m4_v1.c index d0e8373aa36..90959870c49 100644 --- a/arch/arm/src/stm32/stm32_can.c +++ b/arch/arm/src/common/stm32/stm32_can_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_can.c + * arch/arm/src/common/stm32/stm32_can_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_can_sock.c b/arch/arm/src/common/stm32/stm32_can_m3m4_v1_sock.c similarity index 99% rename from arch/arm/src/stm32/stm32_can_sock.c rename to arch/arm/src/common/stm32/stm32_can_m3m4_v1_sock.c index 433ec29e153..60561620cfa 100644 --- a/arch/arm/src/stm32/stm32_can_sock.c +++ b/arch/arm/src/common/stm32/stm32_can_m3m4_v1_sock.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_can_sock.c + * arch/arm/src/common/stm32/stm32_can_m3m4_v1_sock.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_capture.h b/arch/arm/src/common/stm32/stm32_capture.h similarity index 81% rename from arch/arm/src/stm32/stm32_capture.h rename to arch/arm/src/common/stm32/stm32_capture.h index 33f2a3157a1..ab80b5c4c1f 100644 --- a/arch/arm/src/stm32/stm32_capture.h +++ b/arch/arm/src/common/stm32/stm32_capture.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_capture.h + * arch/arm/src/common/stm32/stm32_capture.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_CAPTURE_H -#define __ARCH_ARM_SRC_STM32_STM32_CAPTURE_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_CAPTURE_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_CAPTURE_H /**************************************************************************** * Included Files @@ -29,6 +29,12 @@ #include +#include +#include + +#include +#include + #include "chip.h" #include #include "hardware/stm32_tim.h" @@ -64,48 +70,28 @@ extern "C" #define EXTERN extern #endif -/* Capture Device Structure */ - struct stm32_cap_dev_s { struct stm32_cap_ops_s *ops; }; -/* Capture input EDGE sources */ - typedef enum { - /* Mapped */ - STM32_CAP_MAPPED_MASK = (GTIM_CCMR1_CC1S_MASK), STM32_CAP_MAPPED_TI1 = (GTIM_CCMR_CCS_CCIN1), STM32_CAP_MAPPED_TI2 = (GTIM_CCMR_CCS_CCIN2), STM32_CAP_MAPPED_TI3 = (GTIM_CCMR_CCS_CCIN1), STM32_CAP_MAPPED_TI4 = (GTIM_CCMR_CCS_CCIN2), - -/* TODO STM32_CAP_MAPPED_TRC = (GTIM_CCMR_CCS_CCINTRC), */ - - /* Event prescaler */ - STM32_CAP_INPSC_MASK = (GTIM_CCMR1_IC1PSC_MASK), STM32_CAP_INPSC_NO = (0 << GTIM_CCMR1_IC1PSC_SHIFT), STM32_CAP_INPSC_2EVENTS = (1 << GTIM_CCMR1_IC1PSC_SHIFT), STM32_CAP_INPSC_4EVENTS = (2 << GTIM_CCMR1_IC1PSC_SHIFT), STM32_CAP_INPSC_8EVENTS = (3 << GTIM_CCMR1_IC1PSC_SHIFT), - - /* Event prescaler */ - STM32_CAP_FILTER_MASK = (GTIM_CCMR1_IC1F_MASK), STM32_CAP_FILTER_NO = (0 << GTIM_CCMR1_IC1F_SHIFT), - - /* Internal clock with N time to confirm event */ - STM32_CAP_FILTER_INT_N2 = (1 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_INT_N4 = (2 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_INT_N8 = (3 << GTIM_CCMR1_IC1F_SHIFT), - - /* DTS clock div by D with N time to confirm event */ - STM32_CAP_FILTER_DTS_D2_N6 = (4 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_DTS_D2_N8 = (5 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_DTS_D4_N6 = (6 << GTIM_CCMR1_IC1F_SHIFT), @@ -118,9 +104,6 @@ typedef enum STM32_CAP_FILTER_DTS_D32_N5 = (13 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_DTS_D32_N6 = (14 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_DTS_D32_N8 = (15 << GTIM_CCMR1_IC1F_SHIFT), - - /* EDGE */ - STM32_CAP_EDGE_MASK = (3 << 8), STM32_CAP_EDGE_DISABLED = (0 << 8), STM32_CAP_EDGE_RISING = (1 << 8), @@ -128,12 +111,8 @@ typedef enum STM32_CAP_EDGE_BOTH = (3 << 8), } stm32_cap_ch_cfg_t; -/* Slave mode control configure */ - typedef enum { - /* Slave mode selection */ - STM32_CAP_SMS_MASK = (7 << GTIM_SMCR_SMS_SHIFT), STM32_CAP_SMS_INT = (0 << GTIM_SMCR_SMS_SHIFT), STM32_CAP_SMS_ENC1 = (1 << GTIM_SMCR_SMS_SHIFT), @@ -143,9 +122,6 @@ typedef enum STM32_CAP_SMS_GAT = (5 << GTIM_SMCR_SMS_SHIFT), STM32_CAP_SMS_TRG = (6 << GTIM_SMCR_SMS_SHIFT), STM32_CAP_SMS_EXT = (7 << GTIM_SMCR_SMS_SHIFT), - - /* Trigger selection */ - STM32_CAP_TS_MASK = (7 << GTIM_SMCR_TS_SHIFT), STM32_CAP_TS_ITR0 = (0 << GTIM_SMCR_TS_SHIFT), STM32_CAP_TS_ITR1 = (1 << GTIM_SMCR_TS_SHIFT), @@ -155,25 +131,16 @@ typedef enum STM32_CAP_TS_TI1FP1 = (5 << GTIM_SMCR_TS_SHIFT), STM32_CAP_TS_TI2FP2 = (6 << GTIM_SMCR_TS_SHIFT), STM32_CAP_TS_ETRF = (7 << GTIM_SMCR_TS_SHIFT), - - /* Master/Slave mode setting */ - STM32_CAP_MSM_MASK = (1 << 7) } stm32_cap_smc_cfg_t; -/* Capture flags */ - typedef enum { - /* One of the following */ - STM32_CAP_FLAG_IRQ_COUNTER = (GTIM_SR_UIF), - STM32_CAP_FLAG_IRQ_CH_1 = (GTIM_SR_CC1IF), STM32_CAP_FLAG_IRQ_CH_2 = (GTIM_SR_CC2IF), STM32_CAP_FLAG_IRQ_CH_3 = (GTIM_SR_CC3IF), STM32_CAP_FLAG_IRQ_CH_4 = (GTIM_SR_CC4IF), - STM32_CAP_FLAG_OF_CH_1 = (GTIM_SR_CC1OF), STM32_CAP_FLAG_OF_CH_2 = (GTIM_SR_CC2OF), STM32_CAP_FLAG_OF_CH_3 = (GTIM_SR_CC3OF), @@ -184,8 +151,6 @@ typedef enum #define STM32_CAP_FLAG_OF_CH(ch) (GTIM_SR_CC1OF<<((ch)-1)) #define STM32_CAP_CHANNEL_COUNTER 0 -/* Capture Operations */ - struct stm32_cap_ops_s { int (*setsmc)(struct stm32_cap_dev_s *dev, stm32_cap_smc_cfg_t cfg); @@ -202,38 +167,9 @@ struct stm32_cap_ops_s uint32_t (*rstcounter)(struct stm32_cap_dev_s *dev); }; -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - struct stm32_cap_dev_s *stm32_cap_init(int timer); - -/* Power-down timer, mark it as unused */ - int stm32_cap_deinit(struct stm32_cap_dev_s *dev); - -/**************************************************************************** - * Name: stm32_cap_initialize - * - * Description: - * Initialize one timer for use with the upper_level capture driver. - * - * Input Parameters: - * timer - A number identifying the timer use. The number of valid timer - * IDs varies with the STM32 MCU and MCU family but is somewhere in - * the range of {1,..,5 8,...,14}. - * - * Returned Value: - * On success, a pointer to the STM32 lower half capture driver returned. - * NULL is returned on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_CAPTURE struct cap_lowerhalf_s *stm32_cap_initialize(int timer); -#endif #undef EXTERN #if defined(__cplusplus) @@ -241,4 +177,5 @@ struct cap_lowerhalf_s *stm32_cap_initialize(int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_CAPTURE_H */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_CAPTURE_H */ diff --git a/arch/arm/src/stm32/stm32_capture.c b/arch/arm/src/common/stm32/stm32_capture_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_capture.c rename to arch/arm/src/common/stm32/stm32_capture_m3m4_v1.c index 966f41a0a43..48fcfe57c73 100644 --- a/arch/arm/src/stm32/stm32_capture.c +++ b/arch/arm/src/common/stm32/stm32_capture_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_capture.c + * arch/arm/src/common/stm32/stm32_capture_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_capture_lowerhalf.c b/arch/arm/src/common/stm32/stm32_capture_m3m4_v1_lowerhalf.c similarity index 99% rename from arch/arm/src/stm32/stm32_capture_lowerhalf.c rename to arch/arm/src/common/stm32/stm32_capture_m3m4_v1_lowerhalf.c index 0246f5e28f9..ea4e0b174fb 100644 --- a/arch/arm/src/stm32/stm32_capture_lowerhalf.c +++ b/arch/arm/src/common/stm32/stm32_capture_m3m4_v1_lowerhalf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_capture_lowerhalf.c + * arch/arm/src/common/stm32/stm32_capture_m3m4_v1_lowerhalf.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_flash.c b/arch/arm/src/common/stm32/stm32_ccm.h similarity index 76% rename from arch/arm/src/stm32f0l0g0/stm32_flash.c rename to arch/arm/src/common/stm32/stm32_ccm.h index 010d5059c0c..432d3bf5492 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_flash.c +++ b/arch/arm/src/common/stm32/stm32_ccm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_flash.c + * arch/arm/src/common/stm32/stm32_ccm.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,18 +20,19 @@ * ****************************************************************************/ +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32CCM_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32CCM_H + /**************************************************************************** * Included Files ****************************************************************************/ #include -#if defined(CONFIG_STM32_STM32G0) || defined(CONFIG_STM32_STM32C0) -# include "stm32g0c0_flash.c" +#if defined(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1) +# include "stm32_ccm_m3m4_v1.h" #else -# error "Flash driver unsupported on selected chip." +# error "Unsupported STM32 stm32_ccm" #endif -/**************************************************************************** - * Private Functions - ****************************************************************************/ +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32CCM_H */ diff --git a/arch/arm/src/stm32/stm32_ccm.c b/arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.c similarity index 95% rename from arch/arm/src/stm32/stm32_ccm.c rename to arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.c index 9c87b61d4af..fb4507e1d08 100644 --- a/arch/arm/src/stm32/stm32_ccm.c +++ b/arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_ccm.c + * arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -26,7 +26,7 @@ #include -#include "stm32_ccm.h" +#include "stm32_ccm_m3m4_v1.h" #ifdef HAVE_CCM_HEAP diff --git a/arch/arm/src/stm32/stm32_ccm.h b/arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.h similarity index 93% rename from arch/arm/src/stm32/stm32_ccm.h rename to arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.h index f5a38d3d41b..705a58c0804 100644 --- a/arch/arm/src/stm32/stm32_ccm.h +++ b/arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_ccm.h + * arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_CCM_H -#define __ARCH_ARM_SRC_STM32_STM32_CCM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_CCM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_CCM_H /**************************************************************************** * Included Files @@ -46,7 +46,7 @@ #if defined(CONFIG_STM32_STM32F30XX) # define CCM_START 0x10000000 # define CCM_END 0x10002000 -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || \ +#elif defined(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1) || \ defined(CONFIG_STM32_STM32F33XX) # define CCM_START 0x10000000 # define CCM_END 0x10010000 @@ -122,4 +122,4 @@ EXTERN struct mm_heap_s *g_ccm_heap; #endif /* __ASSEMBLY__ */ #endif /* HAVE_CCM_HEAP */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_CCM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_CCM_H */ diff --git a/arch/arm/src/stm32/stm32_comp_v1.h b/arch/arm/src/common/stm32/stm32_comp.h similarity index 51% rename from arch/arm/src/stm32/stm32_comp_v1.h rename to arch/arm/src/common/stm32/stm32_comp.h index 5389e5ddca1..8178f55e6d4 100644 --- a/arch/arm/src/stm32/stm32_comp_v1.h +++ b/arch/arm/src/common/stm32/stm32_comp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_comp_v1.h + * arch/arm/src/common/stm32/stm32_comp.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,41 +20,55 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_COMP_V1_H -#define __ARCH_ARM_SRC_STM32_STM32_COMP_V1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_COMP_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_COMP_H /**************************************************************************** * Included Files ****************************************************************************/ -#ifdef CONFIG_STM32_COMP +#include + +#if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) + +#include "chip.h" + +#include "hardware/stm32_comp.h" /**************************************************************************** * Pre-processor definitions ****************************************************************************/ -#define COMP_BLANKING_DEFAULT COMP_BLANKING_DIS /* No blanking */ -#define COMP_POL_DEFAULT COMP_POL_NONINVERT /* Output is not inverted */ -#define COMP_INM_DEFAULT COMP_INMSEL_1P4VREF /* 1/4 of Vrefint as INM */ -#define COMP_OUTSEL_DEFAULT COMP_OUTSEL_NOSEL /* Output not selected */ -#define COMP_LOCK_DEFAULT COMP_LOCK_RW /* Do not lock CSR register */ +#ifdef CONFIG_STM32_COMP +# if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) +# define COMP_BLANKING_DEFAULT COMP_BLANKING_DIS +# define COMP_POL_DEFAULT COMP_POL_NONINVERT +# define COMP_INM_DEFAULT COMP_INMSEL_1P4VREF +# define COMP_OUTSEL_DEFAULT COMP_OUTSEL_NOSEL +# define COMP_LOCK_DEFAULT COMP_LOCK_RW -#ifndef CONFIG_STM32_STM32F33XX -#define COMP_MODE_DEFAULT -#define COMP_HYST_DEFAULT -#define COMP_WINMODE_DEFAULT +# ifndef CONFIG_STM32_STM32F33XX +# define COMP_MODE_DEFAULT +# define COMP_HYST_DEFAULT +# define COMP_WINMODE_DEFAULT +# endif +# endif #endif /**************************************************************************** * Public Types ****************************************************************************/ +#ifdef CONFIG_STM32_COMP +# if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) + /* Blanking source */ enum stm32_comp_blanking_e { COMP_BLANKING_DIS, -#if defined(CONFIG_STM32_STM32F33XX) +# if defined(CONFIG_STM32_STM32F33XX) COMP_BLANKING_T1OC5, COMP_BLANKING_T3OC4, COMP_BLANKING_T2OC3, @@ -62,7 +76,7 @@ enum stm32_comp_blanking_e COMP_BLANKING_T15OC1, COMP_BLANKING_T2OC4, COMP_BLANKING_T15OC2, -#endif +# endif }; /* Output polarisation */ @@ -91,7 +105,7 @@ enum stm32_comp_inm_e enum stm32_comp_outsel_e { COMP_OUTSEL_NOSEL, -#if defined(CONFIG_STM32_STM32F33XX) +# if defined(CONFIG_STM32_STM32F33XX) COMP_OUTSEL_BRKACTH, COMP_OUTSEL_BRK2, COMP_OUTSEL_T1OCC, /* COMP2 only */ @@ -106,7 +120,7 @@ enum stm32_comp_outsel_e COMP_OUTSEL_T15OCC, /* COMP4 only */ COMP_OUTSEL_T16CAP1, /* COMP6 only */ COMP_OUTSEL_T3OCC, /* COMP2 and COMP4 only */ -#endif +# endif }; /* CSR register lock state */ @@ -117,9 +131,9 @@ enum stm32_comp_lock_e COMP_LOCK_RO }; -#ifndef CONFIG_STM32_STM32F33XX +# ifndef CONFIG_STM32_STM32F33XX -/* Hysteresis */ +/* Hysteresis */ enum stm32_comp_hyst_e { @@ -147,7 +161,109 @@ enum stm32_comp_winmode_e COMP_WINMODE_EN }; +# endif +# elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) + +/* Inverting input. See Table 196 in RM0440 */ + +enum stm32_comp_inm_e +{ + COMP_INM_1_4_VREF, + COMP_INM_1_2_VREF, + COMP_INM_3_4_VREF, + COMP_INM_VREF, + COMP_INM_DAC_1, + COMP_INM_DAC_2, + COMP_INM_PIN_1, + COMP_INM_PIN_2, +}; + +/* Non-inverting input. See Table 195 in RM0440 */ + +enum stm32_comp_inp_e +{ + COMP_INP_PIN_1, + COMP_INP_PIN_2, +}; + +/* Output polarity */ + +enum stm32_comp_pol_e +{ + COMP_POL_NONINVERT, + COMP_POL_INVERTED +}; + +/* Hysteresis */ + +enum stm32_comp_hyst_e +{ + COMP_HYST_DIS, + COMP_HYST_10MV, + COMP_HYST_20MV, + COMP_HYST_30MV, + COMP_HYST_40MV, + COMP_HYST_50MV, + COMP_HYST_60MV, + COMP_HYST_70MV, +}; + +/* Blanking source */ + +enum stm32_comp_blanking_e +{ + COMP_BLANKING_DIS, + COMP_BLANKING_TIMX_OCY_1, + COMP_BLANKING_TIMX_OCY_2, + COMP_BLANKING_TIMX_OCY_3, + COMP_BLANKING_TIMX_OCY_4, + COMP_BLANKING_TIMX_OCY_5, + COMP_BLANKING_TIMX_OCY_6, + COMP_BLANKING_TIMX_OCY_7, +}; + +# endif +#endif /* CONFIG_STM32_COMP */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern #endif -#endif /* CONFIG_STM23_COMP */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_V1_H */ +/**************************************************************************** + * Name: stm32_compinitialize + * + * Description: + * Initialize the COMP. + * + * Input Parameters: + * intf - The COMP interface number. + * + * Returned Value: + * Valid COMP device structure reference on success; a NULL on failure. + * + * Assumptions: + * 1. Clock to the COMP block has enabled, + * 2. Board-specific logic has already configured + * + ****************************************************************************/ + +struct comp_dev_s *stm32_compinitialize(int intf); + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_STM32_HAVE_IP_COMP_M3M4_V1 || CONFIG_STM32_HAVE_IP_COMP_M3M4_V2 */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_COMP_H */ diff --git a/arch/arm/src/stm32/stm32_comp_v1.c b/arch/arm/src/common/stm32/stm32_comp_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_comp_v1.c rename to arch/arm/src/common/stm32/stm32_comp_m3m4_v1.c index 17e5ccefab2..5af2ab52177 100644 --- a/arch/arm/src/stm32/stm32_comp_v1.c +++ b/arch/arm/src/common/stm32/stm32_comp_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_comp_v1.c + * arch/arm/src/common/stm32/stm32_comp_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -24,6 +24,23 @@ * Included Files ****************************************************************************/ +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_comp.h" +#include "stm32_gpio.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_comp_v2.c b/arch/arm/src/common/stm32/stm32_comp_m3m4_v2.c similarity index 98% rename from arch/arm/src/stm32/stm32_comp_v2.c rename to arch/arm/src/common/stm32/stm32_comp_m3m4_v2.c index d6fbae9c202..8939e4a6ce9 100644 --- a/arch/arm/src/stm32/stm32_comp_v2.c +++ b/arch/arm/src/common/stm32/stm32_comp_m3m4_v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_comp_v2.c + * arch/arm/src/common/stm32/stm32_comp_m3m4_v2.c * * SPDX-License-Identifier: Apache-2.0 * @@ -24,6 +24,23 @@ * Included Files ****************************************************************************/ +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_comp.h" +#include "stm32_gpio.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial.h b/arch/arm/src/common/stm32/stm32_cordic.h similarity index 75% rename from arch/arm/src/stm32f0l0g0/stm32_serial.h rename to arch/arm/src/common/stm32/stm32_cordic.h index 725db01e521..aa536a50f26 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial.h +++ b/arch/arm/src/common/stm32/stm32_cordic.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_serial.h + * arch/arm/src/common/stm32/stm32_cordic.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_SERIAL_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_SERIAL_H +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32CORDIC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32CORDIC_H /**************************************************************************** * Included Files @@ -29,8 +29,10 @@ #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ +#if defined(CONFIG_STM32_HAVE_IP_CORDIC_M3M4_V1) +# include "stm32_cordic_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_cordic" +#endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_SERIAL_H */ +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32CORDIC_H */ diff --git a/arch/arm/src/stm32/stm32_cordic.c b/arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_cordic.c rename to arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.c index a9ab089a7fb..e77afc841a1 100644 --- a/arch/arm/src/stm32/stm32_cordic.c +++ b/arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_cordic.c + * arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -39,7 +39,7 @@ #include "hardware/stm32g4xxxx_cordic.h" -#include "stm32_cordic.h" +#include "stm32_cordic_m3m4_v1.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32/stm32_cordic.h b/arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.h similarity index 90% rename from arch/arm/src/stm32/stm32_cordic.h rename to arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.h index be6da8d85ef..84328ab75c1 100644 --- a/arch/arm/src/stm32/stm32_cordic.h +++ b/arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_cordic.h + * arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_CORDIC_H -#define __ARCH_ARM_SRC_STM32_STM32_CORDIC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_CORDIC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_CORDIC_H /**************************************************************************** * Included Files @@ -54,4 +54,4 @@ struct cordic_lowerhalf_s *stm32_cordicinitialize(void); -#endif /* __ARCH_ARM_SRC_STM32_STM32_CORDIC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_CORDIC_H */ diff --git a/arch/arm/src/stm32/stm32_crypto.c b/arch/arm/src/common/stm32/stm32_crypto_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_crypto.c rename to arch/arm/src/common/stm32/stm32_crypto_m3m4_v1.c index cf4646e04ee..8a88cff4803 100644 --- a/arch/arm/src/stm32/stm32_crypto.c +++ b/arch/arm/src/common/stm32/stm32_crypto_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_crypto.c + * arch/arm/src/common/stm32/stm32_crypto_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_dac.h b/arch/arm/src/common/stm32/stm32_dac.h new file mode 100644 index 00000000000..192a666ec93 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dac.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dac.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32DAC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32DAC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2) +# include "stm32_dac_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_dac" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32DAC_H */ diff --git a/arch/arm/src/stm32/stm32_dac.c b/arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_dac.c rename to arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c index 873e3af5431..c9cb731658f 100644 --- a/arch/arm/src/stm32/stm32_dac.c +++ b/arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dac.c + * arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -41,7 +41,7 @@ #include "arm_internal.h" #include "chip.h" #include "stm32.h" -#include "stm32_dac.h" +#include "stm32_dac_m3m4_v1.h" #include "stm32_rcc.h" #include "stm32_dma.h" #include "stm32_syscfg.h" @@ -145,7 +145,7 @@ # undef CONFIG_STM32_DAC1CH2_DMA # undef CONFIG_STM32_DAC2CH1_DMA # endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) # ifndef CONFIG_STM32_DMA1 # warning "STM32 F4 DAC DMA support requires CONFIG_STM32_DMA1" # undef CONFIG_STM32_DAC1CH1_DMA @@ -235,7 +235,7 @@ # if defined(CONFIG_STM32_DAC2CH1) && !defined(CONFIG_STM32_DAC2CH1_DMA_EXTERNAL) # define DAC2CH1_DMA_CHAN DMACHAN_DAC2_CH1 # endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) # define HAVE_DMA 1 # define DAC_DMA 1 # if defined(CONFIG_STM32_DAC1CH1) && !defined(CONFIG_STM32_DAC1CH1_DMA_EXTERNAL) @@ -524,9 +524,12 @@ #warning "Missing Logic" -/* DMA stream/channel configuration */ +/* DMA stream/channel configuration. The register layout depends on the DMA + * IP version, not the DAC IP version: stream DMA (IPv2) uses the SCR + * register fields, while channel DMA (IPv1) uses the CCR register fields. + */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define DAC_DMA_CONTROL_WORD (DMA_SCR_MSIZE_16BITS | \ DMA_SCR_PSIZE_16BITS | \ DMA_SCR_MINC | \ @@ -603,7 +606,7 @@ static void tim_modifyreg(struct stm32_chan_s *chan, int offset, /* Interrupt handler */ -#if 0 /* defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) */ +#if 0 /* defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) */ static int dac_interrupt(int irq, void *context, void *arg); #endif @@ -971,7 +974,7 @@ static void tim_modifyreg(struct stm32_chan_s *chan, int offset, * ****************************************************************************/ -#if 0 /* defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) */ +#if 0 /* defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) */ static int dac_interrupt(int irq, void *context, void *arg) { #warning "Missing logic" diff --git a/arch/arm/src/stm32/stm32_dac.h b/arch/arm/src/common/stm32/stm32_dac_m3m4_v1.h similarity index 90% rename from arch/arm/src/stm32/stm32_dac.h rename to arch/arm/src/common/stm32/stm32_dac_m3m4_v1.h index b031fa463d8..9683dab6d88 100644 --- a/arch/arm/src/stm32/stm32_dac.h +++ b/arch/arm/src/common/stm32/stm32_dac_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dac.h + * arch/arm/src/common/stm32/stm32_dac_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_DAC_H -#define __ARCH_ARM_SRC_STM32_STM32_DAC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DAC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DAC_H /**************************************************************************** * Included Files @@ -29,6 +29,9 @@ #include +#if defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2) + #include "chip.h" #include "hardware/stm32_dac.h" @@ -136,4 +139,6 @@ struct dac_dev_s *stm32_dacinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_DAC_H */ +#endif /* CONFIG_STM32_HAVE_IP_DAC_M3M4_V1 || CONFIG_STM32_HAVE_IP_DAC_M3M4_V2 */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DAC_H */ diff --git a/arch/arm/src/stm32/stm32_dbgmcu.h b/arch/arm/src/common/stm32/stm32_dbgmcu.h similarity index 82% rename from arch/arm/src/stm32/stm32_dbgmcu.h rename to arch/arm/src/common/stm32/stm32_dbgmcu.h index 1695141ff16..4b1b2f81ee3 100644 --- a/arch/arm/src/stm32/stm32_dbgmcu.h +++ b/arch/arm/src/common/stm32/stm32_dbgmcu.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dbgmcu.h + * arch/arm/src/common/stm32/stm32_dbgmcu.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_DBGMCU_H -#define __ARCH_ARM_SRC_STM32_STM32_DBGMCU_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DBGMCU_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DBGMCU_H /**************************************************************************** * Included Files @@ -29,6 +29,10 @@ #include +#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3) + #include "chip.h" #include "hardware/stm32_dbgmcu.h" @@ -48,4 +52,6 @@ * Public Function Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_STM32_DBGMCU_H */ +#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1 || ... */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DBGMCU_H */ diff --git a/arch/arm/src/common/stm32/stm32_dfumode.h b/arch/arm/src/common/stm32/stm32_dfumode.h new file mode 100644 index 00000000000..593c06fad90 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dfumode.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dfumode.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32DFUMODE_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32DFUMODE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1) +# include "stm32_dfumode_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_dfumode" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32DFUMODE_H */ diff --git a/arch/arm/src/stm32/stm32_dfumode.c b/arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.c similarity index 93% rename from arch/arm/src/stm32/stm32_dfumode.c rename to arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.c index 45b8b0e9cd4..40bb4b28ad0 100644 --- a/arch/arm/src/stm32/stm32_dfumode.c +++ b/arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dfumode.c + * arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -31,7 +31,7 @@ #include -#include "stm32_dfumode.h" +#include "stm32_dfumode_m3m4_v1.h" /**************************************************************************** * Public Functions @@ -56,7 +56,7 @@ * ****************************************************************************/ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1) void stm32_dfumode(void) { #ifdef CONFIG_DEBUG_WARN @@ -77,4 +77,4 @@ void stm32_dfumode(void) __builtin_unreachable(); /* Tell compiler we will not return */ } -#endif /* CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F4XXX */ +#endif /* CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1 */ diff --git a/arch/arm/src/stm32/stm32_dfumode.h b/arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.h similarity index 87% rename from arch/arm/src/stm32/stm32_dfumode.h rename to arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.h index 332ef05c097..5a3c639fc12 100644 --- a/arch/arm/src/stm32/stm32_dfumode.h +++ b/arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dfumode.h + * arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_DFUMODE_H -#define __ARCH_ARM_SRC_STM32_STM32_DFUMODE_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DFUMODE_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DFUMODE_H /**************************************************************************** * Included Files @@ -44,8 +44,8 @@ * ****************************************************************************/ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1) void stm32_dfumode(void) noreturn_function; #endif -#endif /* __ARCH_ARM_SRC_STM32_STM32_DFUMODE_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DFUMODE_H */ diff --git a/arch/arm/src/common/stm32/stm32_dma.h b/arch/arm/src/common/stm32/stm32_dma.h new file mode 100644 index 00000000000..16124d4a4b7 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dma.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dma.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_DMA_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# include "stm32_dma_channel_stream.h" +#else +# error "Unsupported STM32 DMA" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_H */ diff --git a/arch/arm/src/common/stm32/stm32_dma2d.h b/arch/arm/src/common/stm32/stm32_dma2d.h new file mode 100644 index 00000000000..548dd220034 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dma2d.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dma2d.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32DMA2D_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32DMA2D_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_COMMON_LEGACY) +# include "stm32_dma2d_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_dma2d" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32DMA2D_H */ diff --git a/arch/arm/src/stm32/stm32_dma2d.c b/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_dma2d.c rename to arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c index 83b98668454..e129ee671ce 100644 --- a/arch/arm/src/stm32/stm32_dma2d.c +++ b/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dma2d.c + * arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -48,8 +48,8 @@ #include "stm32.h" #include "hardware/stm32_ltdc.h" #include "hardware/stm32_dma2d.h" -#include "stm32_ccm.h" -#include "stm32_dma2d.h" +#include "stm32_dma2d_m3m4_v1.h" +#include "stm32_dma2d_m3m4_v1.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32/stm32_dma2d.h b/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.h similarity index 96% rename from arch/arm/src/stm32/stm32_dma2d.h rename to arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.h index f8627cfe105..5bc43e6da99 100644 --- a/arch/arm/src/stm32/stm32_dma2d.h +++ b/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dma2d.h + * arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_DMA2D_H -#define __ARCH_ARM_SRC_STM32_STM32_DMA2D_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA2D_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA2D_H /**************************************************************************** * Included Files @@ -189,4 +189,4 @@ int stm32_dma2dinitialize(void); void stm32_dma2duninitialize(void); #endif /* CONFIG_FB_OVERLAY */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_DMA2D_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA2D_H */ diff --git a/arch/arm/src/stm32/stm32_dma.h b/arch/arm/src/common/stm32/stm32_dma_channel_stream.h similarity index 97% rename from arch/arm/src/stm32/stm32_dma.h rename to arch/arm/src/common/stm32/stm32_dma_channel_stream.h index f7eb641ef86..aec408a5527 100644 --- a/arch/arm/src/stm32/stm32_dma.h +++ b/arch/arm/src/common/stm32/stm32_dma_channel_stream.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dma.h + * arch/arm/src/common/stm32/stm32_dma_channel_stream.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_DMA_H -#define __ARCH_ARM_SRC_STM32_STM32_DMA_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_CHANNEL_STREAM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_CHANNEL_STREAM_H /**************************************************************************** * Included Files @@ -349,4 +349,4 @@ uint8_t stm32_dma_intget(unsigned int controller, uint8_t stream); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_DMA_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_CHANNEL_STREAM_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_dma_v1.c rename to arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch.c index 3117fad02ec..06ae4eaf7ea 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c +++ b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_dma_v1.c + * arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c rename to arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c index e622ab417d5..6fb57a23624 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c +++ b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c + * arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c * * SPDX-License-Identifier: Apache-2.0 * @@ -37,7 +37,7 @@ #include #include -#include +#include #include "arm_internal.h" #include "sched/sched.h" diff --git a/arch/arm/src/stm32/stm32_dma_v1.c b/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c similarity index 99% rename from arch/arm/src/stm32/stm32_dma_v1.c rename to arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c index ebd0f3d0af5..2d18d541a1a 100644 --- a/arch/arm/src/stm32/stm32_dma_v1.c +++ b/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dma_v1.c + * arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c * * SPDX-License-Identifier: Apache-2.0 * @@ -55,14 +55,14 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) # define DMA1_NCHANNELS 8 #else # define DMA1_NCHANNELS 7 #endif #if STM32_NDMA > 1 -# if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +# if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define DMA2_NCHANNELS 8 # else # define DMA2_NCHANNELS 5 diff --git a/arch/arm/src/stm32/stm32_dma_v1mux.c b/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch_dmamux.c similarity index 99% rename from arch/arm/src/stm32/stm32_dma_v1mux.c rename to arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch_dmamux.c index d518dcf801c..dd8892f0f65 100644 --- a/arch/arm/src/stm32/stm32_dma_v1mux.c +++ b/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch_dmamux.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dma_v1mux.c + * arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch_dmamux.c * * SPDX-License-Identifier: Apache-2.0 * @@ -35,7 +35,7 @@ #include #include -#include +#include #include "arm_internal.h" #include "sched/sched.h" diff --git a/arch/arm/src/stm32/stm32_dma_v2.c b/arch/arm/src/common/stm32/stm32_dma_m3m4_v2_stream.c similarity index 99% rename from arch/arm/src/stm32/stm32_dma_v2.c rename to arch/arm/src/common/stm32/stm32_dma_m3m4_v2_stream.c index ed3784d5388..0fadcf45a61 100644 --- a/arch/arm/src/stm32/stm32_dma_v2.c +++ b/arch/arm/src/common/stm32/stm32_dma_m3m4_v2_stream.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dma_v2.c + * arch/arm/src/common/stm32/stm32_dma_m3m4_v2_stream.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_dumpgpio.c b/arch/arm/src/common/stm32/stm32_dumpgpio_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_dumpgpio.c rename to arch/arm/src/common/stm32/stm32_dumpgpio_m3m4_v1.c index 1f21684650b..429e3e70a16 100644 --- a/arch/arm/src/stm32/stm32_dumpgpio.c +++ b/arch/arm/src/common/stm32/stm32_dumpgpio_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dumpgpio.c + * arch/arm/src/common/stm32/stm32_dumpgpio_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -191,7 +191,7 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) getreg32(base + STM32_GPIO_AFRL_OFFSET), getreg32(base + STM32_GPIO_BRR_OFFSET)); -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V1) DEBUGASSERT(port < STM32_NGPIO_PORTS); _info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", diff --git a/arch/arm/src/common/stm32/stm32_eth.h b/arch/arm/src/common/stm32/stm32_eth.h new file mode 100644 index 00000000000..6e772732396 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_eth.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_eth.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32ETH_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32ETH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) +# include "stm32_eth_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_eth" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32ETH_H */ diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_eth.c rename to arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c index 3f1fdf514a3..3fc669d3ff7 100644 --- a/arch/arm/src/stm32/stm32_eth.c +++ b/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_eth.c + * arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -57,9 +57,11 @@ #include "arm_internal.h" #include "chip.h" #include "stm32_gpio.h" +#include "stm32_eth_m3m4_v1.h" #include "stm32_rcc.h" #include "stm32_syscfg.h" -#include "stm32_eth.h" +#include "stm32_gpio.h" +#include "stm32_eth_m3m4_v1.h" #include @@ -113,7 +115,7 @@ #endif #ifdef CONFIG_STM32_MII -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) # if !defined(CONFIG_STM32_MII_MCO1) && !defined(CONFIG_STM32_MII_MCO2) && !defined(CONFIG_STM32_MII_EXTCLK) # warning "Neither CONFIG_STM32_MII_MCO1, CONFIG_STM32_MII_MCO2, nor CONFIG_STM32_MII_EXTCLK defined" # endif @@ -128,7 +130,7 @@ #endif #ifdef CONFIG_STM32_RMII -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) # if !defined(CONFIG_STM32_RMII_MCO1) && !defined(CONFIG_STM32_RMII_MCO2) && !defined(CONFIG_STM32_RMII_EXTCLK) # warning "Neither CONFIG_STM32_RMII_MCO1, CONFIG_STM32_RMII_MCO2, nor CONFIG_STM32_RMII_EXTCLK defined" # endif @@ -322,7 +324,7 @@ * ETH_MACCR_CSTF Bits 25: CRC stripping for Type frames (F2/F4 only) */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) #define MACCR_CLEAR_BITS \ (ETH_MACCR_RE | ETH_MACCR_TE | ETH_MACCR_DC | ETH_MACCR_BL_MASK | \ ETH_MACCR_APCS | ETH_MACCR_RD | ETH_MACCR_IPCO | ETH_MACCR_DM | \ @@ -518,7 +520,7 @@ * ETH_DMABMR_MB Bit 26: Mixed burst (F2/F4 only) */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) #define DMABMR_CLEAR_MASK \ (ETH_DMABMR_SR | ETH_DMABMR_DA | ETH_DMABMR_DSL_MASK | ETH_DMABMR_EDFE | \ ETH_DMABMR_PBL_MASK | ETH_DMABMR_RTPR_MASK | ETH_DMABMR_FB | ETH_DMABMR_RDP_MASK | \ diff --git a/arch/arm/src/stm32/stm32_eth.h b/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.h similarity index 94% rename from arch/arm/src/stm32/stm32_eth.h rename to arch/arm/src/common/stm32/stm32_eth_m3m4_v1.h index 68515b80006..e2cfbdefe70 100644 --- a/arch/arm/src/stm32/stm32_eth.h +++ b/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_eth.h + * arch/arm/src/common/stm32/stm32_eth_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_ETH_H -#define __ARCH_ARM_SRC_STM32_STM32_ETH_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_ETH_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_ETH_H /**************************************************************************** * Included Files @@ -106,4 +106,4 @@ int stm32_phy_boardinitialize(int intf); #endif /* __ASSEMBLY__ */ #endif /* STM32_NETHERNET > 0 */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_ETH_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_ETH_H */ diff --git a/arch/arm/src/stm32/stm32_exti.h b/arch/arm/src/common/stm32/stm32_exti.h similarity index 94% rename from arch/arm/src/stm32/stm32_exti.h rename to arch/arm/src/common/stm32/stm32_exti.h index ae9ac9dba4c..8e301cf9997 100644 --- a/arch/arm/src/stm32/stm32_exti.h +++ b/arch/arm/src/common/stm32/stm32_exti.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_exti.h + * arch/arm/src/common/stm32/stm32_exti.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_EXTI_H -#define __ARCH_ARM_SRC_STM32_STM32_EXTI_H +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_EXTI_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_EXTI_H /**************************************************************************** * Included Files @@ -31,6 +31,9 @@ #include +#include +#include + #include "chip.h" #include "hardware/stm32_exti.h" @@ -127,4 +130,5 @@ int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_EXTI_H */ + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32/stm32_exti_alarm.c b/arch/arm/src/common/stm32/stm32_exti_alarm_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_exti_alarm.c rename to arch/arm/src/common/stm32/stm32_exti_alarm_m3m4_v1.c index e908fbae17f..e7b7d07cf81 100644 --- a/arch/arm/src/stm32/stm32_exti_alarm.c +++ b/arch/arm/src/common/stm32/stm32_exti_alarm_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_exti_alarm.c + * arch/arm/src/common/stm32/stm32_exti_alarm_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c b/arch/arm/src/common/stm32/stm32_exti_gpio_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c rename to arch/arm/src/common/stm32/stm32_exti_gpio_m0_v1.c index 5e8beb51a12..00b9158085c 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c +++ b/arch/arm/src/common/stm32/stm32_exti_gpio_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c + * arch/arm/src/common/stm32/stm32_exti_gpio_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_exti_gpio.c b/arch/arm/src/common/stm32/stm32_exti_gpio_m3m4_v1v2.c similarity index 99% rename from arch/arm/src/stm32/stm32_exti_gpio.c rename to arch/arm/src/common/stm32/stm32_exti_gpio_m3m4_v1v2.c index abe6146c0be..db62fac13f6 100644 --- a/arch/arm/src/stm32/stm32_exti_gpio.c +++ b/arch/arm/src/common/stm32/stm32_exti_gpio_m3m4_v1v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_exti_gpio.c + * arch/arm/src/common/stm32/stm32_exti_gpio_m3m4_v1v2.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_exti_pwr.h b/arch/arm/src/common/stm32/stm32_exti_pwr.h new file mode 100644 index 00000000000..f99225e5850 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_exti_pwr.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_exti_pwr.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32EXTIPWR_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32EXTIPWR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_COMMON_LEGACY) +# include "stm32_exti_pwr_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_exti_pwr" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32EXTIPWR_H */ diff --git a/arch/arm/src/stm32/stm32_exti_pwr.c b/arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.c similarity index 96% rename from arch/arm/src/stm32/stm32_exti_pwr.c rename to arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.c index 97b0060ac8c..0b83b171c19 100644 --- a/arch/arm/src/stm32/stm32_exti_pwr.c +++ b/arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_exti_pwr.c + * arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -37,8 +37,10 @@ #include "arm_internal.h" #include "chip.h" #include "stm32_gpio.h" +#include "stm32_exti_pwr_m3m4_v1.h" #include "stm32_exti.h" -#include "stm32_exti_pwr.h" +#include "stm32_gpio.h" +#include "stm32_exti_pwr_m3m4_v1.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32/stm32_exti_pwr.h b/arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.h similarity index 90% rename from arch/arm/src/stm32/stm32_exti_pwr.h rename to arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.h index 9eb22090c60..41058ed24aa 100644 --- a/arch/arm/src/stm32/stm32_exti_pwr.h +++ b/arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_exti_pwr.h + * arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef STM32_EXTI_PWR_H_ -#define STM32_EXTI_PWR_H_ +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_EXTI_PWR_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_EXTI_PWR_H /**************************************************************************** * Included Files @@ -55,4 +55,4 @@ int stm32_exti_pvd(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); -#endif /* STM32_EXTI_PWR_H_ */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_EXTI_PWR_H */ diff --git a/arch/arm/src/stm32/stm32_exti_wakeup.c b/arch/arm/src/common/stm32/stm32_exti_wakeup_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_exti_wakeup.c rename to arch/arm/src/common/stm32/stm32_exti_wakeup_m3m4_v1.c index dce70638d43..f3baba30545 100644 --- a/arch/arm/src/stm32/stm32_exti_wakeup.c +++ b/arch/arm/src/common/stm32/stm32_exti_wakeup_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_exti_wakeup.c + * arch/arm/src/common/stm32/stm32_exti_wakeup_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_fdcan.h b/arch/arm/src/common/stm32/stm32_fdcan.h new file mode 100644 index 00000000000..8a2dc52c68a --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_fdcan.h @@ -0,0 +1,80 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_fdcan.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FDCAN_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FDCAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/stm32_fdcan.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Port numbers for use with stm32_fdcan_initialize() */ + +#define FDCAN1 1 + +#if defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1) +# define FDCAN2 2 +# define FDCAN3 3 +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +# define EXTERN extern "C" +extern "C" +{ +#else +# define EXTERN extern +#endif + +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER +struct can_dev_s *stm32_fdcaninitialize(int port); +#endif + +#ifdef CONFIG_STM32_FDCAN_SOCKET +int stm32_fdcansockinitialize(int port); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FDCAN_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_fdcan.c b/arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_fdcan.c rename to arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c index 02d2c0f773d..c9695564c93 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_fdcan.c +++ b/arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_fdcan.c + * arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c b/arch/arm/src/common/stm32/stm32_fdcan_m0_v1_sock.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c rename to arch/arm/src/common/stm32/stm32_fdcan_m0_v1_sock.c index f17be5729df..d118271cf97 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c +++ b/arch/arm/src/common/stm32/stm32_fdcan_m0_v1_sock.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c + * arch/arm/src/common/stm32/stm32_fdcan_m0_v1_sock.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_fdcan.c b/arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_fdcan.c rename to arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1.c index 519b77626e9..4e23a563b1c 100644 --- a/arch/arm/src/stm32/stm32_fdcan.c +++ b/arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_fdcan.c + * arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_fdcan_sock.c b/arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1_sock.c similarity index 99% rename from arch/arm/src/stm32/stm32_fdcan_sock.c rename to arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1_sock.c index b4f37e29c65..55d16f42349 100644 --- a/arch/arm/src/stm32/stm32_fdcan_sock.c +++ b/arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1_sock.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_fdcan_sock.c + * arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1_sock.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_flash.h b/arch/arm/src/common/stm32/stm32_flash.h similarity index 70% rename from arch/arm/src/stm32f0l0g0/stm32_flash.h rename to arch/arm/src/common/stm32/stm32_flash.h index 1c670fa862c..9050b255d6b 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_flash.h +++ b/arch/arm/src/common/stm32/stm32_flash.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_flash.h + * arch/arm/src/common/stm32/stm32_flash.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,48 +20,47 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_FLASH_H +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FLASH_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FLASH_H /**************************************************************************** * Included Files ****************************************************************************/ #include +#include +#include #include #include "chip.h" #include "hardware/stm32_flash.h" /**************************************************************************** - * Included Files + * Public Function Prototypes ****************************************************************************/ #ifndef __ASSEMBLY__ -#undef EXTERN -#if defined(__cplusplus) -# define EXTERN extern "C" -extern "C" -{ -#else -# define EXTERN extern -#endif +#if defined(CONFIG_STM32_HAVE_IP_FLASH_M0_V1) void stm32_flash_getopt(uint32_t *opt); - int stm32_flash_optmodify(uint32_t clear, uint32_t set); - void stm32_flash_lock(void); - void stm32_flash_unlock(void); -#undef EXTERN -#if defined(__cplusplus) -} +#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_V1) + +int stm32_flash_lock(void); +int stm32_flash_unlock(void); +uint32_t stm32_flash_users_optbytes(uint32_t clrbits, uint32_t setbits); +size_t stm32_eeprom_size(void); +size_t stm32_eeprom_getaddress(void); +ssize_t stm32_eeprom_write(size_t addr, const void *buf, size_t buflen); +ssize_t stm32_eeprom_erase(size_t addr, size_t eraselen); + #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_FLASH_H */ \ No newline at end of file +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c b/arch/arm/src/common/stm32/stm32_flash_m0_g0c0.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c rename to arch/arm/src/common/stm32/stm32_flash_m0_g0c0.c index 1acb1b4a597..ec3a06037fb 100644 --- a/arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c +++ b/arch/arm/src/common/stm32/stm32_flash_m0_g0c0.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c + * arch/arm/src/common/stm32/stm32_flash_m0_g0c0.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32f10xxf30xx_flash.c b/arch/arm/src/common/stm32/stm32_flash_m3m4_f1f3.c similarity index 99% rename from arch/arm/src/stm32/stm32f10xxf30xx_flash.c rename to arch/arm/src/common/stm32/stm32_flash_m3m4_f1f3.c index a35d47482ba..5bdb27b1ddc 100644 --- a/arch/arm/src/stm32/stm32f10xxf30xx_flash.c +++ b/arch/arm/src/common/stm32/stm32_flash_m3m4_f1f3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f10xxf30xx_flash.c + * arch/arm/src/common/stm32/stm32_flash_m3m4_f1f3.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32f20xxf40xx_flash.c b/arch/arm/src/common/stm32/stm32_flash_m3m4_f2f4.c similarity index 97% rename from arch/arm/src/stm32/stm32f20xxf40xx_flash.c rename to arch/arm/src/common/stm32/stm32_flash_m3m4_f2f4.c index f8125b7ceb9..afd7300dda0 100644 --- a/arch/arm/src/stm32/stm32f20xxf40xx_flash.c +++ b/arch/arm/src/common/stm32/stm32_flash_m3m4_f2f4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f20xxf40xx_flash.c + * arch/arm/src/common/stm32/stm32_flash_m3m4_f2f4.c * * SPDX-License-Identifier: Apache-2.0 * @@ -47,7 +47,7 @@ /* Only for the STM32F[2|4]0xx family. */ -#if defined(CONFIG_STM32_STM32F20XX) || defined (CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) #if defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) # warning "Default Flash Configuration Used - See Override Flash Size Designator" @@ -449,4 +449,4 @@ uint8_t up_progmem_erasestate(void) return FLASH_ERASEDVALUE; } -#endif /* defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) */ +#endif /* defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) */ diff --git a/arch/arm/src/stm32/stm32g4xxx_flash.c b/arch/arm/src/common/stm32/stm32_flash_m3m4_g4.c similarity index 99% rename from arch/arm/src/stm32/stm32g4xxx_flash.c rename to arch/arm/src/common/stm32/stm32_flash_m3m4_g4.c index c14dd875a9a..f2d722e4799 100644 --- a/arch/arm/src/stm32/stm32g4xxx_flash.c +++ b/arch/arm/src/common/stm32/stm32_flash_m3m4_g4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32g4xxx_flash.c + * arch/arm/src/common/stm32/stm32_flash_m3m4_g4.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32l15xx_flash.c b/arch/arm/src/common/stm32/stm32_flash_m3m4_l1.c similarity index 99% rename from arch/arm/src/stm32/stm32l15xx_flash.c rename to arch/arm/src/common/stm32/stm32_flash_m3m4_l1.c index 4051a7eafda..ec1379498f4 100644 --- a/arch/arm/src/stm32/stm32l15xx_flash.c +++ b/arch/arm/src/common/stm32/stm32_flash_m3m4_l1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32l15xx_flash.c + * arch/arm/src/common/stm32/stm32_flash_m3m4_l1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_fmc.h b/arch/arm/src/common/stm32/stm32_fmc.h new file mode 100644 index 00000000000..c113a799541 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_fmc.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_fmc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32FMC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32FMC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_FMC_M3M4_V1) +# include "stm32_fmc_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_fmc" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32FMC_H */ diff --git a/arch/arm/src/stm32/stm32_fmc.c b/arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_fmc.c rename to arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.c index 4f0ac88e2a1..aa91d1824b2 100644 --- a/arch/arm/src/stm32/stm32_fmc.c +++ b/arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_fmc.c + * arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_fmc.h b/arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.h similarity index 93% rename from arch/arm/src/stm32/stm32_fmc.h rename to arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.h index 9644068d0ee..a29da3062fe 100644 --- a/arch/arm/src/stm32/stm32_fmc.h +++ b/arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_fmc.h + * arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32_STM32_FMC_H -#define __ARCH_ARM_STC_STM32_STM32_FMC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_FMC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_FMC_H /**************************************************************************** * Included Files @@ -29,6 +29,8 @@ #include +#if defined(CONFIG_STM32_HAVE_IP_FMC_M3M4_V1) + #include "chip.h" #include "hardware/stm32_fmc.h" @@ -133,4 +135,6 @@ void stm32_fmc_sdram_command(uint32_t cmd); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_STC_STM32_STM32_FMC_H */ + +#endif /* CONFIG_STM32_HAVE_IP_FMC_M3M4_V1 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_FMC_H */ diff --git a/arch/arm/src/common/stm32/stm32_foc.h b/arch/arm/src/common/stm32/stm32_foc.h new file mode 100644 index 00000000000..4f1b673f567 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_foc.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_foc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32FOC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32FOC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_COMMON_FOC) +# include "stm32_foc_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_foc" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32FOC_H */ diff --git a/arch/arm/src/stm32/stm32_foc.c b/arch/arm/src/common/stm32/stm32_foc_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_foc.c rename to arch/arm/src/common/stm32/stm32_foc_m3m4_v1.c index 4982a812b12..a50572a8bc5 100644 --- a/arch/arm/src/stm32/stm32_foc.c +++ b/arch/arm/src/common/stm32/stm32_foc_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_foc.c + * arch/arm/src/common/stm32/stm32_foc_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -38,13 +38,15 @@ #include "arm_internal.h" #include "stm32_pwm.h" +#include "stm32_foc_m3m4_v1.h" #include "stm32_adc.h" #include "stm32_dma.h" #include #include -#include "stm32_foc.h" +#include "stm32_pwm.h" +#include "stm32_foc_m3m4_v1.h" #include "hardware/stm32_dbgmcu.h" @@ -141,10 +143,9 @@ /* Debug register for PWM timers */ -#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \ - defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3) +#if defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ) # define FOC_PWM_FZ_REG (STM32_DBGMCU_APB2_FZ) -#elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) +#elif defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_CR) # define FOC_PWM_FZ_REG (STM32_DBGMCU_CR) #endif @@ -154,10 +155,9 @@ # define FOC0_PWM (1) # define FOC0_PWM_NCHANNELS (PWM_TIM1_NCHANNELS) # define FOC0_PWM_BASE (STM32_TIM1_BASE) -# if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \ - defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3) +# if defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ) # define FOC0_PWM_FZ_BIT (DBGMCU_APB2_TIM1STOP) -# elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) +# elif defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_CR) # define FOC0_PWM_FZ_BIT (DBGMCU_CR_TIM1STOP) # endif # if CONFIG_STM32_TIM1_MODE != 2 @@ -171,10 +171,9 @@ # define FOC1_PWM (8) # define FOC1_PWM_NCHANNELS (PWM_TIM8_NCHANNELS) # define FOC1_PWM_BASE (STM32_TIM8_BASE) -# if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \ - defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3) +# if defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ) # define FOC1_PWM_FZ_BIT (DBGMCU_APB2_TIM8STOP) -# elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) +# elif defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_CR) # define FOC1_PWM_FZ_BIT (DBGMCU_CR_TIM8STOP) # endif # if CONFIG_STM32_TIM8_MODE != 2 diff --git a/arch/arm/src/stm32/stm32_foc.h b/arch/arm/src/common/stm32/stm32_foc_m3m4_v1.h similarity index 96% rename from arch/arm/src/stm32/stm32_foc.h rename to arch/arm/src/common/stm32/stm32_foc_m3m4_v1.h index bfc145dbda8..58cddf08b2b 100644 --- a/arch/arm/src/stm32/stm32_foc.h +++ b/arch/arm/src/common/stm32/stm32_foc_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_foc.h + * arch/arm/src/common/stm32/stm32_foc_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_FOC_H -#define __ARCH_ARM_SRC_STM32_STM32_FOC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_FOC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_FOC_H /**************************************************************************** * Included Files @@ -200,4 +200,4 @@ struct adc_dev_s *stm32_foc_adcget(struct foc_dev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_FOC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_FOC_H */ diff --git a/arch/arm/src/stm32/stm32_waste.h b/arch/arm/src/common/stm32/stm32_freerun.h similarity index 54% rename from arch/arm/src/stm32/stm32_waste.h rename to arch/arm/src/common/stm32/stm32_freerun.h index 39a9b88893e..155917f7ea3 100644 --- a/arch/arm/src/stm32/stm32_waste.h +++ b/arch/arm/src/common/stm32/stm32_freerun.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_waste.h + * arch/arm/src/common/stm32/stm32_freerun.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,16 +20,36 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_WASTE_H -#define __ARCH_ARM_SRC_STM32_STM32_WASTE_H - -/* Waste CPU Time */ +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_FREERUN_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_FREERUN_H /**************************************************************************** - * Pre-processor Definitions + * Included Files ****************************************************************************/ -#ifndef __ASSEMBLY__ +#include + +#include +#include +#include + +#include "stm32_tim.h" + +#ifdef CONFIG_STM32_FREERUN + +struct stm32_freerun_s +{ + uint8_t chan; + uint8_t width; + struct stm32_tim_dev_s *tch; + uint32_t frequency; +#ifndef CONFIG_CLOCK_TIMEKEEPING + uint32_t overflow; +#endif +#ifdef CONFIG_CLOCK_TIMEKEEPING + uint64_t counter_mask; +#endif +}; #undef EXTERN #if defined(__cplusplus) @@ -40,27 +60,22 @@ extern "C" #define EXTERN extern #endif -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Waste CPU Time - * - * stm32_waste() is the logic that will be executed when portions of kernel - * or user-app is polling some register or similar, waiting for desired - * status. This time is wasted away. This function offers a measure of - * badly written piece of software or some undesired behavior. - * - * At the same time this function adds to some IDLE time which portion - * cannot be used for other purposes (yet). - */ - -void stm32_waste(void); +int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, + uint16_t resolution); +#ifndef CONFIG_CLOCK_TIMEKEEPING +int stm32_freerun_counter(struct stm32_freerun_s *freerun, + struct timespec *ts); +#else +int stm32_freerun_counter(struct stm32_freerun_s *freerun, + uint64_t *counter); +#endif +int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); #undef EXTERN -#if defined(__cplusplus) +#ifdef __cplusplus } #endif -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_WASTE_H */ +#endif /* CONFIG_STM32_FREERUN */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_FREERUN_H */ diff --git a/arch/arm/src/stm32/stm32_freerun.c b/arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_freerun.c rename to arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c index af5599a9314..e8122d5ef41 100644 --- a/arch/arm/src/stm32/stm32_freerun.c +++ b/arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_freerun.c + * arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_fsmc.h b/arch/arm/src/common/stm32/stm32_fsmc.h new file mode 100644 index 00000000000..15951027c41 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_fsmc.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_fsmc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32FSMC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32FSMC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) +# include "stm32_fsmc_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_fsmc" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32FSMC_H */ diff --git a/arch/arm/src/stm32/stm32_fsmc.c b/arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.c similarity index 93% rename from arch/arm/src/stm32/stm32_fsmc.c rename to arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.c index 5bfc967a961..c72cf09477f 100644 --- a/arch/arm/src/stm32/stm32_fsmc.c +++ b/arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_fsmc.c + * arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -49,7 +49,7 @@ void stm32_fsmc_enable(void) modifyreg32(STM32_RCC_AHBENR, 0, RCC_AHBENR_FSMCEN); } -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) void stm32_fsmc_enable(void) { @@ -73,7 +73,7 @@ void stm32_fsmc_disable(void) modifyreg32(STM32_RCC_AHBENR, RCC_AHBENR_FSMCEN, 0); } -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) void stm32_fsmc_disable(void) { diff --git a/arch/arm/src/stm32/stm32_fsmc.h b/arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.h similarity index 88% rename from arch/arm/src/stm32/stm32_fsmc.h rename to arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.h index df340763016..215ce47c016 100644 --- a/arch/arm/src/stm32/stm32_fsmc.h +++ b/arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_fsmc.h + * arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_FSMC_H -#define __ARCH_ARM_SRC_STM32_STM32_FSMC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_FSMC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_FSMC_H /**************************************************************************** * Included Files @@ -29,6 +29,8 @@ #include +#if defined(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) + #include "chip.h" #include "hardware/stm32_fsmc.h" @@ -73,4 +75,6 @@ void stm32_fsmc_disable(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_FSMC_H */ + +#endif /* CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_FSMC_H */ diff --git a/arch/arm/src/common/stm32/stm32_gpio.h b/arch/arm/src/common/stm32/stm32_gpio.h new file mode 100644 index 00000000000..f4910cabef1 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_gpio.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_gpio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_GPIO_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_GPIO_M0_V1) +# include "stm32_gpio_m0_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_GPIO_M3M4_V1) +# include "stm32_gpio_m3m4_v1v2.h" +#else +# error "Unsupported STM32 GPIO" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_gpio.c b/arch/arm/src/common/stm32/stm32_gpio_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_gpio.c rename to arch/arm/src/common/stm32/stm32_gpio_m0_v1.c index 7917ca44a79..3313cba03cd 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_gpio.c +++ b/arch/arm/src/common/stm32/stm32_gpio_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_gpio.c + * arch/arm/src/common/stm32/stm32_gpio_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -33,7 +33,7 @@ #include #include -#include +#include #include #include "arm_internal.h" diff --git a/arch/arm/src/stm32f0l0g0/stm32_gpio.h b/arch/arm/src/common/stm32/stm32_gpio_m0_v1.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_gpio.h rename to arch/arm/src/common/stm32/stm32_gpio_m0_v1.h index 0d6e7c881ac..43990a8514a 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_gpio.h +++ b/arch/arm/src/common/stm32/stm32_gpio_m0_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_gpio.h + * arch/arm/src/common/stm32/stm32_gpio_m0_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_GPIO_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_GPIO_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V2_M0_H /**************************************************************************** * Included Files @@ -35,7 +35,7 @@ #endif #include -#include +#include #include "chip.h" #include "hardware/stm32_gpio.h" @@ -364,4 +364,4 @@ void stm32_gpioinit(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_GPIO_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V2_M0_H */ diff --git a/arch/arm/src/stm32/stm32_gpio.c b/arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c similarity index 99% rename from arch/arm/src/stm32/stm32_gpio.c rename to arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c index 947d75bf042..14fe1654baa 100644 --- a/arch/arm/src/stm32/stm32_gpio.c +++ b/arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_gpio.c + * arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_gpio.h b/arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.h similarity index 99% rename from arch/arm/src/stm32/stm32_gpio.h rename to arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.h index 8fc0ef475eb..17689d672d9 100644 --- a/arch/arm/src/stm32/stm32_gpio.h +++ b/arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_gpio.h + * arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_GPIO_H -#define __ARCH_ARM_SRC_STM32_STM32_GPIO_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V1V2_H /**************************************************************************** * Included Files @@ -559,4 +559,4 @@ void stm32_gpioinit(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_GPIO_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V1V2_H */ diff --git a/arch/arm/src/stm32/stm32_hall3ph.c b/arch/arm/src/common/stm32/stm32_hall3ph.c similarity index 98% rename from arch/arm/src/stm32/stm32_hall3ph.c rename to arch/arm/src/common/stm32/stm32_hall3ph.c index 4eff99aee76..d6f7d360f5c 100644 --- a/arch/arm/src/stm32/stm32_hall3ph.c +++ b/arch/arm/src/common/stm32/stm32_hall3ph.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_hall3ph.c + * arch/arm/src/common/stm32/stm32_hall3ph.c * * SPDX-License-Identifier: Apache-2.0 * @@ -37,6 +37,7 @@ #include "chip.h" #include "arm_internal.h" +#include "stm32_gpio.h" #include "stm32_hall3ph.h" /**************************************************************************** diff --git a/arch/arm/src/stm32/stm32_hall3ph.h b/arch/arm/src/common/stm32/stm32_hall3ph.h similarity index 85% rename from arch/arm/src/stm32/stm32_hall3ph.h rename to arch/arm/src/common/stm32/stm32_hall3ph.h index 97a7bde16bf..e8329f84b29 100644 --- a/arch/arm/src/stm32/stm32_hall3ph.h +++ b/arch/arm/src/common/stm32/stm32_hall3ph.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_hall3ph.h + * arch/arm/src/common/stm32/stm32_hall3ph.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_HALL3PH_H -#define __ARCH_ARM_SRC_STM32_STM32_HALL3PH_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_HALL3PH_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_HALL3PH_H /**************************************************************************** * Included Files @@ -47,10 +47,6 @@ struct stm32_hall3ph_cfg_s * Public Function Prototypes ****************************************************************************/ -/**************************************************************************** - * Name: stm32_hall3ph_initialize - ****************************************************************************/ - /**************************************************************************** * Name: stm32_hall3ph_initialize * @@ -62,4 +58,4 @@ struct stm32_hall3ph_cfg_s int stm32_hall3ph_initialize(const char *devpath, struct stm32_hall3ph_cfg_s *cfg); -#endif /* __ARCH_ARM_SRC_STM32_STM32_HALL3PH_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_HALL3PH_H */ diff --git a/arch/arm/src/common/stm32/stm32_hciuart.h b/arch/arm/src/common/stm32/stm32_hciuart.h new file mode 100644 index 00000000000..f1ae1f79c81 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_hciuart.h @@ -0,0 +1,52 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_hciuart.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_HCIUART_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_HCIUART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +enum hciuart_devno_e +{ + HCIUART1 = 0, + HCIUART2 = 1, + HCIUART3 = 2, + HCIUART5 = 5, + HCIUART6 = 6, + HCIUART7 = 7 +}; + +const struct btuart_lowerhalf_s * +hciuart_instantiate(enum hciuart_devno_e uart); +void hciuart_initialize(void); + +#ifdef CONFIG_STM32_HCIUART_RXDMA +void stm32_serial_dma_poll(void); +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_HCIUART_H */ diff --git a/arch/arm/src/stm32/stm32_hciuart.c b/arch/arm/src/common/stm32/stm32_hciuart_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_hciuart.c rename to arch/arm/src/common/stm32/stm32_hciuart_m3m4_v1.c index cca04ded723..5f77bdc2899 100644 --- a/arch/arm/src/stm32/stm32_hciuart.c +++ b/arch/arm/src/common/stm32/stm32_hciuart_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_hciuart.c + * arch/arm/src/common/stm32/stm32_hciuart_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -46,9 +46,10 @@ #include "arm_internal.h" #include "chip.h" #include "stm32_uart.h" +#include "stm32_hciuart.h" #include "stm32_dma.h" #include "stm32_rcc.h" -#include "stm32_hciuart.h" +#include "stm32_uart.h" #include @@ -66,7 +67,7 @@ #ifdef CONFIG_STM32_HCIUART_RXDMA -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# if defined(CONFIG_STM32_HAVE_IP_DMA_V2) /* Verify that DMA has been enabled and the DMA channel has been defined. */ @@ -152,7 +153,7 @@ defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ defined(CONFIG_STM32_STM32F37XX) # define CONFIG_STM32_HCIUART_RXDMAPRIO DMA_CCR_PRIMED -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define CONFIG_STM32_HCIUART_RXDMAPRIO DMA_SCR_PRIMED # else # error "Unknown STM32 DMA" @@ -164,7 +165,7 @@ # if (CONFIG_STM32_HCIUART_RXDMAPRIO & ~DMA_CCR_PL_MASK) != 0 # error "Illegal value for CONFIG_STM32_HCIUART_RXDMAPRIO" # endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # if (CONFIG_STM32_HCIUART_RXDMAPRIO & ~DMA_SCR_PL_MASK) != 0 # error "Illegal value for CONFIG_STM32_HCIUART_RXDMAPRIO" # endif @@ -174,7 +175,7 @@ /* DMA control word */ -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# if defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define SERIAL_DMA_CONTROL_WORD \ (DMA_SCR_DIR_P2M | \ DMA_SCR_CIRC | \ diff --git a/arch/arm/src/common/stm32/stm32_hrtim.h b/arch/arm/src/common/stm32/stm32_hrtim.h new file mode 100644 index 00000000000..0be3fcfe2f7 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_hrtim.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_hrtim.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32HRTIM_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32HRTIM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_HRTIM_M3M4_V1) +# include "stm32_hrtim_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_hrtim" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32HRTIM_H */ diff --git a/arch/arm/src/stm32/stm32_hrtim.c b/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_hrtim.c rename to arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.c index 86e0a074b26..73791c4c21f 100644 --- a/arch/arm/src/stm32/stm32_hrtim.c +++ b/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_hrtim.c + * arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -37,7 +37,9 @@ #include "chip.h" #include "stm32.h" #include "stm32_gpio.h" -#include "stm32_hrtim.h" +#include "stm32_hrtim_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_hrtim_m3m4_v1.h" #if defined(CONFIG_STM32_HRTIM1) diff --git a/arch/arm/src/stm32/stm32_hrtim.h b/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h similarity index 99% rename from arch/arm/src/stm32/stm32_hrtim.h rename to arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h index 7934ca14bff..026c6e2e7f3 100644 --- a/arch/arm/src/stm32/stm32_hrtim.h +++ b/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_hrtim.h + * arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_HRTIM_H -#define __ARCH_ARM_SRC_STM32_STM32_HRTIM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_HRTIM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_HRTIM_H /**************************************************************************** * Included Files @@ -1136,4 +1136,4 @@ int hrtim_register(const char *path, struct hrtim_dev_s *dev); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_HRTIM1 */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_HRTIM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_HRTIM_H */ diff --git a/arch/arm/src/common/stm32/stm32_hsi48.h b/arch/arm/src/common/stm32/stm32_hsi48.h new file mode 100644 index 00000000000..6116df0117e --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_hsi48.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_hsi48.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32HSI48_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32HSI48_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_HSI48_M0_V1) +# include "stm32_hsi48_m0_v1.h" +#else +# error "Unsupported STM32 stm32_hsi48" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32HSI48_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_hsi48.c b/arch/arm/src/common/stm32/stm32_hsi48_m0_v1.c similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_hsi48.c rename to arch/arm/src/common/stm32/stm32_hsi48_m0_v1.c index 9902f196f26..ac6162fc82b 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_hsi48.c +++ b/arch/arm/src/common/stm32/stm32_hsi48_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_hsi48.c + * arch/arm/src/common/stm32/stm32_hsi48_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -31,7 +31,7 @@ #include "hardware/stm32_rcc.h" #include "hardware/stm32_crs.h" -#include "stm32_hsi48.h" +#include "stm32_hsi48_m0_v1.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32f0l0g0/stm32_hsi48.h b/arch/arm/src/common/stm32/stm32_hsi48_m0_v1.h similarity index 94% rename from arch/arm/src/stm32f0l0g0/stm32_hsi48.h rename to arch/arm/src/common/stm32/stm32_hsi48_m0_v1.h index 216fce2501e..095c9e62cc6 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_hsi48.h +++ b/arch/arm/src/common/stm32/stm32_hsi48_m0_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_hsi48.h + * arch/arm/src/common/stm32/stm32_hsi48_m0_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_HSI48_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_HSI48_H /**************************************************************************** * Included Files @@ -93,4 +93,4 @@ void stm32_enable_hsi48(enum syncsrc_e syncsrc); void stm32_disable_hsi48(void); #endif /* CONFIG_STM32_HAVE_HSI48 */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_HSI48_H */ diff --git a/arch/arm/src/stm32/stm32_i2c.h b/arch/arm/src/common/stm32/stm32_i2c.h similarity index 84% rename from arch/arm/src/stm32/stm32_i2c.h rename to arch/arm/src/common/stm32/stm32_i2c.h index 1ad4f2b7f1a..834372fd75c 100644 --- a/arch/arm/src/stm32/stm32_i2c.h +++ b/arch/arm/src/common/stm32/stm32_i2c.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_i2c.h + * arch/arm/src/common/stm32/stm32_i2c.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_I2C_H -#define __ARCH_ARM_SRC_STM32_STM32_I2C_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_I2C_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_I2C_H /**************************************************************************** * Included Files @@ -88,6 +88,7 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port); int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); +#if defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) || defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) /**************************************************************************** * Name: stm32_i2cbus_slaveinitialize * @@ -104,22 +105,6 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); ****************************************************************************/ struct i2c_slave_s *stm32_i2cbus_slaveinitialize(int port); +#endif -/**************************************************************************** - * Name: stm32_i2cbus_uninitialize - * - * Description: - * De-initialize the selected I2C port, and power down the device. - * - * Input Parameters: - * Device structure as returned by the stm32_i2cbus_initialize() - * - * Returned Value: - * OK on success, ERROR when internal reference count mismatch or dev - * points to invalid hardware device. - * - ****************************************************************************/ - -int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); - -#endif /* __ARCH_ARM_SRC_STM32_STM32_I2C_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_I2C_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_i2c.c b/arch/arm/src/common/stm32/stm32_i2c_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_i2c.c rename to arch/arm/src/common/stm32/stm32_i2c_m0_v1.c index b2f689f9798..b8cbdebce4c 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_i2c.c +++ b/arch/arm/src/common/stm32/stm32_i2c_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_i2c.c + * arch/arm/src/common/stm32/stm32_i2c_m0_v1.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2011 Uros Platise. All rights reserved. diff --git a/arch/arm/src/stm32/stm32_i2c.c b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_i2c.c rename to arch/arm/src/common/stm32/stm32_i2c_m3m4_v1.c index da30fd1342d..4cc9c4f8291 100644 --- a/arch/arm/src/stm32/stm32_i2c.c +++ b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_i2c.c + * arch/arm/src/common/stm32/stm32_i2c_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -89,7 +89,7 @@ */ #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) + defined(CONFIG_STM32_HAVE_IP_DMA_V2) /**************************************************************************** * Pre-processor Definitions @@ -149,7 +149,7 @@ #elif defined(CONFIG_STM32_STM32F10XX) # define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \ GPIO_MODE_50MHz) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\ GPIO_SPEED_50MHz | GPIO_OUTPUT_SET) #endif @@ -1281,7 +1281,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) * from the F1 in that BTF is not set after data is received (only RXNE). */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || \ +#if defined(CONFIG_STM32_HAVE_IP_DMA_V2) || \ defined(CONFIG_STM32_STM32L15XX) if (priv->dcnt <= 0 && (status & (I2C_SR1_BTF | I2C_SR1_RXNE)) != 0) #else @@ -1941,5 +1941,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F4XXX */ +#endif /* CONFIG_STM32_HAVE_IP_I2C_M3M4_V1 */ #endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */ diff --git a/arch/arm/src/stm32/stm32_i2c_alt.c b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_alt.c similarity index 99% rename from arch/arm/src/stm32/stm32_i2c_alt.c rename to arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_alt.c index 115a5a8d103..3f4055fd0bf 100644 --- a/arch/arm/src/stm32/stm32_i2c_alt.c +++ b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_alt.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_i2c_alt.c + * arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_alt.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2016-2017 Gregory Nutt. All rights reserved. @@ -112,7 +112,7 @@ */ #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) + defined(CONFIG_STM32_HAVE_IP_DMA_V2) /**************************************************************************** * Pre-processor Definitions @@ -172,7 +172,7 @@ #elif defined(CONFIG_STM32_STM32F10XX) # define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \ GPIO_MODE_50MHz) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\ GPIO_SPEED_50MHz | GPIO_OUTPUT_SET) #endif @@ -2448,5 +2448,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F4XXX */ +#endif /* CONFIG_STM32_HAVE_IP_I2C_M3M4_V1 */ #endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */ diff --git a/arch/arm/src/stm32/stm32f40xxx_i2c.c b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_f40xxx.c similarity index 99% rename from arch/arm/src/stm32/stm32f40xxx_i2c.c rename to arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_f40xxx.c index 58b769fc5d9..9ed73e228db 100644 --- a/arch/arm/src/stm32/stm32f40xxx_i2c.c +++ b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_f40xxx.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f40xxx_i2c.c + * arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_f40xxx.c * * SPDX-License-Identifier: Apache-2.0 * @@ -89,7 +89,7 @@ */ #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) + defined(CONFIG_STM32_HAVE_IP_DMA_V2) /**************************************************************************** * Pre-processor Definitions @@ -149,7 +149,7 @@ #elif defined(CONFIG_STM32_STM32F10XX) # define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \ GPIO_MODE_50MHz) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\ GPIO_SPEED_50MHz | GPIO_OUTPUT_SET) #endif @@ -2690,5 +2690,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F4XXX */ +#endif /* CONFIG_STM32_HAVE_IP_I2C_M3M4_V1 */ #endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */ diff --git a/arch/arm/src/stm32/stm32_i2c_v2.c b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c similarity index 99% rename from arch/arm/src/stm32/stm32_i2c_v2.c rename to arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c index 87d9a1700e0..8b0fd802c5e 100644 --- a/arch/arm/src/stm32/stm32_i2c_v2.c +++ b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_i2c_v2.c + * arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2016-2017 Gregory Nutt. All rights reserved. diff --git a/arch/arm/src/stm32/stm32_i2cslave_v2.c b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v2_slave.c similarity index 99% rename from arch/arm/src/stm32/stm32_i2cslave_v2.c rename to arch/arm/src/common/stm32/stm32_i2c_m3m4_v2_slave.c index bbf86c2e49d..53ce3975f16 100644 --- a/arch/arm/src/stm32/stm32_i2cslave_v2.c +++ b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v2_slave.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_i2cslave_v2.c + * arch/arm/src/common/stm32/stm32_i2c_m3m4_v2_slave.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/arm/src/stm32/stm32_i2s.h b/arch/arm/src/common/stm32/stm32_i2s.h similarity index 78% rename from arch/arm/src/stm32/stm32_i2s.h rename to arch/arm/src/common/stm32/stm32_i2s.h index 5ed34136591..376fa24efed 100644 --- a/arch/arm/src/stm32/stm32_i2s.h +++ b/arch/arm/src/common/stm32/stm32_i2s.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_i2s.h + * arch/arm/src/common/stm32/stm32_i2s.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,32 +20,35 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_I2S_H -#define __ARCH_ARM_SRC_STM32_STM32_I2S_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_I2S_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_I2S_H /**************************************************************************** * Included Files ****************************************************************************/ #include -#include -#include "chip.h" +#ifdef CONFIG_STM32_HAVE_IP_I2S_M3M4_V1 -#ifndef __ASSEMBLY__ +# include + +# include "chip.h" + +# ifndef __ASSEMBLY__ /**************************************************************************** * Public Data ****************************************************************************/ -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" +# undef EXTERN +# if defined(__cplusplus) +# define EXTERN extern "C" extern "C" { -#else -#define EXTERN extern -#endif +# else +# define EXTERN extern +# endif /**************************************************************************** * Public Function Prototypes @@ -67,10 +70,13 @@ extern "C" struct i2s_dev_s *stm32_i2sbus_initialize(int port); -#undef EXTERN -#if defined(__cplusplus) +# undef EXTERN +# if defined(__cplusplus) } -#endif +# endif -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_I2S_H */ +# endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_STM32_HAVE_IP_I2S_M3M4_V1 */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_I2S_H */ diff --git a/arch/arm/src/stm32/stm32_i2s.c b/arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_i2s.c rename to arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c index af156dd8a7e..49be32aa826 100644 --- a/arch/arm/src/stm32/stm32_i2s.c +++ b/arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_i2s.c + * arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -72,6 +72,7 @@ #include "arm_internal.h" #include "stm32_dma.h" +#include "stm32_i2s.h" #include "stm32_spi.h" #include "stm32_rcc.h" @@ -144,7 +145,7 @@ # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO # elif defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX) # define SPI_DMA_PRIO DMA_CCR_PRIMED -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define SPI_DMA_PRIO DMA_SCR_PRIMED # else # error "Unknown STM32 DMA" @@ -154,7 +155,7 @@ # if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0 # error "Illegal value for CONFIG_SPI_DMAPRIO" # endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # if (SPI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0 # error "Illegal value for CONFIG_SPI_DMAPRIO" # endif @@ -176,7 +177,7 @@ # define SPI_TXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC|DMA_CCR_DIR) # define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS |DMA_CCR_DIR) # define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_DIR) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_16BITS|DMA_SCR_PSIZE_16BITS|DMA_SCR_MINC|DMA_SCR_DIR_P2M) # define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_MINC|DMA_SCR_DIR_P2M) # define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_P2M) diff --git a/arch/arm/src/stm32f0l0g0/stm32_idle.c b/arch/arm/src/common/stm32/stm32_idle_m0_v1.c similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_idle.c rename to arch/arm/src/common/stm32/stm32_idle_m0_v1.c index 1b971a961ca..a9d6ff68a08 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_idle.c +++ b/arch/arm/src/common/stm32/stm32_idle_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_idle.c + * arch/arm/src/common/stm32/stm32_idle_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_idle.c b/arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_idle.c rename to arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c index 22f559f2767..19f57a3117e 100644 --- a/arch/arm/src/stm32/stm32_idle.c +++ b/arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_idle.c + * arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_irq.c b/arch/arm/src/common/stm32/stm32_irq_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_irq.c rename to arch/arm/src/common/stm32/stm32_irq_m0_v1.c index c46388c2641..fb71ce0917a 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_irq.c +++ b/arch/arm/src/common/stm32/stm32_irq_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_irq.c + * arch/arm/src/common/stm32/stm32_irq_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_irq.c b/arch/arm/src/common/stm32/stm32_irq_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_irq.c rename to arch/arm/src/common/stm32/stm32_irq_m3m4_v1.c index 57ed8ba1a44..c79c0bddd8d 100644 --- a/arch/arm/src/stm32/stm32_irq.c +++ b/arch/arm/src/common/stm32/stm32_irq_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_irq.c + * arch/arm/src/common/stm32/stm32_irq_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_iwdg.c b/arch/arm/src/common/stm32/stm32_iwdg_m0_v1.c similarity index 80% rename from arch/arm/src/stm32f0l0g0/stm32_iwdg.c rename to arch/arm/src/common/stm32/stm32_iwdg_m0_v1.c index f2821942020..172534d89e8 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_iwdg.c +++ b/arch/arm/src/common/stm32/stm32_iwdg_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_iwdg.c + * arch/arm/src/common/stm32/stm32_iwdg_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -43,6 +43,14 @@ #include "hardware/stm32_dbgmcu.h" #include "stm32_wdg.h" +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_IWDG) + +/* STM32C0 uses the second CSR register for LSI. */ + +#ifdef CONFIG_ARCH_CHIP_STM32C0 +# define STM32_RCC_CSR STM32_RCC_CSR2 +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -69,6 +77,14 @@ /* Configuration ************************************************************/ +#ifndef CONFIG_STM32_IWDG_DEFTIMOUT +# define CONFIG_STM32_IWDG_DEFTIMOUT IWDG_MAXTIMEOUT +#endif + +#ifndef CONFIG_DEBUG_WATCHDOG_INFO +# undef CONFIG_STM32_IWDG_REGDEBUG +#endif + /* REVISIT: It appears that you can only setup the prescaler and reload * registers once. After that, the SR register's PVU and RVU bits never go * to zero. So we defer setting up these registers until the watchdog @@ -116,17 +132,25 @@ struct stm32_lowerhalf_s /* Register operations ******************************************************/ +#ifdef CONFIG_STM32_IWDG_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint16_t val, uint32_t addr); +#else +# define stm32_getreg(addr) getreg16(addr) +# define stm32_putreg(val,addr) putreg16(val,addr) +#endif + static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv); /* "Lower half" driver methods **********************************************/ -static int stm32_start(struct watchdog_lowerhalf_s *lower); -static int stm32_stop(struct watchdog_lowerhalf_s *lower); -static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); -static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, - struct watchdog_status_s *status); -static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, - uint32_t timeout); +static int stm32_start(struct watchdog_lowerhalf_s *lower); +static int stm32_stop(struct watchdog_lowerhalf_s *lower); +static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); +static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, + struct watchdog_status_s *status); +static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, + uint32_t timeout); /**************************************************************************** * Private Data @@ -153,6 +177,90 @@ static struct stm32_lowerhalf_s g_wdgdev; * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: stm32_getreg + * + * Description: + * Get the contents of an STM32 IWDG register + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_IWDG_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t count = 0; + static uint16_t preval = 0; + + /* Read the value from the register */ + + uint16_t val = getreg16(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + wdinfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + wdinfo("[repeats %d more times]\n", count - 3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + wdinfo("%08" PRIx32 "->%04x\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: stm32_putreg + * + * Description: + * Set the contents of an STM32 register to a value + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_IWDG_REGDEBUG +static void stm32_putreg(uint16_t val, uint32_t addr) +{ + /* Show the register value being written */ + + wdinfo("%08" PRIx32 "<-%04x\n", addr, val); + + /* Write the value */ + + putreg16(val, addr); +} +#endif + /**************************************************************************** * Name: stm32_setprescaler * @@ -170,7 +278,7 @@ static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv) { /* Enable write access to IWDG_PR and IWDG_RLR registers */ - putreg32(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR); /* Wait for the PVU and RVU bits to be reset be hardware. These bits * were set the last time that the PR register was written and may not @@ -181,20 +289,20 @@ static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv) */ #ifndef CONFIG_STM32_IWDG_ONETIMESETUP - while ((getreg32(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)) != 0); + while ((stm32_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)) != 0); #endif /* Set the prescaler */ - putreg32((uint16_t)priv->prescaler << IWDG_PR_SHIFT, STM32_IWDG_PR); + stm32_putreg((uint16_t)priv->prescaler << IWDG_PR_SHIFT, STM32_IWDG_PR); /* Set the reload value */ - putreg32((uint16_t)priv->reload, STM32_IWDG_RLR); + stm32_putreg((uint16_t)priv->reload, STM32_IWDG_RLR); /* Reload the counter (and disable write access) */ - putreg32(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); } /**************************************************************************** @@ -244,7 +352,7 @@ static int stm32_start(struct watchdog_lowerhalf_s *lower) */ flags = enter_critical_section(); - putreg32(IWDG_KR_KEY_START, STM32_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_START, STM32_IWDG_KR); priv->lastreset = clock_systime_ticks(); priv->started = true; leave_critical_section(flags); @@ -303,7 +411,7 @@ static int stm32_keepalive(struct watchdog_lowerhalf_s *lower) /* Reload the IWDG timer */ flags = enter_critical_section(); - putreg32(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); priv->lastreset = clock_systime_ticks(); leave_critical_section(flags); @@ -561,33 +669,41 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) */ stm32_rcc_enablelsi(); -#ifdef STM32_RCC_CSR wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32_RCC_CSR)); -#else - wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32_RCC_CSR1)); -#endif /* Select an arbitrary initial timeout value. But don't start the watchdog * yet. NOTE: If the "Hardware watchdog" feature is enabled through the * device option bits, the watchdog is automatically enabled at power-on. */ - stm32_settimeout((struct watchdog_lowerhalf_s *)priv, IWDG_MAXTIMEOUT); + stm32_settimeout((struct watchdog_lowerhalf_s *)priv, + CONFIG_STM32_IWDG_DEFTIMOUT); /* Register the watchdog driver as /dev/watchdog0 */ watchdog_register(devpath, (struct watchdog_lowerhalf_s *)priv); - /* When the microcontroller enters debug mode (core halted), + /* When the microcontroller enters debug mode (Cortex-M4F core halted), * the IWDG counter either continues to work normally or stops, depending * on DBG_IWDG_STOP configuration bit in DBG module. */ -#ifdef CONFIG_DEBUG_FEATURES +#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ + defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ + defined(CONFIG_STM32_JTAG_SW_ENABLE) { +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ); cr |= DBGMCU_APB1_IWDGSTOP; putreg32(cr, STM32_DBGMCU_APB1_FZ); +#else /* if defined(CONFIG_STM32_STM32F10XX) */ + uint32_t cr = getreg32(STM32_DBGMCU_CR); + cr |= DBGMCU_CR_IWDGSTOP; + putreg32(cr, STM32_DBGMCU_CR); +#endif } #endif } + +#endif /* CONFIG_WATCHDOG && CONFIG_STM32_IWDG */ diff --git a/arch/arm/src/stm32/stm32_iwdg.c b/arch/arm/src/common/stm32/stm32_iwdg_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_iwdg.c rename to arch/arm/src/common/stm32/stm32_iwdg_m3m4_v1.c index 8996a9e845e..026b0edf053 100644 --- a/arch/arm/src/stm32/stm32_iwdg.c +++ b/arch/arm/src/common/stm32/stm32_iwdg_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_iwdg.c + * arch/arm/src/common/stm32/stm32_iwdg_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc.h b/arch/arm/src/common/stm32/stm32_lowputc.h similarity index 90% rename from arch/arm/src/stm32f0l0g0/stm32_lowputc.h rename to arch/arm/src/common/stm32/stm32_lowputc.h index 8158c50f813..0c2ddb9156d 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lowputc.h +++ b/arch/arm/src/common/stm32/stm32_lowputc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lowputc.h + * arch/arm/src/common/stm32/stm32_lowputc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_LOWPUTC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_LOWPUTC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_LOWPUTC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_LOWPUTC_H /**************************************************************************** * Included Files @@ -63,4 +63,4 @@ void stm32_lowsetup(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_LOWPUTC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_LOWPUTC_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c b/arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v3.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c rename to arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v3.c index 2f3e87315b3..03acef0e8d0 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c +++ b/arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c + * arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v3.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c b/arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v4.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c rename to arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v4.c index db8065517c3..154051ca63c 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c +++ b/arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c + * arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v4.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_lowputc.c b/arch/arm/src/common/stm32/stm32_lowputc_usart_m3m4_v1v2v3v4.c similarity index 99% rename from arch/arm/src/stm32/stm32_lowputc.c rename to arch/arm/src/common/stm32/stm32_lowputc_usart_m3m4_v1v2v3v4.c index ff9659c9710..aa83d21a3b3 100644 --- a/arch/arm/src/stm32/stm32_lowputc.c +++ b/arch/arm/src/common/stm32/stm32_lowputc_usart_m3m4_v1v2v3v4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_lowputc.c + * arch/arm/src/common/stm32/stm32_lowputc_usart_m3m4_v1v2v3v4.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_lse.c b/arch/arm/src/common/stm32/stm32_lse_m0_v1.c similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_lse.c rename to arch/arm/src/common/stm32/stm32_lse_m0_v1.c index 9fb81ae318e..0e5bc4fbc3d 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lse.c +++ b/arch/arm/src/common/stm32/stm32_lse_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lse.c + * arch/arm/src/common/stm32/stm32_lse_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_lse.c b/arch/arm/src/common/stm32/stm32_lse_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_lse.c rename to arch/arm/src/common/stm32/stm32_lse_m3m4_v1.c index 7f4d215ddc1..25f33542e59 100644 --- a/arch/arm/src/stm32/stm32_lse.c +++ b/arch/arm/src/common/stm32/stm32_lse_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_lse.c + * arch/arm/src/common/stm32/stm32_lse_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_lsi.c b/arch/arm/src/common/stm32/stm32_lsi_m0_v1.c similarity index 94% rename from arch/arm/src/stm32f0l0g0/stm32_lsi.c rename to arch/arm/src/common/stm32/stm32_lsi_m0_v1.c index cfcc05e1902..19aa04dd4f0 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lsi.c +++ b/arch/arm/src/common/stm32/stm32_lsi_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lsi.c + * arch/arm/src/common/stm32/stm32_lsi_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -33,11 +33,11 @@ * Pre-processor Definitions ****************************************************************************/ -/* STM32C0 use the second CSR register for LSI */ +/* STM32C0 uses the second CSR register for LSI. */ #ifdef CONFIG_ARCH_CHIP_STM32C0 -# define STM32_RCC_CSR STM32_RCC_CSR2 -# define RCC_CSR_LSION RCC_CSR2_LSION +# define STM32_RCC_CSR STM32_RCC_CSR2 +# define RCC_CSR_LSION RCC_CSR2_LSION # define RCC_CSR_LSIRDY RCC_CSR2_LSIRDY #endif diff --git a/arch/arm/src/stm32/stm32_lsi.c b/arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c similarity index 92% rename from arch/arm/src/stm32/stm32_lsi.c rename to arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c index 45d15c8fab1..97ae757a001 100644 --- a/arch/arm/src/stm32/stm32_lsi.c +++ b/arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_lsi.c + * arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -33,6 +33,14 @@ * Pre-processor Definitions ****************************************************************************/ +/* STM32C0 uses the second CSR register for LSI. */ + +#ifdef CONFIG_ARCH_CHIP_STM32C0 +# define STM32_RCC_CSR STM32_RCC_CSR2 +# define RCC_CSR_LSION RCC_CSR2_LSION +# define RCC_CSR_LSIRDY RCC_CSR2_LSIRDY +#endif + /**************************************************************************** * Private Data ****************************************************************************/ diff --git a/arch/arm/src/common/stm32/stm32_ltdc.h b/arch/arm/src/common/stm32/stm32_ltdc.h new file mode 100644 index 00000000000..d51c2b4ba3d --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_ltdc.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_ltdc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32LTDC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32LTDC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_LTDC_M3M4_V1) +# include "stm32_ltdc_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_ltdc" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32LTDC_H */ diff --git a/arch/arm/src/stm32/stm32_ltdc.c b/arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_ltdc.c rename to arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.c index 8e36b797a5e..59bc7fc4484 100644 --- a/arch/arm/src/stm32/stm32_ltdc.c +++ b/arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_ltdc.c + * arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -49,8 +49,8 @@ #include "stm32.h" #include "hardware/stm32_ltdc.h" #include "hardware/stm32_dma2d.h" -#include "stm32_ltdc.h" -#include "stm32_dma2d.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_dma2d_m3m4_v1.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32/stm32_ltdc.h b/arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.h similarity index 91% rename from arch/arm/src/stm32/stm32_ltdc.h rename to arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.h index 50e089869e0..c0e4e3adb5f 100644 --- a/arch/arm/src/stm32/stm32_ltdc.h +++ b/arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_ltdc.h + * arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_LTDC_H -#define __ARCH_ARM_SRC_STM32_STM32_LTDC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_LTDC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_LTDC_H /**************************************************************************** * Included Files @@ -29,6 +29,8 @@ #include +#if defined(CONFIG_STM32_HAVE_IP_LTDC_M3M4_V1) + #include #include @@ -99,4 +101,6 @@ struct fb_vtable_s *stm32_ltdcgetvplane(int vplane); #ifdef CONFIG_STM32_LCD_BACKLIGHT void stm32_backlight(bool blon); #endif -#endif /* __ARCH_ARM_SRC_STM32_STM32_LTDC_H */ + +#endif /* CONFIG_STM32_HAVE_IP_LTDC_M3M4_V1 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_LTDC_H */ diff --git a/arch/arm/src/stm32/stm32_mpuinit.h b/arch/arm/src/common/stm32/stm32_mpuinit.h similarity index 91% rename from arch/arm/src/stm32/stm32_mpuinit.h rename to arch/arm/src/common/stm32/stm32_mpuinit.h index f4af906ef4e..606d589ef28 100644 --- a/arch/arm/src/stm32/stm32_mpuinit.h +++ b/arch/arm/src/common/stm32/stm32_mpuinit.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_mpuinit.h + * arch/arm/src/common/stm32/stm32_mpuinit.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_MPUINIT_H -#define __ARCH_ARM_SRC_STM32_STM32_MPUINIT_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_MPUINIT_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_MPUINIT_H /**************************************************************************** * Included Files @@ -62,4 +62,4 @@ void stm32_mpu_uheap(uintptr_t start, size_t size); # define stm32_mpu_uheap(start,size) #endif -#endif /* __ARCH_ARM_SRC_STM32_STM32_MPUINIT_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_MPUINIT_H */ diff --git a/arch/arm/src/stm32/stm32_mpuinit.c b/arch/arm/src/common/stm32/stm32_mpuinit_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_mpuinit.c rename to arch/arm/src/common/stm32/stm32_mpuinit_m3m4_v1.c index 6cc545c825e..cc066077de6 100644 --- a/arch/arm/src/stm32/stm32_mpuinit.c +++ b/arch/arm/src/common/stm32/stm32_mpuinit_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_mpuinit.c + * arch/arm/src/common/stm32/stm32_mpuinit_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_oneshot.h b/arch/arm/src/common/stm32/stm32_oneshot.h new file mode 100644 index 00000000000..7cb508f67d4 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_oneshot.h @@ -0,0 +1,94 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_oneshot.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_ONESHOT_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_ONESHOT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "stm32_tim.h" + +#ifdef CONFIG_STM32_ONESHOT + +#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ + CONFIG_STM32_ONESHOT_MAXTIMERS < 1 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 +#endif + +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 +# warning Additional logic required to handle more than 8 timers +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 +#endif + +typedef void (*oneshot_handler_t)(void *arg); + +struct stm32_oneshot_s +{ + uint8_t chan; +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 + uint8_t cbndx; +#endif + volatile bool running; + struct stm32_tim_dev_s *tch; + volatile oneshot_handler_t handler; + volatile void *arg; + uint32_t frequency; + uint32_t period; +}; + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, + uint16_t resolution); +int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec); +int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, + oneshot_handler_t handler, void *arg, + const struct timespec *ts); +int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, + struct timespec *ts); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_STM32_ONESHOT */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_ONESHOT_H */ diff --git a/arch/arm/src/stm32/stm32_oneshot.c b/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_oneshot.c rename to arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c index b80df41e762..e8ba155e9da 100644 --- a/arch/arm/src/stm32/stm32_oneshot.c +++ b/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_oneshot.c + * arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_oneshot_lowerhalf.c b/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c similarity index 99% rename from arch/arm/src/stm32/stm32_oneshot_lowerhalf.c rename to arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c index 8d5c5c79a28..729adb4078c 100644 --- a/arch/arm/src/stm32/stm32_oneshot_lowerhalf.c +++ b/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_oneshot_lowerhalf.c + * arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_opamp.h b/arch/arm/src/common/stm32/stm32_opamp.h new file mode 100644 index 00000000000..f3c9827a959 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_opamp.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_opamp.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32OPAMP_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32OPAMP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_OPAMP_M3M4_V1) +# include "stm32_opamp_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_opamp" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32OPAMP_H */ diff --git a/arch/arm/src/stm32/stm32_opamp.c b/arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_opamp.c rename to arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.c index 05f685eab55..7c90dae4b8b 100644 --- a/arch/arm/src/stm32/stm32_opamp.c +++ b/arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_opamp.c + * arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -37,7 +37,9 @@ #include "chip.h" #include "stm32_gpio.h" -#include "stm32_opamp.h" +#include "stm32_opamp_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_opamp_m3m4_v1.h" /* OPAMP "upper half" support must be enabled */ diff --git a/arch/arm/src/stm32/stm32_opamp.h b/arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.h similarity index 96% rename from arch/arm/src/stm32/stm32_opamp.h rename to arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.h index b85acb37bff..d45a7532236 100644 --- a/arch/arm/src/stm32/stm32_opamp.h +++ b/arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_opamp.h + * arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_OPAMP_H -#define __ARCH_ARM_SRC_STM32_STM32_OPAMP_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_OPAMP_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_OPAMP_H /**************************************************************************** * Included Files @@ -216,4 +216,4 @@ struct opamp_dev_s *stm32_opampinitialize(int intf); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_OPAMP */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_OPAMP_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_OPAMP_H */ diff --git a/arch/arm/src/stm32/stm32_otgfs.h b/arch/arm/src/common/stm32/stm32_otgfs.h similarity index 95% rename from arch/arm/src/stm32/stm32_otgfs.h rename to arch/arm/src/common/stm32/stm32_otgfs.h index 42287bc2120..b7cf5962ed0 100644 --- a/arch/arm/src/stm32/stm32_otgfs.h +++ b/arch/arm/src/common/stm32/stm32_otgfs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_otgfs.h + * arch/arm/src/common/stm32/stm32_otgfs.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_OTGFS_H -#define __ARCH_ARM_SRC_STM32_STM32_OTGFS_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGFS_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGFS_H /**************************************************************************** * Included Files @@ -110,4 +110,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_OTGFS */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_OTGFS_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGFS_H */ diff --git a/arch/arm/src/stm32/stm32_otgfsdev.c b/arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_otgfsdev.c rename to arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c index 2f3c1416e7e..af02d027c98 100644 --- a/arch/arm/src/stm32/stm32_otgfsdev.c +++ b/arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_otgfsdev.c + * arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_otgfshost.c b/arch/arm/src/common/stm32/stm32_otgfshost_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_otgfshost.c rename to arch/arm/src/common/stm32/stm32_otgfshost_m3m4_v1.c index b8a44c90178..1197648cd1b 100644 --- a/arch/arm/src/stm32/stm32_otgfshost.c +++ b/arch/arm/src/common/stm32/stm32_otgfshost_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_otgfshost.c + * arch/arm/src/common/stm32/stm32_otgfshost_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -56,7 +56,7 @@ #include "arm_internal.h" #include "stm32_gpio.h" -#include "stm32_usbhost.h" +#include "stm32_usbhost_m3m4_v1.h" #if defined(CONFIG_STM32_USBHOST) && defined(CONFIG_STM32_OTGFS) diff --git a/arch/arm/src/stm32/stm32_otghs.h b/arch/arm/src/common/stm32/stm32_otghs.h similarity index 95% rename from arch/arm/src/stm32/stm32_otghs.h rename to arch/arm/src/common/stm32/stm32_otghs.h index 68016e3793f..c6484304593 100644 --- a/arch/arm/src/stm32/stm32_otghs.h +++ b/arch/arm/src/common/stm32/stm32_otghs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_otghs.h + * arch/arm/src/common/stm32/stm32_otghs.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_OTGHS_H -#define __ARCH_ARM_SRC_STM32_STM32_OTGHS_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGHS_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGHS_H /**************************************************************************** * Included Files @@ -110,4 +110,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_OTGFS */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_OTGHS_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGHS_H */ diff --git a/arch/arm/src/stm32/stm32_otghsdev.c b/arch/arm/src/common/stm32/stm32_otghsdev_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_otghsdev.c rename to arch/arm/src/common/stm32/stm32_otghsdev_m3m4_v1.c index a4fae9cad4f..4a0e61a2132 100644 --- a/arch/arm/src/stm32/stm32_otghsdev.c +++ b/arch/arm/src/common/stm32/stm32_otghsdev_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_otghsdev.c + * arch/arm/src/common/stm32/stm32_otghsdev_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_otghshost.c b/arch/arm/src/common/stm32/stm32_otghshost_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_otghshost.c rename to arch/arm/src/common/stm32/stm32_otghshost_m3m4_v1.c index 4acc263c420..45faa0a4963 100644 --- a/arch/arm/src/stm32/stm32_otghshost.c +++ b/arch/arm/src/common/stm32/stm32_otghshost_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_otghshost.c + * arch/arm/src/common/stm32/stm32_otghshost_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -56,7 +56,7 @@ #include "arm_internal.h" #include "stm32_gpio.h" -#include "stm32_usbhost.h" +#include "stm32_usbhost_m3m4_v1.h" #if defined(CONFIG_STM32_USBHOST) && defined(CONFIG_STM32_OTGHS) diff --git a/arch/arm/src/stm32/stm32_fdcan.h b/arch/arm/src/common/stm32/stm32_pm.h similarity index 58% rename from arch/arm/src/stm32/stm32_fdcan.h rename to arch/arm/src/common/stm32/stm32_pm.h index f157213828d..f9bdebd9f60 100644 --- a/arch/arm/src/stm32/stm32_fdcan.h +++ b/arch/arm/src/common/stm32/stm32_pm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_fdcan.h + * arch/arm/src/common/stm32/stm32_pm.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_FDCAN_H -#define __ARCH_ARM_SRC_STM32_STM32_FDCAN_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_PM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_PM_H /**************************************************************************** * Included Files @@ -29,33 +29,25 @@ #include -#include "chip.h" -#include "hardware/stm32_fdcan.h" +#include -#include +#include "chip.h" +#include "arm_internal.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Port numbers for use with stm32_fdcan_initialize() */ - -#define FDCAN1 1 -#define FDCAN2 2 -#define FDCAN3 3 - /**************************************************************************** * Public Types ****************************************************************************/ -#ifndef __ASSEMBLY__ - /**************************************************************************** * Public Data ****************************************************************************/ -#undef EXTERN -#if defined(__cplusplus) +#ifndef __ASSEMBLY__ +#ifdef __cplusplus #define EXTERN extern "C" extern "C" { @@ -67,48 +59,69 @@ extern "C" * Public Function Prototypes ****************************************************************************/ -#ifdef CONFIG_STM32_FDCAN_CHARDRIVER - /**************************************************************************** - * Name: stm32_fdcaninitialize + * Name: stm32_pmstop * * Description: - * Initialize the selected FDCAN port + * Enter STOP mode. * * Input Parameters: - * Port number (for hardware that has multiple FDCAN interfaces) + * lpds - true: To further reduce power consumption in Stop mode, put the + * internal voltage regulator in low-power mode using the LPDS bit + * of the Power control register (PWR_CR). * * Returned Value: - * Valid FDCAN device structure reference on success; a NULL on failure + * Zero means that the STOP was successfully entered and the system has + * been re-awakened. The internal voltage regulator is back to its + * original state. Otherwise, STOP mode did not occur and a negated + * errno value is returned to indicate the cause of the failure. * ****************************************************************************/ -struct can_dev_s *stm32_fdcaninitialize(int port); -#endif - -#ifdef CONFIG_STM32_FDCAN_SOCKET +int stm32_pmstop(bool lpds); /**************************************************************************** - * Name: stm32_fdcansockinitialize + * Name: stm32_pmstandby * * Description: - * Initialize the selected FDCAN port as SocketCAN interface + * Enter STANDBY mode. * * Input Parameters: - * Port number (for hardware that has multiple FDCAN interfaces) + * None * * Returned Value: - * OK on success; Negated errno on failure. + * On success, this function will not return (STANDBY mode can only be + * terminated with a reset event). Otherwise, STANDBY mode did not occur + * and a negated errno value is returned to indicate the cause of the + * failure. * ****************************************************************************/ -int stm32_fdcansockinitialize(int port); -#endif +int stm32_pmstandby(void); + +/**************************************************************************** + * Name: stm32_pmsleep + * + * Description: + * Enter SLEEP mode. + * + * Input Parameters: + * sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is + * executed, the MCU enters Sleep mode as soon as it + * exits the lowest priority ISR. + * - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep + * mode as soon as WFI or WFE instruction is executed. + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_pmsleep(bool sleeponexit); #undef EXTERN -#if defined(__cplusplus) +#ifdef __cplusplus } #endif - #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_FDCAN_H */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_PM_H */ diff --git a/arch/arm/src/stm32/stm32_pminitialize.c b/arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c similarity index 97% rename from arch/arm/src/stm32/stm32_pminitialize.c rename to arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c index 2f9883b2123..6120feeb7c4 100644 --- a/arch/arm/src/stm32/stm32_pminitialize.c +++ b/arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pminitialize.c + * arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_pmsleep.c b/arch/arm/src/common/stm32/stm32_pmsleep_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_pmsleep.c rename to arch/arm/src/common/stm32/stm32_pmsleep_m3m4_v1.c index 5f78cc86268..24113447340 100644 --- a/arch/arm/src/stm32/stm32_pmsleep.c +++ b/arch/arm/src/common/stm32/stm32_pmsleep_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pmsleep.c + * arch/arm/src/common/stm32/stm32_pmsleep_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_pmstandby.c b/arch/arm/src/common/stm32/stm32_pmstandby_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_pmstandby.c rename to arch/arm/src/common/stm32/stm32_pmstandby_m3m4_v1.c index d8b9825aed5..71195ed4bc5 100644 --- a/arch/arm/src/stm32/stm32_pmstandby.c +++ b/arch/arm/src/common/stm32/stm32_pmstandby_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pmstandby.c + * arch/arm/src/common/stm32/stm32_pmstandby_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_pmstop.c b/arch/arm/src/common/stm32/stm32_pmstop_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_pmstop.c rename to arch/arm/src/common/stm32/stm32_pmstop_m3m4_v1.c index 9acf05990f9..82ce0a60bc0 100644 --- a/arch/arm/src/stm32/stm32_pmstop.c +++ b/arch/arm/src/common/stm32/stm32_pmstop_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pmstop.c + * arch/arm/src/common/stm32/stm32_pmstop_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_pulsecount.h b/arch/arm/src/common/stm32/stm32_pulsecount.h similarity index 87% rename from arch/arm/src/stm32/stm32_pulsecount.h rename to arch/arm/src/common/stm32/stm32_pulsecount.h index 20ccf3608fe..ec76dfe48e4 100644 --- a/arch/arm/src/stm32/stm32_pulsecount.h +++ b/arch/arm/src/common/stm32/stm32_pulsecount.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pulsecount.h + * arch/arm/src/common/stm32/stm32_pulsecount.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_PULSECOUNT_H -#define __ARCH_ARM_SRC_STM32_STM32_PULSECOUNT_H +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PULSECOUNT_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PULSECOUNT_H /**************************************************************************** * Included Files @@ -36,4 +36,4 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer); -#endif /* __ARCH_ARM_SRC_STM32_STM32_PULSECOUNT_H */ +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PULSECOUNT_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pulsecount.c b/arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_pulsecount.c rename to arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c index e644f31003f..e64d5be88fe 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pulsecount.c +++ b/arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pulsecount.c + * arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_pulsecount.c b/arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c similarity index 99% rename from arch/arm/src/stm32/stm32_pulsecount.c rename to arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c index c8aea22c4e1..d73a83d0022 100644 --- a/arch/arm/src/stm32/stm32_pulsecount.c +++ b/arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pulsecount.c + * arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_pwm.h b/arch/arm/src/common/stm32/stm32_pwm.h new file mode 100644 index 00000000000..c2a9a907897 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_pwm.h @@ -0,0 +1,42 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_pwm.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PWM_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PWM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) +# include "stm32_pwm_m0_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) +# include "stm32_pwm_m3m4_v1v2v3.h" +#else +# error "Unsupported STM32 PWM" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PWM_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwm.c b/arch/arm/src/common/stm32/stm32_pwm_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_pwm.c rename to arch/arm/src/common/stm32/stm32_pwm_m0_v1.c index 0710973de1b..cf7e6a3b238 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwm.c +++ b/arch/arm/src/common/stm32/stm32_pwm_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pwm.c + * arch/arm/src/common/stm32/stm32_pwm_m0_v1.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwm.h b/arch/arm/src/common/stm32/stm32_pwm_m0_v1.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_pwm.h rename to arch/arm/src/common/stm32/stm32_pwm_m0_v1.h index fc5beb4482c..eafff64985f 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwm.h +++ b/arch/arm/src/common/stm32/stm32_pwm_m0_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pwm.h + * arch/arm/src/common/stm32/stm32_pwm_m0_v1.h * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. @@ -34,8 +34,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWM_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V3_H /* The STM32F0L0G0 does not have dedicated PWM hardware. Rather, pulsed * output control is a capability of the STM32F0L0G0 timers. The logic in @@ -560,4 +560,4 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); #endif /* CONFIG_STM32_TIMx_PWM */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V3_H */ diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.c similarity index 99% rename from arch/arm/src/stm32/stm32_pwm.c rename to arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.c index 4b7d1378d82..17fff3b6e3e 100644 --- a/arch/arm/src/stm32/stm32_pwm.c +++ b/arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pwm.c + * arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_pwm.h b/arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.h similarity index 99% rename from arch/arm/src/stm32/stm32_pwm.h rename to arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.h index f2f7191bcf0..032a0410d40 100644 --- a/arch/arm/src/stm32/stm32_pwm.h +++ b/arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pwm.h + * arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_PWM_H -#define __ARCH_ARM_SRC_STM32_STM32_PWM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V1V2V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V1V2V3_H /* The STM32 does not have dedicated PWM hardware. Rather, pulsed output * control is a capability of the STM32 timers. The logic in this file @@ -1175,4 +1175,4 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_PWM */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_PWM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V1V2V3_H */ diff --git a/arch/arm/src/stm32/stm32_pwr.h b/arch/arm/src/common/stm32/stm32_pwr.h similarity index 94% rename from arch/arm/src/stm32/stm32_pwr.h rename to arch/arm/src/common/stm32/stm32_pwr.h index 141f81a3609..f7d0ec2b909 100644 --- a/arch/arm/src/stm32/stm32_pwr.h +++ b/arch/arm/src/common/stm32/stm32_pwr.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pwr.h + * arch/arm/src/common/stm32/stm32_pwr.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_PWR_H -#define __ARCH_ARM_SRC_STM32_STM32_PWR_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_PWR_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_PWR_H /**************************************************************************** * Included Files @@ -30,29 +30,17 @@ #include #include +#include #include "chip.h" #include "hardware/stm32_pwr.h" /**************************************************************************** - * Pre-processor Definitions + * Public Types ****************************************************************************/ #ifndef __ASSEMBLY__ -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - /* Identify MCU-specific wakeup pin. * Different STM32 parts support differing numbers of wakeup pins. */ @@ -68,6 +56,15 @@ enum stm32_pwr_wupin_e * Public Function Prototypes ****************************************************************************/ +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + /**************************************************************************** * Name: stm32_pwr_enablesdadc * @@ -112,7 +109,7 @@ void stm32_pwr_initbkp(bool writable); * * Description: * Enables access to the backup domain - * (RTC registers, RTC backup data registers and backup SRAM). + * (RTC registers, RTC backup data registers and backup SRAM). * * NOTE: * Reference counting is used in order to supported nested calls to this @@ -214,8 +211,9 @@ void stm32_pwr_enablebreg(bool region); * ****************************************************************************/ -#ifdef CONFIG_STM32_ENERGYLITE +#if defined(CONFIG_STM32_ENERGYLITE) || defined(CONFIG_STM32_STM32G0) void stm32_pwr_setvos(uint16_t vos); +#endif /**************************************************************************** * Name: stm32_pwr_setpvd @@ -234,6 +232,7 @@ void stm32_pwr_setvos(uint16_t vos); * ****************************************************************************/ +#ifdef CONFIG_STM32_ENERGYLITE void stm32_pwr_setpvd(uint16_t pls); /**************************************************************************** @@ -264,4 +263,5 @@ void stm32_pwr_disablepvd(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_PWR_H */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_PWR_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32g0_pwr.c b/arch/arm/src/common/stm32/stm32_pwr_m0_g0.c similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32g0_pwr.c rename to arch/arm/src/common/stm32/stm32_pwr_m0_g0.c index 0e8b03e12ef..d1627f7fa5f 100644 --- a/arch/arm/src/stm32f0l0g0/stm32g0_pwr.c +++ b/arch/arm/src/common/stm32/stm32_pwr_m0_g0.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32g0_pwr.c + * arch/arm/src/common/stm32/stm32_pwr_m0_g0.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c b/arch/arm/src/common/stm32/stm32_pwr_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c rename to arch/arm/src/common/stm32/stm32_pwr_m0_v1.c index 6516b14f98c..5ff40ed9e66 100644 --- a/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c +++ b/arch/arm/src/common/stm32/stm32_pwr_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c + * arch/arm/src/common/stm32/stm32_pwr_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_pwr.c b/arch/arm/src/common/stm32/stm32_pwr_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_pwr.c rename to arch/arm/src/common/stm32/stm32_pwr_m3m4_v1.c index b55c301cd36..0d2bed7a90f 100644 --- a/arch/arm/src/stm32/stm32_pwr.c +++ b/arch/arm/src/common/stm32/stm32_pwr_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pwr.c + * arch/arm/src/common/stm32/stm32_pwr_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_qencoder.h b/arch/arm/src/common/stm32/stm32_qencoder.h similarity index 84% rename from arch/arm/src/stm32/stm32_qencoder.h rename to arch/arm/src/common/stm32/stm32_qencoder.h index a8c9ff66e00..e82881b3032 100644 --- a/arch/arm/src/stm32/stm32_qencoder.h +++ b/arch/arm/src/common/stm32/stm32_qencoder.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_qencoder.h + * arch/arm/src/common/stm32/stm32_qencoder.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_QENCODER_H -#define __ARCH_ARM_SRC_STM32_STM32_QENCODER_H +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_QENCODER_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_QENCODER_H /**************************************************************************** * Included Files @@ -34,13 +34,13 @@ #ifdef CONFIG_SENSORS_QENCODER /**************************************************************************** - * Included Files + * Pre-processor Definitions ****************************************************************************/ /* Timer devices may be used for different purposes. One special purpose is * as a quadrature encoder input device. If CONFIG_STM32_TIMn is defined - * then the CONFIG_STM32_TIMn_QE must also be defined to indicate that timer - * "n" is intended to be used for as a quadrature encoder. + * then CONFIG_STM32_TIMn_QE indicates that timer "n" is intended to be used + * as a quadrature encoder. */ #ifndef CONFIG_STM32_TIM1 @@ -62,9 +62,7 @@ # undef CONFIG_STM32_TIM8_QE #endif -/* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder (at least - * for the STM32 F4) - */ +/* Basic and small general-purpose timers do not support encoder mode. */ #undef CONFIG_STM32_TIM6_QE #undef CONFIG_STM32_TIM7_QE @@ -74,9 +72,12 @@ #undef CONFIG_STM32_TIM12_QE #undef CONFIG_STM32_TIM13_QE #undef CONFIG_STM32_TIM14_QE +#undef CONFIG_STM32_TIM15_QE +#undef CONFIG_STM32_TIM16_QE +#undef CONFIG_STM32_TIM17_QE /**************************************************************************** - * Included Files + * Public Function Prototypes ****************************************************************************/ /**************************************************************************** @@ -84,12 +85,11 @@ * * Description: * Initialize a quadrature encoder interface. This function must be called - * from board-specific logic.. + * from board-specific logic. * * Input Parameters: * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. 'tim' must be an element of - * {1,2,3,4,5,8} + * tim - The timer number to use. * * Returned Value: * Zero on success; A negated errno value is returned on failure. @@ -118,4 +118,5 @@ int stm32_qe_index_init(int tim, uint32_t gpio); #endif #endif /* CONFIG_SENSORS_QENCODER */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_QENCODER_H */ + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_QENCODER_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_qencoder.c b/arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_qencoder.c rename to arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c index 65cc9945546..e88ff33418d 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_qencoder.c +++ b/arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_qencoder.c + * arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_qencoder.c b/arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c similarity index 99% rename from arch/arm/src/stm32/stm32_qencoder.c rename to arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c index 1c0a9921b4e..f5c4bea0d22 100644 --- a/arch/arm/src/stm32/stm32_qencoder.c +++ b/arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_qencoder.c + * arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwr.h b/arch/arm/src/common/stm32/stm32_rcc.h similarity index 51% rename from arch/arm/src/stm32f0l0g0/stm32_pwr.h rename to arch/arm/src/common/stm32/stm32_rcc.h index 1562b607328..c2c57a6a0b6 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwr.h +++ b/arch/arm/src/common/stm32/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pwr.h + * arch/arm/src/common/stm32/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_RCC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_RCC_H /**************************************************************************** * Included Files @@ -29,12 +29,10 @@ #include -#include - +#include "arm_internal.h" #include "chip.h" -#include "hardware/stm32_pwr.h" -#ifdef CONFIG_STM32_PWR +#include "hardware/stm32_rcc.h" /**************************************************************************** * Pre-processor Definitions @@ -52,177 +50,178 @@ extern "C" #endif /**************************************************************************** - * Public Types + * Inline Functions ****************************************************************************/ -/* Identify MCU-specific wakeup pin. Different STM32 parts support differing - * numbers of wakeup pins. - */ +/**************************************************************************** + * Name: stm32_mco1config + * + * Description: + * Selects the clock source to output on MCO1 pin (PA8). PA8 should be + * configured in alternate function mode. + * + ****************************************************************************/ -enum stm32_pwr_wupin_e +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +static inline void stm32_mco1config(uint32_t source, uint32_t div) { - PWR_WUPIN_1 = 0, /* Wake-up pin 1 (all parts) */ - PWR_WUPIN_2, /* Wake-up pin 2 */ - PWR_WUPIN_3 /* Wake-up pin 3 */ -}; + uint32_t regval; + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_MCO1_MASK | RCC_CFGR_MCO1PRE_MASK); + regval |= (source | div); + putreg32(regval, STM32_RCC_CFGR); +} +#endif /**************************************************************************** - * Public Functions Prototypes + * Name: stm32_mcoconfig + * + * Description: + * Selects the clock source to output on MC pin (PA8) for stm32f10xxx. + * PA8 should be configured in alternate function mode. + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_CONNECTIVITYLINE) +static inline void stm32_mcoconfig(uint32_t source) +{ + uint32_t regval; + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_MCO_MASK); + regval |= (source & RCC_CFGR_MCO_MASK); + putreg32(regval, STM32_RCC_CFGR); +} +#endif + +/**************************************************************************** + * Name: stm32_mcodivconfig + * + * Description: + * Selects the clock source to output and clock divider on MC pin (PA4) for + * stm32l1xxx. PA4 should be configured in alternate function mode. + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) +static inline void stm32_mcodivconfig(uint32_t source, uint32_t divider) +{ + uint32_t regval; + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_MCOSEL_MASK); + regval |= (source & RCC_CFGR_MCOSEL_MASK); + regval &= ~(RCC_CFGR_MCOPRE_MASK); + regval |= (divider & RCC_CFGR_MCOPRE_MASK); + putreg32(regval, STM32_RCC_CFGR); +} +#endif + +/**************************************************************************** + * Name: stm32_mco2config + * + * Description: + * Selects the clock source to output on MCO2 pin (PC9). PC9 should be + * configured in alternate function mode. + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +static inline void stm32_mco2config(uint32_t source, uint32_t div) +{ + uint32_t regval; + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_MCO2_MASK | RCC_CFGR_MCO2PRE_MASK); + regval |= (source | div); + putreg32(regval, STM32_RCC_CFGR); +} +#endif + +/**************************************************************************** + * Public Function Prototypes ****************************************************************************/ /**************************************************************************** - * Name: stm32_pwr_initbkp + * Name: stm32_clockconfig * * Description: - * Insures the referenced count access to the backup domain (RTC registers, - * RTC backup data registers and backup SRAM is consistent with the HW - * state without relying on a variable. + * Called to initialize the STM32F0XX. + * This does whatever setup is needed to put the MCU in a usable state. + * This includes the initialization of clocking using the settings + * in board.h. * - * NOTE: This function should only be called by SoC Start up code. + ****************************************************************************/ + +void stm32_clockconfig(void); + +/**************************************************************************** + * Name: stm32_board_clockconfig + * + * Description: + * Any STM32 board may replace the standard board clock configuration logic + * with its own custom clock configuration logic. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG +void stm32_board_clockconfig(void); +#endif + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings after low-power + * modes. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void); +#endif + +/**************************************************************************** + * Name: stm32_rcc_enablelse + * + * Description: + * Enable the External Low-Speed (LSE) Oscillator. * * Input Parameters: - * writable - set the initial state of the enable and the - * bkp_writable_counter + * None * * Returned Value: * None * ****************************************************************************/ -void stm32_pwr_initbkp(bool writable); +void stm32_rcc_enablelse(void); /**************************************************************************** - * Name: stm32_pwr_enablebkp + * Name: stm32_rcc_enablelsi * * Description: - * Enables access to the backup domain (RTC registers, RTC backup data - * registers and backup SRAM). - * - * NOTE: - * Reference counting is used in order to supported nested calls to this - * function. As a consequence, every call to stm32_pwr_enablebkp(true) - * must be followed by a matching call to stm32_pwr_enablebkp(false). - * - * Input Parameters: - * writable - True: enable ability to write to backup domain registers - * - * Returned Value: - * None + * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32_pwr_enablebkp(bool writable); +void stm32_rcc_enablelsi(void); /**************************************************************************** - * Name: stm32_pwr_enablewkup + * Name: stm32_rcc_disablelsi * * Description: - * Enables the WKUP pin. - * - * Input Parameters: - * wupin - Selects the WKUP pin to enable/disable - * wupon - state to set it to - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. The only cause of failure is if the selected MCU does not - * support the requested wakeup pin. + * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -int stm32_pwr_enablewkup(enum stm32_pwr_wupin_e wupin, bool wupon); - -/**************************************************************************** - * Name: stm32_pwr_getsbf - * - * Description: - * Return the standby flag. - * - ****************************************************************************/ - -bool stm32_pwr_getsbf(void); - -/**************************************************************************** - * Name: stm32_pwr_getwuf - * - * Description: - * Return the wakeup flag. - * - ****************************************************************************/ - -bool stm32_pwr_getwuf(void); - -/**************************************************************************** - * Name: stm32_pwr_setvos - * - * Description: - * Set voltage scaling for EnergyLite devices. - * - * Input Parameters: - * vos - Properly aligned voltage scaling select bits for the PWR_CR - * register. - * - * Returned Value: - * None - * - * Assumptions: - * At present, this function is called only from initialization logic. If - * used for any other purpose that protection to assure that its operation - * is atomic will be required. - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_ENERGYLITE) || defined(CONFIG_STM32_STM32G0) -void stm32_pwr_setvos(uint16_t vos); -#endif /* CONFIG_STM32_ENERGYLITE || CONFIG_STM32_STM32G0 */ - -/**************************************************************************** - * Name: stm32_pwr_setpvd - * - * Description: - * Sets power voltage detector for EnergyLite devices. - * - * Input Parameters: - * pls - PVD level - * - * Returned Value: - * None - * - * Assumptions: - * At present, this function is called only from initialization logic. - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_ENERGYLITE) -void stm32_pwr_setpvd(uint16_t pls); - -/**************************************************************************** - * Name: stm32_pwr_enablepvd - * - * Description: - * Enable the Programmable Voltage Detector - * - ****************************************************************************/ - -void stm32_pwr_enablepvd(void); - -/**************************************************************************** - * Name: stm32_pwr_disablepvd - * - * Description: - * Disable the Programmable Voltage Detector - * - ****************************************************************************/ - -void stm32_pwr_disablepvd(void); - -#endif /* CONFIG_STM32_ENERGYLITE */ +void stm32_rcc_disablelsi(void); #undef EXTERN #if defined(__cplusplus) } #endif - #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32_PWR */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_RCC_H */ diff --git a/arch/arm/src/stm32/stm32_rng.c b/arch/arm/src/common/stm32/stm32_rng_m0_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_rng.c rename to arch/arm/src/common/stm32/stm32_rng_m0_v1.c index 9a4c46aaa0b..837ed6ce85e 100644 --- a/arch/arm/src/stm32/stm32_rng.c +++ b/arch/arm/src/common/stm32/stm32_rng_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_rng.c + * arch/arm/src/common/stm32/stm32_rng_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_rng.c b/arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c similarity index 96% rename from arch/arm/src/stm32f0l0g0/stm32_rng.c rename to arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c index 2ccebb1060b..a40caf80bd5 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_rng.c +++ b/arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_rng.c + * arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -158,7 +158,7 @@ static int stm32_rng_interrupt(int irq, void *context, void *arg) rngsr = getreg32(STM32_RNG_SR); if ((rngsr & (RNG_SR_SEIS | RNG_SR_CEIS)) /* Check for error bits */ - || !(rngsr & RNG_SR_DRDY)) /* Data ready must be set */ + || !(rngsr & RNG_SR_DRDY)) /* Data ready must be set */ { /* This random value is not valid, we will try again. */ @@ -172,8 +172,8 @@ static int stm32_rng_interrupt(int irq, void *context, void *arg) * RNGEN bit should not be used, but saved for comparison with the next * generated random number. Each subsequent generated random number has to * be compared with the previously generated number. The test fails if any - * two compared numbers are equal - * (continuous random number generator test). + * two compared numbers are equal (continuous random number generator + * test). */ if (g_rngdev.rd_first) @@ -223,8 +223,8 @@ static int stm32_rng_interrupt(int irq, void *context, void *arg) * Name: stm32_rng_read ****************************************************************************/ -static ssize_t stm32_rng_read(struct file *filep, - char *buffer, size_t buflen) +static ssize_t stm32_rng_read(struct file *filep, char *buffer, + size_t buflen) { int ret; @@ -234,7 +234,7 @@ static ssize_t stm32_rng_read(struct file *filep, return ret; } - /* We've got the semaphore. */ + /* We've got the mutex. */ /* Reset the operation semaphore with 0 for blocking until the * buffer is filled from interrupts. diff --git a/arch/arm/src/stm32/stm32_rtc.h b/arch/arm/src/common/stm32/stm32_rtc.h similarity index 96% rename from arch/arm/src/stm32/stm32_rtc.h rename to arch/arm/src/common/stm32/stm32_rtc.h index 3df1ac02a7b..96c8e4f5b8b 100644 --- a/arch/arm/src/stm32/stm32_rtc.h +++ b/arch/arm/src/common/stm32/stm32_rtc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_rtc.h + * arch/arm/src/common/stm32/stm32_rtc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -24,11 +24,13 @@ * Included Files ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_RTC_H -#define __ARCH_ARM_SRC_STM32_STM32_RTC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_RTC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_RTC_H #include +#ifdef CONFIG_STM32_HAVE_IP_RTC_M3M4_V1 + #include "chip.h" /* The STM32 F1 has a simple battery-backed counter for its RTC and has a @@ -222,4 +224,6 @@ struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void); } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_RTC_H */ + +#endif /* CONFIG_STM32_HAVE_IP_RTC_M3M4_V1 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_RTC_H */ diff --git a/arch/arm/src/stm32/stm32_rtc_lowerhalf.c b/arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c similarity index 99% rename from arch/arm/src/stm32/stm32_rtc_lowerhalf.c rename to arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c index 69c59d6f887..e8c1c75fc9d 100644 --- a/arch/arm/src/stm32/stm32_rtc_lowerhalf.c +++ b/arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_rtc_lowerhalf.c + * arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_f4.c similarity index 99% rename from arch/arm/src/stm32/stm32f40xxx_rtcc.c rename to arch/arm/src/common/stm32/stm32_rtcc_m3m4_f4.c index 6917d43fd34..9dff0b4bcca 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c +++ b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_f4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f40xxx_rtcc.c + * arch/arm/src/common/stm32/stm32_rtcc_m3m4_f4.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32l15xxx_rtcc.c b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_l1.c similarity index 99% rename from arch/arm/src/stm32/stm32l15xxx_rtcc.c rename to arch/arm/src/common/stm32/stm32_rtcc_m3m4_l1.c index 3a37110089d..06d729c437b 100644 --- a/arch/arm/src/stm32/stm32l15xxx_rtcc.c +++ b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_l1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32l15xxx_rtcc.c + * arch/arm/src/common/stm32/stm32_rtcc_m3m4_l1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_rtcc.c b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_rtcc.c rename to arch/arm/src/common/stm32/stm32_rtcc_m3m4_v1.c index cd0e55db467..fac37d3b563 100644 --- a/arch/arm/src/stm32/stm32_rtcc.c +++ b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_rtcc.c + * arch/arm/src/common/stm32/stm32_rtcc_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_rtcounter.c b/arch/arm/src/common/stm32/stm32_rtcounter_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_rtcounter.c rename to arch/arm/src/common/stm32/stm32_rtcounter_m3m4_v1.c index a93fcb4f890..6f5259e4498 100644 --- a/arch/arm/src/stm32/stm32_rtcounter.c +++ b/arch/arm/src/common/stm32/stm32_rtcounter_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_rtcounter.c + * arch/arm/src/common/stm32/stm32_rtcounter_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_sdadc.h b/arch/arm/src/common/stm32/stm32_sdadc.h new file mode 100644 index 00000000000..f69f80d1d56 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_sdadc.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_sdadc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDADC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDADC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_SDADC_M3M4_V1) +# include "stm32_sdadc_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_sdadc" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDADC_H */ diff --git a/arch/arm/src/stm32/stm32_sdadc.c b/arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_sdadc.c rename to arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c index 783dd03c6cc..23e5fc8a33f 100644 --- a/arch/arm/src/stm32/stm32_sdadc.c +++ b/arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_sdadc.c + * arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2015-2017 Gregory Nutt. All rights reserved. @@ -64,8 +64,10 @@ #include "chip.h" #include "stm32.h" #include "stm32_dma.h" +#include "stm32_sdadc_m3m4_v1.h" #include "stm32_pwr.h" -#include "stm32_sdadc.h" +#include "stm32_dma.h" +#include "stm32_sdadc_m3m4_v1.h" #ifdef CONFIG_STM32_SDADC diff --git a/arch/arm/src/stm32/stm32_sdadc.h b/arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.h similarity index 98% rename from arch/arm/src/stm32/stm32_sdadc.h rename to arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.h index 75d474efa56..6906d43f07c 100644 --- a/arch/arm/src/stm32/stm32_sdadc.h +++ b/arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_sdadc.h + * arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.h * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2015 Gregory Nutt. All rights reserved. @@ -37,8 +37,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_SDADC_H -#define __ARCH_ARM_SRC_STM32_STM32_SDADC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_SDADC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_SDADC_H /**************************************************************************** * Included Files @@ -428,4 +428,4 @@ struct adc_dev_s *stm32_sdadcinitialize(int intf, #endif /* CONFIG_STM32_SDADC1 || CONFIG_STM32_SDADC2 || * CONFIG_STM32_SDADC3 */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_SDADC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_SDADC_H */ diff --git a/arch/arm/src/common/stm32/stm32_sdio.h b/arch/arm/src/common/stm32/stm32_sdio.h new file mode 100644 index 00000000000..8dc71bb2709 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_sdio.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_sdio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDIO_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1) +# include "stm32_sdio_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_sdio" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDIO_H */ diff --git a/arch/arm/src/stm32/stm32_sdio.c b/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_sdio.c rename to arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c index 5d6e5cfc441..3387e111c4e 100644 --- a/arch/arm/src/stm32/stm32_sdio.c +++ b/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_sdio.c + * arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -49,7 +49,9 @@ #include "arm_internal.h" #include "stm32.h" #include "stm32_dma.h" -#include "stm32_sdio.h" +#include "stm32_sdio_m3m4_v1.h" +#include "stm32_dma.h" +#include "stm32_sdio_m3m4_v1.h" #ifdef CONFIG_STM32_SDIO @@ -107,7 +109,7 @@ # ifndef CONFIG_STM32_SDIO_DMAPRIO # if defined(CONFIG_STM32_STM32F10XX) # define CONFIG_STM32_SDIO_DMAPRIO DMA_CCR_PRIMED -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define CONFIG_STM32_SDIO_DMAPRIO DMA_SCR_PRIVERYHI # else # error "Unknown STM32 DMA" @@ -117,7 +119,7 @@ # if (CONFIG_STM32_SDIO_DMAPRIO & ~DMA_CCR_PL_MASK) != 0 # error "Illegal value for CONFIG_STM32_SDIO_DMAPRIO" # endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # if (CONFIG_STM32_SDIO_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 # error "Illegal value for CONFIG_STM32_SDIO_DMAPRIO" # endif @@ -199,7 +201,7 @@ /* STM32 F4 stream configuration register (SCR) settings. */ -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define SDIO_RXDMA32_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_P2M|DMA_SCR_MINC | \ DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \ CONFIG_STM32_SDIO_DMAPRIO | DMA_SCR_PBURST_INCR4 | \ @@ -219,7 +221,7 @@ #if defined(CONFIG_STM32_STM32F10XX) # define SDIO_DMACHAN DMACHAN_SDIO -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define SDIO_DMACHAN DMAMAP_SDIO #else # error "Unknown STM32 DMA" diff --git a/arch/arm/src/stm32/stm32_sdio.h b/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.h similarity index 93% rename from arch/arm/src/stm32/stm32_sdio.h rename to arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.h index d74b3fe3989..8ffd42b7eec 100644 --- a/arch/arm/src/stm32/stm32_sdio.h +++ b/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_sdio.h + * arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,14 +20,17 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_SDIO_H -#define __ARCH_ARM_SRC_STM32_STM32_SDIO_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_SDIO_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_SDIO_H /**************************************************************************** * Included Files ****************************************************************************/ #include + +#ifdef CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1 + #include #include @@ -133,4 +136,6 @@ void sdio_set_sdio_card_isr(struct sdio_dev_s *dev, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_SDIO_H */ + +#endif /* CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_SDIO_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c b/arch/arm/src/common/stm32/stm32_serial_m0_v3.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_serial_v1.c rename to arch/arm/src/common/stm32/stm32_serial_m0_v3.c index 444e4888721..504e31b9c49 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c +++ b/arch/arm/src/common/stm32/stm32_serial_m0_v3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_serial_v1.c + * arch/arm/src/common/stm32/stm32_serial_m0_v3.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c b/arch/arm/src/common/stm32/stm32_serial_m0_v4.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_serial_v2.c rename to arch/arm/src/common/stm32/stm32_serial_m0_v4.c index 0d9d208c67f..feb3307bc6d 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c +++ b/arch/arm/src/common/stm32/stm32_serial_m0_v4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_serial_v2.c + * arch/arm/src/common/stm32/stm32_serial_m0_v4.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c similarity index 99% rename from arch/arm/src/stm32/stm32_serial.c rename to arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c index 09cbe58c2fc..c5b3f861d10 100644 --- a/arch/arm/src/stm32/stm32_serial.c +++ b/arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_serial.c + * arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_spi.h b/arch/arm/src/common/stm32/stm32_spi.h similarity index 94% rename from arch/arm/src/stm32/stm32_spi.h rename to arch/arm/src/common/stm32/stm32_spi.h index 13a48fb92ce..9e861bcc690 100644 --- a/arch/arm/src/stm32/stm32_spi.h +++ b/arch/arm/src/common/stm32/stm32_spi.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_spi.h + * arch/arm/src/common/stm32/stm32_spi.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_SPI_H -#define __ARCH_ARM_SRC_STM32_STM32_SPI_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_SPI_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_SPI_H /**************************************************************************** * Included Files @@ -29,6 +29,13 @@ #include +#if !(defined(CONFIG_STM32_HAVE_IP_SPI_V1) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V2) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V3) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V4)) +# error "Unsupported STM32 SPI" +#endif + #include #include "chip.h" @@ -206,4 +213,4 @@ int stm32_spi6register(struct spi_dev_s *dev, spi_mediachange_t callback, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_SPI_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_SPI_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_spi.c b/arch/arm/src/common/stm32/stm32_spi_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_spi.c rename to arch/arm/src/common/stm32/stm32_spi_m0_v1.c index ae149747b08..9b32cd490f5 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_spi.c +++ b/arch/arm/src/common/stm32/stm32_spi_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_spi.c + * arch/arm/src/common/stm32/stm32_spi_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_spi.c b/arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c similarity index 99% rename from arch/arm/src/stm32/stm32_spi.c rename to arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c index 62b019ce07e..567f79a95fe 100644 --- a/arch/arm/src/stm32/stm32_spi.c +++ b/arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_spi.c + * arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c * * SPDX-License-Identifier: Apache-2.0 * @@ -103,7 +103,7 @@ # elif defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX) || \ defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32G4XXX) # define SPI_DMA_PRIO DMA_CCR_PRIMED -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define SPI_DMA_PRIO DMA_SCR_PRIMED # else # error "Unknown STM32 DMA" @@ -114,7 +114,7 @@ # if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0 # error "Illegal value for CONFIG_SPI_DMAPRIO" # endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # if (SPI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0 # error "Illegal value for CONFIG_SPI_DMAPRIO" # endif @@ -135,7 +135,7 @@ # define SPI_TXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC|DMA_CCR_DIR) # define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS |DMA_CCR_DIR) # define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_DIR) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_16BITS|DMA_SCR_PSIZE_16BITS|DMA_SCR_MINC|DMA_SCR_DIR_P2M) # define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_MINC|DMA_SCR_DIR_P2M) # define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_P2M) diff --git a/arch/arm/src/stm32f0l0g0/stm32_start.h b/arch/arm/src/common/stm32/stm32_start.h similarity index 91% rename from arch/arm/src/stm32f0l0g0/stm32_start.h rename to arch/arm/src/common/stm32/stm32_start.h index 34691d3ac80..ad9bbda5e31 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_start.h +++ b/arch/arm/src/common/stm32/stm32_start.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_start.h + * arch/arm/src/common/stm32/stm32_start.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_START_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_START_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_START_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_START_H /**************************************************************************** * Included Files @@ -61,4 +61,4 @@ void stm32_boardinitialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_START_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_START_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_start.c b/arch/arm/src/common/stm32/stm32_start_m0_v1.c similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_start.c rename to arch/arm/src/common/stm32/stm32_start_m0_v1.c index 9b1449d4fb7..b2585f49bc6 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_start.c +++ b/arch/arm/src/common/stm32/stm32_start_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_start.c + * arch/arm/src/common/stm32/stm32_start_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_start.c b/arch/arm/src/common/stm32/stm32_start_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_start.c rename to arch/arm/src/common/stm32/stm32_start_m3m4_v1.c index e4abdb7d3e9..ad74f104e3c 100644 --- a/arch/arm/src/stm32/stm32_start.c +++ b/arch/arm/src/common/stm32/stm32_start_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_start.c + * arch/arm/src/common/stm32/stm32_start_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_syscfg.h b/arch/arm/src/common/stm32/stm32_syscfg.h similarity index 90% rename from arch/arm/src/stm32/stm32_syscfg.h rename to arch/arm/src/common/stm32/stm32_syscfg.h index 74d049711a6..1e95d770342 100644 --- a/arch/arm/src/stm32/stm32_syscfg.h +++ b/arch/arm/src/common/stm32/stm32_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_syscfg.h + * arch/arm/src/common/stm32/stm32_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_SYSCFG_H -#define __ARCH_ARM_SRC_STM32_STM32_SYSCFG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_SYSCFG_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_SYSCFG_H /**************************************************************************** * Included Files @@ -50,4 +50,4 @@ * Pre-processor Definitions ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_STM32_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_SYSCFG_H */ diff --git a/arch/arm/src/stm32/stm32_tickless.c b/arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_tickless.c rename to arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c index 3cd076bf1d7..1e49c2a3cb3 100644 --- a/arch/arm/src/stm32/stm32_tickless.c +++ b/arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_tickless.c + * arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2016-2017 Gregory Nutt. All rights reserved. diff --git a/arch/arm/src/common/stm32/stm32_tim.h b/arch/arm/src/common/stm32/stm32_tim.h new file mode 100644 index 00000000000..77d884e0672 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_tim.h @@ -0,0 +1,42 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_tim.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_TIM_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_TIM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) +# include "stm32_tim_m0_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) +# include "stm32_tim_m3m4_v1v2v3.h" +#else +# error "Unsupported STM32 TIM" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_TIM_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_tim.c b/arch/arm/src/common/stm32/stm32_tim_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_tim.c rename to arch/arm/src/common/stm32/stm32_tim_m0_v1.c index 48a549aa415..9401a884a27 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_tim.c +++ b/arch/arm/src/common/stm32/stm32_tim_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_tim.c + * arch/arm/src/common/stm32/stm32_tim_m0_v1.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. diff --git a/arch/arm/src/stm32f0l0g0/stm32_tim.h b/arch/arm/src/common/stm32/stm32_tim_m0_v1.h similarity index 97% rename from arch/arm/src/stm32f0l0g0/stm32_tim.h rename to arch/arm/src/common/stm32/stm32_tim_m0_v1.h index ba9d7c7fbc4..07c0ef1f7e5 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_tim.h +++ b/arch/arm/src/common/stm32/stm32_tim_m0_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_tim.h + * arch/arm/src/common/stm32/stm32_tim_m0_v1.h * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. @@ -34,8 +34,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_TIM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V3_H /**************************************************************************** * Included Files @@ -230,4 +230,4 @@ int stm32_timer_initialize(const char *devpath, int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_TIM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V3_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c b/arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c rename to arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c index dbb558fa81b..356a3e9e6c7 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c +++ b/arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c + * arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c similarity index 99% rename from arch/arm/src/stm32/stm32_tim.c rename to arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c index 71774e2898b..65a9a062d05 100644 --- a/arch/arm/src/stm32/stm32_tim.c +++ b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_tim.c + * arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_tim.h b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h similarity index 96% rename from arch/arm/src/stm32/stm32_tim.h rename to arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h index 6e01e6693d7..9bd99fb862f 100644 --- a/arch/arm/src/stm32/stm32_tim.h +++ b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_tim.h + * arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32_STM32_TIM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V1V2V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V1V2V3_H /**************************************************************************** * Included Files @@ -222,4 +222,4 @@ int stm32_timer_initialize(const char *devpath, int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_TIM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V1V2V3_H */ diff --git a/arch/arm/src/stm32/stm32_tim_lowerhalf.c b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c similarity index 99% rename from arch/arm/src/stm32/stm32_tim_lowerhalf.c rename to arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c index 14407bdc4f7..25d5b631926 100644 --- a/arch/arm/src/stm32/stm32_tim_lowerhalf.c +++ b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_tim_lowerhalf.c + * arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2015 Wail Khemir. All rights reserved. diff --git a/arch/arm/src/stm32f0l0g0/stm32_timerisr.c b/arch/arm/src/common/stm32/stm32_timerisr_armv6m.c similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_timerisr.c rename to arch/arm/src/common/stm32/stm32_timerisr_armv6m.c index 9a92038c401..a3136b86579 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_timerisr.c +++ b/arch/arm/src/common/stm32/stm32_timerisr_armv6m.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_timerisr.c + * arch/arm/src/common/stm32/stm32_timerisr_armv6m.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_timerisr.c b/arch/arm/src/common/stm32/stm32_timerisr_armv7m.c similarity index 99% rename from arch/arm/src/stm32/stm32_timerisr.c rename to arch/arm/src/common/stm32/stm32_timerisr_armv7m.c index c4fa9c76fb6..b7f8e713252 100644 --- a/arch/arm/src/stm32/stm32_timerisr.c +++ b/arch/arm/src/common/stm32/stm32_timerisr_armv7m.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_timerisr.c + * arch/arm/src/common/stm32/stm32_timerisr_armv7m.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_uart.h b/arch/arm/src/common/stm32/stm32_uart.h new file mode 100644 index 00000000000..29de62701fe --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_uart.h @@ -0,0 +1,46 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_uart.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UART_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if defined(CONFIG_ARCH_ARMV6M) +# if defined(CONFIG_STM32_HAVE_IP_USART_V3) || \ + defined(CONFIG_STM32_HAVE_IP_USART_V4) +# include "stm32_uart_m0_v1.h" +# else +# error "Unsupported STM32 UART core for M0" +# endif +#elif defined(CONFIG_STM32_HAVE_IP_USART_V1) || \ + defined(CONFIG_STM32_HAVE_IP_USART_V2) || \ + defined(CONFIG_STM32_HAVE_IP_USART_V3) || \ + defined(CONFIG_STM32_HAVE_IP_USART_V4) +# include "stm32_uart_m3m4_v1v2.h" +#else +# error "Unsupported STM32 UART" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UART_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_uart.h b/arch/arm/src/common/stm32/stm32_uart_m0_v1.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_uart.h rename to arch/arm/src/common/stm32/stm32_uart_m0_v1.h index 9ebcefc8fc5..5844f46e084 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_uart.h +++ b/arch/arm/src/common/stm32/stm32_uart_m0_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_uart.h + * arch/arm/src/common/stm32/stm32_uart_m0_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_M0_H /**************************************************************************** * Included Files @@ -449,4 +449,4 @@ void stm32_serial_dma_poll(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_M0_H */ diff --git a/arch/arm/src/stm32/stm32_uart.h b/arch/arm/src/common/stm32/stm32_uart_m3m4_v1v2.h similarity index 96% rename from arch/arm/src/stm32/stm32_uart.h rename to arch/arm/src/common/stm32/stm32_uart_m3m4_v1v2.h index 3723edd4c1e..c4e20a1a781 100644 --- a/arch/arm/src/stm32/stm32_uart.h +++ b/arch/arm/src/common/stm32/stm32_uart_m3m4_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_uart.h + * arch/arm/src/common/stm32/stm32_uart_m3m4_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32_STM32_UART_H -#define __ARCH_ARM_STC_STM32_STM32_UART_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_V1V2_H /**************************************************************************** * Included Files @@ -31,23 +31,7 @@ #include #include "chip.h" - -#if defined(CONFIG_STM32_STM32L15XX) -# include "hardware/stm32l15xxx_uart.h" -#elif defined(CONFIG_STM32_STM32F10XX) -# include "hardware/stm32f10xxx_uart.h" -#elif defined(CONFIG_STM32_STM32F20XX) -# include "hardware/stm32f20xxx_uart.h" -#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) -# include "hardware/stm32f30xxx_uart.h" -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "hardware/stm32f40xxx_uart.h" -#elif defined(CONFIG_STM32_STM32G4XXX) -# include "hardware/stm32g4xxxx_uart.h" -#else -# error "Unsupported STM32 UART" -#endif +#include "hardware/stm32_uart.h" /**************************************************************************** * Pre-processor Definitions @@ -665,4 +649,4 @@ void stm32_serial_dma_poll(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_STC_STM32_STM32_UART_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_V1V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_uid.h b/arch/arm/src/common/stm32/stm32_uid.h similarity index 79% rename from arch/arm/src/stm32f0l0g0/stm32_uid.h rename to arch/arm/src/common/stm32/stm32_uid.h index 34661df85de..e925374353e 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_uid.h +++ b/arch/arm/src/common/stm32/stm32_uid.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_uid.h + * arch/arm/src/common/stm32/stm32_uid.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,19 +20,25 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_UID_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_UID_H +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UID_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UID_H /**************************************************************************** * Included Files ****************************************************************************/ +#include + #include /**************************************************************************** * Public Function Prototypes ****************************************************************************/ +#if defined(CONFIG_STM32_HAVE_IP_UID_M0_V1) void stm32_get_uniqueid(uint32_t *uid); +#elif defined(CONFIG_STM32_HAVE_IP_UID_M3M4_V1) +void stm32_get_uniqueid(uint8_t uniqueid[12]); +#endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_UID_H */ \ No newline at end of file +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UID_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_uid.c b/arch/arm/src/common/stm32/stm32_uid_m0_v1.c similarity index 97% rename from arch/arm/src/stm32f0l0g0/stm32_uid.c rename to arch/arm/src/common/stm32/stm32_uid_m0_v1.c index a57b048b8a7..9f9be6610a7 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_uid.c +++ b/arch/arm/src/common/stm32/stm32_uid_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_uid.c + * arch/arm/src/common/stm32/stm32_uid_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_uid.c b/arch/arm/src/common/stm32/stm32_uid_m3m4_v1v2.c similarity index 98% rename from arch/arm/src/stm32/stm32_uid.c rename to arch/arm/src/common/stm32/stm32_uid_m3m4_v1v2.c index fa274e1d62a..9986db93d7c 100644 --- a/arch/arm/src/stm32/stm32_uid.c +++ b/arch/arm/src/common/stm32/stm32_uid_m3m4_v1v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_uid.c + * arch/arm/src/common/stm32/stm32_uid_m3m4_v1v2.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. diff --git a/arch/arm/src/stm32f0l0g0/stm32_usbdev.h b/arch/arm/src/common/stm32/stm32_usbdev.h similarity index 85% rename from arch/arm/src/stm32f0l0g0/stm32_usbdev.h rename to arch/arm/src/common/stm32/stm32_usbdev.h index afa99490451..1d1a989b0d0 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_usbdev.h +++ b/arch/arm/src/common/stm32/stm32_usbdev.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_usbdev.h + * arch/arm/src/common/stm32/stm32_usbdev.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_USBDEV_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_USBDEV_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_USBDEV_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_USBDEV_H /**************************************************************************** * Included Files @@ -34,6 +34,16 @@ #include "chip.h" #include "hardware/stm32_usbdev.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Number of endpoints */ + +#ifndef STM32_NENDPOINTS +# define STM32_NENDPOINTS (8) +#endif + /**************************************************************************** * Public Functions Prototypes ****************************************************************************/ @@ -81,4 +91,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_USBDEV_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_USBDEV_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_usbdev.c b/arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_usbdev.c rename to arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c index d98ef7274af..59632743a29 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_usbdev.c +++ b/arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_usbdev.c + * arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_usbdev.c b/arch/arm/src/common/stm32/stm32_usbdev_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_usbdev.c rename to arch/arm/src/common/stm32/stm32_usbdev_m3m4_v1.c index 09e73931312..f84789892b1 100644 --- a/arch/arm/src/stm32/stm32_usbdev.c +++ b/arch/arm/src/common/stm32/stm32_usbdev_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_usbdev.c + * arch/arm/src/common/stm32/stm32_usbdev_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_usbfs.h b/arch/arm/src/common/stm32/stm32_usbfs.h new file mode 100644 index 00000000000..443a87bacfe --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_usbfs.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_usbfs.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBFS_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_USBFS_M3M4_V1) +# include "stm32_usbfs_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_usbfs" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBFS_H */ diff --git a/arch/arm/src/stm32/stm32_usbfs.c b/arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_usbfs.c rename to arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.c index cb6cf7f4745..418dcf33211 100644 --- a/arch/arm/src/stm32/stm32_usbfs.c +++ b/arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_usbfs.c + * arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -47,8 +47,10 @@ #include "arm_internal.h" #include "stm32.h" #include "stm32_syscfg.h" +#include "stm32_usbfs_m3m4_v1.h" #include "stm32_gpio.h" -#include "stm32_usbfs.h" +#include "stm32_syscfg.h" +#include "stm32_usbfs_m3m4_v1.h" #if defined(CONFIG_STM32_USBFS) diff --git a/arch/arm/src/stm32/stm32_usbfs.h b/arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.h similarity index 92% rename from arch/arm/src/stm32/stm32_usbfs.h rename to arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.h index b9c7ed0405b..8a5b8adf762 100644 --- a/arch/arm/src/stm32/stm32_usbfs.h +++ b/arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_usbfs.h + * arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_USBFS_H -#define __ARCH_ARM_SRC_STM32_STM32_USBFS_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_USBFS_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_USBFS_H /**************************************************************************** * Included Files @@ -76,4 +76,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_USBFS_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_USBFS_H */ diff --git a/arch/arm/src/common/stm32/stm32_usbhost.h b/arch/arm/src/common/stm32/stm32_usbhost.h new file mode 100644 index 00000000000..c659a23a25b --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_usbhost.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_usbhost.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBHOST_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBHOST_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_COMMON_LEGACY) +# include "stm32_usbhost_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_usbhost" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBHOST_H */ diff --git a/arch/arm/src/stm32/stm32_usbhost.c b/arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_usbhost.c rename to arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.c index 1314be9c5e4..d6241c81881 100644 --- a/arch/arm/src/stm32/stm32_usbhost.c +++ b/arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_usbhost.c + * arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ #include #include -#include "stm32_usbhost.h" +#include "stm32_usbhost_m3m4_v1.h" #ifdef HAVE_USBHOST_TRACE diff --git a/arch/arm/src/stm32/stm32_usbhost.h b/arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.h similarity index 98% rename from arch/arm/src/stm32/stm32_usbhost.h rename to arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.h index b71a9e46a7c..867260f81c8 100644 --- a/arch/arm/src/stm32/stm32_usbhost.h +++ b/arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_usbhost.h + * arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_USBHOST_H -#define __ARCH_ARM_SRC_STM32_STM32_USBHOST_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_USBHOST_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_USBHOST_H /**************************************************************************** * Included Files @@ -280,4 +280,4 @@ void stm32_usbhost_vbusdrive(int iface, bool enable); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_OTGFS && CONFIG_STM32_USBHOST */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_USBHOST_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_USBHOST_H */ diff --git a/arch/arm/src/stm32/stm32_comp.h b/arch/arm/src/common/stm32/stm32_userspace.h similarity index 66% rename from arch/arm/src/stm32/stm32_comp.h rename to arch/arm/src/common/stm32/stm32_userspace.h index 02e74e84972..36da6f4a783 100644 --- a/arch/arm/src/stm32/stm32_comp.h +++ b/arch/arm/src/common/stm32/stm32_userspace.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_comp.h + * arch/arm/src/common/stm32/stm32_userspace.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_COMP_H -#define __ARCH_ARM_SRC_STM32_STM32_COMP_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_USERSPACE_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_USERSPACE_H /**************************************************************************** * Included Files @@ -29,61 +29,35 @@ #include -#include "chip.h" - -#include "hardware/stm32_comp.h" - -#if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) -# include "stm32_comp_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) -# include "stm32_comp_v2.h" -#endif - /**************************************************************************** - * Pre-processor definitions + * Pre-processor Definitions ****************************************************************************/ /**************************************************************************** * Public Types ****************************************************************************/ +/**************************************************************************** + * Public Data + ****************************************************************************/ + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - /**************************************************************************** - * Name: stm32_compinitialize + * Name: stm32_userspace * * Description: - * Initialize the COMP. - * - * Input Parameters: - * intf - The COMP interface number. - * - * Returned Value: - * Valid COMP device structure reference on success; a NULL on failure. - * - * Assumptions: - * 1. Clock to the COMP block has enabled, - * 2. Board-specific logic has already configured + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. * ****************************************************************************/ -struct comp_dev_s *stm32_compinitialize(int intf); - -#undef EXTERN -#ifdef __cplusplus -} +#ifdef CONFIG_BUILD_PROTECTED +void stm32_userspace(void); #endif -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_USERSPACE_H */ diff --git a/arch/arm/src/stm32/stm32_userspace.c b/arch/arm/src/common/stm32/stm32_userspace_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_userspace.c rename to arch/arm/src/common/stm32/stm32_userspace_m3m4_v1.c index 92897821b35..31f567ecd02 100644 --- a/arch/arm/src/stm32/stm32_userspace.c +++ b/arch/arm/src/common/stm32/stm32_userspace_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_userspace.c + * arch/arm/src/common/stm32/stm32_userspace_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_waste.h b/arch/arm/src/common/stm32/stm32_waste.h new file mode 100644 index 00000000000..702c166346a --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_waste.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_waste.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_WASTE_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_WASTE_H + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +void stm32_waste(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_WASTE_H */ diff --git a/arch/arm/src/stm32/stm32_waste.c b/arch/arm/src/common/stm32/stm32_waste_m3m4_v1.c similarity index 97% rename from arch/arm/src/stm32/stm32_waste.c rename to arch/arm/src/common/stm32/stm32_waste_m3m4_v1.c index ce40916f4f9..b689d1d91b0 100644 --- a/arch/arm/src/stm32/stm32_waste.c +++ b/arch/arm/src/common/stm32/stm32_waste_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_waste.c + * arch/arm/src/common/stm32/stm32_waste_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_wdg.h b/arch/arm/src/common/stm32/stm32_wdg.h similarity index 94% rename from arch/arm/src/stm32f0l0g0/stm32_wdg.h rename to arch/arm/src/common/stm32/stm32_wdg.h index 96ce766df55..c70b669ad87 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_wdg.h +++ b/arch/arm/src/common/stm32/stm32_wdg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_wdg.h + * arch/arm/src/common/stm32/stm32_wdg.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_WDG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_WDG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_WDG_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_WDG_H /**************************************************************************** * Included Files @@ -101,4 +101,4 @@ void stm32_wwdginitialize(const char *devpath); #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_WDG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_WDG_H */ diff --git a/arch/arm/src/stm32/stm32_wwdg.c b/arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_wwdg.c rename to arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c index 26decaa9e5f..9ec66a9fa92 100644 --- a/arch/arm/src/stm32/stm32_wwdg.c +++ b/arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_wwdg.c + * arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_wwdg.c b/arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c similarity index 80% rename from arch/arm/src/stm32f0l0g0/stm32_wwdg.c rename to arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c index f8717ce0f2c..8d8ccdac2b0 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_wwdg.c +++ b/arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_wwdg.c + * arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -40,6 +40,8 @@ #include "hardware/stm32_dbgmcu.h" #include "stm32_wdg.h" +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_WWDG) + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -63,6 +65,16 @@ #define WWDG_FMIN (STM32_PCLK1_FREQUENCY / 4096 / 8) #define WWDG_MAXTIMEOUT (1000 * (WWDG_CR_T_MAX+1) / WWDG_FMIN) +/* Configuration ************************************************************/ + +#ifndef CONFIG_STM32_WWDG_DEFTIMOUT +# define CONFIG_STM32_WWDG_DEFTIMOUT WWDG_MAXTIMEOUT +#endif + +#ifndef CONFIG_DEBUG_WATCHDOG_INFO +# undef CONFIG_STM32_WWDG_REGDEBUG +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -89,25 +101,33 @@ struct stm32_lowerhalf_s /* Register operations ******************************************************/ -static void stm32_setwindow(struct stm32_lowerhalf_s *priv, uint8_t window); +#ifdef CONFIG_STM32_WWDG_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint16_t val, uint32_t addr); +#else +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(val,addr) putreg32(val,addr) +#endif +static void stm32_setwindow(struct stm32_lowerhalf_s *priv, + uint8_t window); /* Interrupt handling *******************************************************/ -static int stm32_interrupt(int irq, void *context, void *arg); +static int stm32_interrupt(int irq, void *context, void *arg); /* "Lower half" driver methods **********************************************/ -static int stm32_start(struct watchdog_lowerhalf_s *lower); -static int stm32_stop(struct watchdog_lowerhalf_s *lower); -static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); -static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, - struct watchdog_status_s *status); -static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, - uint32_t timeout); -static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, - xcpt_t handler); -static int stm32_ioctl(struct watchdog_lowerhalf_s *lower, int cmd, - unsigned long arg); +static int stm32_start(struct watchdog_lowerhalf_s *lower); +static int stm32_stop(struct watchdog_lowerhalf_s *lower); +static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); +static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, + struct watchdog_status_s *status); +static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, + uint32_t timeout); +static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, + xcpt_t handler); +static int stm32_ioctl(struct watchdog_lowerhalf_s *lower, int cmd, + unsigned long arg); /**************************************************************************** * Private Data @@ -134,6 +154,90 @@ static struct stm32_lowerhalf_s g_wdgdev; * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: stm32_getreg + * + * Description: + * Get the contents of an STM32 register + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_WWDG_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t count = 0; + static uint16_t preval = 0; + + /* Read the value from the register */ + + uint16_t val = getreg16(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + wdinfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + wdinfo("[repeats %d more times]\n", count - 3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + wdinfo("%08" PRIx32 "->%04x\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: stm32_putreg + * + * Description: + * Set the contents of an STM32 register to a value + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_WWDG_REGDEBUG +static void stm32_putreg(uint16_t val, uint32_t addr) +{ + /* Show the register value being written */ + + wdinfo("%08" PRIx32 "<-%04x\n", addr, val); + + /* Write the value */ + + putreg16(val, addr); +} +#endif + /**************************************************************************** * Name: stm32_setwindow * @@ -145,16 +249,17 @@ static struct stm32_lowerhalf_s g_wdgdev; * ****************************************************************************/ -static void stm32_setwindow(struct stm32_lowerhalf_s *priv, uint8_t window) +static void stm32_setwindow(struct stm32_lowerhalf_s *priv, + uint8_t window) { uint16_t regval; /* Set W[6:0] bits according to selected window value */ - regval = getreg32(STM32_WWDG_CFR); + regval = stm32_getreg(STM32_WWDG_CFR); regval &= ~WWDG_CFR_W_MASK; regval |= window << WWDG_CFR_W_SHIFT; - putreg32(regval, STM32_WWDG_CFR); + stm32_putreg(regval, STM32_WWDG_CFR); /* Remember the window setting */ @@ -182,7 +287,7 @@ static int stm32_interrupt(int irq, void *context, void *arg) /* Check if the EWI interrupt is really pending */ - regval = getreg32(STM32_WWDG_SR); + regval = stm32_getreg(STM32_WWDG_SR); if ((regval & WWDG_SR_EWIF) != 0) { /* Is there a registered handler? */ @@ -202,7 +307,7 @@ static int stm32_interrupt(int irq, void *context, void *arg) */ regval &= ~WWDG_SR_EWIF; - putreg32(regval, STM32_WWDG_SR); + stm32_putreg(regval, STM32_WWDG_SR); } return OK; @@ -235,7 +340,7 @@ static int stm32_start(struct watchdog_lowerhalf_s *lower) * except by a reset. */ - putreg32(WWDG_CR_WDGA | WWDG_CR_T_RESET | priv->reload, STM32_WWDG_CR); + stm32_putreg(WWDG_CR_WDGA | WWDG_CR_T_RESET | priv->reload, STM32_WWDG_CR); priv->started = true; return OK; } @@ -300,7 +405,7 @@ static int stm32_keepalive(struct watchdog_lowerhalf_s *lower) * a read-modify-write; writing a 0 to WDGA bit does nothing. */ - putreg32((WWDG_CR_T_RESET | priv->reload), STM32_WWDG_CR); + stm32_putreg((WWDG_CR_T_RESET | priv->reload), STM32_WWDG_CR); return OK; } @@ -349,7 +454,7 @@ static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, /* Get the time remaining until the watchdog expires (in milliseconds) */ - reload = (getreg32(STM32_WWDG_CR) >> WWDG_CR_T_SHIFT) & 0x7f; + reload = (stm32_getreg(STM32_WWDG_CR) >> WWDG_CR_T_SHIFT) & 0x7f; elapsed = priv->reload - reload; status->timeleft = (priv->timeout * elapsed) / (priv->reload + 1); @@ -479,10 +584,10 @@ static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, /* Set WDGTB[1:0] bits according to calculated value */ - regval = getreg32(STM32_WWDG_CFR); + regval = stm32_getreg(STM32_WWDG_CFR); regval &= ~WWDG_CFR_WDGTB_MASK; regval |= (uint16_t)wdgtb << WWDG_CFR_WDGTB_SHIFT; - putreg32(regval, STM32_WWDG_CFR); + stm32_putreg(regval, STM32_WWDG_CFR); /* Reset the 7-bit window value to the maximum value.. essentially * disabling the lower limit of the watchdog reset time. @@ -536,13 +641,13 @@ static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, /* Are we attaching or detaching the handler? */ - regval = getreg32(STM32_WWDG_CFR); + regval = stm32_getreg(STM32_WWDG_CFR); if (handler) { /* Attaching... Enable the EWI interrupt */ regval |= WWDG_CFR_EWI; - putreg32(regval, STM32_WWDG_CFR); + stm32_putreg(regval, STM32_WWDG_CFR); up_enable_irq(STM32_IRQ_WWDG); } @@ -551,7 +656,7 @@ static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, /* Detaching... Disable the EWI interrupt */ regval &= ~WWDG_CFR_EWI; - putreg32(regval, STM32_WWDG_CFR); + stm32_putreg(regval, STM32_WWDG_CFR); up_disable_irq(STM32_IRQ_WWDG); } @@ -581,7 +686,7 @@ static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, ****************************************************************************/ static int stm32_ioctl(struct watchdog_lowerhalf_s *lower, int cmd, - unsigned long arg) + unsigned long arg) { struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; int ret = -ENOTTY; @@ -663,7 +768,8 @@ void stm32_wwdginitialize(const char *devpath) * device option bits, the watchdog is automatically enabled at power-on. */ - stm32_settimeout((struct watchdog_lowerhalf_s *)priv, WWDG_MAXTIMEOUT); + stm32_settimeout((struct watchdog_lowerhalf_s *)priv, + CONFIG_STM32_WWDG_DEFTIMOUT); /* Register the watchdog driver as /dev/watchdog0 */ @@ -674,11 +780,22 @@ void stm32_wwdginitialize(const char *devpath) * on DBG_WWDG_STOP configuration bit in DBG module. */ -#ifdef CONFIG_DEBUG_FEATURES +#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ + defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ + defined(CONFIG_STM32_JTAG_SW_ENABLE) { +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ); cr |= DBGMCU_APB1_WWDGSTOP; putreg32(cr, STM32_DBGMCU_APB1_FZ); +#else /* if defined(CONFIG_STM32_STM32F10XX) */ + uint32_t cr = getreg32(STM32_DBGMCU_CR); + cr |= DBGMCU_CR_WWDGSTOP; + putreg32(cr, STM32_DBGMCU_CR); +#endif } #endif } + +#endif /* CONFIG_WATCHDOG && CONFIG_STM32_WWDG */ diff --git a/arch/arm/src/stm32/CMakeLists.txt b/arch/arm/src/stm32/CMakeLists.txt index 6c370d70d10..f36e41d25df 100644 --- a/arch/arm/src/stm32/CMakeLists.txt +++ b/arch/arm/src/stm32/CMakeLists.txt @@ -30,32 +30,8 @@ list( stm32_rcc.c stm32_lse.c stm32_lsi.c - stm32_gpio.c - stm32_exti_gpio.c - stm32_flash.c stm32_irq.c - stm32_lowputc.c - stm32_spi.c - stm32_i2s.c - stm32_sdio.c - stm32_tim.c - stm32_waste.c - stm32_ccm.c - stm32_uid.c - stm32_capture.c - stm32_dfumode.c) - -if(CONFIG_STM32_USART) - list(APPEND SRCS stm32_serial.c) -endif() - -if(CONFIG_STM32_DMA) - list(APPEND SRCS stm32_dma.c) -endif() - -if(CONFIG_TIMER) - list(APPEND SRCS stm32_tim_lowerhalf.c) -endif() + stm32_lowputc.c) if(CONFIG_STM32_TICKLESS_TIMER) list(APPEND SRCS stm32_tickless.c) @@ -63,64 +39,10 @@ else() list(APPEND SRCS stm32_timerisr.c) endif() -if(CONFIG_STM32_ONESHOT) - list(APPEND SRCS stm32_oneshot.c stm32_oneshot_lowerhalf.c) -endif() - -if(CONFIG_STM32_FREERUN) - list(APPEND SRCS stm32_freerun.c) -endif() - if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32_userspace.c stm32_mpuinit.c) endif() -if(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) - if(CONFIG_STM32_I2C_ALT) - list(APPEND SRCS stm32_i2c_alt.c) - elseif(CONFIG_STM32_STM32F4XXX) - list(APPEND SRCS stm32f40xxx_i2c.c) - else() - list(APPEND SRCS stm32_i2c.c) - endif() -elseif(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) - list(APPEND SRCS stm32_i2c_v2.c) - if(CONFIG_STM32_I2C_SLAVE) - list(APPEND SRCS stm32_i2cslave_v2.c) - endif() -endif() - -if(CONFIG_USBDEV) - if(CONFIG_STM32_USB) - list(APPEND SRCS stm32_usbdev.c) - endif() - if(CONFIG_STM32_USBFS) - list(APPEND SRCS stm32_usbfs.c) - endif() - if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_otgfsdev.c) - endif() - if(CONFIG_STM32_OTGHS) - list(APPEND SRCS stm32_otghsdev.c) - endif() -endif() - -if(CONFIG_STM32_USBHOST) - if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_otgfshost.c) - endif() - if(CONFIG_STM32_OTGHS) - list(APPEND SRCS stm32_otghshost.c) - endif() - if(CONFIG_USBHOST_TRACE) - list(APPEND SRCS stm32_usbhost.c) - else() - if(CONFIG_DEBUG_USB) - list(APPEND SRCS stm32_usbhost.c) - endif() - endif() -endif() - if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS stm32_idle.c) endif() @@ -131,149 +53,5 @@ if(NOT CONFIG_ARCH_CUSTOM_PMINIT) list(APPEND SRCS stm32_pminitialize.c) endif() -if(CONFIG_STM32_ETHMAC) - list(APPEND SRCS stm32_eth.c) -endif() - -if(CONFIG_STM32_PWR) - list(APPEND SRCS stm32_pwr.c stm32_exti_pwr.c) -endif() - -if(CONFIG_STM32_RTC) - list(APPEND SRCS stm32_rtc.c) - if(CONFIG_RTC_ALARM) - list(APPEND SRCS stm32_exti_alarm.c) - endif() - if(CONFIG_RTC_PERIODIC) - list(APPEND SRCS stm32_exti_wakeup.c) - endif() - if(CONFIG_RTC_DRIVER) - list(APPEND SRCS stm32_rtc_lowerhalf.c) - endif() -endif() - -if(CONFIG_STM32_SDADC) - list(APPEND SRCS stm32_sdadc.c) -endif() - -if(CONFIG_STM32_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_DAC) - list(APPEND SRCS stm32_dac.c) -endif() - -if(CONFIG_STM32_COMP) - list(APPEND SRCS stm32_comp.c) -endif() - -if(CONFIG_STM32_OPAMP) - list(APPEND SRCS stm32_opamp.c) -endif() - -if(CONFIG_STM32_HRTIM) - list(APPEND SRCS stm32_hrtim.c) -endif() - -if(CONFIG_STM32_1WIREDRIVER) - list(APPEND SRCS stm32_1wire.c) -endif() - -if(CONFIG_STM32_HCIUART) - list(APPEND SRCS stm32_hciuart.c) -endif() - -if(CONFIG_STM32_RNG) - list(APPEND SRCS stm32_rng.c) -endif() - -if(CONFIG_STM32_LTDC) - list(APPEND SRCS stm32_ltdc.c) -endif() - -if(CONFIG_STM32_DMA2D) - list(APPEND SRCS stm32_dma2d.c) -endif() - -if(CONFIG_STM32_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_PULSECOUNT) - list(APPEND SRCS stm32_pulsecount.c) -endif() - -if(CONFIG_STM32_CAP) - list(APPEND SRCS stm32_capture_lowerhalf.c) -endif() - -if(CONFIG_SENSORS_QENCODER) - if(CONFIG_STM32_QE) - list(APPEND SRCS stm32_qencoder.c) - endif() -endif() - -if(CONFIG_SENSORS_HALL3PHASE) - list(APPEND SRCS stm32_hall3ph.c) -endif() - -if(CONFIG_STM32_CAN) - if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) - endif() - if(CONFIG_STM32_CAN_SOCKET) - list(APPEND SRCS stm32_can_sock.c) - endif() -endif() - -if(CONFIG_STM32_FDCAN) - if(CONFIG_STM32_FDCAN_CHARDRIVER) - list(APPEND SRCS stm32_fdcan.c) - endif() - if(CONFIG_STM32_FDCAN_SOCKET) - list(APPEND SRCS stm32_fdcan_sock.c) - endif() -endif() - -if(CONFIG_STM32_IWDG) - list(APPEND SRCS stm32_iwdg.c) -endif() - -if(CONFIG_STM32_WWDG) - list(APPEND SRCS stm32_wwdg.c) -endif() - -if(CONFIG_DEBUG_FEATURES) - list(APPEND SRCS stm32_dumpgpio.c) -endif() - -if(CONFIG_STM32_AES) - list(APPEND SRCS stm32_aes.c) -endif() - -if(CONFIG_CRYPTO_CRYPTODEV_HARDWARE) - list(APPEND SRCS stm32_crypto.c) -endif() - -if(CONFIG_STM32_BBSRAM) - list(APPEND SRCS stm32_bbsram.c) -endif() - -if(CONFIG_STM32_FMC) - list(APPEND SRCS stm32_fmc.c) -endif() - -if(CONFIG_STM32_FSMC) - list(APPEND SRCS stm32_fsmc.c) -endif() - -if(CONFIG_STM32_FOC) - list(APPEND SRCS stm32_foc.c) -endif() - -if(CONFIG_STM32_CORDIC) - list(APPEND SRCS stm32_cordic.c) -endif() - target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../common/stm32 stm32_common) diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs index 0f0b7e4cd0f..a7cf6decf4b 100644 --- a/arch/arm/src/stm32/Make.defs +++ b/arch/arm/src/stm32/Make.defs @@ -23,23 +23,7 @@ include armv7-m/Make.defs CHIP_CSRCS = stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c -CHIP_CSRCS += stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c -CHIP_CSRCS += stm32_irq.c stm32_lowputc.c -CHIP_CSRCS += stm32_spi.c stm32_i2s.c stm32_sdio.c stm32_tim.c -CHIP_CSRCS += stm32_waste.c stm32_ccm.c stm32_uid.c stm32_capture.c -CHIP_CSRCS += stm32_dfumode.c - -ifeq ($(CONFIG_STM32_USART),y) -CHIP_CSRCS += stm32_serial.c -endif - -ifeq ($(CONFIG_STM32_DMA),y) -CHIP_CSRCS += stm32_dma.c -endif - -ifeq ($(CONFIG_TIMER),y) -CHIP_CSRCS += stm32_tim_lowerhalf.c -endif +CHIP_CSRCS += stm32_lsi.c stm32_irq.c stm32_lowputc.c ifdef CONFIG_STM32_TICKLESS_TIMER CHIP_CSRCS += stm32_tickless.c @@ -47,64 +31,10 @@ else CHIP_CSRCS += stm32_timerisr.c endif -ifeq ($(CONFIG_STM32_ONESHOT),y) -CHIP_CSRCS += stm32_oneshot.c stm32_oneshot_lowerhalf.c -endif - -ifeq ($(CONFIG_STM32_FREERUN),y) -CHIP_CSRCS += stm32_freerun.c -endif - ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32_userspace.c stm32_mpuinit.c endif -ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1),y) -ifeq ($(CONFIG_STM32_I2C_ALT),y) -CHIP_CSRCS += stm32_i2c_alt.c -else ifeq ($(CONFIG_STM32_STM32F4XXX),y) -CHIP_CSRCS += stm32f40xxx_i2c.c -else -CHIP_CSRCS += stm32_i2c.c -endif -else ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2),y) -CHIP_CSRCS += stm32_i2c_v2.c -ifeq ($(CONFIG_STM32_I2C_SLAVE),y) -CHIP_CSRCS += stm32_i2cslave_v2.c -endif -endif - -ifeq ($(CONFIG_USBDEV),y) -ifeq ($(CONFIG_STM32_USB),y) -CHIP_CSRCS += stm32_usbdev.c -endif -ifeq ($(CONFIG_STM32_USBFS),y) -CHIP_CSRCS += stm32_usbfs.c -endif -ifeq ($(CONFIG_STM32_OTGFS),y) -CHIP_CSRCS += stm32_otgfsdev.c -endif -ifeq ($(CONFIG_STM32_OTGHS),y) -CHIP_CSRCS += stm32_otghsdev.c -endif -endif - -ifeq ($(CONFIG_STM32_USBHOST),y) -ifeq ($(CONFIG_STM32_OTGFS),y) -CHIP_CSRCS += stm32_otgfshost.c -endif -ifeq ($(CONFIG_STM32_OTGHS),y) -CHIP_CSRCS += stm32_otghshost.c -endif -ifeq ($(CONFIG_USBHOST_TRACE),y) -CHIP_CSRCS += stm32_usbhost.c -else -ifeq ($(CONFIG_DEBUG_USB),y) -CHIP_CSRCS += stm32_usbhost.c -endif -endif -endif - ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32_idle.c endif @@ -115,147 +45,4 @@ ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) CHIP_CSRCS += stm32_pminitialize.c endif -ifeq ($(CONFIG_STM32_ETHMAC),y) -CHIP_CSRCS += stm32_eth.c -endif - -ifeq ($(CONFIG_STM32_PWR),y) -CHIP_CSRCS += stm32_pwr.c stm32_exti_pwr.c -endif - -ifeq ($(CONFIG_STM32_RTC),y) -CHIP_CSRCS += stm32_rtc.c -ifeq ($(CONFIG_RTC_ALARM),y) -CHIP_CSRCS += stm32_exti_alarm.c -endif -ifeq ($(CONFIG_RTC_PERIODIC),y) -CHIP_CSRCS += stm32_exti_wakeup.c -endif -ifeq ($(CONFIG_RTC_DRIVER),y) -CHIP_CSRCS += stm32_rtc_lowerhalf.c -endif -endif - -ifeq ($(CONFIG_STM32_ADC),y) -CHIP_CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_SDADC),y) -CHIP_CSRCS += stm32_sdadc.c -endif - -ifeq ($(CONFIG_STM32_DAC),y) -CHIP_CSRCS += stm32_dac.c -endif - -ifeq ($(CONFIG_STM32_COMP),y) -CHIP_CSRCS += stm32_comp.c -endif - -ifeq ($(CONFIG_STM32_OPAMP),y) -CHIP_CSRCS += stm32_opamp.c -endif - -ifeq ($(CONFIG_STM32_HRTIM),y) -CHIP_CSRCS += stm32_hrtim.c -endif - -ifeq ($(CONFIG_STM32_1WIREDRIVER),y) -CHIP_CSRCS += stm32_1wire.c -endif - -ifeq ($(CONFIG_STM32_HCIUART),y) -CHIP_CSRCS += stm32_hciuart.c -endif - -ifeq ($(CONFIG_STM32_RNG),y) -CHIP_CSRCS += stm32_rng.c -endif - -ifeq ($(CONFIG_STM32_LTDC),y) -CHIP_CSRCS += stm32_ltdc.c -endif - -ifeq ($(CONFIG_STM32_DMA2D),y) -CHIP_CSRCS += stm32_dma2d.c -endif - -ifeq ($(CONFIG_STM32_PWM),y) -CHIP_CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_STM32_PULSECOUNT),y) -CHIP_CSRCS += stm32_pulsecount.c -endif - -ifeq ($(CONFIG_STM32_CAP),y) -CHIP_CSRCS += stm32_capture_lowerhalf.c -endif - -ifeq ($(CONFIG_SENSORS_QENCODER),y) - ifeq ($(CONFIG_STM32_QE),y) - CHIP_CSRCS += stm32_qencoder.c - endif -endif - -ifeq ($(CONFIG_SENSORS_HALL3PHASE),y) -CHIP_CSRCS += stm32_hall3ph.c -endif - -ifeq ($(CONFIG_STM32_CAN),y) -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CHIP_CSRCS += stm32_can.c -endif -ifeq ($(CONFIG_STM32_CAN_SOCKET),y) -CHIP_CSRCS += stm32_can_sock.c -endif -endif - -ifeq ($(CONFIG_STM32_FDCAN),y) -ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) -CHIP_CSRCS += stm32_fdcan.c -endif -ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) -CHIP_CSRCS += stm32_fdcan_sock.c -endif -endif - -ifeq ($(CONFIG_STM32_IWDG),y) -CHIP_CSRCS += stm32_iwdg.c -endif - -ifeq ($(CONFIG_STM32_WWDG),y) -CHIP_CSRCS += stm32_wwdg.c -endif - -ifeq ($(CONFIG_DEBUG_FEATURES),y) -CHIP_CSRCS += stm32_dumpgpio.c -endif - -ifeq ($(CONFIG_STM32_AES),y) -CHIP_CSRCS += stm32_aes.c -endif - -ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE),y) -CHIP_CSRCS += stm32_crypto.c -endif - -ifeq ($(CONFIG_STM32_BBSRAM),y) -CHIP_CSRCS += stm32_bbsram.c -endif - -ifeq ($(CONFIG_STM32_FMC),y) -CHIP_CSRCS += stm32_fmc.c -endif - -ifeq ($(CONFIG_STM32_FSMC),y) -CHIP_CSRCS += stm32_fsmc.c -endif - -ifeq ($(CONFIG_STM32_FOC),y) -CHIP_CSRCS += stm32_foc.c -endif - -ifeq ($(CONFIG_STM32_CORDIC),y) -CHIP_CSRCS += stm32_cordic.c -endif +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32/hardware/stm32_pinmap.h b/arch/arm/src/stm32/hardware/stm32_pinmap.h deleted file mode 100644 index 7e35c3b9b75..00000000000 --- a/arch/arm/src/stm32/hardware/stm32_pinmap.h +++ /dev/null @@ -1,136 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_pinmap.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PINMAP_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PINMAP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/* STM32L EnergyLite Line ***************************************************/ - -#if defined(CONFIG_STM32_ENERGYLITE) - -/* STM32L15xx family */ - -# if defined(CONFIG_STM32_STM32L15XX) -# include "hardware/stm32l15xxx_pinmap.h" -# else -# error "Unsupported EnergyLite chip" -# endif - -/* STM32 F1 Family **********************************************************/ - -#elif defined(CONFIG_STM32_STM32F10XX) - -/* STM32F100 Value Line */ - -# if defined(CONFIG_STM32_VALUELINE) -# include "hardware/stm32f100_pinmap.h" - -/* STM32 F102 USB Access Medium Density Family */ -# elif defined(CONFIG_ARCH_CHIP_STM32F102CB) -# include "hardware/stm32f102_pinmap.h" - -/* STM32 F103 Low / Medium Density Family */ -# elif defined(CONFIG_ARCH_CHIP_STM32F103C4) || \ - defined(CONFIG_ARCH_CHIP_STM32F103C8) || \ - defined(CONFIG_ARCH_CHIP_STM32F103CB) -# include "hardware/stm32f103c_pinmap.h" - -/* STM32 F103 High Density Family */ - -/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin - * packages and differ only in the available FLASH and SRAM. - */ - -# elif defined(CONFIG_ARCH_CHIP_STM32F103RB) || \ - defined(CONFIG_ARCH_CHIP_STM32F103RC) || \ - defined(CONFIG_ARCH_CHIP_STM32F103RD) || \ - defined(CONFIG_ARCH_CHIP_STM32F103RE) || \ - defined(CONFIG_ARCH_CHIP_STM32F103RG) -# include "hardware/stm32f103r_pinmap.h" - -/* STM32F103VC, STM32F103VD, and STM32F103VE are all provided in 100 pin - * packages and differ only in the available FLASH and SRAM. - */ - -# elif defined(CONFIG_ARCH_CHIP_STM32F103VC) || defined(CONFIG_ARCH_CHIP_STM32F103VE) -# include "hardware/stm32f103v_pinmap.h" - -/* STM32F103ZC, STM32F103ZD, and STM32F103ZE are all provided in 144 pin - * packages and differ only in the available FLASH and SRAM. - */ -# elif defined(CONFIG_ARCH_CHIP_STM32F103ZE) -# include "hardware/stm32f103z_pinmap.h" - -/* STM32 F105/F107 Connectivity Line */ - -# elif defined(CONFIG_ARCH_CHIP_STM32F105VB) -# include "hardware/stm32f105v_pinmap.h" - -# elif defined(CONFIG_ARCH_CHIP_STM32F105RB) -# include "hardware/stm32f105r_pinmap.h" - -# elif defined(CONFIG_ARCH_CHIP_STM32F107VC) -# include "hardware/stm32f107v_pinmap.h" -# else -# error "Unsupported STM32F10XXX chip" -# endif - -/* STM32 F2 Family **********************************************************/ - -#elif defined(CONFIG_STM32_STM32F20XX) -# include "hardware/stm32f20xxx_pinmap.h" - -/* STM32 F3 Family **********************************************************/ - -#elif defined(CONFIG_STM32_STM32F30XX) -# include "hardware/stm32f30xxx_pinmap.h" -#elif defined(CONFIG_STM32_STM32F33XX) -# include "hardware/stm32f33xxx_pinmap.h" -#elif defined(CONFIG_STM32_STM32F37XX) -# include "hardware/stm32f37xxx_pinmap.h" - -/* STM32 F412 Family ********************************************************/ - -#elif defined(CONFIG_STM32_STM32F412) -# include "hardware/stm32f412xx_pinmap.h" - -/* STM32 F4 Family **********************************************************/ - -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "hardware/stm32f40xxx_pinmap.h" - -/* STM32 G4 Family **********************************************************/ - -#elif defined(CONFIG_STM32_STM32G4XXX) -# include "hardware/stm32g4xxxx_pinmap.h" - -#else -# error "No pinmap file for this STM32 chip" -#endif - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/stm32_comp.c b/arch/arm/src/stm32/stm32_comp.c deleted file mode 100644 index b095de41efa..00000000000 --- a/arch/arm/src/stm32/stm32_comp.c +++ /dev/null @@ -1,60 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_comp.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_comp.h" -#include "stm32_gpio.h" - -/* This file is only a thin shell that includes the correct COMP - * implementation. At this moment STM32 COMP IP versions 1 and 2 are - * supported. - * - STM32 COMP IP version 1: SMT32F33XX - * - STM32 COMP IP version 2: SMT32G4XXX - */ - -#if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) -# include "stm32_comp_v1.c" -#elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) -# include "stm32_comp_v2.c" -#else -# error "STM32 COMP IP version not supported." -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ \ No newline at end of file diff --git a/arch/arm/src/stm32/stm32_comp_v2.h b/arch/arm/src/stm32/stm32_comp_v2.h deleted file mode 100644 index 3b748b01a9e..00000000000 --- a/arch/arm/src/stm32/stm32_comp_v2.h +++ /dev/null @@ -1,99 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_comp_v2.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_COMP_V2_H -#define __ARCH_ARM_SRC_STM32_STM32_COMP_V2_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifdef CONFIG_STM32_COMP - -/**************************************************************************** - * Pre-processor definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* Inverting input. See Table 196 in RM0440 */ - -enum stm32_comp_inm_e -{ - COMP_INM_1_4_VREF, - COMP_INM_1_2_VREF, - COMP_INM_3_4_VREF, - COMP_INM_VREF, - COMP_INM_DAC_1, - COMP_INM_DAC_2, - COMP_INM_PIN_1, - COMP_INM_PIN_2, -}; - -/* Non-inverting input. See Table 195 in RM0440 */ - -enum stm32_comp_inp_e -{ - COMP_INP_PIN_1, - COMP_INP_PIN_2, -}; - -/* Output polarity */ - -enum stm32_comp_pol_e -{ - COMP_POL_NONINVERT, - COMP_POL_INVERTED -}; - -/* Hysteresis */ - -enum stm32_comp_hyst_e -{ - COMP_HYST_DIS, - COMP_HYST_10MV, - COMP_HYST_20MV, - COMP_HYST_30MV, - COMP_HYST_40MV, - COMP_HYST_50MV, - COMP_HYST_60MV, - COMP_HYST_70MV, -}; - -/* Blanking source */ - -enum stm32_comp_blanking_e -{ - COMP_BLANKING_DIS, - COMP_BLANKING_TIMX_OCY_1, - COMP_BLANKING_TIMX_OCY_2, - COMP_BLANKING_TIMX_OCY_3, - COMP_BLANKING_TIMX_OCY_4, - COMP_BLANKING_TIMX_OCY_5, - COMP_BLANKING_TIMX_OCY_6, - COMP_BLANKING_TIMX_OCY_7, -}; - -#endif /* CONFIG_STM32_COMP */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_V2_H */ diff --git a/arch/arm/src/stm32/stm32_dma.c b/arch/arm/src/stm32/stm32_dma.c deleted file mode 100644 index f5d1f1047a8..00000000000 --- a/arch/arm/src/stm32/stm32_dma.c +++ /dev/null @@ -1,53 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_dma.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/* This file is only a thin shell that includes the correct DMA - * implementation for the selected STM32 IP core: - * - STM32 DMA IP version 1 - F0, F1, F3, G4, L0, L1, L4 - * - STM32 DMA IP version 2 - F2, F4, F7, H7 - * - * The STM32 DMA IPv2 differs from the STM32 DMA IPv1 primarily in that it - * adds the concept of "streams" that are used to associate DMA sources with - * DMA channels. - */ - -#if defined(CONFIG_STM32_HAVE_IP_DMA_V1) -# if defined(CONFIG_STM32_HAVE_DMAMUX) -# include "stm32_dma_v1mux.c" -# else -# include "stm32_dma_v1.c" -# endif -#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) -# include "stm32_dma_v2.c" -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_flash.c b/arch/arm/src/stm32/stm32_flash.c deleted file mode 100644 index 0afd013d872..00000000000 --- a/arch/arm/src/stm32/stm32_flash.c +++ /dev/null @@ -1,49 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_flash.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Provides standard flash access functions, to be used by the flash mtd - * driver. The interface is defined in the include/nuttx/progmem.h - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/* Include the correct FLASH implementation for the selection STM32 part */ - -#if defined(CONFIG_STM32_STM32L15XX) -# include "stm32l15xx_flash.c" -#elif defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) -# include "stm32f10xxf30xx_flash.c" -#elif defined(CONFIG_STM32_STM32F20XX) || defined (CONFIG_STM32_STM32F4XXX) -# include "stm32f20xxf40xx_flash.c" -#elif defined(CONFIG_STM32_STM32G4XXX) -# include "stm32g4xxx_flash.c" -#else -# warning "No FLASH support for the selected part" -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_flash.h b/arch/arm/src/stm32/stm32_flash.h deleted file mode 100644 index 6a67d7b2ce6..00000000000 --- a/arch/arm/src/stm32/stm32_flash.h +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_flash.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_FLASH_H -#define __ARCH_ARM_SRC_STM32_STM32_FLASH_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "chip.h" -#include "hardware/stm32_flash.h" - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -int stm32_flash_lock(void); -int stm32_flash_unlock(void); - -/**************************************************************************** - * Name: stm32_flash_user_optbytes - * - * Description: - * Modify the contents of the user option bytes (USR OPT) on the flash. - * This does not set OBL_LAUNCH so new options take effect only after - * next power reset. - * - * Input Parameters: - * clrbits - Bits in the option bytes to be cleared - * setbits - Bits in the option bytes to be set - * - * Returned Value: - * Option bytes after operation is completed - * - ****************************************************************************/ - -uint32_t stm32_flash_users_optbytes(uint32_t clrbits, uint32_t setbits); - -/**************************************************************************** - * Name: stm32_eeprom_size - * - * Description: - * Get EEPROM data memory size - * - * Returned Value: - * Length of EEPROM memory region - * - ****************************************************************************/ - -size_t stm32_eeprom_size(void); - -/**************************************************************************** - * Name: stm32_eeprom_getaddress - * - * Description: - * Get EEPROM data memory address - * - * Returned Value: - * Address of EEPROM memory region - * - ****************************************************************************/ - -size_t stm32_eeprom_getaddress(void); - -/**************************************************************************** - * Name: stm32_eeprom_write - * - * Description: - * Write buffer to EEPROM data memory address - * - * Returned Value: - * Number of written bytes or error code. - * - ****************************************************************************/ - -ssize_t stm32_eeprom_write(size_t addr, const void *buf, size_t buflen); - -/**************************************************************************** - * Name: stm32_eeprom_erase - * - * Description: - * Erase memory on EEPROM data memory address - * - * Returned Value: - * Number of erased bytes or error code. - * - ****************************************************************************/ - -ssize_t stm32_eeprom_erase(size_t addr, size_t eraselen); - -#endif /* __ARCH_ARM_SRC_STM32_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32/stm32_freerun.h b/arch/arm/src/stm32/stm32_freerun.h deleted file mode 100644 index 4dbaadeee3c..00000000000 --- a/arch/arm/src/stm32/stm32_freerun.h +++ /dev/null @@ -1,161 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_freerun.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_FREERUN_H -#define __ARCH_ARM_SRC_STM32_STM32_FREERUN_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include "stm32_tim.h" - -#ifdef CONFIG_STM32_FREERUN - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* The freerun client must allocate an instance of this structure and called - * stm32_freerun_initialize() before using the freerun facilities. The - * client should not access the contents of this structure directly since - * the contents are subject to change. - */ - -struct stm32_freerun_s -{ - uint8_t chan; /* The timer/counter in use */ - uint8_t width; /* Width of timer (16- or 32-bits) */ - struct stm32_tim_dev_s *tch; /* Handle returned by stm32_tim_init() */ - uint32_t frequency; - -#ifndef CONFIG_CLOCK_TIMEKEEPING - uint32_t overflow; /* Timer counter overflow */ -#endif - -#ifdef CONFIG_CLOCK_TIMEKEEPING - uint64_t counter_mask; -#endif -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_freerun_initialize - * - * Description: - * Initialize the freerun timer wrapper - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, - uint16_t resolution); - -/**************************************************************************** - * Name: stm32_freerun_counter - * - * Description: - * Read the counter register of the free-running timer. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -#ifndef CONFIG_CLOCK_TIMEKEEPING - -int stm32_freerun_counter(struct stm32_freerun_s *freerun, - struct timespec *ts); - -#else /* CONFIG_CLOCK_TIMEKEEPING */ - -int stm32_freerun_counter(struct stm32_freerun_s *freerun, - uint64_t *counter); - -#endif /* CONFIG_CLOCK_TIMEKEEPING */ - -/**************************************************************************** - * Name: stm32_freerun_uninitialize - * - * Description: - * Stop the free-running timer and release all resources that it uses. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* CONFIG_STM32_FREERUN */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_FREERUN_H */ diff --git a/arch/arm/src/stm32/stm32_hciuart.h b/arch/arm/src/stm32/stm32_hciuart.h deleted file mode 100644 index ccbc7af5f4d..00000000000 --- a/arch/arm/src/stm32/stm32_hciuart.h +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_hciuart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_HCIUART_H -#define __ARCH_ARM_SRC_STM32_STM32_HCIUART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -enum hciuart_devno_e -{ - HCIUART1 = 0, /* HCI UART on STM32 USART1 */ - HCIUART2 = 1, /* HCI UART on STM32 USART2 */ - HCIUART3 = 2, /* HCI UART on STM32 USART3 */ - /* UARTs 4-5 do not support RTS/CTS flow control */ - HCIUART5 = 5, /* HCI UART on STM32 USART6 */ - HCIUART6 = 6, /* HCI UART on STM32 UART7 */ - HCIUART7 = 7 /* HCI UART on STM32 UART8 */ -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: hciuart_instantiate - * - * Description: - * Obtain an instance of the HCI UART interface for the specified HCI UART - * This assumes that hciuart_initialize was called previously. - * - * Input Parameters: - * uart - Identifies the HCI UART to be configured - * - * Returned Value: - * On success, a reference to the HCI UART lower driver for the associated - * U[S]ART - * - ****************************************************************************/ - -const struct btuart_lowerhalf_s * -hciuart_instantiate(enum hciuart_devno_e uart); - -/**************************************************************************** - * Name: hciuart_initialize - * - * Description: - * Performs the low-level, one-time USART initialization. This must be - * called before hciuart_instantiate. - * - ****************************************************************************/ - -void hciuart_initialize(void); - -/**************************************************************************** - * Name: stm32_serial_dma_poll - * - * Description: - * Checks receive DMA buffers for received bytes that have not accumulated - * to the point where the DMA half/full interrupt has triggered. - * - * This function should be called from a timer or other periodic context. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_HCIUART_RXDMA -void stm32_serial_dma_poll(void); -#endif - -#endif /* __ARCH_ARM_SRC_STM32_STM32_HCIUART_H */ diff --git a/arch/arm/src/stm32/stm32_oneshot.h b/arch/arm/src/stm32/stm32_oneshot.h deleted file mode 100644 index 913321fa60e..00000000000 --- a/arch/arm/src/stm32/stm32_oneshot.h +++ /dev/null @@ -1,197 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_oneshot.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_ONESHOT_H -#define __ARCH_ARM_SRC_STM32_STM32_ONESHOT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "stm32_tim.h" - -#ifdef CONFIG_STM32_ONESHOT - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ - CONFIG_STM32_ONESHOT_MAXTIMERS < 1 -# undef CONFIG_STM32_ONESHOT_MAXTIMERS -# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 -#endif - -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 -# warning Additional logic required to handle more than 8 timers -# undef CONFIG_STM32_ONESHOT_MAXTIMERS -# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* This describes the callback function that will be invoked when the oneshot - * timer expires. The oneshot fires, the client will receive: - * - * arg - The opaque argument provided when the interrupt was registered - */ - -typedef void (*oneshot_handler_t)(void *arg); - -/* The oneshot client must allocate an instance of this structure and called - * stm32_oneshot_initialize() before using the oneshot facilities. The - * client should not access the contents of this structure directly since - * the contents are subject to change. - */ - -struct stm32_oneshot_s -{ - uint8_t chan; /* The timer/counter in use */ -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 - uint8_t cbndx; /* Timer callback handler index */ -#endif - volatile bool running; /* True: the timer is running */ - struct stm32_tim_dev_s *tch; /* Pointer returned by - * stm32_tim_init() */ - volatile oneshot_handler_t handler; /* Oneshot expiration callback */ - volatile void *arg; /* The argument that will accompany - * the callback */ - uint32_t frequency; - uint32_t period; -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_initialize - * - * Description: - * Initialize the oneshot timer wrapper - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, - uint16_t resolution); - -/**************************************************************************** - * Name: stm32_oneshot_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - ****************************************************************************/ - -int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec); - -/**************************************************************************** - * Name: stm32_oneshot_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, - oneshot_handler_t handler, void *arg, - const struct timespec *ts); - -/**************************************************************************** - * Name: stm32_oneshot_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, - struct timespec *ts); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* CONFIG_STM32_ONESHOT */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_ONESHOT_H */ diff --git a/arch/arm/src/stm32/stm32_rtc.c b/arch/arm/src/stm32/stm32_rtc.c deleted file mode 100644 index 7d191c98825..00000000000 --- a/arch/arm/src/stm32/stm32_rtc.c +++ /dev/null @@ -1,61 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_rtc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/* This file is only a thin shell that includes the correct RTC - * implementation for the selected STM32 family. The correct file cannot be - * selected by the make system because it needs the intelligence that only - * exists in chip.h that can associate an STM32 part number with an STM32 - * family. - */ - -/* The STM32 F1 has a simple battery-backed counter for its RTC and has a - * separate block for the BKP registers. - */ - -#if defined(CONFIG_STM32_STM32F10XX) -# include "stm32_rtcounter.c" - -/* The other families use a more traditional Realtime Clock/Calendar (RTCC) - * with broken-out data/time in BCD format. The backup registers are - * integrated into the RTCC in these families. - */ - -#elif defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) -# include "stm32_rtcc.c" -#elif defined(CONFIG_STM32_STM32L15XX) -# include "stm32l15xxx_rtcc.c" -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "stm32f40xxx_rtcc.c" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_uid.h b/arch/arm/src/stm32/stm32_uid.h deleted file mode 100644 index d820fcee8c6..00000000000 --- a/arch/arm/src/stm32/stm32_uid.h +++ /dev/null @@ -1,52 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_uid.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_UID_H -#define __ARCH_ARM_SRC_STM32_STM32_UID_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]); - -#endif /* __ARCH_ARM_SRC_STM32_STM32_UID_H */ diff --git a/arch/arm/src/stm32/stm32_usbdev.h b/arch/arm/src/stm32/stm32_usbdev.h deleted file mode 100644 index 350bbb234d3..00000000000 --- a/arch/arm/src/stm32/stm32_usbdev.h +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_usbdev.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_USBDEV_H -#define __ARCH_ARM_SRC_STM32_STM32_USBDEV_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include "chip.h" -#include "hardware/stm32_usbdev.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Number of endpoints */ - -#define STM32_NENDPOINTS (8) - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB - * software connect and disconnect), then the board software must provide - * stm32_pullup. See include/nuttx/usb/usbdev.h for additional description - * of this method. - * - ****************************************************************************/ - -int stm32_usbpullup(struct usbdev_s *dev, bool enable); - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. This is an opportunity for the board logic to shutdown - * clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_USBDEV_H */ diff --git a/arch/arm/src/stm32/stm32_wdg.h b/arch/arm/src/stm32/stm32_wdg.h deleted file mode 100644 index 0ad2d4eb362..00000000000 --- a/arch/arm/src/stm32/stm32_wdg.h +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_wdg.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_WDG_H -#define __ARCH_ARM_SRC_STM32_STM32_WDG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_wdg.h" - -#ifdef CONFIG_WATCHDOG - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_iwdginitialize - * - * Description: - * Initialize the IWDG watchdog time. The watchdog timer is initialized - * and registers as 'devpath. The initial state of the watchdog time is - * disabled. - * - * Input Parameters: - * devpath - The full path to the watchdog. This should be of the form - * /dev/watchdog0 - * lsifreq - The calibrated LSI clock frequency - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_IWDG -void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); -#endif - -/**************************************************************************** - * Name: stm32_wwdginitialize - * - * Description: - * Initialize the WWDG watchdog time. The watchdog timer is initializeed - * and registers as 'devpath. The initial state of the watchdog time is - * disabled. - * - * Input Parameters: - * devpath - The full path to the watchdog. This should be of the form - * /dev/watchdog0 - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_WWDG -void stm32_wwdginitialize(const char *devpath); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* CONFIG_WATCHDOG */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_WDG_H */ diff --git a/arch/arm/src/stm32f0l0g0/CMakeLists.txt b/arch/arm/src/stm32f0l0g0/CMakeLists.txt index 44b85031e93..7eca474eaf9 100644 --- a/arch/arm/src/stm32f0l0g0/CMakeLists.txt +++ b/arch/arm/src/stm32f0l0g0/CMakeLists.txt @@ -26,23 +26,15 @@ list( APPEND SRCS stm32_start.c - stm32_gpio.c - stm32_exti_gpio.c stm32_irq.c stm32_lowputc.c - stm32_serial.c stm32_lsi.c - stm32_rcc.c - stm32_uid.c) + stm32_rcc.c) if(CONFIG_STM32_RTC_LSECLOCK OR CONFIG_LCD_LSECLOCK) list(APPEND SRCS stm32_lse.c) endif() -if(CONFIG_STM32_DMA) - list(APPEND SRCS stm32_dma.c) -endif() - if(CONFIG_STM32_PWR) list(APPEND SRCS stm32_pwr.c) endif() @@ -59,77 +51,5 @@ if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32_userspace.c) endif() -if(CONFIG_STM32_PROGMEM) - list(APPEND SRCS stm32_flash.c) -endif() - -if(CONFIG_STM32_GPIOIRQ) - list(APPEND SRCS stm32_gpioint.c) -endif() - -if(CONFIG_ARCH_IRQPRIO) - list(APPEND SRCS stm32_irqprio.c) -endif() - -if(CONFIG_STM32_HAVE_HSI48) - list(APPEND SRCS stm32_hsi48.c) -endif() - -if(CONFIG_STM32_USB) - list(APPEND SRCS stm32_usbdev.c) -endif() - -if(CONFIG_STM32_I2C) - list(APPEND SRCS stm32_i2c.c) -endif() - -if(CONFIG_STM32_SPI) - list(APPEND SRCS stm32_spi.c) -endif() - -if(CONFIG_STM32_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_PULSECOUNT AND CONFIG_STM32_TIM1_PULSECOUNT) - list(APPEND SRCS stm32_pulsecount.c) -endif() - -if(CONFIG_STM32_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_AES) - list(APPEND SRCS stm32_aes.c) -endif() - -if(CONFIG_STM32_RNG) - list(APPEND SRCS stm32_rng.c) -endif() - -if(CONFIG_STM32_TIM) - list(APPEND SRCS stm32_tim.c stm32_tim_lowerhalf.c) -endif() - -if(CONFIG_STM32_IWDG) - list(APPEND SRCS stm32_iwdg.c) -endif() - -if(CONFIG_STM32_WWDG) - list(APPEND SRCS stm32_wwdg.c) -endif() - -if(CONFIG_STM32_FDCAN) - if(CONFIG_STM32_FDCAN_CHARDRIVER) - list(APPEND SRCS stm32_fdcan.c) - endif() - if(CONFIG_STM32_FDCAN_SOCKET) - list(APPEND SRCS stm32_fdcan_sock.c) - endif() -endif() - -if(CONFIG_SENSORS_QENCODER) - list(APPEND SRCS stm32_qencoder.c) -endif() - target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../common/stm32 stm32_common) diff --git a/arch/arm/src/stm32f0l0g0/Make.defs b/arch/arm/src/stm32f0l0g0/Make.defs index 8ff7580bde2..9b02c489210 100644 --- a/arch/arm/src/stm32f0l0g0/Make.defs +++ b/arch/arm/src/stm32f0l0g0/Make.defs @@ -22,17 +22,13 @@ include armv6-m/Make.defs -CHIP_CSRCS = stm32_start.c stm32_gpio.c stm32_exti_gpio.c stm32_irq.c -CHIP_CSRCS += stm32_lowputc.c stm32_serial.c stm32_rcc.c stm32_lsi.c stm32_uid.c +CHIP_CSRCS = stm32_start.c stm32_irq.c stm32_lowputc.c +CHIP_CSRCS += stm32_rcc.c stm32_lsi.c ifneq ($(CONFIG_STM32_RTC_LSECLOCK)$(CONFIG_STM32_LCD_LSECLOCK),) CHIP_CSRCS += stm32_lse.c endif -ifeq ($(CONFIG_STM32_DMA),y) -CHIP_CSRCS += stm32_dma.c -endif - ifeq ($(CONFIG_STM32_PWR),y) CHIP_CSRCS += stm32_pwr.c endif @@ -49,73 +45,4 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32_userspace.c endif -ifeq ($(CONFIG_STM32_PROGMEM),y) -CHIP_CSRCS += stm32_flash.c -endif - -ifeq ($(CONFIG_STM32_GPIOIRQ),y) -CHIP_CSRCS += stm32_gpioint.c -endif - -ifeq ($(CONFIG_STM32_HAVE_HSI48),y) -CHIP_CSRCS += stm32_hsi48.c -endif - -ifeq ($(CONFIG_STM32_USB),y) -CHIP_CSRCS += stm32_usbdev.c -endif - -ifeq ($(CONFIG_STM32_I2C),y) -CHIP_CSRCS += stm32_i2c.c -endif - -ifeq ($(CONFIG_STM32_SPI),y) -CHIP_CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_STM32_PWM),y) -CHIP_CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_PULSECOUNT),y) -ifeq ($(CONFIG_STM32_TIM1_PULSECOUNT),y) -CHIP_CSRCS += stm32_pulsecount.c -endif -endif - -ifeq ($(CONFIG_STM32_ADC),y) -CHIP_CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_AES),y) -CHIP_CSRCS += stm32_aes.c -endif - -ifeq ($(CONFIG_STM32_RNG),y) -CHIP_CSRCS += stm32_rng.c -endif - -ifeq ($(CONFIG_STM32_TIM),y) -CHIP_CSRCS += stm32_tim.c stm32_tim_lowerhalf.c -endif - -ifeq ($(CONFIG_STM32_IWDG),y) -CHIP_CSRCS += stm32_iwdg.c -endif - -ifeq ($(CONFIG_STM32_WWDG),y) -CHIP_CSRCS += stm32_wwdg.c -endif - -ifeq ($(CONFIG_STM32_FDCAN),y) -ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) -CHIP_CSRCS += stm32_fdcan.c -endif -ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) -CHIP_CSRCS += stm32_fdcan_sock.c -endif -endif - -ifeq ($(CONFIG_SENSORS_QENCODER),y) -CHIP_CSRCS += stm32_qencoder.c -endif +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h deleted file mode 100644 index f6f07839c12..00000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h +++ /dev/null @@ -1,49 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_MEMORYMAP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_STM32_STM32F03X) -# include "hardware/stm32f03x_memorymap.h" -#elif defined(CONFIG_STM32_STM32F05X) || \ - defined(CONFIG_STM32_STM32F07X) || \ - defined(CONFIG_STM32_STM32F09X) -# include "hardware/stm32f05xf07xf09x_memorymap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include "hardware/stm32l0_memorymap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include "hardware/stm32g0_memorymap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# include "hardware/stm32c0_memorymap.h" -#else -# error "Unsupported STM32 M0 memory map" -#endif - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h deleted file mode 100644 index 3f1e617b3cb..00000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h +++ /dev/null @@ -1,51 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PINMAP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_STM32_STM32F03X) -# include "hardware/stm32f03x_pinmap.h" -#elif defined(CONFIG_STM32_STM32F05X) -# include "hardware/stm32f05x_pinmap.h" -#elif defined(CONFIG_STM32_STM32F07X) -# include "hardware/stm32f07x_pinmap.h" -#elif defined(CONFIG_STM32_STM32F09X) -# include "hardware/stm32f09x_pinmap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include "hardware/stm32l0_pinmap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include "hardware/stm32g0_pinmap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# include "hardware/stm32c0_pinmap.h" -#else -# error "Unsupported STM32 M0 pin map" -#endif - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_aes.h b/arch/arm/src/stm32f0l0g0/stm32_aes.h deleted file mode 100644 index f499aa8b95d..00000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_aes.h +++ /dev/null @@ -1,50 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_aes.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_AES_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_AES_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "chip.h" - -#include "hardware/stm32_aes.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_AES_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma.h b/arch/arm/src/stm32f0l0g0/stm32_dma.h deleted file mode 100644 index ce5cb1a18af..00000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_dma.h +++ /dev/null @@ -1,327 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_dma.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_DMA_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_DMA_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "hardware/stm32_dma_v1.h" - -#ifdef CONFIG_STM32_HAVE_DMAMUX -# include "hardware/stm32_dmamux.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* These definitions provide the bit encoding of the 'status' parameter - * passed to the DMA callback function (see dma_callback_t). - */ - -#define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */ -#define DMA_STATUS_HTIF DMA_CHAN_HTIF_BIT /* Channel Half Transfer */ -#define DMA_STATUS_TCIF DMA_CHAN_TCIF_BIT /* Channel Transfer Complete */ - -#define DMA_STATUS_ERROR (DMA_STATUS_TEIF) -#define DMA_STATUS_SUCCESS (DMA_STATUS_TCIF | DMA_STATUS_HTIF) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* DMA_HANDLE provides an opaque reference that can be used to represent a - * DMA channel (F1) or a DMA stream (F4). - */ - -typedef void *DMA_HANDLE; - -/* Description: - * This is the type of the callback that is used to inform the user of the - * completion of the DMA. - * - * Input Parameters: - * handle - Refers to the DMA channel or stream - * status - A bit encoded value that provides the completion status. See - * the DMASTATUS_* definitions above. - * arg - A user-provided value that was provided when stm32_dmastart() - * was called. - */ - -typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg); - -#ifdef CONFIG_DEBUG_DMA_INFO -struct stm32_dmaregs_s -{ - uint32_t isr; - uint32_t ccr; - uint32_t cndtr; - uint32_t cpar; - uint32_t cmar; -}; -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dmachannel - * - * Description: - * Allocate a DMA channel. This function gives the caller mutually - * exclusive access to the DMA channel specified by the 'chan' argument. - * DMA channels are shared on the STM32: Devices sharing the same DMA - * channel cannot do DMA concurrently! See the DMACHAN_* definitions in - * stm32_dma.h. - * - * If the DMA channel is not available, then stm32_dmachannel() will wait - * until the holder of the channel relinquishes the channel by calling - * stm32_dmafree(). WARNING: If you have two devices sharing a DMA - * channel and the code never releases the channel, the stm32_dmachannel - * call for the other will hang forever in this function! Don't let your - * design do that! - * - * Hmm.. I suppose this interface could be extended to make a non-blocking - * version. Feel free to do that if that is what you need. - * - * Input Parameters: - * chan - Identifies the stream/channel resource - * For the STM32 F1, this is simply the channel number as provided by - * the DMACHAN_* definitions in chip/stm32f10xxx_dma.h. - * For the STM32 F4, this is a bit encoded value as provided by the - * the DMAMAP_* definitions in chip/stm32f40xxx_dma.h - * - * Returned Value: - * Provided that 'chan' is valid, this function ALWAYS returns a non-NULL, - * void* DMA channel handle. (If 'chan' is invalid, the function will - * assert if debug is enabled or do something ignorant otherwise). - * - * Assumptions: - * - The caller does not hold he DMA channel. - * - The caller can wait for the DMA channel to be freed if it is no - * available. - * - ****************************************************************************/ - -DMA_HANDLE stm32_dmachannel(unsigned int chan); - -/**************************************************************************** - * Name: stm32_dmafree - * - * Description: - * Release a DMA channel. If another thread is waiting for this DMA - * channel in a call to stm32_dmachannel, then this function will - * re-assign the DMA channel to that thread and wake it up. - * - * NOTE: The 'handle' used in this argument must NEVER be used again - * until stm32_dmachannel() is called again to re-gain access to - * the channel. - * - * Returned Value: - * None - * - * Assumptions: - * - The caller holds the DMA channel. - * - There is no DMA in progress - * - ****************************************************************************/ - -void stm32_dmafree(DMA_HANDLE handle); - -/**************************************************************************** - * Name: stm32_dmasetup - * - * Description: - * Configure DMA before using - * - ****************************************************************************/ - -void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, - size_t ntransfers, uint32_t ccr); - -/**************************************************************************** - * Name: stm32_dmastart - * - * Description: - * Start the DMA transfer - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - No DMA in progress - * - ****************************************************************************/ - -void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, - bool half); - -/**************************************************************************** - * Name: stm32_dmastop - * - * Description: - * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is - * reset and stm32_dmasetup() must be called before stm32_dmastart() can - * be called again - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -void stm32_dmastop(DMA_HANDLE handle); - -/**************************************************************************** - * Name: stm32_dmaresidual - * - * Description: - * Returns the number of bytes remaining to be transferred - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -size_t stm32_dmaresidual(DMA_HANDLE handle); - -/**************************************************************************** - * Name: stm32_dmacapable - * - * Description: - * Check if the DMA controller can transfer data to/from given memory - * address with the given configuration. This depends on the internal - * connections in the ARM bus matrix of the processor. Note that this - * only applies to memory addresses, it will return false for any - * peripheral address. - * - * Returned Value: - * True, if transfer is possible. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_DMACAPABLE -bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); -#else -# define stm32_dmacapable(maddr, count, ccr) (true) -#endif - -/**************************************************************************** - * Name: stm32_dmasample - * - * Description: - * Sample DMA register contents - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); -#else -# define stm32_dmasample(handle,regs) -#endif - -/**************************************************************************** - * Name: stm32_dmadump - * - * Description: - * Dump previously sampled DMA register contents - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, - const char *msg); -#else -# define stm32_dmadump(handle,regs,msg) -#endif - -/* High performance, zero latency DMA interrupts need some additional - * interfaces. - * - * TODO: For now the interface is different for STM32 DMAv1 and STM32 DMAv2. - * It should be unified somehow. - */ - -#ifdef CONFIG_ARCH_HIPRI_INTERRUPT - -/**************************************************************************** - * Name: stm32_dma_intack - * - * Description: - * Public visible interface to acknowledge interrupts on DMA channel - * - ****************************************************************************/ - -#if defined(HAVE_IP_DMA_V1) -void stm32_dma_intack(unsigned int chndx, uint32_t isr); -#elif defined(HAVE_IP_DMA_V2) -void stm32_dma_intack(unsigned int controller, uint8_t stream, uint32_t isr); -#endif - -/**************************************************************************** - * Name: stm32_dma_intget - * - * Description: - * Public visible interface to get pending interrupts from DMA channel - * - ****************************************************************************/ - -#if defined(HAVE_IP_DMA_V1) -uint32_t stm32_dma_intget(unsigned int chndx); -#elif defined(HAVE_IP_DMA_V2) -uint8_t stm32_dma_intget(unsigned int controller, uint8_t stream); -#endif - -#endif /* CONFIG_ARCH_HIPRI_INTERRUPT */ - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_DMA_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_exti.h b/arch/arm/src/stm32f0l0g0/stm32_exti.h deleted file mode 100644 index 33156f0dece..00000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_exti.h +++ /dev/null @@ -1,131 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_exti.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_EXTI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "chip.h" -#include "hardware/stm32_exti.h" - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpiosetevent - * - * Description: - * Sets/clears GPIO based event and interrupt triggers. - * - * Input Parameters: - * - pinset: gpio pin configuration - * - rising/falling edge: enables - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func, void *arg); - -/**************************************************************************** - * Name: stm32_exti_alarm - * - * Description: - * Sets/clears EXTI alarm interrupt. - * - * Input Parameters: - * - rising/falling edge: enables interrupt on rising/falling edges - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -int stm32_exti_alarm(bool risingedge, bool fallingedge, - bool event, xcpt_t func, - void *arg); -#endif - -/**************************************************************************** - * Name: stm32_exti_wakeup - * - * Description: - * Sets/clears EXTI wakeup interrupt. - * - * Input Parameters: - * - rising/falling edge: enables interrupt on rising/falling edges - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_PERIODIC -int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, - xcpt_t func, void *arg); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_fdcan.h b/arch/arm/src/stm32f0l0g0/stm32_fdcan.h deleted file mode 100644 index 83893b284ef..00000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_fdcan.h +++ /dev/null @@ -1,112 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_fdcan.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_FDCAN_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_FDCAN_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_fdcan.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Port numbers for use with stm32_fdcan_initialize() */ - -#define FDCAN1 1 - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef CONFIG_STM32_FDCAN_CHARDRIVER - -/**************************************************************************** - * Name: stm32_fdcaninitialize - * - * Description: - * Initialize the selected FDCAN port - * - * Input Parameters: - * Port number (for hardware that has multiple FDCAN interfaces) - * - * Returned Value: - * Valid FDCAN device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct can_dev_s *stm32_fdcaninitialize(int port); -#endif - -#ifdef CONFIG_STM32_FDCAN_SOCKET - -/**************************************************************************** - * Name: stm32_fdcansockinitialize - * - * Description: - * Initialize the selected FDCAN port as SocketCAN interface - * - * Input Parameters: - * Port number (for hardware that has multiple FDCAN interfaces) - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int stm32_fdcansockinitialize(int port); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_FDCAN_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_i2c.h b/arch/arm/src/stm32f0l0g0/stm32_i2c.h deleted file mode 100644 index 9d1d09b17a9..00000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_i2c.h +++ /dev/null @@ -1,91 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_i2c.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_I2C_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_I2C_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "chip.h" -#include "hardware/stm32_i2c.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* If a dynamic timeout is selected, then a non-negative, non-zero micro- - * seconds per byte value must be provided as well. - */ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO -# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32_I2C_DYNTIMEO -# endif -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2cbus_initialize - * - * Description: - * Initialize the selected I2C port. And return a unique instance of struct - * struct i2c_master_s. This function may be called to obtain multiple - * instances of the interface, each of which may be set up with a - * different frequency and slave address. - * - * Input Parameters: - * Port number (for hardware that has multiple I2C interfaces) - * - * Returned Value: - * Valid I2C device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct i2c_master_s *stm32_i2cbus_initialize(int port); - -/**************************************************************************** - * Name: stm32_i2cbus_uninitialize - * - * Description: - * De-initialize the selected I2C port, and power down the device. - * - * Input Parameters: - * Device structure as returned by the stm32_i2cbus_initialize() - * - * Returned Value: - * OK on success, ERROR when internal reference count mismatch or dev - * points to invalid hardware device. - * - ****************************************************************************/ - -int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_I2C_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pulsecount.h b/arch/arm/src/stm32f0l0g0/stm32_pulsecount.h deleted file mode 100644 index 8c8aca535f1..00000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_pulsecount.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pulsecount.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_PULSECOUNT_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_PULSECOUNT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer); - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_PULSECOUNT_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_qencoder.h b/arch/arm/src/stm32f0l0g0/stm32_qencoder.h deleted file mode 100644 index c46fbdf9135..00000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_qencoder.h +++ /dev/null @@ -1,116 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_qencoder.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_QENCODER_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_QENCODER_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -#ifdef CONFIG_SENSORS_QENCODER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Timer devices may be used for different purposes. One special purpose is - * as a quadrature encoder input device. If CONFIG_STM32_TIMn is - * defined then the CONFIG_STM32_TIMn_QE must also be defined to - * indicate that timer "n" is intended to be used for as a quadrature - * encoder. - */ - -#ifndef CONFIG_STM32_TIM1 -# undef CONFIG_STM32_TIM1_QE -#endif -#ifndef CONFIG_STM32_TIM2 -# undef CONFIG_STM32_TIM2_QE -#endif -#ifndef CONFIG_STM32_TIM3 -# undef CONFIG_STM32_TIM3_QE -#endif -#ifndef CONFIG_STM32_TIM4 -# undef CONFIG_STM32_TIM4_QE -#endif - -/* Only timers 1-4 can be used as a quadrature encoder (timers with - * encoder mode support). - * TIM6, TIM7, TIM14-17 are basic/general purpose timers without encoder - * capability. - */ - -#undef CONFIG_STM32_TIM6_QE -#undef CONFIG_STM32_TIM7_QE -#undef CONFIG_STM32_TIM14_QE -#undef CONFIG_STM32_TIM15_QE -#undef CONFIG_STM32_TIM16_QE -#undef CONFIG_STM32_TIM17_QE - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_qeinitialize - * - * Description: - * Initialize a quadrature encoder interface. - * This function must be called from board-specific logic. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. - * 'tim' must be an element of {1,2,3,4} - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qeinitialize(const char *devpath, int tim); - -#ifdef CONFIG_STM32_QENCODER_INDEX_PIN -/**************************************************************************** - * Name: stm32_qe_index_init - * - * Description: - * Register the encoder index pin to a given Qencoder timer - * - * Input Parameters: - * tim - The qenco timer number - * gpio - gpio pin configuration - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qe_index_init(int tim, uint32_t gpio); -#endif - -#endif /* CONFIG_SENSORS_QENCODER */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_QENCODER_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_spi.h b/arch/arm/src/stm32f0l0g0/stm32_spi.h deleted file mode 100644 index dd99c76575a..00000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_spi.h +++ /dev/null @@ -1,171 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_spi.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_SPI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_SPI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_spi.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -struct spi_dev_s; - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spibus_initialize - * - * Description: - * Initialize the selected SPI bus - * - * Input Parameters: - * bus number (for hardware that has multiple SPI interfaces) - * - * Returned Value: - * Valid SPI device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct spi_dev_s *stm32_spibus_initialize(int bus); - -/**************************************************************************** - * Name: stm32_spi1/2/...select and stm32_spi1/2/...status - * - * Description: - * The external functions, stm32_spi1/2/...select, stm32_spi1/2/...status, - * and stm32_spi1/2/...cmddata must be provided by board-specific logic. - * These are implementations of the select, status, and cmddata methods of - * the SPI interface defined by struct spi_ops_s - * (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_board_initialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status() - * functions in your board-specific logic. These functions will perform - * chip selection and status operations using GPIOs in the way your - * board is configured. - * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, - * then provide stm32_spi1/2/...cmddata() functions in your - * board-specific logic. These functions will perform cmd/data selection - * operations using GPIOs in the way your board is configured. - * 4. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 5. The handle returned by stm32_spibus_initialize() may then be used - * to bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver - * to the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected); -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected); -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, - bool selected); -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); -#endif - -/**************************************************************************** - * Name: stm32_spi1/2/...register - * - * Description: - * If the board supports a card detect callback to inform the SPI-based - * MMC/SD driver when an SD card is inserted or removed, then - * CONFIG_SPI_CALLBACK should be defined and the following function(s) - * must be implemented. These functions implements the registercallback - * method of the SPI interface (see include/nuttx/spi/spi.h for details) - * - * Input Parameters: - * dev - Device-specific state data - * callback - The function to call on the media change - * arg - A caller provided value to return with the callback - * - * Returned Value: - * 0 on success; negated errno on failure. - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg); -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg); -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg); -#endif -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_SPI_H */