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arch/arm/src/stm32f0l0:  Some fixes for a clean build.  Still have a problem with lots of error messages coming from kconfig-mconf, but the configuation looks fine.  Sometimes kconfig errors are difficult to spot.  I would appreciate it anyone can spot the issue.

    arch/arm/src/stm32f0l0/hardware:  Rename the chip directory to hardware.  This will hopefully eliminate some problems that I have seen with the chip include paths not being unique in more complex configuartions.

    configs/nucleo-f072rb, configs/nucleo-f091rc, configs/stm32f051-discovery, and configs/stm32f072-discovery:  Update for all of the naming changes made in arch/arm/src/stm32f0l0

    arch/arm/include/stm32f0l0:  Rename stm32f0 to stm32f0l0 to make a speace for STM32 L0.  Rename files, functions and defines, removeing the f0_ from the names in order to make them MCU agnostic.

    arch/arm/src/stm32f0l0:  Rename stm32f0 to stm32f0l0 to make a speace for STM32 L0.  Rename files, functions and defines, removeing the f0_ from the names in order to make them MCU agnostic.
This commit is contained in:
Gregory Nutt 2018-12-16 10:50:16 -06:00
parent 4a1400dc6e
commit b4ab6bc7f2
90 changed files with 6373 additions and 6198 deletions
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15
arch/arm/Kconfig
View file

@ -304,7 +304,13 @@ config ARCH_CHIP_STM32F0
bool "STMicro STM32 F0"
select ARCH_CORTEXM0
---help---
STMicro STM32 architectures (ARM Cortex-M0).
STMicro STM32F0 architectures (ARM Cortex-M0).
config ARCH_CHIP_STM32L0
bool "STMicro STM32 L0"
select ARCH_CORTEXM0
---help---
STMicro STM32L0 architectures (ARM Cortex-M0).
config ARCH_CHIP_STM32F7
bool "STMicro STM32 F7"
@ -616,7 +622,7 @@ config ARCH_CHIP
default "sam34" if ARCH_CHIP_SAM34
default "samv7" if ARCH_CHIP_SAMV7
default "stm32" if ARCH_CHIP_STM32
default "stm32f0" if ARCH_CHIP_STM32F0
default "stm32f0l0" if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0
default "stm32f7" if ARCH_CHIP_STM32F7
default "stm32h7" if ARCH_CHIP_STM32H7
default "stm32l4" if ARCH_CHIP_STM32L4
@ -871,7 +877,10 @@ if ARCH_CHIP_STM32
source arch/arm/src/stm32/Kconfig
endif
if ARCH_CHIP_STM32F0
source arch/arm/src/stm32f0/Kconfig
source arch/arm/src/stm32f0l0/Kconfig
endif
if ARCH_CHIP_STM32L0
source arch/arm/src/stm32f0l0/Kconfig
endif
if ARCH_CHIP_STM32F7
source arch/arm/src/stm32f7/Kconfig

264
arch/arm/include/stm32f0/chip.h
View file

@ -1,264 +0,0 @@
/************************************************************************************
* arch/arm/include/stm32f0/chip.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_STM32F0_CHIP_H
#define __ARCH_ARM_INCLUDE_STM32F0_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Get customizations for each supported chip */
#if defined(CONFIG_ARCH_CHIP_STM32F051R8)
# define STM32F051x 1 /* STM32F051x family */
# undef STM32F072x /* Not STM32F072x family */
# undef STM32F091x /* Not STM32F091x family */
# define STM32F0_FLASH_SIZE (64*1024) /* 64Kb */
# define STM32F0_SRAM_SIZE (8*1024) /* 8Kb */
# define STM32F0_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32F0_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32F0_NI2C 2 /* Two I2C modules */
# define STM32F0_NUSART 2 /* Two USARTs modules */
# define STM32F0_NCAN 0 /* No CAN controllers */
# define STM32F0_NUSBDEV 1 /* One USB device controller */
# define STM32F0_NDAC 1 /* One DAC module */
# define STM32F0_NDACCHAN 1 /* One DAC channels */
# define STM32F0_NCOMP 2 /* Two Analog Comparators */
# define STM32F0_NCAP 13 /* Capacitive sensing channels (14 on UFQFPN32)) */
# define STM32F0_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#elif defined(CONFIG_ARCH_CHIP_STM32F072C8) || defined(CONFIG_ARCH_CHIP_STM32F072CB)
# undef STM32F051x /* Not STM32F051x family */
# define STM32F072x 1 /* STM32F072x family */
# undef STM32F091x /* Not STM32F091x family */
# ifdef CONFIG_ARCH_CHIP_STM32F072C8
# define STM32F0_FLASH_SIZE (64*1024) /* 64Kb */
# else
# define STM32F0_FLASH_SIZE (128*1024) /* 128Kb */
# endif
# define STM32F0_SRAM_SIZE (16*1024) /* 16Kb */
# define STM32F0_NATIM 1 /* One advanced timer TIM1 */
# define STM32F0_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
# define STM32F0_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
# define STM32F0_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
# define STM32F0_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32F0_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32F0_NI2C 2 /* Two I2C modules */
# define STM32F0_NUSART 4 /* Four USARTs module */
# define STM32F0_NCAN 1 /* One CAN controller */
# define STM32F0_NUSBDEV 1 /* One USB device controller */
# define STM32F0_NCEC 1 /* One HDMI-CEC controller */
# define STM32F0_NADC12 1 /* One 12-bit module */
# define STM32F0_NADCCHAN 10 /* Ten external channels */
# define STM32F0_NADCINT 3 /* Three internal channels */
# define STM32F0_NDAC 1 /* One DAC module */
# define STM32F0_NDACCHAN 2 /* Two DAC channels */
# define STM32F0_NCOMP 2 /* Two Analog Comparators */
# define STM32F0_NCAP 17 /* Capacitive sensing channels */
# define STM32F0_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#elif defined(CONFIG_ARCH_CHIP_STM32F072R8) || defined(CONFIG_ARCH_CHIP_STM32F072RB)
# undef STM32F051x /* Not STM32F051x family */
# define STM32F072x 1 /* STM32F072x family */
# undef STM32F091x /* Not STM32F091x family */
# ifdef CONFIG_ARCH_CHIP_STM32F072R8
# define STM32F0_FLASH_SIZE (64*1024) /* 64Kb */
# else
# define STM32F0_FLASH_SIZE (128*1024) /* 128Kb */
# endif
# define STM32F0_SRAM_SIZE (16*1024) /* 16Kb */
# define STM32F0_NATIM 1 /* One advanced timer TIM1 */
# define STM32F0_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
# define STM32F0_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
# define STM32F0_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
# define STM32F0_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32F0_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32F0_NI2C 2 /* Two I2C modules */
# define STM32F0_NUSART 4 /* Four USARTs module */
# define STM32F0_NCAN 1 /* One CAN controller */
# define STM32F0_NUSBDEV 1 /* One USB device controller */
# define STM32F0_NCEC 1 /* One HDMI-CEC controller */
# define STM32F0_NADC12 1 /* One 12-bit module */
# define STM32F0_NADCCHAN 16 /* 16 external channels */
# define STM32F0_NADCINT 3 /* Three internal channels */
# define STM32F0_NDAC 1 /* One DAC module */
# define STM32F0_NDACCHAN 2 /* Two DAC channels */
# define STM32F0_NCOMP 2 /* Two Analog Comparators */
# define STM32F0_NCAP 18 /* Capacitive sensing channels */
# define STM32F0_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#elif defined(CONFIG_ARCH_CHIP_STM32F072V8) || defined(CONFIG_ARCH_CHIP_STM32F072VB)
# undef STM32F051x /* Not STM32F051x family */
# define STM32F072x 1 /* STM32F072x family */
# undef STM32F091x /* Not STM32F091x family */
# ifdef CONFIG_ARCH_CHIP_STM32F072V8
# define STM32F0_FLASH_SIZE (64*1024) /* 64Kb */
# else
# define STM32F0_FLASH_SIZE (128*1024) /* 128Kb */
# endif
# define STM32F0_SRAM_SIZE (16*1024) /* 16Kb */
# define STM32F0_NATIM 1 /* One advanced timer TIM1 */
# define STM32F0_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
# define STM32F0_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
# define STM32F0_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
# define STM32F0_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32F0_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32F0_NI2C 2 /* Two I2C modules */
# define STM32F0_NUSART 4 /* Four USARTs module */
# define STM32F0_NCAN 1 /* One CAN controller */
# define STM32F0_NUSBDEV 1 /* One USB device controller */
# define STM32F0_NCEC 1 /* One HDMI-CEC controller */
# define STM32F0_NADC12 1 /* One 12-bit module */
# define STM32F0_NADCCHAN 16 /* 16 external channels */
# define STM32F0_NADCINT 3 /* Three internal channels */
# define STM32F0_NDAC 1 /* One DAC module */
# define STM32F0_NDACCHAN 2 /* Two DAC channels */
# define STM32F0_NCOMP 2 /* Two Analog Comparators */
# define STM32F0_NCAP 24 /* Capacitive sensing channels */
# define STM32F0_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#elif defined(CONFIG_ARCH_CHIP_STM32F091CB) || defined(CONFIG_ARCH_CHIP_STM32F091CC)
# undef STM32F051x /* Not STM32F051x family */
# undef STM32F072x /* Not STM32F072x family */
# define STM32F091x 1 /* STM32F091x family */
# ifdef CONFIG_ARCH_CHIP_STM32F091CB
# define STM32F0_FLASH_SIZE (128*1024) /* 128Kb */
# else
# define STM32F0_FLASH_SIZE (256*1024) /* 256Kb */
# endif
# define STM32F0_SRAM_SIZE (32*1024) /* 32Kb */
# define STM32F0_NATIM 1 /* One advanced timer TIM1 */
# define STM32F0_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
# define STM32F0_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
# define STM32F0_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
# define STM32F0_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32F0_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32F0_NI2C 2 /* Two I2C modules */
# define STM32F0_NUSART 6 /* Six USARTs modules */
# define STM32F0_NCAN 1 /* One CAN controller */
# define STM32F0_NUSBDEV 0 /* No USB device controller */
# define STM32F0_NCEC 1 /* One HDMI-CEC controller */
# define STM32F0_NADC12 1 /* One 12-bit module */
# define STM32F0_NADCCHAN 10 /* 10 external channels */
# define STM32F0_NADCINT 3 /* Three internal channels */
# define STM32F0_NDAC 1 /* One DAC module */
# define STM32F0_NDACCHAN 2 /* Two DAC channels */
# define STM32F0_NCOMP 2 /* Two Analog Comparators */
# define STM32F0_NCAP 17 /* Capacitive sensing channels */
# define STM32F0_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#elif defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091RC) \
|| defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC)
# undef STM32F051x /* Not STM32F051x family */
# undef STM32F072x /* Not STM32F072x family */
# define STM32F091x 1 /* STM32F091x family */
# if defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091VB)
# define STM32F0_FLASH_SIZE (128*1024) /* 128Kb */
# else
# define STM32F0_FLASH_SIZE (256*1024) /* 256Kb */
# endif
# define STM32F0_SRAM_SIZE (32*1024) /* 32Kb */
# define STM32F0_NATIM 1 /* One advanced timer TIM1 */
# define STM32F0_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
# define STM32F0_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
# define STM32F0_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
# define STM32F0_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32F0_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32F0_NI2C 2 /* Two I2C modules */
# define STM32F0_NUSART 8 /* Eight USARTs modules */
# define STM32F0_NCAN 1 /* One CAN controller */
# define STM32F0_NUSBDEV 0 /* No USB device controller */
# define STM32F0_NCEC 1 /* One HDMI-CEC controller */
# define STM32F0_NADC12 1 /* One 12-bit module */
# define STM32F0_NADCCHAN 16 /* 16 external channels */
# define STM32F0_NADCINT 3 /* Three internal channels */
# define STM32F0_NDAC 1 /* One DAC module */
# define STM32F0_NDACCHAN 2 /* Two DAC channels */
# define STM32F0_NCOMP 2 /* Two Analog Comparators */
# if defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC)
# define STM32F0_NCAP 24 /* Capacitive sensing channels */
# else
# define STM32F0_NCAP 18 /* Capacitive sensing channels */
# endif
# define STM32F0_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#else
# error "Unsupported STM32F0xx chip"
#endif
/* NVIC priority levels *************************************************************/
/* Each priority field holds a priority value, 0-31. The lower the value, the greater
* the priority of the corresponding interrupt. The processor implements only
* bits[7:6] of each field, bits[5:0] read as zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_STM32F0_CHIP_H */

264
arch/arm/include/stm32f0l0/chip.h Normal file
View file

@ -0,0 +1,264 @@
/************************************************************************************
* arch/arm/include/stm32f0l0/chip.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_CHIP_H
#define __ARCH_ARM_INCLUDE_STM32F0L0_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Get customizations for each supported chip */
#if defined(CONFIG_ARCH_CHIP_STM32F051R8)
# define STM32F051x 1 /* STM32F051x family */
# undef STM32F072x /* Not STM32F072x family */
# undef STM32F091x /* Not STM32F091x family */
# define STM32_FLASH_SIZE (64*1024) /* 64Kb */
# define STM32_SRAM_SIZE (8*1024) /* 8Kb */
# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32_NI2C 2 /* Two I2C modules */
# define STM32_NUSART 2 /* Two USARTs modules */
# define STM32_NCAN 0 /* No CAN controllers */
# define STM32_NUSBDEV 1 /* One USB device controller */
# define STM32_NDAC 1 /* One DAC module */
# define STM32_NDACCHAN 1 /* One DAC channels */
# define STM32_NCOMP 2 /* Two Analog Comparators */
# define STM32_NCAP 13 /* Capacitive sensing channels (14 on UFQFPN32)) */
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#elif defined(CONFIG_ARCH_CHIP_STM32F072C8) || defined(CONFIG_ARCH_CHIP_STM32F072CB)
# undef STM32F051x /* Not STM32F051x family */
# define STM32F072x 1 /* STM32F072x family */
# undef STM32F091x /* Not STM32F091x family */
# ifdef CONFIG_ARCH_CHIP_STM32F072C8
# define STM32_FLASH_SIZE (64*1024) /* 64Kb */
# else
# define STM32_FLASH_SIZE (128*1024) /* 128Kb */
# endif
# define STM32_SRAM_SIZE (16*1024) /* 16Kb */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32_NI2C 2 /* Two I2C modules */
# define STM32_NUSART 4 /* Four USARTs module */
# define STM32_NCAN 1 /* One CAN controller */
# define STM32_NUSBDEV 1 /* One USB device controller */
# define STM32_NCEC 1 /* One HDMI-CEC controller */
# define STM32_NADC12 1 /* One 12-bit module */
# define STM32_NADCCHAN 10 /* Ten external channels */
# define STM32_NADCINT 3 /* Three internal channels */
# define STM32_NDAC 1 /* One DAC module */
# define STM32_NDACCHAN 2 /* Two DAC channels */
# define STM32_NCOMP 2 /* Two Analog Comparators */
# define STM32_NCAP 17 /* Capacitive sensing channels */
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#elif defined(CONFIG_ARCH_CHIP_STM32F072R8) || defined(CONFIG_ARCH_CHIP_STM32F072RB)
# undef STM32F051x /* Not STM32F051x family */
# define STM32F072x 1 /* STM32F072x family */
# undef STM32F091x /* Not STM32F091x family */
# ifdef CONFIG_ARCH_CHIP_STM32F072R8
# define STM32_FLASH_SIZE (64*1024) /* 64Kb */
# else
# define STM32_FLASH_SIZE (128*1024) /* 128Kb */
# endif
# define STM32_SRAM_SIZE (16*1024) /* 16Kb */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32_NI2C 2 /* Two I2C modules */
# define STM32_NUSART 4 /* Four USARTs module */
# define STM32_NCAN 1 /* One CAN controller */
# define STM32_NUSBDEV 1 /* One USB device controller */
# define STM32_NCEC 1 /* One HDMI-CEC controller */
# define STM32_NADC12 1 /* One 12-bit module */
# define STM32_NADCCHAN 16 /* 16 external channels */
# define STM32_NADCINT 3 /* Three internal channels */
# define STM32_NDAC 1 /* One DAC module */
# define STM32_NDACCHAN 2 /* Two DAC channels */
# define STM32_NCOMP 2 /* Two Analog Comparators */
# define STM32_NCAP 18 /* Capacitive sensing channels */
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#elif defined(CONFIG_ARCH_CHIP_STM32F072V8) || defined(CONFIG_ARCH_CHIP_STM32F072VB)
# undef STM32F051x /* Not STM32F051x family */
# define STM32F072x 1 /* STM32F072x family */
# undef STM32F091x /* Not STM32F091x family */
# ifdef CONFIG_ARCH_CHIP_STM32F072V8
# define STM32_FLASH_SIZE (64*1024) /* 64Kb */
# else
# define STM32_FLASH_SIZE (128*1024) /* 128Kb */
# endif
# define STM32_SRAM_SIZE (16*1024) /* 16Kb */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32_NI2C 2 /* Two I2C modules */
# define STM32_NUSART 4 /* Four USARTs module */
# define STM32_NCAN 1 /* One CAN controller */
# define STM32_NUSBDEV 1 /* One USB device controller */
# define STM32_NCEC 1 /* One HDMI-CEC controller */
# define STM32_NADC12 1 /* One 12-bit module */
# define STM32_NADCCHAN 16 /* 16 external channels */
# define STM32_NADCINT 3 /* Three internal channels */
# define STM32_NDAC 1 /* One DAC module */
# define STM32_NDACCHAN 2 /* Two DAC channels */
# define STM32_NCOMP 2 /* Two Analog Comparators */
# define STM32_NCAP 24 /* Capacitive sensing channels */
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#elif defined(CONFIG_ARCH_CHIP_STM32F091CB) || defined(CONFIG_ARCH_CHIP_STM32F091CC)
# undef STM32F051x /* Not STM32F051x family */
# undef STM32F072x /* Not STM32F072x family */
# define STM32F091x 1 /* STM32F091x family */
# ifdef CONFIG_ARCH_CHIP_STM32F091CB
# define STM32_FLASH_SIZE (128*1024) /* 128Kb */
# else
# define STM32_FLASH_SIZE (256*1024) /* 256Kb */
# endif
# define STM32_SRAM_SIZE (32*1024) /* 32Kb */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32_NI2C 2 /* Two I2C modules */
# define STM32_NUSART 6 /* Six USARTs modules */
# define STM32_NCAN 1 /* One CAN controller */
# define STM32_NUSBDEV 0 /* No USB device controller */
# define STM32_NCEC 1 /* One HDMI-CEC controller */
# define STM32_NADC12 1 /* One 12-bit module */
# define STM32_NADCCHAN 10 /* 10 external channels */
# define STM32_NADCINT 3 /* Three internal channels */
# define STM32_NDAC 1 /* One DAC module */
# define STM32_NDACCHAN 2 /* Two DAC channels */
# define STM32_NCOMP 2 /* Two Analog Comparators */
# define STM32_NCAP 17 /* Capacitive sensing channels */
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#elif defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091RC) \
|| defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC)
# undef STM32F051x /* Not STM32F051x family */
# undef STM32F072x /* Not STM32F072x family */
# define STM32F091x 1 /* STM32F091x family */
# if defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091VB)
# define STM32_FLASH_SIZE (128*1024) /* 128Kb */
# else
# define STM32_FLASH_SIZE (256*1024) /* 256Kb */
# endif
# define STM32_SRAM_SIZE (32*1024) /* 32Kb */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32_NI2C 2 /* Two I2C modules */
# define STM32_NUSART 8 /* Eight USARTs modules */
# define STM32_NCAN 1 /* One CAN controller */
# define STM32_NUSBDEV 0 /* No USB device controller */
# define STM32_NCEC 1 /* One HDMI-CEC controller */
# define STM32_NADC12 1 /* One 12-bit module */
# define STM32_NADCCHAN 16 /* 16 external channels */
# define STM32_NADCINT 3 /* Three internal channels */
# define STM32_NDAC 1 /* One DAC module */
# define STM32_NDACCHAN 2 /* Two DAC channels */
# define STM32_NCOMP 2 /* Two Analog Comparators */
# if defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC)
# define STM32_NCAP 24 /* Capacitive sensing channels */
# else
# define STM32_NCAP 18 /* Capacitive sensing channels */
# endif
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#else
# error "Unsupported STM32F0xx chip"
#endif
/* NVIC priority levels *************************************************************/
/* Each priority field holds a priority value, 0-31. The lower the value, the greater
* the priority of the corresponding interrupt. The processor implements only
* bits[7:6] of each field, bits[5:0] read as zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_CHIP_H */

74
arch/arm/include/stm32f0/irq.h → arch/arm/include/stm32f0l0/irq.h
View file

@ -38,8 +38,8 @@
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_STM32F0_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F0_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F0L0_IRQ_H
/****************************************************************************
* Included Files
@ -48,11 +48,12 @@
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
#include <arch/stm32f0/chip.h>
#include <arch/stm32f0l0/chip.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
@ -60,55 +61,32 @@
/* Common Processor Exceptions (vectors 0-15) */
#define STM32F0_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define STM32F0_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define STM32F0_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
/* Vectors 4-10: Reserved */
#define STM32F0_IRQ_SVCALL (11) /* Vector 11: SVC call */
/* Vector 12-13: Reserved */
#define STM32F0_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define STM32F0_IRQ_SYSTICK (15) /* Vector 15: System tick */
#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
/* Vectors 4-10: Reserved */
#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */
/* Vector 12-13: Reserved */
#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16) */
#define STM32F0_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
#define STM32F0_IRQ_WWDG (16) /* Vector 16: WWDG */
#define STM32F0_IRQ_PVD_VDDIO2 (17) /* Vector 17: PVD_VDDIO2 */
#define STM32F0_IRQ_RTC (18) /* Vector 18: RTC */
#define STM32F0_IRQ_FLASH (19) /* Vector 19: FLASH */
#define STM32F0_IRQ_RCC_CRS (20) /* Vector 20: RCC and CRS */
#define STM32F0_IRQ_EXTI0_1 (21) /* Vector 21: EXTI0_1 */
#define STM32F0_IRQ_EXTI2_3 (22) /* Vector 22: EXTI2_3 */
#define STM32F0_IRQ_EXTI4_15 (23) /* Vector 23: EXTI4_15 */
#define STM32F0_IRQ_TSC (24) /* Vector 24: TSC */
#define STM32F0_IRQ_DMA_CH1 (25) /* Vector 25: DMA_CH1 */
#define STM32F0_IRQ_DMA_CH23 (26) /* Vector 26: DMA_CH2_3 and DMA2_CH1_2 */
#define STM32F0_IRQ_DMA_CH4567 (27) /* Vector 27: DMA_CH4_5_6_7 and DMA2_CH3_4_5 */
#define STM32F0_IRQ_ADC_COMP (28) /* Vector 28: ADC_COMP */
#define STM32F0_IRQ_TIM1_BRK (29) /* Vector 29: TIM1_BRK_UP_TRG_COM */
#define STM32F0_IRQ_TIM1_CC (30) /* Vector 30: TIM1_CC */
#define STM32F0_IRQ_TIM2 (31) /* Vector 31: TIM2 */
#define STM32F0_IRQ_TIM3 (32) /* Vector 32: TIM3 */
#define STM32F0_IRQ_TIM6_DAC (33) /* Vector 33: TIM6 and DAC */
#define STM32F0_IRQ_TIM7 (34) /* Vector 34: TIM7 */
#define STM32F0_IRQ_TIM14 (35) /* Vector 35: TIM14 */
#define STM32F0_IRQ_TIM15 (36) /* Vector 36: TIM15 */
#define STM32F0_IRQ_TIM16 (37) /* Vector 37: TIM16 */
#define STM32F0_IRQ_TIM17 (38) /* Vector 38: TIM17 */
#define STM32F0_IRQ_I2C1 (39) /* Vector 39: I2C1 */
#define STM32F0_IRQ_I2C2 (40) /* Vector 40: I2C2 */
#define STM32F0_IRQ_SPI1 (41) /* Vector 41: SPI1 */
#define STM32F0_IRQ_SPI2 (42) /* Vector 42: SPI2 */
#define STM32F0_IRQ_USART1 (43) /* Vector 43: USART1 */
#define STM32F0_IRQ_USART2 (44) /* Vector 44: USART2 */
#define STM32F0_IRQ_USART345678 (45) /* Vector 45: USART3_4_5_6_7_8 */
#define STM32F0_IRQ_CEC_CAN (46) /* Vector 46: HDMI CEC and CAN */
#define STM32F0_IRQ_USB (47) /* Vector 47: USB */
/* Include MCU-specific external interrupt definitions */
#define NR_IRQS (48) /* 32 interrupts plus 16 exceptions */
#if defined(CONFIG_STM32F0L0_STM32F0)
# include <arch/stm32f0l0/stm32f0_irq.h>
#elif defined(CONFIG_STM32F0L0_STM32L0)
# include <arch/stm32f0l0/stm32l0_irq.h>
#else
# error Unrecognized STM32 Cortex M0 family
#endif
#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINT)
/****************************************************************************
* Public Types
@ -139,4 +117,4 @@ extern "C"
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_STM32F0_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_IRQ_H */

123
arch/arm/include/stm32f0l0/stm32f0_irq.h Normal file
View file

@ -0,0 +1,123 @@
/****************************************************************************
* arch/arm/include/stm32f0l0/stm32f0_irq.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_STM32F0_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F0L0_STM32F0_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
#include <arch/stm32f0l0/chip.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Include STM32F0-specific external interrupt definitions */
#define STM32_IRQ_WWDG (16) /* Vector 16: WWDG */
#define STM32_IRQ_PVD_VDDIO2 (17) /* Vector 17: PVD_VDDIO2 */
#define STM32_IRQ_RTC (18) /* Vector 18: RTC */
#define STM32_IRQ_FLASH (19) /* Vector 19: FLASH */
#define STM32_IRQ_RCC_CRS (20) /* Vector 20: RCC and CRS */
#define STM32_IRQ_EXTI0_1 (21) /* Vector 21: EXTI0_1 */
#define STM32_IRQ_EXTI2_3 (22) /* Vector 22: EXTI2_3 */
#define STM32_IRQ_EXTI4_15 (23) /* Vector 23: EXTI4_15 */
#define STM32_IRQ_TSC (24) /* Vector 24: TSC */
#define STM32_IRQ_DMA_CH1 (25) /* Vector 25: DMA_CH1 */
#define STM32_IRQ_DMA_CH23 (26) /* Vector 26: DMA_CH2_3 and DMA2_CH1_2 */
#define STM32_IRQ_DMA_CH4567 (27) /* Vector 27: DMA_CH4_5_6_7 and DMA2_CH3_4_5 */
#define STM32_IRQ_ADC_COMP (28) /* Vector 28: ADC_COMP */
#define STM32_IRQ_TIM1_BRK (29) /* Vector 29: TIM1_BRK_UP_TRG_COM */
#define STM32_IRQ_TIM1_CC (30) /* Vector 30: TIM1_CC */
#define STM32_IRQ_TIM2 (31) /* Vector 31: TIM2 */
#define STM32_IRQ_TIM3 (32) /* Vector 32: TIM3 */
#define STM32_IRQ_TIM6_DAC (33) /* Vector 33: TIM6 and DAC */
#define STM32_IRQ_TIM7 (34) /* Vector 34: TIM7 */
#define STM32_IRQ_TIM14 (35) /* Vector 35: TIM14 */
#define STM32_IRQ_TIM15 (36) /* Vector 36: TIM15 */
#define STM32_IRQ_TIM16 (37) /* Vector 37: TIM16 */
#define STM32_IRQ_TIM17 (38) /* Vector 38: TIM17 */
#define STM32_IRQ_I2C1 (39) /* Vector 39: I2C1 */
#define STM32_IRQ_I2C2 (40) /* Vector 40: I2C2 */
#define STM32_IRQ_SPI1 (41) /* Vector 41: SPI1 */
#define STM32_IRQ_SPI2 (42) /* Vector 42: SPI2 */
#define STM32_IRQ_USART1 (43) /* Vector 43: USART1 */
#define STM32_IRQ_USART2 (44) /* Vector 44: USART2 */
#define STM32_IRQ_USART345678 (45) /* Vector 45: USART3_4_5_6_7_8 */
#define STM32_IRQ_CEC_CAN (46) /* Vector 46: HDMI CEC and CAN */
#define STM32_IRQ_USB (47) /* Vector 47: USB */
#define STM32_IRQ_NEXTINT (32) /* 32 external interrupts */
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
typedef void (*vic_vector_t)(uint32_t *regs);
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
extern "C"
{
#endif
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_STM32F0_IRQ_H */

1510
arch/arm/src/stm32f0/Kconfig
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File diff suppressed because it is too large Load diff

157
arch/arm/src/stm32f0/chip/stm32f05xf07xf09x_memorymap.h
View file

@ -1,157 +0,0 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f05xf07xf09x_memorymap.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_ST32F05XF07XF09X_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_ST32F05XF07XF09X_MEMORYMAP_H
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* ST32F05XF07X Address Blocks ******************************************************/
#define STM32F0_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
#define STM32F0_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
#define STM32F0_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
/* 0x60000000-0xdfffffff: Reserved */
#define STM32F0_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
#define STM32F0_REGION_MASK 0xf0000000
#define STM32F0_IS_SRAM(a) ((((uint32_t)(a)) & STM32F0_REGION_MASK) == STM32F0_SRAM_BASE)
/* Code Base Addresses **************************************************************/
#define STM32F0_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
/* 0x00100000-0x07ffffff: Reserved */
#define STM32F0_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */
/* 0x08100000-0x0fffffff: Reserved */
#define STM32F0_CCMRAM_BASE 0x10000000 /* 0x10000000-0x1000ffff: 64Kb CCM data RAM */
/* 0x10010000-0x1ffeffff: Reserved */
#define STM32F0_SYSMEM_BASE 0x1fffd800 /* 0x1fff0000-0x1fff7a0f: System memory */
/* 0x1fff7a10-0x1fff7fff: Reserved */
#define STM32F0_OPTION_BASE 0x1ffff800 /* 0x1fffc000-0x1fffc007: Option bytes */
/* 0x1fffc008-0x1fffffff: Reserved */
/* System Memory Addresses **********************************************************/
#define STM32F0_SYSMEM_UID 0x1ffff7ac /* The 96-bit unique device identifier */
#define STM32F0_SYSMEM_FSIZE 0x1ffff7cc /* This bitfield indicates the size of
* the device Flash memory expressed in
* Kbytes. Example: 0x040 corresponds
* to 64 Kbytes
*/
/* Peripheral Base Addresses ********************************************************/
#define STM32F0_APB1_BASE 0x40000000 /* 0x40000000-0x40009fff: APB1 */
/* 0x4000a000-0x4000ffff: Reserved */
#define STM32F0_APB2_BASE 0x40010000 /* 0x40010000-0x40006bff: APB2 */
/* 0x40016c00-0x4001ffff: Reserved */
#define STM32F0_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */
/* 0x40024400-0x4007ffff: Reserved */
#define STM32F0_AHB2_BASE 0x48000000 /* 0x48000000-0x480017ff: AHB2 */
/* 0x48001800-0x4fffFfff: Reserved */
#define STM32F0_AHB3_BASE 0x50000000 /* 0x50000000-0x500007ff: AHB3 */
/* APB1 Base Addresses **************************************************************/
#define STM32F0_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff TIM2 */
#define STM32F0_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff TIM3 */
#define STM32F0_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */
#define STM32F0_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */
#define STM32F0_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff TIM14 */
#define STM32F0_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */
#define STM32F0_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */
#define STM32F0_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */
#define STM32F0_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff SPI2, or */
#define STM32F0_I2S2_BASE 0x40003800 /* 0x40003800-0x40003bff I2S2 */
#define STM32F0_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff USART2 */
#define STM32F0_USART3_BASE 0x40004800 /* 0x40004800-0x40004bff USART3 */
#define STM32F0_USART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff USART4 */
#define STM32F0_USART5_BASE 0x40005000 /* 0x40005000-0x400053ff USART5 */
#define STM32F0_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff I2C1 */
#define STM32F0_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff I2C2 */
#define STM32F0_USB_BASE 0x40005c00 /* 0x40005c00-0x40005fff USB device FS */
#define STM32F0_USBRAM_BASE 0x40006000 /* 0x40006000-0x400063ff USB SRAM 512B */
#define STM32F0_CAN_BASE 0x40006400 /* 0x40006400-0x400067ff bxCAN */
#define STM32F0_CRS_BASE 0x40006c00 /* 0x40006c00-0x40006fff CRS */
#define STM32F0_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */
#define STM32F0_DAC_BASE 0x40007400 /* 0x40007400-0x400077ff DAC */
#define STM32F0_CEC_BASE 0x40007800 /* 0x40007800-0x40007bff HDMI CEC */
/* APB2 Base Addresses **************************************************************/
#define STM32F0_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103ff SYSCFG + COMP + OPAMP */
#define STM32F0_EXTI_BASE 0x40010400 /* 0x40010400-0x400107ff EXTI */
#define STM32F0_USART6_BASE 0x40011400 /* 0x40011400-0x400117ff USART6 */
#define STM32F0_USART7_BASE 0x40011800 /* 0x40011800-0x40011bff USART7 */
#define STM32F0_USART8_BASE 0x40011c00 /* 0x40011c00-0x40011fff USART8 */
#define STM32F0_ADC_BASE 0x40012400 /* 0x40012400-0x400127ff ADC */
#define STM32F0_TIM1_BASE 0x40012c00 /* 0x40012c00-0x40012fff TIM1 */
#define STM32F0_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */
#define STM32F0_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */
#define STM32F0_TIM15_BASE 0x40014000 /* 0x40014000-0x400143ff TIM15 */
#define STM32F0_TIM16_BASE 0x40014400 /* 0x40014400-0x400147ff TIM16 */
#define STM32F0_TIM17_BASE 0x40014800 /* 0x40014800-0x40014bff TIM17 */
#define STM32F0_DBGMCU_BASE 0x40015800 /* 0x40015800-0x40015bff DBGMCU */
/* AHB1 Base Addresses **************************************************************/
#define STM32F0_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */
#define STM32F0_DMA2_BASE 0x40020400 /* 0x40020400-0x400207ff: DMA2 */
#define STM32F0_RCC_BASE 0x40021000 /* 0x40021000-0x400213ff: Reset and Clock control RCC */
#define STM32F0_FLASHIF_BASE 0x40022000 /* 0x40022000-0x400223ff: Flash memory interface */
#define STM32F0_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */
#define STM32F0_TSC_BASE 0x40024000 /* 0x40024000-0x400243ff: TSC */
/* AHB2 Base Addresses **************************************************************/
#define STM32F0_GPIOA_BASE 0x48000000 /* 0x48000000-0x480003ff: GPIO Port A */
#define STM32F0_GPIOB_BASE 0x48000400 /* 0x48000400-0x480007ff: GPIO Port B */
#define STM32F0_GPIOC_BASE 0x48000800 /* 0x48000800-0x48000bff: GPIO Port C */
#define STM32F0_GPIOD_BASE 0X48000C00 /* 0x48000c00-0x48000fff: GPIO Port D */
#define STM32F0_GPIOE_BASE 0x48001000 /* 0x48001000-0x480013ff: GPIO Port E */
#define STM32F0_GPIOF_BASE 0x48001400 /* 0x48001400-0x480017ff: GPIO Port F */
/* Cortex-M4 Base Addresses *********************************************************/
/* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in this
* address range
*/
#define STM32F0_SCS_BASE 0xe000e000
#define STM32F0_DEBUGMCU_BASE 0xe0042000
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_ST32F05XF07XF09X_MEMORYMAP_H */

195
arch/arm/src/stm32f0/chip/stm32f0_adc.h
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@ -1,195 +0,0 @@
/********************************************************************************
* arch/arm/src/stm32f0/chip/stm32f0_adc.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_ADC_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_ADC_H
/********************************************************************************
* Included Files
********************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/********************************************************************************
* Pre-processor Definitions
********************************************************************************/
/* Register Offsets *********************************************************************************/
#define STM32F0_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */
#define STM32F0_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */
#define STM32F0_ADC_CR_OFFSET 0x0008 /* ADC control register */
#define STM32F0_ADC_CFGR1_OFFSET 0x000c /* ADC configuration register 1 */
#define STM32F0_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */
#define STM32F0_ADC_SMPR_OFFSET 0x0014 /* ADC sample time register */
#define STM32F0_ADC_TR_OFFSET 0x0020 /* ADC watchdog threshold register */
#define STM32F0_ADC_CHSELR_OFFSET 0x0028 /* ADC channel selection register */
#define STM32F0_ADC_DR_OFFSET 0x0040 /* ADC regular data register */
#define STM32F0_ADC_CCR_OFFSET 0x0308 /* ADC common configuration register */
/* Register Addresses *******************************************************************************/
#define STM32F0_ADC_ISR (STM32F0_ADC_BASE+STM32F0_ADC_ISR_OFFSET)
#define STM32F0_ADC_IER (STM32F0_ADC_BASE+STM32F0_ADC_IER_OFFSET)
#define STM32F0_ADC_CR (STM32F0_ADC_BASE+STM32F0_ADC_CR_OFFSET)
#define STM32F0_ADC_CFGR1 (STM32F0_ADC_BASE+STM32F0_ADC_CFGR1_OFFSET)
#define STM32F0_ADC_CFGR2 (STM32F0_ADC_BASE+STM32F0_ADC_CFGR2_OFFSET)
#define STM32F0_ADC_SMPR (STM32F0_ADC_BASE+STM32F0_ADC_SMPR_OFFSET)
#define STM32F0_ADC_TR (STM32F0_ADC_BASE+STM32F0_ADC_TR_OFFSET)
#define STM32F0_ADC_CHSELR (STM32F0_ADC_BASE+STM32F0_ADC_CHSELR_OFFSET)
#define STM32F0_ADC_DR (STM32F0_ADC_BASE+STM32F0_ADC_DR_OFFSET)
#define STM32F0_ADC_CCR (STM32F0_ADC_BASE+STM32F0_ADC_CCR_OFFSET)
/* Register Bitfield Definitions ************************************************/
/* ADC interrupt and status register (ISR) and ADC interrupt enable register (IER) */
#define ADC_INT_ARDY (1 << 0) /* Bit 0: ADC ready */
#define ADC_INT_EOSMP (1 << 1) /* Bit 1: End of sampling flag */
#define ADC_INT_EOC (1 << 2) /* Bit 2: End of conversion */
#define ADC_INT_EOS (1 << 3) /* Bit 3: End of regular sequence flag */
#define ADC_INT_OVR (1 << 4) /* Bit 4: Overrun */
#define ADC_INT_AWD (1 << 7) /* Bit 7: Analog watchdog flag */
/* ADC control register */
#define ADC_CR_ADEN (1 << 0) /* Bit 0: ADC enable control */
#define ADC_CR_ADDIS (1 << 1) /* Bit 1: ADC disable command */
#define ADC_CR_ADSTART (1 << 2) /* Bit 2: ADC start of regular conversion */
#define ADC_CR_ADSTP (1 << 4) /* Bit 4: ADC stop of regular conversion command */
#define ADC_CR_ADCAL (1 << 31) /* Bit 31: ADC calibration */
/* ADC configuration register 1 */
#define ADC_CFGR1_DMAEN (1 << 0) /* Bit 0: Direct memory access enable */
#define ADC_CFGR1_DMACFG (1 << 1) /* Bit 1: Direct memory access configuration */
#define ADC_CFGR1_SCANDIR (1 << 2) /* Bit 2: Scan sequence direction */
#define ADC_CFGR1_RES_SHIFT (3) /* Bits 3-4: Data resolution */
#define ADC_CFGR1_RES_MASK (3 << ADC_CFGR1_RES_SHIFT)
# define ADC_CFGR1_RES_12BIT (0 << ADC_CFGR1_RES_SHIFT) /* 15 ADCCLK clyes */
# define ADC_CFGR1_RES_10BIT (1 << ADC_CFGR1_RES_SHIFT) /* 13 ADCCLK clyes */
# define ADC_CFGR1_RES_8BIT (2 << ADC_CFGR1_RES_SHIFT) /* 11 ADCCLK clyes */
# define ADC_CFGR1_RES_6BIT (3 << ADC_CFGR1_RES_SHIFT) /* 9 ADCCLK clyes */
#define ADC_CFGR1_ALIGN (1 << 5) /* Bit 5: Data Alignment */
#define ADC_CFGR1_EXTSEL_SHIFT (6) /* Bits 6-8: External trigger selection */
#define ADC_CFGR1_EXTSEL_MASK (7 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_TRG0 (0 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_TRG1 (1 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_TRG2 (2 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_TRG3 (3 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_TRG4 (4 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_TRG5 (5 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_TRG6 (6 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_TRG7 (7 << ADC_CFGR1_EXTSEL_SHIFT)
#define ADC_CFGR1_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */
#define ADC_CFGR1_EXTEN_MASK (3 << ADC_CFGR1_EXTEN_SHIFT)
# define ADC_CFGR1_EXTEN_NONE (0 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection disabled */
# define ADC_CFGR1_EXTEN_RISING (1 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the rising edge */
# define ADC_CFGR1_EXTEN_FALLING (2 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the falling edge */
# define ADC_CFGR1_EXTEN_BOTH (3 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on both edges */
#define ADC_CFGR1_OVRMOD (1 << 12) /* Bit 12: Overrun Mode */
#define ADC_CFGR1_CONT (1 << 13) /* Bit 13: Continuous mode for regular conversions */
#define ADC_CFGR1_WAIT (1 << 14) /* Bit 14: Wait convertion mode */
#define ADC_CFGR1_AUTOFF (1 << 15) /* Bit 15: Auto-off mode */
#define ADC_CFGR1_DISCEN (1 << 16) /* Bit 16: Discontinuous mode on regular channels */
#define ADC_CFGR1_AWDSGL (1 << 22) /* Bit 22: Enable watchdog on single/all channels */
#define ADC_CFGR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable */
#define ADC_CFGR1_AWDCH_SHIFT (26) /* Bits 26-30: Analog watchdog 1 channel select bits */
#define ADC_CFGR1_AWDCH_MASK (31 << ADC_CFGR1_AWDCH_SHIFT)
# define ADC_CFGR1_AWDCH_DISABLED (0 << ADC_CFGR1_AWDCH_SHIFT)
/* ADC configuration register 2 */
#define ADC_CFGR2_CKMODE_SHIFT (30) /* Bits 30-31: ADC clock mode */
#define ADC_CFGR2_CKMODE_MASK (3 << ADC_CFGR2_CKMODE_SHIFT)
# define ADC_CFGR2_CKMODE_ADCCLK (0 << ADC_CFGR2_CKMODE_SHIFT) /* 00: ADCCLK (Asynchronous) generated at product level */
# define ADC_CFGR2_CKMODE_PCLKd2 (1 << ADC_CFGR2_CKMODE_SHIFT) /* 01: PCLK/2 (Synchronous clock mode) */
# define ADC_CFGR2_CKMODE_PCLKd4 (2 << ADC_CFGR2_CKMODE_SHIFT) /* 10: PCLK/4 (Synchronous clock mode) */
/* ADC sample time register */
#define ADC_SMPR_SMP_SHIFT (0) /* Bits 0-2: Sampling time selection */
#define ADC_SMPR_SMP_MASK (7 << ADC_SMPR_SMP_SHIFT)
#define ADC_SMPR_SMP_1p5 (0 << ADC_SMPR_SMP_SHIFT) /* 000: 1.5 cycles */
#define ADC_SMPR_SMP_7p5 (1 << ADC_SMPR_SMP_SHIFT) /* 001: 7.5 cycles */
#define ADC_SMPR_SMP_13p5 (2 << ADC_SMPR_SMP_SHIFT) /* 010: 13.5 cycles */
#define ADC_SMPR_SMP_28p5 (3 << ADC_SMPR_SMP_SHIFT) /* 011: 28.5 cycles */
#define ADC_SMPR_SMP_41p5 (4 << ADC_SMPR_SMP_SHIFT) /* 100: 41.5 cycles */
#define ADC_SMPR_SMP_55p5 (5 << ADC_SMPR_SMP_SHIFT) /* 101: 55.5 cycles */
#define ADC_SMPR_SMP_71p5 (6 << ADC_SMPR_SMP_SHIFT) /* 110: 71.5 cycles */
#define ADC_SMPR_SMP_239p5 (7 << ADC_SMPR_SMP_SHIFT) /* 111: 239.5 cycles */
/* ADC watchdog threshold register */
#define ADC_TR_LT_SHIFT (0) /* Bits 0-11: Analog watchdog lower threshold */
#define ADC_TR_LT_MASK (0x0fff << ADC_TR_LT_SHIFT)
#define ADC_TR_HT_SHIFT (16) /* Bits 16-27: Analog watchdog higher threshold */
#define ADC_TR_HT_MASK (0x0fff << ADC_TR_HT_SHIFT)
/* ADC channel selection register */
#define ADC_CHSELR_CHSEL0 (1 << 0) /* Select channel 0 */
#define ADC_CHSELR_CHSEL1 (1 << 1) /* Select channel 1 */
#define ADC_CHSELR_CHSEL2 (1 << 2) /* Select channel 2 */
#define ADC_CHSELR_CHSEL3 (1 << 3) /* Select channel 3 */
#define ADC_CHSELR_CHSEL4 (1 << 4) /* Select channel 4 */
#define ADC_CHSELR_CHSEL5 (1 << 5) /* Select channel 5 */
#define ADC_CHSELR_CHSEL6 (1 << 6) /* Select channel 6 */
#define ADC_CHSELR_CHSEL7 (1 << 7) /* Select channel 7 */
#define ADC_CHSELR_CHSEL8 (1 << 8) /* Select channel 8 */
#define ADC_CHSELR_CHSEL9 (1 << 9) /* Select channel 9 */
#define ADC_CHSELR_CHSEL10 (1 << 10) /* Select channel 10 */
#define ADC_CHSELR_CHSEL11 (1 << 11) /* Select channel 11 */
#define ADC_CHSELR_CHSEL12 (1 << 12) /* Select channel 12 */
#define ADC_CHSELR_CHSEL13 (1 << 13) /* Select channel 13 */
#define ADC_CHSELR_CHSEL14 (1 << 14) /* Select channel 14 */
#define ADC_CHSELR_CHSEL15 (1 << 15) /* Select channel 15 */
#define ADC_CHSELR_CHSEL16 (1 << 16) /* Select channel 16 */
#define ADC_CHSELR_CHSEL17 (1 << 17) /* Select channel 17 */
#define ADC_CHSELR_CHSEL18 (1 << 18) /* Select channel 18 */
#define ADC_DR_RDATA_SHIFT (0)
#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT)
/* Common configuration register */
#define ADC_CCR_VREFEN (1 << 22) /* Bit 22: VREFINT enable */
#define ADC_CCR_TSEN (1 << 23) /* Bit 23: Temperature sensor enable */
#define ADC_CCR_VBATEN (1 << 24) /* Bit 22: VBAT enable */
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_ADC_H */

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arch/arm/src/stm32f0/chip/stm32f0_dma.h
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@ -1,456 +0,0 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f0_dma.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_DMA_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_DMA_H
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* 12 Channels Total: 7 DMA1 Channels(1-7) (and 5 DMA2 channels (1-5) if STM32F09x) */
#define DMA1 0
#define DMA2 1
#define DMA3 2
#define DMA4 3
#define DMA5 4
#define DMA6 5
#define DMA7 6
/* Register Offsets *****************************************************************/
#define STM32F0_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
#define STM32F0_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
#define STM32F0_DMACHAN_OFFSET(n) (0x0014*(n))
#define STM32F0_DMACHAN1_OFFSET 0x0000
#define STM32F0_DMACHAN2_OFFSET 0x0014
#define STM32F0_DMACHAN3_OFFSET 0x0028
#define STM32F0_DMACHAN4_OFFSET 0x003c
#define STM32F0_DMACHAN5_OFFSET 0x0050
#define STM32F0_DMACHAN6_OFFSET 0x0064
#define STM32F0_DMACHAN7_OFFSET 0x0078
#define STM32F0_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
#define STM32F0_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
#define STM32F0_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */
#define STM32F0_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */
#define STM32F0_DMA_CCR_OFFSET(n) (STM32F0_DMACHAN_CCR_OFFSET+STM32F0_DMACHAN_OFFSET(n))
#define STM32F0_DMA_CNDTR_OFFSET(n) (STM32F0_DMACHAN_CNDTR_OFFSET+STM32F0_DMACHAN_OFFSET(n))
#define STM32F0_DMA_CPAR_OFFSET(n) (STM32F0_DMACHAN_CPAR_OFFSET+STM32F0_DMACHAN_OFFSET(n))
#define STM32F0_DMA_CMAR_OFFSET(n) (STM32F0_DMACHAN_CMAR_OFFSET+STM32F0_DMACHAN_OFFSET(n))
#define STM32F0_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
#define STM32F0_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
#define STM32F0_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
#define STM32F0_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
#define STM32F0_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
#define STM32F0_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
#define STM32F0_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
#define STM32F0_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
#define STM32F0_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
#define STM32F0_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
#define STM32F0_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
#define STM32F0_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
#define STM32F0_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
#define STM32F0_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
#define STM32F0_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
#define STM32F0_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
#define STM32F0_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
#define STM32F0_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
#define STM32F0_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
#define STM32F0_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
#define STM32F0_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
#define STM32F0_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
#define STM32F0_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
#define STM32F0_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
#define STM32F0_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
#define STM32F0_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
#define STM32F0_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
#define STM32F0_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
#define STM32F0_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */
/* Register Addresses ***************************************************************/
#define STM32F0_DMA1_ISRC (STM32F0_DMA1_BASE+STM32F0_DMA_ISR_OFFSET)
#define STM32F0_DMA1_IFCR (STM32F0_DMA1_BASE+STM32F0_DMA_IFCR_OFFSET)
#define STM32F0_DMA1_CCR(n) (STM32F0_DMA1_BASE+STM32F0_DMA_CCR_OFFSET(n))
#define STM32F0_DMA1_CCR1 (STM32F0_DMA1_BASE+STM32F0_DMA_CCR1_OFFSET)
#define STM32F0_DMA1_CCR2 (STM32F0_DMA1_BASE+STM32F0_DMA_CCR2_OFFSET)
#define STM32F0_DMA1_CCR3 (STM32F0_DMA1_BASE+STM32F0_DMA_CCR3_OFFSET)
#define STM32F0_DMA1_CCR4 (STM32F0_DMA1_BASE+STM32F0_DMA_CCR4_OFFSET)
#define STM32F0_DMA1_CCR5 (STM32F0_DMA1_BASE+STM32F0_DMA_CCR5_OFFSET)
#define STM32F0_DMA1_CCR6 (STM32F0_DMA1_BASE+STM32F0_DMA_CCR6_OFFSET)
#define STM32F0_DMA1_CCR7 (STM32F0_DMA1_BASE+STM32F0_DMA_CCR7_OFFSET)
#define STM32F0_DMA1_CNDTR(n) (STM32F0_DMA1_BASE+STM32F0_DMA_CNDTR_OFFSET(n))
#define STM32F0_DMA1_CNDTR1 (STM32F0_DMA1_BASE+STM32F0_DMA_CNDTR1_OFFSET)
#define STM32F0_DMA1_CNDTR2 (STM32F0_DMA1_BASE+STM32F0_DMA_CNDTR2_OFFSET)
#define STM32F0_DMA1_CNDTR3 (STM32F0_DMA1_BASE+STM32F0_DMA_CNDTR3_OFFSET)
#define STM32F0_DMA1_CNDTR4 (STM32F0_DMA1_BASE+STM32F0_DMA_CNDTR4_OFFSET)
#define STM32F0_DMA1_CNDTR5 (STM32F0_DMA1_BASE+STM32F0_DMA_CNDTR5_OFFSET)
#define STM32F0_DMA1_CNDTR6 (STM32F0_DMA1_BASE+STM32F0_DMA_CNDTR6_OFFSET)
#define STM32F0_DMA1_CNDTR7 (STM32F0_DMA1_BASE+STM32F0_DMA_CNDTR7_OFFSET)
#define STM32F0_DMA1_CPAR(n) (STM32F0_DMA1_BASE+STM32F0_DMA_CPAR_OFFSET(n))
#define STM32F0_DMA1_CPAR1 (STM32F0_DMA1_BASE+STM32F0_DMA_CPAR1_OFFSET)
#define STM32F0_DMA1_CPAR2 (STM32F0_DMA1_BASE+STM32F0_DMA_CPAR2_OFFSET)
#define STM32F0_DMA1_CPAR3 (STM32F0_DMA1_BASE+STM32F0_DMA_CPAR3_OFFSET)
#define STM32F0_DMA1_CPAR4 (STM32F0_DMA1_BASE+STM32F0_DMA_CPAR4_OFFSET)
#define STM32F0_DMA1_CPAR5 (STM32F0_DMA1_BASE+STM32F0_DMA_CPAR5_OFFSET)
#define STM32F0_DMA1_CPAR6 (STM32F0_DMA1_BASE+STM32F0_DMA_CPAR6_OFFSET)
#define STM32F0_DMA1_CPAR7 (STM32F0_DMA1_BASE+STM32F0_DMA_CPAR7_OFFSET)
#define STM32F0_DMA1_CMAR(n) (STM32F0_DMA1_BASE+STM32F0_DMA_CMAR_OFFSET(n))
#define STM32F0_DMA1_CMAR1 (STM32F0_DMA1_BASE+STM32F0_DMA_CMAR1_OFFSET)
#define STM32F0_DMA1_CMAR2 (STM32F0_DMA1_BASE+STM32F0_DMA_CMAR2_OFFSET)
#define STM32F0_DMA1_CMAR3 (STM32F0_DMA1_BASE+STM32F0_DMA_CMAR3_OFFSET)
#define STM32F0_DMA1_CMAR4 (STM32F0_DMA1_BASE+STM32F0_DMA_CMAR4_OFFSET)
#define STM32F0_DMA1_CMAR5 (STM32F0_DMA1_BASE+STM32F0_DMA_CMAR5_OFFSET)
#define STM32F0_DMA1_CMAR6 (STM32F0_DMA1_BASE+STM32F0_DMA_CMAR6_OFFSET)
#define STM32F0_DMA1_CMAR7 (STM32F0_DMA1_BASE+STM32F0_DMA_CMAR7_OFFSET)
#define STM32F0_DMA2_ISRC (STM32F0_DMA2_BASE+STM32F0_DMA_ISR_OFFSET)
#define STM32F0_DMA2_IFCR (STM32F0_DMA2_BASE+STM32F0_DMA_IFCR_OFFSET)
#define STM32F0_DMA2_CCR(n) (STM32F0_DMA2_BASE+STM32F0_DMA_CCR_OFFSET(n))
#define STM32F0_DMA2_CCR1 (STM32F0_DMA2_BASE+STM32F0_DMA_CCR1_OFFSET)
#define STM32F0_DMA2_CCR2 (STM32F0_DMA2_BASE+STM32F0_DMA_CCR2_OFFSET)
#define STM32F0_DMA2_CCR3 (STM32F0_DMA2_BASE+STM32F0_DMA_CCR3_OFFSET)
#define STM32F0_DMA2_CCR4 (STM32F0_DMA2_BASE+STM32F0_DMA_CCR4_OFFSET)
#define STM32F0_DMA2_CCR5 (STM32F0_DMA2_BASE+STM32F0_DMA_CCR5_OFFSET)
#define STM32F0_DMA2_CCR6 (STM32F0_DMA2_BASE+STM32F0_DMA_CCR6_OFFSET)
#define STM32F0_DMA2_CCR7 (STM32F0_DMA2_BASE+STM32F0_DMA_CCR7_OFFSET)
#define STM32F0_DMA2_CNDTR(n) (STM32F0_DMA2_BASE+STM32F0_DMA_CNDTR_OFFSET(n))
#define STM32F0_DMA2_CNDTR1 (STM32F0_DMA2_BASE+STM32F0_DMA_CNDTR1_OFFSET)
#define STM32F0_DMA2_CNDTR2 (STM32F0_DMA2_BASE+STM32F0_DMA_CNDTR2_OFFSET)
#define STM32F0_DMA2_CNDTR3 (STM32F0_DMA2_BASE+STM32F0_DMA_CNDTR3_OFFSET)
#define STM32F0_DMA2_CNDTR4 (STM32F0_DMA2_BASE+STM32F0_DMA_CNDTR4_OFFSET)
#define STM32F0_DMA2_CNDTR5 (STM32F0_DMA2_BASE+STM32F0_DMA_CNDTR5_OFFSET)
#define STM32F0_DMA2_CNDTR6 (STM32F0_DMA2_BASE+STM32F0_DMA_CNDTR6_OFFSET)
#define STM32F0_DMA2_CNDTR7 (STM32F0_DMA2_BASE+STM32F0_DMA_CNDTR7_OFFSET)
#define STM32F0_DMA2_CPAR(n) (STM32F0_DMA2_BASE+STM32F0_DMA_CPAR_OFFSET(n))
#define STM32F0_DMA2_CPAR1 (STM32F0_DMA2_BASE+STM32F0_DMA_CPAR1_OFFSET)
#define STM32F0_DMA2_CPAR2 (STM32F0_DMA2_BASE+STM32F0_DMA_CPAR2_OFFSET)
#define STM32F0_DMA2_CPAR3 (STM32F0_DMA2_BASE+STM32F0_DMA_CPAR3_OFFSET)
#define STM32F0_DMA2_CPAR4 (STM32F0_DMA2_BASE+STM32F0_DMA_CPAR4_OFFSET)
#define STM32F0_DMA2_CPAR5 (STM32F0_DMA2_BASE+STM32F0_DMA_CPAR5_OFFSET)
#define STM32F0_DMA2_CPAR6 (STM32F0_DMA2_BASE+STM32F0_DMA_CPAR6_OFFSET)
#define STM32F0_DMA2_CPAR7 (STM32F0_DMA2_BASE+STM32F0_DMA_CPAR7_OFFSET)
#define STM32F0_DMA2_CMAR(n) (STM32F0_DMA2_BASE+STM32F0_DMA_CMAR_OFFSET(n))
#define STM32F0_DMA2_CMAR1 (STM32F0_DMA2_BASE+STM32F0_DMA_CMAR1_OFFSET)
#define STM32F0_DMA2_CMAR2 (STM32F0_DMA2_BASE+STM32F0_DMA_CMAR2_OFFSET)
#define STM32F0_DMA2_CMAR3 (STM32F0_DMA2_BASE+STM32F0_DMA_CMAR3_OFFSET)
#define STM32F0_DMA2_CMAR4 (STM32F0_DMA2_BASE+STM32F0_DMA_CMAR4_OFFSET)
#define STM32F0_DMA2_CMAR5 (STM32F0_DMA2_BASE+STM32F0_DMA_CMAR5_OFFSET)
#define STM32F0_DMA2_CMAR6 (STM32F0_DMA2_BASE+STM32F0_DMA_CMAR6_OFFSET)
#define STM32F0_DMA2_CMAR7 (STM32F0_DMA2_BASE+STM32F0_DMA_CMAR7_OFFSET)
/* Register Bitfield Definitions ****************************************************/
#define DMA_CHAN_SHIFT(n) ((n) << 2)
#define DMA_CHAN_MASK 0x0f
#define DMA_CHAN_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */
#define DMA_CHAN_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */
#define DMA_CHAN_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */
#define DMA_CHAN_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */
/* DMA interrupt status register */
#define DMA_ISR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
#define DMA_ISR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_ISR_CHAN_SHIFT(n))
#define DMA_ISR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */
#define DMA_ISR_CHAN1_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN1_SHIFT)
#define DMA_ISR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */
#define DMA_ISR_CHAN2_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN2_SHIFT)
#define DMA_ISR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */
#define DMA_ISR_CHAN3_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN3_SHIFT)
#define DMA_ISR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */
#define DMA_ISR_CHAN4_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN4_SHIFT)
#define DMA_ISR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */
#define DMA_ISR_CHAN5_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN5_SHIFT)
#define DMA_ISR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */
#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT)
#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */
#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT)
#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n))
#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n))
#define DMA_ISR_HTIF(n) (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n))
#define DMA_ISR_TEIF(n) (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n))
/* DMA interrupt flag clear register */
#define DMA_IFCR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
#define DMA_IFCR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_IFCR_CHAN_SHIFT(n))
#define DMA_IFCR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt flag clear */
#define DMA_IFCR_CHAN1_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN1_SHIFT)
#define DMA_IFCR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt flag clear */
#define DMA_IFCR_CHAN2_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN2_SHIFT)
#define DMA_IFCR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt flag clear */
#define DMA_IFCR_CHAN3_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN3_SHIFT)
#define DMA_IFCR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt flag clear */
#define DMA_IFCR_CHAN4_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN4_SHIFT)
#define DMA_IFCR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt flag clear */
#define DMA_IFCR_CHAN5_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN5_SHIFT)
#define DMA_IFCR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt flag clear */
#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT)
#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */
#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT)
#define DMA_IFCR_ALLCHANNELS (0x0fffffff)
#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
#define DMA_IFCR_CHTIF(n) (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
#define DMA_IFCR_CTEIF(n) (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
/* DMA channel configuration register */
#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */
#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */
#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */
#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */
#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */
#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */
#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */
#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */
#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 8-9: Peripheral size */
#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT)
# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */
# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */
# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */
#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 10-11: Memory size */
#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT)
# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */
# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */
# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */
#define DMA_CCR_PL_SHIFT (12) /* Bits 12-13: Channel Priority level */
#define DMA_CCR_PL_MASK (3 << DMA_CCR_PL_SHIFT)
# define DMA_CCR_PRILO (0 << DMA_CCR_PL_SHIFT) /* 00: Low */
# define DMA_CCR_PRIMED (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */
# define DMA_CCR_PRIHI (2 << DMA_CCR_PL_SHIFT) /* 10: High */
# define DMA_CCR_PRIVERYHI (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */
#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */
#define DMA_CCR_ALLINTS (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE)
/* DMA channel number of data register */
#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT)
/* DMA Channel mapping. Each DMA channel has a mapping to one of several
* possible sources/sinks of data. The requests from peripherals assigned to a
* channel are multiplexed together before entering the DMA block. This means
* that only one request on a given channel can be enabled at once.
*
* Alternative DMA channel selections are provided with a numeric suffix like _1,
* _2, etc. Drivers, however, will use the pin selection without the numeric suffix.
* Additional definitions are required in the board.h file.
*/
/* REVISE IT: based on STM32L4 DMA Header */
#define STM32F0_DMA1_CHAN1 (0)
#define STM32F0_DMA1_CHAN2 (1)
#define STM32F0_DMA1_CHAN3 (2)
#define STM32F0_DMA1_CHAN4 (3)
#define STM32F0_DMA1_CHAN5 (4)
#define STM32F0_DMA1_CHAN6 (5)
#define STM32F0_DMA1_CHAN7 (6)
#define STM32F0_DMA2_CHAN1 (7)
#define STM32F0_DMA2_CHAN2 (8)
#define STM32F0_DMA2_CHAN3 (9)
#define STM32F0_DMA2_CHAN4 (10)
#define STM32F0_DMA2_CHAN5 (11)
#define DMACHAN_SETTING(chan, sel) ( ( ( (sel) & 0xff) << 8) | ( (chan) & 0xff) )
#define DMACHAN_SETTING_CHANNEL_MASK 0x00FF
#define DMACHAN_SETTING_CHANNEL_SHIFT (0)
#define DMACHAN_SETTING_FUNCTION_MASK 0xFF00
#define DMACHAN_SETTING_FUNCTION_SHIFT (8)
/* ADC */
#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN1, 0)
#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN3, 0)
#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN1, 0)
#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN4, 0)
#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN1, 0)
#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN5, 0)
/* AES */
#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32F0_DMA2_CHAN1, 6)
#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN5, 6)
#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32F0_DMA2_CHAN2, 6)
#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN3, 6)
/* DAC */
#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN3, 6)
#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32F0_DMA1_CHAN4, 5)
#define DMACHAN_DAC1_3 DMACHAN_SETTING(STM32F0_DMA2_CHAN4, 3)
#define DMACHAN_DAC2 DMACHAN_SETTING(STM32F0_DMA2_CHAN5, 3)
/* I2C */
#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN7, 3)
#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN6, 5)
#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN6, 3)
#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN7, 5)
#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32F0_DMA1_CHAN5, 3)
#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32F0_DMA1_CHAN4, 3)
#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32F0_DMA1_CHAN3, 2)
#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32F0_DMA1_CHAN2, 3)
/* QUADSPI */
#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN5, 5)
#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN7, 3)
/* SPI */
#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN2, 1)
#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN3, 4)
#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN3, 0)
#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN4, 4)
#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32F0_DMA1_CHAN4, 1)
#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32F0_DMA1_CHAN5, 1)
#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32F0_DMA2_CHAN1, 3)
#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32F0_DMA2_CHAN2, 3)
/* TIM */
#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32F0_DMA1_CHAN2, 7)
#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32F0_DMA1_CHAN3, 7)
#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32F0_DMA1_CHAN7, 7)
#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32F0_DMA1_CHAN4, 7)
#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32F0_DMA1_CHAN4, 7)
#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32F0_DMA1_CHAN4, 7)
#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32F0_DMA1_CHAN6, 7)
#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32F0_DMA1_CHAN5, 4)
#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32F0_DMA1_CHAN7, 4)
#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32F0_DMA1_CHAN1, 4)
#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32F0_DMA1_CHAN7, 4)
#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32F0_DMA1_CHAN2, 4)
#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32F0_DMA1_CHAN6, 5)
#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32F0_DMA1_CHAN2, 5)
#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32F0_DMA1_CHAN3, 5)
#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32F0_DMA1_CHAN6, 5)
#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32F0_DMA1_CHAN3, 5)
#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32F0_DMA1_CHAN1, 6)
#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32F0_DMA1_CHAN4, 6)
#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32F0_DMA1_CHAN5, 6)
#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32F0_DMA1_CHAN7, 6)
#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32F0_DMA2_CHAN5, 5)
#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32F0_DMA2_CHAN4, 5)
#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32F0_DMA2_CHAN2, 5)
#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32F0_DMA2_CHAN1, 5)
#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32F0_DMA2_CHAN1, 5)
#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32F0_DMA2_CHAN1, 5)
#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32F0_DMA2_CHAN2, 5)
#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN3, 6)
#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN4, 3)
#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN4, 5)
#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN5, 3)
#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32F0_DMA2_CHAN6, 7)
#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32F0_DMA2_CHAN7, 7)
#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32F0_DMA2_CHAN1, 7)
#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32F0_DMA2_CHAN2, 7)
#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32F0_DMA2_CHAN2, 7)
#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32F0_DMA2_CHAN2, 7)
#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32F0_DMA2_CHAN1, 7)
#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32F0_DMA1_CHAN5, 7)
#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32F0_DMA1_CHAN5, 7)
#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32F0_DMA1_CHAN5, 7)
#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32F0_DMA1_CHAN5, 7)
#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN3, 4)
#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32F0_DMA1_CHAN6, 4)
#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN3, 4)
#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32F0_DMA1_CHAN6, 4)
#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN1, 5)
#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32F0_DMA1_CHAN7, 5)
#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN1, 5)
#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32F0_DMA1_CHAN7, 5)
/* USARTs */
#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN5, 2)
#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN7, 2)
#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN4, 2)
#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN6, 2)
#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32F0_DMA1_CHAN6, 2)
#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32F0_DMA1_CHAN7, 2)
#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32F0_DMA1_CHAN3, 1)
#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32F0_DMA1_CHAN2, 2)
#define DMACHAN_USART4_RX DMACHAN_SETTING(STM32F0_DMA2_CHAN5, 2)
#define DMACHAN_USART4_TX DMACHAN_SETTING(STM32F0_DMA2_CHAN3, 2)
#define DMACHAN_USART5_RX DMACHAN_SETTING(STM32F0_DMA2_CHAN2, 2)
#define DMACHAN_USART5_TX DMACHAN_SETTING(STM32F0_DMA2_CHAN1, 2)
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_DMA_H */

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arch/arm/src/stm32f0/chip/stm32f0_exti.h
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/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f0_exti.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_EXTI_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_EXTI_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#define STM32F0_NEXTI 31
#define STM32F0_EXTI_MASK 0xffffffff
#define STM32F0_EXTI_BIT(n) (1 << (n))
/* Register Offsets *****************************************************************/
#define STM32F0_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */
#define STM32F0_EXTI_EMR_OFFSET 0x0004 /* Event mask register */
#define STM32F0_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */
#define STM32F0_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */
#define STM32F0_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */
#define STM32F0_EXTI_PR_OFFSET 0x0014 /* Pending register */
/* Register Addresses ***************************************************************/
#define STM32F0_EXTI_IMR (STM32F0_EXTI_BASE+STM32F0_EXTI_IMR_OFFSET)
#define STM32F0_EXTI_EMR (STM32F0_EXTI_BASE+STM32F0_EXTI_EMR_OFFSET)
#define STM32F0_EXTI_RTSR (STM32F0_EXTI_BASE+STM32F0_EXTI_RTSR_OFFSET)
#define STM32F0_EXTI_FTSR (STM32F0_EXTI_BASE+STM32F0_EXTI_FTSR_OFFSET)
#define STM32F0_EXTI_SWIER (STM32F0_EXTI_BASE+STM32F0_EXTI_SWIER_OFFSET)
#define STM32F0_EXTI_PR (STM32F0_EXTI_BASE+STM32F0_EXTI_PR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* EXTI lines > 15 are associated with internal devices: */
#define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */
#define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */
#define EXTI_USB_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB wake up event */
#define EXTI_RTC_TAMPER (1 << 19) /* EXTI line 19 is connected to the RTC Tamper and TimeStamp events */
#define EXTI_RTC_WAKEUP (1 << 20) /* EXTI line 20 is connected to the RTC Wakeup event */
#define EXTI_COMP1 (1 << 21) /* EXTI line 21 is connected to the COMP1 (comparator) output */
#define EXTI_COMP2 (1 << 22) /* EXTI line 22 is connected to the COMP2 (comparator) output */
#define EXTI_I2C1 (1 << 23) /* EXTI line 23 is connected to the I2C1 wakeup */
/* EXTI line 24 is reserved (internally held low) */
#define EXTI_USART1 (1 << 25) /* EXTI line 25 is connected to the USART1 wakeup */
#define EXTI_USART2 (1 << 26) /* EXTI line 26 is connected to the USART2 wakeup */
#define EXTI_CEC (1 << 27) /* EXTI line 27 is connected to the CEC wakeup */
#define EXTI_USART3 (1 << 28) /* EXTI line 28 is connected to the USART3 wakeup */
/* EXTI line 29 is reserved (internally held low) */
/* EXTI line 30 is reserved (internally held low) */
#define EXTI_VDDIO2 (1 << 31) /* EXTI line 31 is connected to the Vddio2 supply comparator */
/* Interrupt mask register */
#define EXTI_IMR_BIT(n) STM32F0_EXTI_BIT(n) /* 1=Interrupt request from line x is not masked */
#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */
#define EXTI_IMR_MASK STM32F0_EXTI_MASK
/* Event mask register */
#define EXTI_EMR_BIT(n) STM32F0_EXTI_BIT(n) /* 1=Event request from line x is not mask */
#define EXTI_EMR_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */
#define EXTI_EMR_MASK STM32F0_EXTI_MASK
/* Rising Trigger selection register */
#define EXTI_RTSR_BIT(n) STM32F0_EXTI_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */
#define EXTI_RTSR_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */
#define EXTI_RTSR_MASK STM32F0_EXTI_MASK
/* Falling Trigger selection register */
#define EXTI_FTSR_BIT(n) STM32F0_EXTI_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */
#define EXTI_FTSR_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */
#define EXTI_FTSR_MASK STM32F0_EXTI_MASK
/* Software interrupt event register */
#define EXTI_SWIER_BIT(n) STM32F0_EXTI_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */
#define EXTI_SWIER_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */
#define EXTI_SWIER_MASK STM32F0_EXTI_MASK
/* Pending register */
#define EXTI_PR_BIT(n) STM32F0_EXTI_BIT(n) /* 1=Selected trigger request occurred */
#define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
#define EXTI_PR_MASK STM32F0_EXTI_MASK
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_EXTI_H */

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/****************************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f0_syscfg.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_SYSCFG_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_SYSCFG_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* Register Offsets *********************************************************************************/
#define STM32F0_SYSCFG_CFGR1_OFFSET 0x0000 /* SYSCFG configuration register 1 */
#define STM32F0_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
#define STM32F0_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
#define STM32F0_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
#define STM32F0_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
#define STM32F0_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
#define STM32F0_SYSCFG_CFGR2_OFFSET 0x0018 /* SYSCFG configuration register 2 */
#define STM32F0_SYSCFG_ITLINE0_OFFSET 0x0080 /* SYSCFG interrupt line 0 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE1_OFFSET 0x0084 /* SYSCFG interrupt line 1 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE2_OFFSET 0x0088 /* SYSCFG interrupt line 2 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE3_OFFSET 0x008c /* SYSCFG interrupt line 3 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE4_OFFSET 0x0090 /* SYSCFG interrupt line 4 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE5_OFFSET 0x0094 /* SYSCFG interrupt line 5 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE6_OFFSET 0x0098 /* SYSCFG interrupt line 6 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE7_OFFSET 0x009c /* SYSCFG interrupt line 7 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE8_OFFSET 0x00a0 /* SYSCFG interrupt line 8 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE9_OFFSET 0x00a4 /* SYSCFG interrupt line 9 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE10_OFFSET 0x00a8 /* SYSCFG interrupt line 10 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE11_OFFSET 0x00ac /* SYSCFG interrupt line 11 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE12_OFFSET 0x00b0 /* SYSCFG interrupt line 12 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE13_OFFSET 0x00b4 /* SYSCFG interrupt line 13 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE14_OFFSET 0x00b8 /* SYSCFG interrupt line 14 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE15_OFFSET 0x00bc /* SYSCFG interrupt line 15 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE16_OFFSET 0x00c0 /* SYSCFG interrupt line 16 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE17_OFFSET 0x00c4 /* SYSCFG interrupt line 17 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE18_OFFSET 0x00c8 /* SYSCFG interrupt line 18 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE19_OFFSET 0x00cc /* SYSCFG interrupt line 19 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE20_OFFSET 0x00d0 /* SYSCFG interrupt line 20 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE21_OFFSET 0x00d4 /* SYSCFG interrupt line 21 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE22_OFFSET 0x00d8 /* SYSCFG interrupt line 22 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE23_OFFSET 0x00dc /* SYSCFG interrupt line 23 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE24_OFFSET 0x00e0 /* SYSCFG interrupt line 24 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE25_OFFSET 0x00e4 /* SYSCFG interrupt line 25 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE26_OFFSET 0x00e8 /* SYSCFG interrupt line 26 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE27_OFFSET 0x00ec /* SYSCFG interrupt line 27 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE28_OFFSET 0x00f0 /* SYSCFG interrupt line 28 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE29_OFFSET 0x00f4 /* SYSCFG interrupt line 29 status register (STM32F09x) */
#define STM32F0_SYSCFG_ITLINE30_OFFSET 0x00f8 /* SYSCFG interrupt line 30 status register (STM32F09x) */
/* Register Addresses *******************************************************************************/
#define STM32F0_SYSCFG_CFGR1 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_CFGR1_OFFSET)
#define STM32F0_SYSCFG_EXTICR(p) (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_EXTICR_OFFSET(p))
#define STM32F0_SYSCFG_EXTICR1 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_EXTICR1_OFFSET)
#define STM32F0_SYSCFG_EXTICR2 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_EXTICR2_OFFSET)
#define STM32F0_SYSCFG_EXTICR3 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_EXTICR3_OFFSET)
#define STM32F0_SYSCFG_EXTICR4 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_EXTICR4_OFFSET)
#define STM32F0_SYSCFG_CFGR2 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_CFGR2_OFFSET)
#define STM32F0_SYSCFG_ITLINE0 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE0_OFFSET)
#define STM32F0_SYSCFG_ITLINE1 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE1_OFFSET)
#define STM32F0_SYSCFG_ITLINE2 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE2_OFFSET)
#define STM32F0_SYSCFG_ITLINE3 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE3_OFFSET)
#define STM32F0_SYSCFG_ITLINE4 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE4_OFFSET)
#define STM32F0_SYSCFG_ITLINE5 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE5_OFFSET)
#define STM32F0_SYSCFG_ITLINE6 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE6_OFFSET)
#define STM32F0_SYSCFG_ITLINE7 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE7_OFFSET)
#define STM32F0_SYSCFG_ITLINE8 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE8_OFFSET)
#define STM32F0_SYSCFG_ITLINE9 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE9_OFFSET)
#define STM32F0_SYSCFG_ITLINE10 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE10_OFFSET)
#define STM32F0_SYSCFG_ITLINE11 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE11_OFFSET)
#define STM32F0_SYSCFG_ITLINE12 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE12_OFFSET)
#define STM32F0_SYSCFG_ITLINE13 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE13_OFFSET)
#define STM32F0_SYSCFG_ITLINE14 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE14_OFFSET)
#define STM32F0_SYSCFG_ITLINE15 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE15_OFFSET)
#define STM32F0_SYSCFG_ITLINE16 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE16_OFFSET)
#define STM32F0_SYSCFG_ITLINE17 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE17_OFFSET)
#define STM32F0_SYSCFG_ITLINE18 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE18_OFFSET)
#define STM32F0_SYSCFG_ITLINE19 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE19_OFFSET)
#define STM32F0_SYSCFG_ITLINE20 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE20_OFFSET)
#define STM32F0_SYSCFG_ITLINE21 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE21_OFFSET)
#define STM32F0_SYSCFG_ITLINE22 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE22_OFFSET)
#define STM32F0_SYSCFG_ITLINE23 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE23_OFFSET)
#define STM32F0_SYSCFG_ITLINE24 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE24_OFFSET)
#define STM32F0_SYSCFG_ITLINE25 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE25_OFFSET)
#define STM32F0_SYSCFG_ITLINE26 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE26_OFFSET)
#define STM32F0_SYSCFG_ITLINE27 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE27_OFFSET)
#define STM32F0_SYSCFG_ITLINE28 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE28_OFFSET)
#define STM32F0_SYSCFG_ITLINE29 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE29_OFFSET)
#define STM32F0_SYSCFG_ITLINE30 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE30_OFFSET)
/* Register Bitfield Definitions ********************************************************************/
/* SYSCFG memory remap register */
#define SYSCFG_CFGR1_MEMMODE_SHIFT (0) /* Bits 1:0 MEM_MODE: Memory mapping selection */
#define SYSCFG_CFGR1_MEMMODE_MASK (3 << SYSCFG_CFGR1_MEMMODE_SHIFT)
# define SYSCFG_CFGR1_MEMMODE_FLASH (0 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 00: Main Flash at 0x00000000 */
# define SYSCFG_CFGR1_MEMMODE_SYSTEM (1 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 01: System Flash at 0x00000000 */
# define SYSCFG_CFGR1_MEMMODE_SRAM (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 11: Embedded SRAM at 0x00000000 */
#define SYSCFG_CFGR1_PA11_PA12_RMP (1 << 4) /* Bit 4: PA11 and PA12 remapping bit for small packages */
#define SYSCFG_CFGR1_IRMOD_SHIFT (6) /* Bits 6-7: IR Modulation Envelope signal selection */
#define SYSCFG_CFGR1_IRMOD_MASK (3 << SYSCFG_CFGR1_IRMOD_SHIFT)
# define SYSCFG_CFGR1_IRMOD_TIM16 (0 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 00: TIM16 selected */
# define SYSCFG_CFGR1_IRMOD_USART1 (1 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 01: USART1 selected */
# define SYSCFG_CFGR1_IRMOD_USART4 (2 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 10: USART1 selected */
#define SYSCFG_CFGR1_ADC_DMARMP (1 << 8) /* Bit 8: ADC DMA remapping bit. Only STM32F03x/F04x/F05x/F07x */
#define SYSCFG_CFGR1_USART1_TXDMARMP (1 << 9) /* Bit 9: USART1_TX_DMA request remapping bit. Only STM32F03x/F04x/F05x/F07x */
#define SYSCFG_CFGR1_USART1_RXDMARMP (1 << 10) /* Bit 10: USART1_TX_DMA request remapping bit. Only STM32F03x/F04x/F05x/F07x */
#define SYSCFG_CFGR1_TIM16_DMARMP (1 << 11) /* Bit 11: TIM16 DMA request remapping bit */
#define SYSCFG_CFGR1_TIM17_DMARMP (1 << 12) /* Bit 12: TIM17 DMA request remapping bit */
#define SYSCFG_CFGR1_TIM16_DMARMP2 (1 << 13) /* Bit 13: TIM16 alternate DMA request remapping bit */
#define SYSCFG_CFGR1_TIM17_DMARMP2 (1 << 14) /* Bit 14: TIM17 alternate DMA request remapping bit */
#define SYSCFG_CFGR1_I2C_PBXFMP_SHIFT (16) /* Bits 16-19: Fast Mode Plus (FM+) driving capability */
#define SYSCFG_CFGR1_I2C_PBXFMP_MASK (15 << SYSCFG_CFGR1_I2C_PBXFMP_SHIFT)
#define SYSCFG_CFGR1_I2C1_FMP (1 << 20) /* Bit 20: I2C1 fast mode Plus driving capability */
#define SYSCFG_CFGR1_I2C2_FMP (1 << 21) /* Bit 21: I2C2 fast mode Plus driving capability */
#define SYSCFG_CFGR1_I2C_PAXFMP_SHIFT (22) /* Bits 22-23: Fast Mode Plus (FM+) driving capability */
#define SYSCFG_CFGR1_I2C_PAXFMP_MASK (3 << SYSCFG_CFGR1_I2C_PAXFMP_SHIFT)
#define SYSCFG_CFGR1_SPI2_DMARMP (1 << 24) /* Bit 24: SPI2 DMA request remapping bit. */
#define SYSCFG_CFGR1_USART2_DMARMP (1 << 25) /* Bit 25: USART2 DMA request remapping bit. */
#define SYSCFG_CFGR1_USART3_DMARMP (1 << 26) /* Bit 26: USART3 DMA request remapping bit. */
#define SYSCFG_CFGR1_I2C1_DMARMP (1 << 27) /* Bit 27: I2C1 DMA request remapping bit. */
#define SYSCFG_CFGR1_TIM1_DMARMP (1 << 28) /* Bit 28: TIM1 DMA request remapping bit. */
#define SYSCFG_CFGR1_TIM2_DMARMP (1 << 29) /* Bit 29: TIM2 DMA request remapping bit. */
#define SYSCFG_CFGR1_TIM3_DMARMP (1 << 30) /* Bit 30: TIM3 DMA request remapping bit. */
/* SYSCFG external interrupt configuration register 1-4 */
#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */
#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */
#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */
#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[x] pin */
#define SYSCFG_EXTICR_PORT_MASK (15)
#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 coinfiguration */
#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 coinfiguration */
#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 coinfiguration */
#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 coinfiguration */
#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 coinfiguration */
#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 coinfiguration */
#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 coinfiguration */
#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 coinfiguration */
#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 coinfiguration */
#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 coinfiguration */
#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 coinfiguration */
#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 coinfiguration */
#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 coinfiguration */
#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 coinfiguration */
#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 coinfiguration */
#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 coinfiguration */
#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
/* SYSCFG configuration register 2 */
#define SYSCFG_CFGR2_LOCKUPLOCK (1 << 0) /* Bit 0: Cortex-M0 Hardfault output bit enable */
#define SYSCFG_CFGR2_SRAM_PARITYLOCK (1 << 1) /* Bit 1: RAM parity lock */
#define SYSCFG_CFGR2_PVDLOCK (1 << 2) /* Bit 2: PVD lock enable */
#define SYSCFG_CFGR2_SRAM_PEF (1 << 8) /* Bit 8: SRAM parity error */
/* SYSCFG interrupt line 0 status register */
#define SYSCFG_ITLINE0_WWDG (1 << 0) /* Bit 0: Window Watchdog interrupt pending flag */
/* SYSCFG interrupt line 1 status register */
#define SYSCFG_ITLINE1_PVDOUT (1 << 0) /* Bit 0: PVD supply monitoring interrupt request pending (EXTI line 16) */
#define SYSCFG_ITLINE1_VDDIO2 (1 << 0) /* Bit 1: VDDIO2 supply monitoring interrupt request pending (EXTI line 31) */
/* SYSCFG interrupt line 2 status register */
#define SYSCFG_ITLINE2_RTC_WAKEUP (1 << 0) /* Bit 0: RTC Wake Up interrupt request pending (EXTI line 20) */
#define SYSCFG_ITLINE2_RTC_TSTAMP (1 << 1) /* Bit 1: RTC Tamper and TimeStamp interrupt request pending (EXTI line 19) */
#define SYSCFG_ITLINE2_RTC_ALRA (1 << 2) /* Bit 2: RTC Alarm interrupt request pending (EXTI line 17) */
/* SYSCFG interrupt line 3 status register */
#define SYSCFG_ITLINE3_FLASH_ITF (1 << 0) /* Bit 0: Flash interface interrupt request pending */
/* SYSCFG interrupt line 4 status register */
#define SYSCFG_ITLINE4_RCC (1 << 0) /* Bit 0: Reset and clock control interrupt request pending */
#define SYSCFG_ITLINE4_CRS (1 << 1) /* Bit 1: Clock recovery system interrupt request pending */
/* SYSCFG interrupt line 5 status register */
#define SYSCFG_ITLINE5_EXTI0 (1 << 0) /* Bit 0: EXTI line 0 interrupt request pending */
#define SYSCFG_ITLINE5_EXTI1 (1 << 1) /* Bit 1: EXTI line 1 interrupt request pending */
/* SYSCFG interrupt line 6 status register */
#define SYSCFG_ITLINE6_EXTI2 (1 << 0) /* Bit 0: EXTI line 2 interrupt request pending */
#define SYSCFG_ITLINE6_EXTI3 (1 << 1) /* Bit 1: EXTI line 3 interrupt request pending */
/* SYSCFG interrupt line 7 status register */
#define SYSCFG_ITLINE7_EXTI4 (1 << 0) /* Bit 0: EXTI line 4 interrupt request pending */
#define SYSCFG_ITLINE7_EXTI5 (1 << 1) /* Bit 1: EXTI line 5 interrupt request pending */
#define SYSCFG_ITLINE7_EXTI6 (1 << 2) /* Bit 2: EXTI line 6 interrupt request pending */
#define SYSCFG_ITLINE7_EXTI7 (1 << 3) /* Bit 3: EXTI line 7 interrupt request pending */
#define SYSCFG_ITLINE7_EXTI8 (1 << 4) /* Bit 4: EXTI line 8 interrupt request pending */
#define SYSCFG_ITLINE7_EXTI9 (1 << 5) /* Bit 5: EXTI line 9 interrupt request pending */
#define SYSCFG_ITLINE7_EXTI10 (1 << 6) /* Bit 6: EXTI line 10 interrupt request pending */
#define SYSCFG_ITLINE7_EXTI11 (1 << 7) /* Bit 7: EXTI line 11 interrupt request pending */
#define SYSCFG_ITLINE7_EXTI12 (1 << 8) /* Bit 8: EXTI line 12 interrupt request pending */
#define SYSCFG_ITLINE7_EXTI13 (1 << 9) /* Bit 9: EXTI line 13 interrupt request pending */
#define SYSCFG_ITLINE7_EXTI14 (1 << 10) /* Bit 10: EXTI line 14 interrupt request pending */
#define SYSCFG_ITLINE7_EXTI15 (1 << 11) /* Bit 11: EXTI line 15 interrupt request pending */
/* SYSCFG interrupt line 8 status register */
#define SYSCFG_ITLINE8_TCS_MCE (1 << 0) /* Bit 0: Touch sensing controller max count error interrupt request pending */
#define SYSCFG_ITLINE8_TCS_EOA (1 << 1) /* Bit 1: Touch sensing controller end of acquisition interrupt request pending */
/* SYSCFG interrupt line 9 status register */
#define SYSCFG_ITLINE9_DMA1_CH1 (1 << 0) /* Bit 0: DMA1 channel 1 interrupt request pending */
/* SYSCFG interrupt line 10 status register */
#define SYSCFG_ITLINE10_DMA1_CH2 (1 << 0) /* Bit 0: DMA1 channel 2 interrupt request pending */
#define SYSCFG_ITLINE10_DMA1_CH3 (1 << 1) /* Bit 1: DMA1 channel 3 interrupt request pending */
#define SYSCFG_ITLINE10_DMA2_CH1 (1 << 2) /* Bit 0: DMA2 channel 1 interrupt request pending */
#define SYSCFG_ITLINE10_DMA2_CH2 (1 << 3) /* Bit 1: DMA2 channel 2 interrupt request pending */
/* SYSCFG interrupt line 11 status register */
#define SYSCFG_ITLINE11_DMA1_CH4 (1 << 0) /* Bit 0: DMA1 channel 4 interrupt request pending */
#define SYSCFG_ITLINE11_DMA1_CH5 (1 << 1) /* Bit 1: DMA1 channel 5 interrupt request pending */
#define SYSCFG_ITLINE11_DMA1_CH6 (1 << 2) /* Bit 2: DMA1 channel 6 interrupt request pending */
#define SYSCFG_ITLINE11_DMA1_CH7 (1 << 3) /* Bit 3: DMA1 channel 7 interrupt request pending */
#define SYSCFG_ITLINE11_DMA2_CH3 (1 << 4) /* Bit 4: DMA2 channel 3 interrupt request pending */
#define SYSCFG_ITLINE11_DMA2_CH4 (1 << 5) /* Bit 5: DMA2 channel 4 interrupt request pending */
#define SYSCFG_ITLINE11_DMA2_CH5 (1 << 6) /* Bit 6: DMA2 channel 5 interrupt request pending */
/* SYSCFG interrupt line 12 status register */
#define SYSCFG_ITLINE12_ADC (1 << 0) /* Bit 0: ADC interrupt request pending */
#define SYSCFG_ITLINE12_COMP1 (1 << 1) /* Bit 1: Comparator 1 interrupt request pending */
#define SYSCFG_ITLINE12_COMP2 (1 << 2) /* Bit 2: Comparator 2 interrupt request pending */
/* SYSCFG interrupt line 13 status register */
#define SYSCFG_ITLINE13_TIM1_CCU (1 << 0) /* Bit 0: TIM1 commutation interrupt request pending */
#define SYSCFG_ITLINE13_TIM1_TRG (1 << 1) /* Bit 1: TIM1 triggerinterrupt request pending */
#define SYSCFG_ITLINE13_TIM1_UPD (1 << 2) /* Bit 2: TIM1 update interrupt request pending */
#define SYSCFG_ITLINE13_TIM1_BRK (1 << 3) /* Bit 3: TIM1 break interrupt request pending */
/* SYSCFG interrupt line 14 status register */
#define SYSCFG_ITLINE14_TIM1_CC (1 << 0) /* Bit 0: TIM1 capture compare interrupt request pending */
/* SYSCFG interrupt line 15 status register */
#define SYSCFG_ITLINE15_TIM2 (1 << 0) /* Bit 0: Timer 2 interrupt request pending */
/* SYSCFG interrupt line 16 status register */
#define SYSCFG_ITLINE16_TIM3 (1 << 0) /* Bit 0: Timer 3 interrupt request pending */
/* SYSCFG interrupt line 17 status register */
#define SYSCFG_ITLINE17_TIM6 (1 << 0) /* Bit 0: Timer 6 interrupt request pending */
#define SYSCFG_ITLINE17_DAC (1 << 1) /* Bit 1: DAC underrun interrupt request pending */
/* SYSCFG interrupt line 18 status register */
#define SYSCFG_ITLINE18_TIM7 (1 << 0) /* Bit 0: Timer 7 interrupt request pending */
/* SYSCFG interrupt line 19 status register */
#define SYSCFG_ITLINE19_TIM14 (1 << 0) /* Bit 0: Timer 14 interrupt request pending */
/* SYSCFG interrupt line 20 status register */
#define SYSCFG_ITLINE20_TIM15 (1 << 0) /* Bit 0: Timer 15 interrupt request pending */
/* SYSCFG interrupt line 21 status register */
#define SYSCFG_ITLINE21_TIM16 (1 << 0) /* Bit 0: Timer 16 interrupt request pending */
/* SYSCFG interrupt line 22 status register */
#define SYSCFG_ITLINE22_TIM17 (1 << 0) /* Bit 0: Timer 17 interrupt request pending */
/* SYSCFG interrupt line 23 status register */
#define SYSCFG_ITLINE23_I2C1 (1 << 0) /* Bit 0: I2C1 interrupt request pending, combined with EXTI line 23 */
/* SYSCFG interrupt line 24 status register */
#define SYSCFG_ITLINE24_I2C2 (1 << 0) /* Bit 0: I2C2 interrupt request pending */
/* SYSCFG interrupt line 25 status register */
#define SYSCFG_ITLINE25_SPI1 (1 << 0) /* Bit 0: SPI1 interrupt request pending */
/* SYSCFG interrupt line 26 status register */
#define SYSCFG_ITLINE26_SPI2 (1 << 0) /* Bit 0: SPI2 interrupt request pending */
/* SYSCFG interrupt line 27 status register */
#define SYSCFG_ITLINE27_USART1 (1 << 0) /* Bit 0: USART1 interrupt request pending */
/* SYSCFG interrupt line 28 status register */
#define SYSCFG_ITLINE28_USART2 (1 << 0) /* Bit 0: USART2 interrupt request pending */
/* SYSCFG interrupt line 29 status register */
#define SYSCFG_ITLINE29_USART3 (1 << 0) /* Bit 0: USART3 interrupt request pending */
#define SYSCFG_ITLINE29_USART4 (1 << 1) /* Bit 1: USART4 interrupt request pending */
#define SYSCFG_ITLINE29_USART5 (1 << 2) /* Bit 2: USART5 interrupt request pending */
#define SYSCFG_ITLINE29_USART6 (1 << 3) /* Bit 3: USART6 interrupt request pending */
#define SYSCFG_ITLINE29_USART7 (1 << 4) /* Bit 4: USART7 interrupt request pending */
#define SYSCFG_ITLINE29_USART8 (1 << 5) /* Bit 5: USART8 interrupt request pending */
/* SYSCFG interrupt line 30 status register */
#define SYSCFG_ITLINE30_CEC (1 << 0) /* Bit 0: CEC interrupt request pending, combined with EXTI line 27 */
#define SYSCFG_ITLINE30_CAN (1 << 1) /* Bit 1: CAN interrupt request pending */
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_SYSCFG_H */

142
arch/arm/src/stm32f0/chip/stm32f0_wdt.h
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@ -1,142 +0,0 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f0_wdg.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_WDG_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_WDG_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define STM32F0_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */
#define STM32F0_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */
#define STM32F0_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */
#define STM32F0_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */
#define STM32F0_IWDG_WINR_OFFSET 0x0010 /* Window register (32-bit) */
#define STM32F0_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */
#define STM32F0_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */
#define STM32F0_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */
/* Register Addresses ***************************************************************/
#define STM32F0_IWDG_KR (STM32F0_IWDG_BASE+STM32F0_IWDG_KR_OFFSET)
#define STM32F0_IWDG_PR (STM32F0_IWDG_BASE+STM32F0_IWDG_PR_OFFSET)
#define STM32F0_IWDG_RLR (STM32F0_IWDG_BASE+STM32F0_IWDG_RLR_OFFSET)
#define STM32F0_IWDG_SR (STM32F0_IWDG_BASE+STM32F0_IWDG_SR_OFFSET)
#define STM32F0_IWDG_WINR (STM32F0_IWDG_BASE+STM32F0_IWDG_WINR_OFFSET)
#define STM32F0_WWDG_CR (STM32F0_WWDG_BASE+STM32F0_WWDG_CR_OFFSET)
#define STM32F0_WWDG_CFR (STM32F0_WWDG_BASE+STM32F0_WWDG_CFR_OFFSET)
#define STM32F0_WWDG_SR (STM32F0_WWDG_BASE+STM32F0_WWDG_SR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* Key register (32-bit) */
#define IWDG_KR_KEY_SHIFT (0) /* Bits 15-0: Key value (write only, read 0000h) */
#define IWDG_KR_KEY_MASK (0xffff << IWDG_KR_KEY_SHIFT)
#define IWDG_KR_KEY_ENABLE (0x5555) /* Enable register access */
#define IWDG_KR_KEY_DISABLE (0x0000) /* Disable register access */
#define IWDG_KR_KEY_RELOAD (0xaaaa) /* Reload the counter */
#define IWDG_KR_KEY_START (0xcccc) /* Start the watchdog */
/* Prescaler register (32-bit) */
#define IWDG_PR_SHIFT (0) /* Bits 2-0: Prescaler divider */
#define IWDG_PR_MASK (7 << IWDG_PR_SHIFT)
# define IWDG_PR_DIV4 (0 << IWDG_PR_SHIFT) /* 000: divider /4 */
# define IWDG_PR_DIV8 (1 << IWDG_PR_SHIFT) /* 001: divider /8 */
# define IWDG_PR_DIV16 (2 << IWDG_PR_SHIFT) /* 010: divider /16 */
# define IWDG_PR_DIV32 (3 << IWDG_PR_SHIFT) /* 011: divider /32 */
# define IWDG_PR_DIV64 (4 << IWDG_PR_SHIFT) /* 100: divider /64 */
# define IWDG_PR_DIV128 (5 << IWDG_PR_SHIFT) /* 101: divider /128 */
# define IWDG_PR_DIV256 (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */
/* Reload register (32-bit) */
#define IWDG_RLR_RL_SHIFT (0) /* Bits11:0 RL[11:0]: Watchdog counter reload value */
#define IWDG_RLR_RL_MASK (0x0fff << IWDG_RLR_RL_SHIFT)
#define IWDG_RLR_MAX (0xfff)
/* Status register (32-bit) */
#define IWDG_SR_PVU (1 << 0) /* Bit 0: Watchdog prescaler value update */
#define IWDG_SR_RVU (1 << 1) /* Bit 1: Watchdog counter reload value update */
#define IWDG_SR_WVU (1 << 2) /* Bit 2: Watchdog counter window value update */
/* Window register (32-bit) */
#define IWDG_WINR_SHIFT (0)
#define IWDG_WINR_MASK (0x0fff << IWDG_WINR_SHIFT)
/* Control Register (32-bit) */
#define WWDG_CR_T_SHIFT (0) /* Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) */
#define WWDG_CR_T_MASK (0x7f << WWDG_CR_T_SHIFT)
# define WWDG_CR_T_MAX (0x3f << WWDG_CR_T_SHIFT)
# define WWDG_CR_T_RESET (0x40 << WWDG_CR_T_SHIFT)
#define WWDG_CR_WDGA (1 << 7) /* Bit 7: Activation bit */
/* Configuration register (32-bit) */
#define WWDG_CFR_W_SHIFT (0) /* Bits 6:0 W[6:0] 7-bit window value */
#define WWDG_CFR_W_MASK (0x7f << WWDG_CFR_W_SHIFT)
#define WWDG_CFR_WDGTB_SHIFT (7) /* Bits 8:7 [1:0]: Timer Base */
#define WWDG_CFR_WDGTB_MASK (3 << WWDG_CFR_WDGTB_SHIFT)
# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */
# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */
# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */
# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */
#define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */
/* Status register (32-bit) */
#define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_WDG_H */

1522
arch/arm/src/stm32f0l0/Kconfig Normal file
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File diff suppressed because it is too large Load diff

40
arch/arm/src/stm32f0/Make.defs → arch/arm/src/stm32f0l0/Make.defs
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@ -1,5 +1,5 @@
############################################################################
# arch/arm/src/stm32f0/Make.defs
# arch/arm/src/stm32f0l0/Make.defs
#
# Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
@ -65,51 +65,51 @@ CMN_CSRCS += up_dumpnvic.c
endif
CHIP_ASRCS =
CHIP_CSRCS = stm32f0_clockconfig.c stm32f0_gpio.c stm32f0_irq.c
CHIP_CSRCS += stm32f0_lowputc.c stm32f0_serial.c stm32f0_start.c
CHIP_CSRCS = stm32_clockconfig.c stm32_gpio.c stm32_irq.c
CHIP_CSRCS += stm32_lowputc.c stm32_serial.c stm32_start.c
# Configuration-dependent STM32F0xx files
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CHIP_CSRCS += stm32f0_idle.c
CHIP_CSRCS += stm32_idle.c
endif
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += stm32f0_timerisr.c
CHIP_CSRCS += stm32_timerisr.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += stm32f0_userspace.c
CHIP_CSRCS += stm32_userspace.c
endif
ifeq ($(CONFIG_STM32F0_GPIOIRQ),y)
CHIP_CSRCS += stm32f0_gpioint.c
ifeq ($(CONFIG_STM32F0L0_GPIOIRQ),y)
CHIP_CSRCS += stm32_gpioint.c
endif
ifeq ($(CONFIG_ARCH_IRQPRIO),y)
CHIP_CSRCS += stm32f0_irqprio.c
CHIP_CSRCS += stm32_irqprio.c
endif
ifeq ($(CONFIG_STM32F0_HAVE_HSI48),y)
CHIP_CSRCS += stm32f0_hsi48.c
ifeq ($(CONFIG_STM32F0L0_HAVE_HSI48),y)
CHIP_CSRCS += stm32_hsi48.c
endif
ifeq ($(CONFIG_STM32F0_USB),y)
CHIP_CSRCS += stm32f0_usbdev.c
ifeq ($(CONFIG_STM32F0L0_USB),y)
CHIP_CSRCS += stm32_usbdev.c
endif
ifeq ($(CONFIG_STM32F0_I2C),y)
CHIP_CSRCS += stm32f0_i2c.c
ifeq ($(CONFIG_STM32F0L0_I2C),y)
CHIP_CSRCS += stm32_i2c.c
endif
ifeq ($(CONFIG_STM32F0_SPI0),y)
CHIP_CSRCS += stm32f0_spi.c
ifeq ($(CONFIG_STM32F0L0_SPI0),y)
CHIP_CSRCS += stm32_spi.c
else
ifeq ($(CONFIG_STM32F0_SPI1),y)
CHIP_CSRCS += stm32f0_spi.c
ifeq ($(CONFIG_STM32F0L0_SPI1),y)
CHIP_CSRCS += stm32_spi.c
endif
endif
ifeq ($(CONFIG_PWM),y)
CHIP_CSRCS += stm32f0_pwm.c
CHIP_CSRCS += stm32_pwm.c
endif

12
arch/arm/src/stm32f0/chip.h → arch/arm/src/stm32f0l0/chip.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip.h
* arch/arm/src/stm32f0l0/chip.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_H
/************************************************************************************
* Included Files
@ -46,7 +46,7 @@
/* Include the chip capabilities file */
#include <arch/stm32f0/chip.h>
#include <arch/stm32f0l0/chip.h>
#define ARMV6M_PERIPHERAL_INTERRUPTS 32
@ -54,6 +54,6 @@
* this file for the proper setup.
*/
#include "chip/stm32f0_memorymap.h"
#include "hardware/stm32_memorymap.h"
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_H */

195
arch/arm/src/stm32f0l0/hardware/stm32_adc.h Normal file
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@ -0,0 +1,195 @@
/********************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_adc.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_ADC_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_ADC_H
/********************************************************************************
* Included Files
********************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/********************************************************************************
* Pre-processor Definitions
********************************************************************************/
/* Register Offsets *********************************************************************************/
#define STM32_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */
#define STM32_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */
#define STM32_ADC_CR_OFFSET 0x0008 /* ADC control register */
#define STM32_ADC_CFGR1_OFFSET 0x000c /* ADC configuration register 1 */
#define STM32_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */
#define STM32_ADC_SMPR_OFFSET 0x0014 /* ADC sample time register */
#define STM32_ADC_TR_OFFSET 0x0020 /* ADC watchdog threshold register */
#define STM32_ADC_CHSELR_OFFSET 0x0028 /* ADC channel selection register */
#define STM32_ADC_DR_OFFSET 0x0040 /* ADC regular data register */
#define STM32_ADC_CCR_OFFSET 0x0308 /* ADC common configuration register */
/* Register Addresses *******************************************************************************/
#define STM32_ADC_ISR (STM32_ADC_BASE + STM32_ADC_ISR_OFFSET)
#define STM32_ADC_IER (STM32_ADC_BASE + STM32_ADC_IER_OFFSET)
#define STM32_ADC_CR (STM32_ADC_BASE + STM32_ADC_CR_OFFSET)
#define STM32_ADC_CFGR1 (STM32_ADC_BASE + STM32_ADC_CFGR1_OFFSET)
#define STM32_ADC_CFGR2 (STM32_ADC_BASE + STM32_ADC_CFGR2_OFFSET)
#define STM32_ADC_SMPR (STM32_ADC_BASE + STM32_ADC_SMPR_OFFSET)
#define STM32_ADC_TR (STM32_ADC_BASE + STM32_ADC_TR_OFFSET)
#define STM32_ADC_CHSELR (STM32_ADC_BASE + STM32_ADC_CHSELR_OFFSET)
#define STM32_ADC_DR (STM32_ADC_BASE + STM32_ADC_DR_OFFSET)
#define STM32_ADC_CCR (STM32_ADC_BASE + STM32_ADC_CCR_OFFSET)
/* Register Bitfield Definitions ************************************************/
/* ADC interrupt and status register (ISR) and ADC interrupt enable register (IER) */
#define ADC_INT_ARDY (1 << 0) /* Bit 0: ADC ready */
#define ADC_INT_EOSMP (1 << 1) /* Bit 1: End of sampling flag */
#define ADC_INT_EOC (1 << 2) /* Bit 2: End of conversion */
#define ADC_INT_EOS (1 << 3) /* Bit 3: End of regular sequence flag */
#define ADC_INT_OVR (1 << 4) /* Bit 4: Overrun */
#define ADC_INT_AWD (1 << 7) /* Bit 7: Analog watchdog flag */
/* ADC control register */
#define ADC_CR_ADEN (1 << 0) /* Bit 0: ADC enable control */
#define ADC_CR_ADDIS (1 << 1) /* Bit 1: ADC disable command */
#define ADC_CR_ADSTART (1 << 2) /* Bit 2: ADC start of regular conversion */
#define ADC_CR_ADSTP (1 << 4) /* Bit 4: ADC stop of regular conversion command */
#define ADC_CR_ADCAL (1 << 31) /* Bit 31: ADC calibration */
/* ADC configuration register 1 */
#define ADC_CFGR1_DMAEN (1 << 0) /* Bit 0: Direct memory access enable */
#define ADC_CFGR1_DMACFG (1 << 1) /* Bit 1: Direct memory access configuration */
#define ADC_CFGR1_SCANDIR (1 << 2) /* Bit 2: Scan sequence direction */
#define ADC_CFGR1_RES_SHIFT (3) /* Bits 3-4: Data resolution */
#define ADC_CFGR1_RES_MASK (3 << ADC_CFGR1_RES_SHIFT)
# define ADC_CFGR1_RES_12BIT (0 << ADC_CFGR1_RES_SHIFT) /* 15 ADCCLK clyes */
# define ADC_CFGR1_RES_10BIT (1 << ADC_CFGR1_RES_SHIFT) /* 13 ADCCLK clyes */
# define ADC_CFGR1_RES_8BIT (2 << ADC_CFGR1_RES_SHIFT) /* 11 ADCCLK clyes */
# define ADC_CFGR1_RES_6BIT (3 << ADC_CFGR1_RES_SHIFT) /* 9 ADCCLK clyes */
#define ADC_CFGR1_ALIGN (1 << 5) /* Bit 5: Data Alignment */
#define ADC_CFGR1_EXTSEL_SHIFT (6) /* Bits 6-8: External trigger selection */
#define ADC_CFGR1_EXTSEL_MASK (7 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_TRG0 (0 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_TRG1 (1 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_TRG2 (2 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_TRG3 (3 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_TRG4 (4 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_TRG5 (5 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_TRG6 (6 << ADC_CFGR1_EXTSEL_SHIFT)
# define ADC12_CFGR1_EXTSEL_TRG7 (7 << ADC_CFGR1_EXTSEL_SHIFT)
#define ADC_CFGR1_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */
#define ADC_CFGR1_EXTEN_MASK (3 << ADC_CFGR1_EXTEN_SHIFT)
# define ADC_CFGR1_EXTEN_NONE (0 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection disabled */
# define ADC_CFGR1_EXTEN_RISING (1 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the rising edge */
# define ADC_CFGR1_EXTEN_FALLING (2 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the falling edge */
# define ADC_CFGR1_EXTEN_BOTH (3 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on both edges */
#define ADC_CFGR1_OVRMOD (1 << 12) /* Bit 12: Overrun Mode */
#define ADC_CFGR1_CONT (1 << 13) /* Bit 13: Continuous mode for regular conversions */
#define ADC_CFGR1_WAIT (1 << 14) /* Bit 14: Wait convertion mode */
#define ADC_CFGR1_AUTOFF (1 << 15) /* Bit 15: Auto-off mode */
#define ADC_CFGR1_DISCEN (1 << 16) /* Bit 16: Discontinuous mode on regular channels */
#define ADC_CFGR1_AWDSGL (1 << 22) /* Bit 22: Enable watchdog on single/all channels */
#define ADC_CFGR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable */
#define ADC_CFGR1_AWDCH_SHIFT (26) /* Bits 26-30: Analog watchdog 1 channel select bits */
#define ADC_CFGR1_AWDCH_MASK (31 << ADC_CFGR1_AWDCH_SHIFT)
# define ADC_CFGR1_AWDCH_DISABLED (0 << ADC_CFGR1_AWDCH_SHIFT)
/* ADC configuration register 2 */
#define ADC_CFGR2_CKMODE_SHIFT (30) /* Bits 30-31: ADC clock mode */
#define ADC_CFGR2_CKMODE_MASK (3 << ADC_CFGR2_CKMODE_SHIFT)
# define ADC_CFGR2_CKMODE_ADCCLK (0 << ADC_CFGR2_CKMODE_SHIFT) /* 00: ADCCLK (Asynchronous) generated at product level */
# define ADC_CFGR2_CKMODE_PCLKd2 (1 << ADC_CFGR2_CKMODE_SHIFT) /* 01: PCLK/2 (Synchronous clock mode) */
# define ADC_CFGR2_CKMODE_PCLKd4 (2 << ADC_CFGR2_CKMODE_SHIFT) /* 10: PCLK/4 (Synchronous clock mode) */
/* ADC sample time register */
#define ADC_SMPR_SMP_SHIFT (0) /* Bits 0-2: Sampling time selection */
#define ADC_SMPR_SMP_MASK (7 << ADC_SMPR_SMP_SHIFT)
#define ADC_SMPR_SMP_1p5 (0 << ADC_SMPR_SMP_SHIFT) /* 000: 1.5 cycles */
#define ADC_SMPR_SMP_7p5 (1 << ADC_SMPR_SMP_SHIFT) /* 001: 7.5 cycles */
#define ADC_SMPR_SMP_13p5 (2 << ADC_SMPR_SMP_SHIFT) /* 010: 13.5 cycles */
#define ADC_SMPR_SMP_28p5 (3 << ADC_SMPR_SMP_SHIFT) /* 011: 28.5 cycles */
#define ADC_SMPR_SMP_41p5 (4 << ADC_SMPR_SMP_SHIFT) /* 100: 41.5 cycles */
#define ADC_SMPR_SMP_55p5 (5 << ADC_SMPR_SMP_SHIFT) /* 101: 55.5 cycles */
#define ADC_SMPR_SMP_71p5 (6 << ADC_SMPR_SMP_SHIFT) /* 110: 71.5 cycles */
#define ADC_SMPR_SMP_239p5 (7 << ADC_SMPR_SMP_SHIFT) /* 111: 239.5 cycles */
/* ADC watchdog threshold register */
#define ADC_TR_LT_SHIFT (0) /* Bits 0-11: Analog watchdog lower threshold */
#define ADC_TR_LT_MASK (0x0fff << ADC_TR_LT_SHIFT)
#define ADC_TR_HT_SHIFT (16) /* Bits 16-27: Analog watchdog higher threshold */
#define ADC_TR_HT_MASK (0x0fff << ADC_TR_HT_SHIFT)
/* ADC channel selection register */
#define ADC_CHSELR_CHSEL0 (1 << 0) /* Select channel 0 */
#define ADC_CHSELR_CHSEL1 (1 << 1) /* Select channel 1 */
#define ADC_CHSELR_CHSEL2 (1 << 2) /* Select channel 2 */
#define ADC_CHSELR_CHSEL3 (1 << 3) /* Select channel 3 */
#define ADC_CHSELR_CHSEL4 (1 << 4) /* Select channel 4 */
#define ADC_CHSELR_CHSEL5 (1 << 5) /* Select channel 5 */
#define ADC_CHSELR_CHSEL6 (1 << 6) /* Select channel 6 */
#define ADC_CHSELR_CHSEL7 (1 << 7) /* Select channel 7 */
#define ADC_CHSELR_CHSEL8 (1 << 8) /* Select channel 8 */
#define ADC_CHSELR_CHSEL9 (1 << 9) /* Select channel 9 */
#define ADC_CHSELR_CHSEL10 (1 << 10) /* Select channel 10 */
#define ADC_CHSELR_CHSEL11 (1 << 11) /* Select channel 11 */
#define ADC_CHSELR_CHSEL12 (1 << 12) /* Select channel 12 */
#define ADC_CHSELR_CHSEL13 (1 << 13) /* Select channel 13 */
#define ADC_CHSELR_CHSEL14 (1 << 14) /* Select channel 14 */
#define ADC_CHSELR_CHSEL15 (1 << 15) /* Select channel 15 */
#define ADC_CHSELR_CHSEL16 (1 << 16) /* Select channel 16 */
#define ADC_CHSELR_CHSEL17 (1 << 17) /* Select channel 17 */
#define ADC_CHSELR_CHSEL18 (1 << 18) /* Select channel 18 */
#define ADC_DR_RDATA_SHIFT (0)
#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT)
/* Common configuration register */
#define ADC_CCR_VREFEN (1 << 22) /* Bit 22: VREFINT enable */
#define ADC_CCR_TSEN (1 << 23) /* Bit 23: Temperature sensor enable */
#define ADC_CCR_VBATEN (1 << 24) /* Bit 22: VBAT enable */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_ADC_H */

266
arch/arm/src/stm32f0/chip/stm32f0_can.h → arch/arm/src/stm32f0l0/hardware/stm32_can.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f0_can.h
* arch/arm/src/stm32f0l0/hardware/stm32_can.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_CAN_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_CAN_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CAN_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CAN_H
/************************************************************************************
* Included Files
@ -68,63 +68,63 @@
/* CAN control and status registers */
#define STM32F0_CAN_MCR_OFFSET 0x0000 /* CAN master control register */
#define STM32F0_CAN_MSR_OFFSET 0x0004 /* CAN master status register */
#define STM32F0_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */
#define STM32_CAN_MCR_OFFSET 0x0000 /* CAN master control register */
#define STM32_CAN_MSR_OFFSET 0x0004 /* CAN master status register */
#define STM32_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */
#define STM32F0_CAN_RFR_OFFSET(m) (0x000c+((m)<<2))
#define STM32F0_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */
#define STM32F0_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */
#define STM32_CAN_RFR_OFFSET(m) (0x000c + ((m) << 2))
#define STM32_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */
#define STM32_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */
#define STM32F0_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */
#define STM32F0_CAN_ESR_OFFSET 0x0018 /* CAN error status register */
#define STM32F0_CAN_BTR_OFFSET 0x001c /* CAN bit timing register */
#define STM32_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */
#define STM32_CAN_ESR_OFFSET 0x0018 /* CAN error status register */
#define STM32_CAN_BTR_OFFSET 0x001c /* CAN bit timing register */
/* CAN mailbox registers (3 TX and 2 RX) */
#define STM32F0_CAN_TIR_OFFSET(m) (0x0180+((m)<<4))
#define STM32F0_CAN_TI0R_OFFSET 0x0180 /* TX mailbox identifier register 0 */
#define STM32F0_CAN_TI1R_OFFSET 0x0190 /* TX mailbox identifier register 1 */
#define STM32F0_CAN_TI2R_OFFSET 0x01a0 /* TX mailbox identifier register 2 */
#define STM32_CAN_TIR_OFFSET(m) (0x0180 + ((m) << 4))
#define STM32_CAN_TI0R_OFFSET 0x0180 /* TX mailbox identifier register 0 */
#define STM32_CAN_TI1R_OFFSET 0x0190 /* TX mailbox identifier register 1 */
#define STM32_CAN_TI2R_OFFSET 0x01a0 /* TX mailbox identifier register 2 */
#define STM32F0_CAN_TDTR_OFFSET(m) (0x0184+((m)<<4))
#define STM32F0_CAN_TDT0R_OFFSET 0x0184 /* Mailbox data length control and time stamp register 0 */
#define STM32F0_CAN_TDT1R_OFFSET 0x0194 /* Mailbox data length control and time stamp register 1 */
#define STM32F0_CAN_TDT2R_OFFSET 0x01a4 /* Mailbox data length control and time stamp register 2 */
#define STM32_CAN_TDTR_OFFSET(m) (0x0184 + ((m) << 4))
#define STM32_CAN_TDT0R_OFFSET 0x0184 /* Mailbox data length control and time stamp register 0 */
#define STM32_CAN_TDT1R_OFFSET 0x0194 /* Mailbox data length control and time stamp register 1 */
#define STM32_CAN_TDT2R_OFFSET 0x01a4 /* Mailbox data length control and time stamp register 2 */
#define STM32F0_CAN_TDLR_OFFSET(m) (0x0188+((m)<<4))
#define STM32F0_CAN_TDL0R_OFFSET 0x0188 /* Mailbox data low register 0 */
#define STM32F0_CAN_TDL1R_OFFSET 0x0198 /* Mailbox data low register 1 */
#define STM32F0_CAN_TDL2R_OFFSET 0x01a8 /* Mailbox data low register 2 */
#define STM32_CAN_TDLR_OFFSET(m) (0x0188 + ((m) << 4))
#define STM32_CAN_TDL0R_OFFSET 0x0188 /* Mailbox data low register 0 */
#define STM32_CAN_TDL1R_OFFSET 0x0198 /* Mailbox data low register 1 */
#define STM32_CAN_TDL2R_OFFSET 0x01a8 /* Mailbox data low register 2 */
#define STM32F0_CAN_TDHR_OFFSET(m) (0x018c+((m)<<4))
#define STM32F0_CAN_TDH0R_OFFSET 0x018c /* Mailbox data high register 0 */
#define STM32F0_CAN_TDH1R_OFFSET 0x019c /* Mailbox data high register 1 */
#define STM32F0_CAN_TDH2R_OFFSET 0x01ac /* Mailbox data high register 2 */
#define STM32_CAN_TDHR_OFFSET(m) (0x018c + ((m) << 4))
#define STM32_CAN_TDH0R_OFFSET 0x018c /* Mailbox data high register 0 */
#define STM32_CAN_TDH1R_OFFSET 0x019c /* Mailbox data high register 1 */
#define STM32_CAN_TDH2R_OFFSET 0x01ac /* Mailbox data high register 2 */
#define STM32F0_CAN_RIR_OFFSET(m) (0x01b0+((m)<<4))
#define STM32F0_CAN_RI0R_OFFSET 0x01b0 /* Rx FIFO mailbox identifier register 0 */
#define STM32F0_CAN_RI1R_OFFSET 0x01c0 /* Rx FIFO mailbox identifier register 1 */
#define STM32_CAN_RIR_OFFSET(m) (0x01b0 + ((m) << 4))
#define STM32_CAN_RI0R_OFFSET 0x01b0 /* Rx FIFO mailbox identifier register 0 */
#define STM32_CAN_RI1R_OFFSET 0x01c0 /* Rx FIFO mailbox identifier register 1 */
#define STM32F0_CAN_RDTR_OFFSET(m) (0x01b4+((m)<<4))
#define STM32F0_CAN_RDT0R_OFFSET 0x01b4 /* Rx FIFO mailbox data length control and time stamp register 0 */
#define STM32F0_CAN_RDT1R_OFFSET 0x01c4 /* Rx FIFO mailbox data length control and time stamp register 1 */
#define STM32_CAN_RDTR_OFFSET(m) (0x01b4 + ((m) << 4))
#define STM32_CAN_RDT0R_OFFSET 0x01b4 /* Rx FIFO mailbox data length control and time stamp register 0 */
#define STM32_CAN_RDT1R_OFFSET 0x01c4 /* Rx FIFO mailbox data length control and time stamp register 1 */
#define STM32F0_CAN_RDLR_OFFSET(m) (0x01b8+((m)<<4))
#define STM32F0_CAN_RDL0R_OFFSET 0x01b8 /* Receive FIFO mailbox data low register 0 */
#define STM32F0_CAN_RDL1R_OFFSET 0x01c8 /* Receive FIFO mailbox data low register 1 */
#define STM32_CAN_RDLR_OFFSET(m) (0x01b8 + ((m) << 4))
#define STM32_CAN_RDL0R_OFFSET 0x01b8 /* Receive FIFO mailbox data low register 0 */
#define STM32_CAN_RDL1R_OFFSET 0x01c8 /* Receive FIFO mailbox data low register 1 */
#define STM32F0_CAN_RDHR_OFFSET(m) (0x01bc+((m)<<4))
#define STM32F0_CAN_RDH0R_OFFSET 0x01bc /* Receive FIFO mailbox data high register 0 */
#define STM32F0_CAN_RDH1R_OFFSET 0x01cc /* Receive FIFO mailbox data high register 1 */
#define STM32_CAN_RDHR_OFFSET(m) (0x01bc + ((m) << 4))
#define STM32_CAN_RDH0R_OFFSET 0x01bc /* Receive FIFO mailbox data high register 0 */
#define STM32_CAN_RDH1R_OFFSET 0x01cc /* Receive FIFO mailbox data high register 1 */
/* CAN filter registers */
#define STM32F0_CAN_FMR_OFFSET 0x0200 /* CAN filter master register */
#define STM32F0_CAN_FM1R_OFFSET 0x0204 /* CAN filter mode register */
#define STM32F0_CAN_FS1R_OFFSET 0x020c /* CAN filter scale register */
#define STM32F0_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */
#define STM32F0_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */
#define STM32_CAN_FMR_OFFSET 0x0200 /* CAN filter master register */
#define STM32_CAN_FM1R_OFFSET 0x0204 /* CAN filter mode register */
#define STM32_CAN_FS1R_OFFSET 0x020c /* CAN filter scale register */
#define STM32_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */
#define STM32_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */
/* There are 14 or 28 filter banks (depending) on the device.
* Each filter bank is composed of two 32-bit registers, CAN_FiR:
@ -135,116 +135,116 @@
* ...
*/
#define STM32F0_CAN_FIR_OFFSET(f,i) (0x240+((f)<<3)+(((i)-1)<<2))
#define STM32_CAN_FIR_OFFSET(f,i) (0x240 + ((f) << 3)+(((i) - 1) << 2))
/* Register Addresses ***************************************************************/
#if STM32F0_NCAN > 0
# define STM32F0_CAN1_MCR (STM32F0_CAN1_BASE+STM32F0_CAN_MCR_OFFSET)
# define STM32F0_CAN1_MSR (STM32F0_CAN1_BASE+STM32F0_CAN_MSR_OFFSET)
# define STM32F0_CAN1_TSR (STM32F0_CAN1_BASE+STM32F0_CAN_TSR_OFFSET)
# define STM32F0_CAN1_RF0R (STM32F0_CAN1_BASE+STM32F0_CAN_RF0R_OFFSET)
# define STM32F0_CAN1_RF1R (STM32F0_CAN1_BASE+STM32F0_CAN_RF1R_OFFSET)
# define STM32F0_CAN1_IER (STM32F0_CAN1_BASE+STM32F0_CAN_IER_OFFSET)
# define STM32F0_CAN1_ESR (STM32F0_CAN1_BASE+STM32F0_CAN_ESR_OFFSET)
# define STM32F0_CAN1_BTR (STM32F0_CAN1_BASE+STM32F0_CAN_BTR_OFFSET)
#if STM32_NCAN > 0
# define STM32_CAN1_MCR (STM32_CAN1_BASE + STM32_CAN_MCR_OFFSET)
# define STM32_CAN1_MSR (STM32_CAN1_BASE + STM32_CAN_MSR_OFFSET)
# define STM32_CAN1_TSR (STM32_CAN1_BASE + STM32_CAN_TSR_OFFSET)
# define STM32_CAN1_RF0R (STM32_CAN1_BASE + STM32_CAN_RF0R_OFFSET)
# define STM32_CAN1_RF1R (STM32_CAN1_BASE + STM32_CAN_RF1R_OFFSET)
# define STM32_CAN1_IER (STM32_CAN1_BASE + STM32_CAN_IER_OFFSET)
# define STM32_CAN1_ESR (STM32_CAN1_BASE + STM32_CAN_ESR_OFFSET)
# define STM32_CAN1_BTR (STM32_CAN1_BASE + STM32_CAN_BTR_OFFSET)
# define STM32F0_CAN1_TIR(m) (STM32F0_CAN1_BASE+STM32F0_CAN_TIR_OFFSET(m))
# define STM32F0_CAN1_TI0R (STM32F0_CAN1_BASE+STM32F0_CAN_TI0R_OFFSET)
# define STM32F0_CAN1_TI1R (STM32F0_CAN1_BASE+STM32F0_CAN_TI1R_OFFSET)
# define STM32F0_CAN1_TI2R (STM32F0_CAN1_BASE+STM32F0_CAN_TI2R_OFFSET)
# define STM32_CAN1_TIR(m) (STM32_CAN1_BASE + STM32_CAN_TIR_OFFSET(m))
# define STM32_CAN1_TI0R (STM32_CAN1_BASE + STM32_CAN_TI0R_OFFSET)
# define STM32_CAN1_TI1R (STM32_CAN1_BASE + STM32_CAN_TI1R_OFFSET)
# define STM32_CAN1_TI2R (STM32_CAN1_BASE + STM32_CAN_TI2R_OFFSET)
# define STM32F0_CAN1_TDTR(m) (STM32F0_CAN1_BASE+STM32F0_CAN_TDTR_OFFSET(m))
# define STM32F0_CAN1_TDT0R (STM32F0_CAN1_BASE+STM32F0_CAN_TDT0R_OFFSET)
# define STM32F0_CAN1_TDT1R (STM32F0_CAN1_BASE+STM32F0_CAN_TDT1R_OFFSET)
# define STM32F0_CAN1_TDT2R (STM32F0_CAN1_BASE+STM32F0_CAN_TDT2R_OFFSET)
# define STM32_CAN1_TDTR(m) (STM32_CAN1_BASE + STM32_CAN_TDTR_OFFSET(m))
# define STM32_CAN1_TDT0R (STM32_CAN1_BASE + STM32_CAN_TDT0R_OFFSET)
# define STM32_CAN1_TDT1R (STM32_CAN1_BASE + STM32_CAN_TDT1R_OFFSET)
# define STM32_CAN1_TDT2R (STM32_CAN1_BASE + STM32_CAN_TDT2R_OFFSET)
# define STM32F0_CAN1_TDLR(m) (STM32F0_CAN1_BASE+STM32F0_CAN_TDLR_OFFSET(m))
# define STM32F0_CAN1_TDL0R (STM32F0_CAN1_BASE+STM32F0_CAN_TDL0R_OFFSET)
# define STM32F0_CAN1_TDL1R (STM32F0_CAN1_BASE+STM32F0_CAN_TDL1R_OFFSET)
# define STM32F0_CAN1_TDL2R (STM32F0_CAN1_BASE+STM32F0_CAN_TDL2R_OFFSET)
# define STM32_CAN1_TDLR(m) (STM32_CAN1_BASE + STM32_CAN_TDLR_OFFSET(m))
# define STM32_CAN1_TDL0R (STM32_CAN1_BASE + STM32_CAN_TDL0R_OFFSET)
# define STM32_CAN1_TDL1R (STM32_CAN1_BASE + STM32_CAN_TDL1R_OFFSET)
# define STM32_CAN1_TDL2R (STM32_CAN1_BASE + STM32_CAN_TDL2R_OFFSET)
# define STM32F0_CAN1_TDHR(m) (STM32F0_CAN1_BASE+STM32F0_CAN_TDHR_OFFSET(m))
# define STM32F0_CAN1_TDH0R (STM32F0_CAN1_BASE+STM32F0_CAN_TDH0R_OFFSET)
# define STM32F0_CAN1_TDH1R (STM32F0_CAN1_BASE+STM32F0_CAN_TDH1R_OFFSET)
# define STM32F0_CAN1_TDH2R (STM32F0_CAN1_BASE+STM32F0_CAN_TDH2R_OFFSET)
# define STM32_CAN1_TDHR(m) (STM32_CAN1_BASE + STM32_CAN_TDHR_OFFSET(m))
# define STM32_CAN1_TDH0R (STM32_CAN1_BASE + STM32_CAN_TDH0R_OFFSET)
# define STM32_CAN1_TDH1R (STM32_CAN1_BASE + STM32_CAN_TDH1R_OFFSET)
# define STM32_CAN1_TDH2R (STM32_CAN1_BASE + STM32_CAN_TDH2R_OFFSET)
# define STM32F0_CAN1_RIR(m) (STM32F0_CAN1_BASE+STM32F0_CAN_RIR_OFFSET(m))
# define STM32F0_CAN1_RI0R (STM32F0_CAN1_BASE+STM32F0_CAN_RI0R_OFFSET)
# define STM32F0_CAN1_RI1R (STM32F0_CAN1_BASE+STM32F0_CAN_RI1R_OFFSET)
# define STM32_CAN1_RIR(m) (STM32_CAN1_BASE + STM32_CAN_RIR_OFFSET(m))
# define STM32_CAN1_RI0R (STM32_CAN1_BASE + STM32_CAN_RI0R_OFFSET)
# define STM32_CAN1_RI1R (STM32_CAN1_BASE + STM32_CAN_RI1R_OFFSET)
# define STM32F0_CAN1_RDTR(m) (STM32F0_CAN1_BASE+STM32F0_CAN_RDTR_OFFSET(m))
# define STM32F0_CAN1_RDT0R (STM32F0_CAN1_BASE+STM32F0_CAN_RDT0R_OFFSET)
# define STM32F0_CAN1_RDT1R (STM32F0_CAN1_BASE+STM32F0_CAN_RDT1R_OFFSET)
# define STM32_CAN1_RDTR(m) (STM32_CAN1_BASE + STM32_CAN_RDTR_OFFSET(m))
# define STM32_CAN1_RDT0R (STM32_CAN1_BASE + STM32_CAN_RDT0R_OFFSET)
# define STM32_CAN1_RDT1R (STM32_CAN1_BASE + STM32_CAN_RDT1R_OFFSET)
# define STM32F0_CAN1_RDLR(m) (STM32F0_CAN1_BASE+STM32F0_CAN_RDLR_OFFSET(m))
# define STM32F0_CAN1_RDL0R (STM32F0_CAN1_BASE+STM32F0_CAN_RDL0R_OFFSET)
# define STM32F0_CAN1_RDL1R (STM32F0_CAN1_BASE+STM32F0_CAN_RDL1R_OFFSET)
# define STM32_CAN1_RDLR(m) (STM32_CAN1_BASE + STM32_CAN_RDLR_OFFSET(m))
# define STM32_CAN1_RDL0R (STM32_CAN1_BASE + STM32_CAN_RDL0R_OFFSET)
# define STM32_CAN1_RDL1R (STM32_CAN1_BASE + STM32_CAN_RDL1R_OFFSET)
# define STM32F0_CAN1_RDHR(m) (STM32F0_CAN1_BASE+STM32F0_CAN_RDHR_OFFSET(m))
# define STM32F0_CAN1_RDH0R (STM32F0_CAN1_BASE+STM32F0_CAN_RDH0R_OFFSET)
# define STM32F0_CAN1_RDH1R (STM32F0_CAN1_BASE+STM32F0_CAN_RDH1R_OFFSET)
# define STM32_CAN1_RDHR(m) (STM32_CAN1_BASE + STM32_CAN_RDHR_OFFSET(m))
# define STM32_CAN1_RDH0R (STM32_CAN1_BASE + STM32_CAN_RDH0R_OFFSET)
# define STM32_CAN1_RDH1R (STM32_CAN1_BASE + STM32_CAN_RDH1R_OFFSET)
# define STM32F0_CAN1_FMR (STM32F0_CAN1_BASE+STM32F0_CAN_FMR_OFFSET)
# define STM32F0_CAN1_FM1R (STM32F0_CAN1_BASE+STM32F0_CAN_FM1R_OFFSET)
# define STM32F0_CAN1_FS1R (STM32F0_CAN1_BASE+STM32F0_CAN_FS1R_OFFSET)
# define STM32F0_CAN1_FFA1R (STM32F0_CAN1_BASE+STM32F0_CAN_FFA1R_OFFSET)
# define STM32F0_CAN1_FA1R (STM32F0_CAN1_BASE+STM32F0_CAN_FA1R_OFFSET)
# define STM32F0_CAN1_FIR(b,i) (STM32F0_CAN1_BASE+STM32F0_CAN_FIR_OFFSET(b,i))
# define STM32_CAN1_FMR (STM32_CAN1_BASE + STM32_CAN_FMR_OFFSET)
# define STM32_CAN1_FM1R (STM32_CAN1_BASE + STM32_CAN_FM1R_OFFSET)
# define STM32_CAN1_FS1R (STM32_CAN1_BASE + STM32_CAN_FS1R_OFFSET)
# define STM32_CAN1_FFA1R (STM32_CAN1_BASE + STM32_CAN_FFA1R_OFFSET)
# define STM32_CAN1_FA1R (STM32_CAN1_BASE + STM32_CAN_FA1R_OFFSET)
# define STM32_CAN1_FIR(b,i) (STM32_CAN1_BASE + STM32_CAN_FIR_OFFSET(b,i))
#endif
#if STM32F0_NCAN > 1
# define STM32F0_CAN2_MCR (STM32F0_CAN2_BASE+STM32F0_CAN_MCR_OFFSET)
# define STM32F0_CAN2_MSR (STM32F0_CAN2_BASE+STM32F0_CAN_MSR_OFFSET)
# define STM32F0_CAN2_TSR (STM32F0_CAN2_BASE+STM32F0_CAN_TSR_OFFSET)
# define STM32F0_CAN2_RF0R (STM32F0_CAN2_BASE+STM32F0_CAN_RF0R_OFFSET)
# define STM32F0_CAN2_RF1R (STM32F0_CAN2_BASE+STM32F0_CAN_RF1R_OFFSET)
# define STM32F0_CAN2_IER (STM32F0_CAN2_BASE+STM32F0_CAN_IER_OFFSET)
# define STM32F0_CAN2_ESR (STM32F0_CAN2_BASE+STM32F0_CAN_ESR_OFFSET)
# define STM32F0_CAN2_BTR (STM32F0_CAN2_BASE+STM32F0_CAN_BTR_OFFSET)
#if STM32_NCAN > 1
# define STM32_CAN2_MCR (STM32_CAN2_BASE + STM32_CAN_MCR_OFFSET)
# define STM32_CAN2_MSR (STM32_CAN2_BASE + STM32_CAN_MSR_OFFSET)
# define STM32_CAN2_TSR (STM32_CAN2_BASE + STM32_CAN_TSR_OFFSET)
# define STM32_CAN2_RF0R (STM32_CAN2_BASE + STM32_CAN_RF0R_OFFSET)
# define STM32_CAN2_RF1R (STM32_CAN2_BASE + STM32_CAN_RF1R_OFFSET)
# define STM32_CAN2_IER (STM32_CAN2_BASE + STM32_CAN_IER_OFFSET)
# define STM32_CAN2_ESR (STM32_CAN2_BASE + STM32_CAN_ESR_OFFSET)
# define STM32_CAN2_BTR (STM32_CAN2_BASE + STM32_CAN_BTR_OFFSET)
# define STM32F0_CAN2_TIR(m) (STM32F0_CAN2_BASE+STM32F0_CAN_TIR_OFFSET(m))
# define STM32F0_CAN2_TI0R (STM32F0_CAN2_BASE+STM32F0_CAN_TI0R_OFFSET)
# define STM32F0_CAN2_TI1R (STM32F0_CAN2_BASE+STM32F0_CAN_TI1R_OFFSET)
# define STM32F0_CAN2_TI2R (STM32F0_CAN2_BASE+STM32F0_CAN_TI2R_OFFSET)
# define STM32_CAN2_TIR(m) (STM32_CAN2_BASE + STM32_CAN_TIR_OFFSET(m))
# define STM32_CAN2_TI0R (STM32_CAN2_BASE + STM32_CAN_TI0R_OFFSET)
# define STM32_CAN2_TI1R (STM32_CAN2_BASE + STM32_CAN_TI1R_OFFSET)
# define STM32_CAN2_TI2R (STM32_CAN2_BASE + STM32_CAN_TI2R_OFFSET)
# define STM32F0_CAN2_TDTR(m) (STM32F0_CAN2_BASE+STM32F0_CAN_TDTR_OFFSET(m))
# define STM32F0_CAN2_TDT0R (STM32F0_CAN2_BASE+STM32F0_CAN_TDT0R_OFFSET)
# define STM32F0_CAN2_TDT1R (STM32F0_CAN2_BASE+STM32F0_CAN_TDT1R_OFFSET)
# define STM32F0_CAN2_TDT2R (STM32F0_CAN2_BASE+STM32F0_CAN_TDT2R_OFFSET)
# define STM32_CAN2_TDTR(m) (STM32_CAN2_BASE + STM32_CAN_TDTR_OFFSET(m))
# define STM32_CAN2_TDT0R (STM32_CAN2_BASE + STM32_CAN_TDT0R_OFFSET)
# define STM32_CAN2_TDT1R (STM32_CAN2_BASE + STM32_CAN_TDT1R_OFFSET)
# define STM32_CAN2_TDT2R (STM32_CAN2_BASE + STM32_CAN_TDT2R_OFFSET)
# define STM32F0_CAN2_TDLR(m) (STM32F0_CAN2_BASE+STM32F0_CAN_TDLR_OFFSET(m))
# define STM32F0_CAN2_TDL0R (STM32F0_CAN2_BASE+STM32F0_CAN_TDL0R_OFFSET)
# define STM32F0_CAN2_TDL1R (STM32F0_CAN2_BASE+STM32F0_CAN_TDL1R_OFFSET)
# define STM32F0_CAN2_TDL2R (STM32F0_CAN2_BASE+STM32F0_CAN_TDL2R_OFFSET)
# define STM32_CAN2_TDLR(m) (STM32_CAN2_BASE + STM32_CAN_TDLR_OFFSET(m))
# define STM32_CAN2_TDL0R (STM32_CAN2_BASE + STM32_CAN_TDL0R_OFFSET)
# define STM32_CAN2_TDL1R (STM32_CAN2_BASE + STM32_CAN_TDL1R_OFFSET)
# define STM32_CAN2_TDL2R (STM32_CAN2_BASE + STM32_CAN_TDL2R_OFFSET)
# define STM32F0_CAN2_TDHR(m) (STM32F0_CAN2_BASE+STM32F0_CAN_TDHR_OFFSET(m))
# define STM32F0_CAN2_TDH0R (STM32F0_CAN2_BASE+STM32F0_CAN_TDH0R_OFFSET)
# define STM32F0_CAN2_TDH1R (STM32F0_CAN2_BASE+STM32F0_CAN_TDH1R_OFFSET)
# define STM32F0_CAN2_TDH2R (STM32F0_CAN2_BASE+STM32F0_CAN_TDH2R_OFFSET)
# define STM32_CAN2_TDHR(m) (STM32_CAN2_BASE + STM32_CAN_TDHR_OFFSET(m))
# define STM32_CAN2_TDH0R (STM32_CAN2_BASE + STM32_CAN_TDH0R_OFFSET)
# define STM32_CAN2_TDH1R (STM32_CAN2_BASE + STM32_CAN_TDH1R_OFFSET)
# define STM32_CAN2_TDH2R (STM32_CAN2_BASE + STM32_CAN_TDH2R_OFFSET)
# define STM32F0_CAN2_RIR(m) (STM32F0_CAN2_BASE+STM32F0_CAN_RIR_OFFSET(m))
# define STM32F0_CAN2_RI0R (STM32F0_CAN2_BASE+STM32F0_CAN_RI0R_OFFSET)
# define STM32F0_CAN2_RI1R (STM32F0_CAN2_BASE+STM32F0_CAN_RI1R_OFFSET)
# define STM32_CAN2_RIR(m) (STM32_CAN2_BASE + STM32_CAN_RIR_OFFSET(m))
# define STM32_CAN2_RI0R (STM32_CAN2_BASE + STM32_CAN_RI0R_OFFSET)
# define STM32_CAN2_RI1R (STM32_CAN2_BASE + STM32_CAN_RI1R_OFFSET)
# define STM32F0_CAN2_RDTR(m) (STM32F0_CAN2_BASE+STM32F0_CAN_RDTR_OFFSET(m))
# define STM32F0_CAN2_RDT0R (STM32F0_CAN2_BASE+STM32F0_CAN_RDT0R_OFFSET)
# define STM32F0_CAN2_RDT1R (STM32F0_CAN2_BASE+STM32F0_CAN_RDT1R_OFFSET)
# define STM32_CAN2_RDTR(m) (STM32_CAN2_BASE + STM32_CAN_RDTR_OFFSET(m))
# define STM32_CAN2_RDT0R (STM32_CAN2_BASE + STM32_CAN_RDT0R_OFFSET)
# define STM32_CAN2_RDT1R (STM32_CAN2_BASE + STM32_CAN_RDT1R_OFFSET)
# define STM32F0_CAN2_RDLR(m) (STM32F0_CAN2_BASE+STM32F0_CAN_RDLR_OFFSET(m))
# define STM32F0_CAN2_RDL0R (STM32F0_CAN2_BASE+STM32F0_CAN_RDL0R_OFFSET)
# define STM32F0_CAN2_RDL1R (STM32F0_CAN2_BASE+STM32F0_CAN_RDL1R_OFFSET)
# define STM32_CAN2_RDLR(m) (STM32_CAN2_BASE + STM32_CAN_RDLR_OFFSET(m))
# define STM32_CAN2_RDL0R (STM32_CAN2_BASE + STM32_CAN_RDL0R_OFFSET)
# define STM32_CAN2_RDL1R (STM32_CAN2_BASE + STM32_CAN_RDL1R_OFFSET)
# define STM32F0_CAN2_RDHR(m) (STM32F0_CAN2_BASE+STM32F0_CAN_RDHR_OFFSET(m))
# define STM32F0_CAN2_RDH0R (STM32F0_CAN2_BASE+STM32F0_CAN_RDH0R_OFFSET)
# define STM32F0_CAN2_RDH1R (STM32F0_CAN2_BASE+STM32F0_CAN_RDH1R_OFFSET)
# define STM32_CAN2_RDHR(m) (STM32_CAN2_BASE + STM32_CAN_RDHR_OFFSET(m))
# define STM32_CAN2_RDH0R (STM32_CAN2_BASE + STM32_CAN_RDH0R_OFFSET)
# define STM32_CAN2_RDH1R (STM32_CAN2_BASE + STM32_CAN_RDH1R_OFFSET)
# define STM32F0_CAN2_FMR (STM32F0_CAN2_BASE+STM32F0_CAN_FMR_OFFSET)
# define STM32F0_CAN2_FM1R (STM32F0_CAN2_BASE+STM32F0_CAN_FM1R_OFFSET)
# define STM32F0_CAN2_FS1R (STM32F0_CAN2_BASE+STM32F0_CAN_FS1R_OFFSET)
# define STM32F0_CAN2_FFA1R (STM32F0_CAN2_BASE+STM32F0_CAN_FFA1R_OFFSET)
# define STM32F0_CAN2_FA1R (STM32F0_CAN2_BASE+STM32F0_CAN_FA1R_OFFSET)
# define STM32F0_CAN2_FIR(b,i) (STM32F0_CAN2_BASE+STM32F0_CAN_FIR_OFFSET(b,i))
# define STM32_CAN2_FMR (STM32_CAN2_BASE + STM32_CAN_FMR_OFFSET)
# define STM32_CAN2_FM1R (STM32_CAN2_BASE + STM32_CAN_FM1R_OFFSET)
# define STM32_CAN2_FS1R (STM32_CAN2_BASE + STM32_CAN_FS1R_OFFSET)
# define STM32_CAN2_FFA1R (STM32_CAN2_BASE + STM32_CAN_FFA1R_OFFSET)
# define STM32_CAN2_FA1R (STM32_CAN2_BASE + STM32_CAN_FA1R_OFFSET)
# define STM32_CAN2_FIR(b,i) (STM32_CAN2_BASE + STM32_CAN_FIR_OFFSET(b,i))
#endif
/* Register Bitfield Definitions ****************************************************/
@ -466,4 +466,4 @@
#define CAN_FA1R_FACT_SHIFT (0) /* Bits 13:0: Filter Active */
#define CAN_FA1R_FACT_MASK (0x3fff << CAN_FA1R_FACT_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_CAN_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CAN_H */

12
arch/arm/src/stm32f0/chip/stm32f0_comp.h → arch/arm/src/stm32f0l0/hardware/stm32_comp.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f0_comp.h
* arch/arm/src/stm32f0l0/hardware/stm32_comp.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_COMP_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_COMP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_COMP_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_COMP_H
/************************************************************************************
* Included Files
@ -51,11 +51,11 @@
/* Register Offsets *****************************************************************/
#define STM32F0_COMP_CSR_OFFSET 0x001c /* COMP1/COMP2 Control register */
#define STM32_COMP_CSR_OFFSET 0x001c /* COMP1/COMP2 Control register */
/* Register Addresses ***************************************************************/
#define STM32F0_COMP_CSR (STM32F0_COMP_BASE+STM32F0_COMP_CSR_OFFSET)
#define STM32_COMP_CSR (STM32_COMP_BASE + STM32_COMP_CSR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
@ -135,4 +135,4 @@
#define COMP_CSR_COMP2OUT (1 << 14) /* Bit 14: Comparator 1 output */
#define COMP_CSR_COMP2LOCK (1 << 15) /* Bit 15: Comparator 1 lock */
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_COMP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_COMP_H */

58
arch/arm/src/stm32f0/chip/stm32f0_crc.h → arch/arm/src/stm32f0l0/hardware/stm32_crc.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f0_crc.h
* arch/arm/src/stm32f0l0/hardware/stm32_crc.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_CRC_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_CRC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRC_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRC_H
/************************************************************************************
* Included Files
@ -50,41 +50,41 @@
/* Register Offsets *****************************************************************/
#define STM32F0_CRC_DR_OFFSET 0x0000 /* Data register */
#define STM32F0_CRC_IDR_OFFSET 0x0004 /* Independent Data register */
#define STM32F0_CRC_CR_OFFSET 0x0008 /* Control register */
#define STM32F0_CRC_INIT_OFFSET 0x0010 /* Initial CRC value register */
#define STM32F0_CRC_POL_OFFSET 0x0014 /* CRC polynomial register */
#define STM32_CRC_DR_OFFSET 0x0000 /* Data register */
#define STM32_CRC_IDR_OFFSET 0x0004 /* Independent Data register */
#define STM32_CRC_CR_OFFSET 0x0008 /* Control register */
#define STM32_CRC_INIT_OFFSET 0x0010 /* Initial CRC value register */
#define STM32_CRC_POL_OFFSET 0x0014 /* CRC polynomial register */
/* Register Addresses ***************************************************************/
#define STM32F0_CRC_DR (STM32F0_CRC_BASE+STM32F0_CRC_DR_OFFSET)
#define STM32F0_CRC_IDR (STM32F0_CRC_BASE+STM32F0_CRC_IDR_OFFSET)
#define STM32F0_CRC_CR (STM32F0_CRC_BASE+STM32F0_CRC_CR_OFFSET)
#define STM32F0_CRC_INIT (STM32F0_CRC_BASE+STM32F0_CRC_INIT_OFFSET)
#define STM32F0_CRC_POL (STM32F0_CRC_BASE+STM32F0_CRC_POL_OFFSET)
#define STM32_CRC_DR (STM32_CRC_BASE + STM32_CRC_DR_OFFSET)
#define STM32_CRC_IDR (STM32_CRC_BASE + STM32_CRC_IDR_OFFSET)
#define STM32_CRC_CR (STM32_CRC_BASE + STM32_CRC_CR_OFFSET)
#define STM32_CRC_INIT (STM32_CRC_BASE + STM32_CRC_INIT_OFFSET)
#define STM32_CRC_POL (STM32_CRC_BASE + STM32_CRC_POL_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* CRC independent data register */
#define CRC_IDR_MASK 0xff /* These bits as a temporary location for one byte, not affected by RESET bit of CR */
#define CRC_IDR_MASK 0xff /* These bits as a temporary location for one byte, not affected by RESET bit of CR */
/* CRC control register */
#define CRC_CR_RESET (1 << 0) /* This bit reset the CRC calculation unit and load CRC_DR with value of CRC_INIT */
#define CRC_CR_POLYSIZE_SHIFT 3 /* Bits 3-4: Polynomial size (for STM32F07x and STM32F09x) */
#define CRC_CR_POLYSIZE_MASK (3 << CRC_CR_POLYSIZE_SHIFT)
# define CRC_CR_POLYSIZE_32 (0 << CRC_CR_POLYSIZE_SHIFT) /* 00: 32 bit polynomial */
# define CRC_CR_POLYSIZE_16 (1 << CRC_CR_POLYSIZE_SHIFT) /* 01: 16 bit polynomial */
# define CRC_CR_POLYSIZE_8 (2 << CRC_CR_POLYSIZE_SHIFT) /* 10: 8 bit polynomial */
# define CRC_CR_POLYSIZE_7 (3 << CRC_CR_POLYSIZE_SHIFT) /* 10: 8 bit polynomial */
#define CRC_CR_REVIN_SHIFT 5 /* Bits 5-6: These bits ontrol the reversal of the bit order of the input data */
#define CRC_CR_REVIN_MASK (3 << CRC_CR_REVIN_SHIFT)
# define CRC_CR_REVIN_NONE (0 << CRC_CR_REVIN_SHIFT) /* 00: bit order is not affected */
# define CRC_CR_REVIN_BYTE (1 << CRC_CR_REVIN_SHIFT) /* 01: reversal done by byte */
# define CRC_CR_REVIN_HWORD (2 << CRC_CR_REVIN_SHIFT) /* 10: reversal done by half-word */
# define CRC_CR_REVIN_WORD (3 << CRC_CR_REVIN_SHIFT) /* 11: reversal done by word */
#define CRC_CR_REVOUT (1 << 7) /* This bit controls the reversal of the bit order of the output data */
#define CRC_CR_RESET (1 << 0) /* This bit reset the CRC calculation unit and load CRC_DR with value of CRC_INIT */
#define CRC_CR_POLYSIZE_SHIFT 3 /* Bits 3-4: Polynomial size (for STM32F07x and STM32F09x) */
#define CRC_CR_POLYSIZE_MASK (3 << CRC_CR_POLYSIZE_SHIFT)
# define CRC_CR_POLYSIZE_32 (0 << CRC_CR_POLYSIZE_SHIFT) /* 00: 32 bit polynomial */
# define CRC_CR_POLYSIZE_16 (1 << CRC_CR_POLYSIZE_SHIFT) /* 01: 16 bit polynomial */
# define CRC_CR_POLYSIZE_8 (2 << CRC_CR_POLYSIZE_SHIFT) /* 10: 8 bit polynomial */
# define CRC_CR_POLYSIZE_7 (3 << CRC_CR_POLYSIZE_SHIFT) /* 10: 8 bit polynomial */
#define CRC_CR_REVIN_SHIFT 5 /* Bits 5-6: These bits ontrol the reversal of the bit order of the input data */
#define CRC_CR_REVIN_MASK (3 << CRC_CR_REVIN_SHIFT)
# define CRC_CR_REVIN_NONE (0 << CRC_CR_REVIN_SHIFT) /* 00: bit order is not affected */
# define CRC_CR_REVIN_BYTE (1 << CRC_CR_REVIN_SHIFT) /* 01: reversal done by byte */
# define CRC_CR_REVIN_HWORD (2 << CRC_CR_REVIN_SHIFT) /* 10: reversal done by half-word */
# define CRC_CR_REVIN_WORD (3 << CRC_CR_REVIN_SHIFT) /* 11: reversal done by word */
#define CRC_CR_REVOUT (1 << 7) /* This bit controls the reversal of the bit order of the output data */
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_CRC_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRC_H */

24
arch/arm/src/stm32f0/chip/stm32f0_crs.h → arch/arm/src/stm32f0l0/hardware/stm32_crs.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f0_crs.h
* arch/arm/src/stm32f0l0/hardware/stm32_crs.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_CRS_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_CRS_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRS_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRS_H
/************************************************************************************
* Pre-processor Definitions
@ -43,17 +43,17 @@
/* Register Offsets *****************************************************************/
#define STM32F0_CRS_CR_OFFSET 0x0000 /* CRS control register */
#define STM32F0_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */
#define STM32F0_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */
#define STM32F0_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */
#define STM32_CRS_CR_OFFSET 0x0000 /* CRS control register */
#define STM32_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */
#define STM32_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */
#define STM32_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */
/* Register Addresses ***************************************************************/
#define STM32F0_CRS_CR (STM32F0_CRS_BASE+STM32F0_CRS_CR_OFFSET)
#define STM32F0_CRS_CFGR (STM32F0_CRS_BASE+STM32F0_CRS_CFGR_OFFSET)
#define STM32F0_CRS_ISR (STM32F0_CRS_BASE+STM32F0_CRS_ISR_OFFSET)
#define STM32F0_CRS_ICR (STM32F0_CRS_BASE+STM32F0_CRS_ICR_OFFSET)
#define STM32_CRS_CR (STM32_CRS_BASE + STM32_CRS_CR_OFFSET)
#define STM32_CRS_CFGR (STM32_CRS_BASE + STM32_CRS_CFGR_OFFSET)
#define STM32_CRS_ISR (STM32_CRS_BASE + STM32_CRS_ISR_OFFSET)
#define STM32_CRS_ICR (STM32_CRS_BASE + STM32_CRS_ICR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
@ -112,4 +112,4 @@
#define CRS_ICR_ERRC (1 << 2) /* Bit 2: Error clear flag */
#define CRS_ICR_ESYNCC (1 << 3) /* Bit 3: Expected SYNC clear flag */
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_CRS_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRS_H */

64
arch/arm/src/stm32f0/chip/stm32f0_dac.h → arch/arm/src/stm32f0l0/hardware/stm32_dac.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f0_dac.h
* arch/arm/src/stm32f0l0/hardware/stm32_dac.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_DAC_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_DAC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DAC_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DAC_H
/************************************************************************************
* Included Files
@ -50,39 +50,39 @@
/* Register Offsets *****************************************************************/
#define STM32F0_DAC_CR_OFFSET 0x0000 /* DAC control register */
#define STM32F0_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */
#define STM32F0_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */
#define STM32F0_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */
#define STM32F0_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */
#define STM32F0_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */
#define STM32F0_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */
#define STM32F0_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */
#define STM32F0_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */
#define STM32F0_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */
#define STM32F0_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */
#define STM32F0_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */
#define STM32F0_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */
#define STM32F0_DAC_SR_OFFSET 0x0034 /* DAC status register */
#define STM32_DAC_CR_OFFSET 0x0000 /* DAC control register */
#define STM32_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */
#define STM32_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */
#define STM32_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */
#define STM32_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */
#define STM32_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */
#define STM32_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */
#define STM32_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */
#define STM32_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */
#define STM32_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */
#define STM32_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */
#define STM32_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */
#define STM32_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */
#define STM32_DAC_SR_OFFSET 0x0034 /* DAC status register */
/* Register Addresses ***************************************************************/
/* DAC */
# define STM32F0_DAC1_CR (STM32F0_DAC1_BASE+STM32F0_DAC_CR_OFFSET)
# define STM32F0_DAC1_SWTRIGR (STM32F0_DAC1_BASE+STM32F0_DAC_SWTRIGR_OFFSET)
# define STM32F0_DAC1_DHR12R1 (STM32F0_DAC1_BASE+STM32F0_DAC_DHR12R1_OFFSET)
# define STM32F0_DAC1_DHR12L1 (STM32F0_DAC1_BASE+STM32F0_DAC_DHR12L1_OFFSET)
# define STM32F0_DAC1_DHR8R1 (STM32F0_DAC1_BASE+STM32F0_DAC_DHR8R1_OFFSET)
# define STM32F0_DAC1_DHR12R2 (STM32F0_DAC1_BASE+STM32F0_DAC_DHR12R2_OFFSET)
# define STM32F0_DAC1_DHR12L2 (STM32F0_DAC1_BASE+STM32F0_DAC_DHR12L2_OFFSET)
# define STM32F0_DAC1_DHR8R2 (STM32F0_DAC1_BASE+STM32F0_DAC_DHR8R2_OFFSET)
# define STM32F0_DAC1_DHR12RD (STM32F0_DAC1_BASE+STM32F0_DAC_DHR12RD_OFFSET)
# define STM32F0_DAC1_DHR12LD (STM32F0_DAC1_BASE+STM32F0_DAC_DHR12LD_OFFSET)
# define STM32F0_DAC1_DHR8RD (STM32F0_DAC1_BASE+STM32F0_DAC_DHR8RD_OFFSET)
# define STM32F0_DAC1_DOR1 (STM32F0_DAC1_BASE+STM32F0_DAC_DOR1_OFFSET)
# define STM32F0_DAC1_DOR2 (STM32F0_DAC1_BASE+STM32F0_DAC_DOR2_OFFSET)
# define STM32F0_DAC1_SR (STM32F0_DAC1_BASE+STM32F0_DAC_SR_OFFSET)
#define STM32_DAC1_CR (STM32_DAC1_BASE + STM32_DAC_CR_OFFSET)
#define STM32_DAC1_SWTRIGR (STM32_DAC1_BASE + STM32_DAC_SWTRIGR_OFFSET)
#define STM32_DAC1_DHR12R1 (STM32_DAC1_BASE + STM32_DAC_DHR12R1_OFFSET)
#define STM32_DAC1_DHR12L1 (STM32_DAC1_BASE + STM32_DAC_DHR12L1_OFFSET)
#define STM32_DAC1_DHR8R1 (STM32_DAC1_BASE + STM32_DAC_DHR8R1_OFFSET)
#define STM32_DAC1_DHR12R2 (STM32_DAC1_BASE + STM32_DAC_DHR12R2_OFFSET)
#define STM32_DAC1_DHR12L2 (STM32_DAC1_BASE + STM32_DAC_DHR12L2_OFFSET)
#define STM32_DAC1_DHR8R2 (STM32_DAC1_BASE + STM32_DAC_DHR8R2_OFFSET)
#define STM32_DAC1_DHR12RD (STM32_DAC1_BASE + STM32_DAC_DHR12RD_OFFSET)
#define STM32_DAC1_DHR12LD (STM32_DAC1_BASE + STM32_DAC_DHR12LD_OFFSET)
#define STM32_DAC1_DHR8RD (STM32_DAC1_BASE + STM32_DAC_DHR8RD_OFFSET)
#define STM32_DAC1_DOR1 (STM32_DAC1_BASE + STM32_DAC_DOR1_OFFSET)
#define STM32_DAC1_DOR2 (STM32_DAC1_BASE + STM32_DAC_DOR2_OFFSET)
#define STM32_DAC1_SR (STM32_DAC1_BASE + STM32_DAC_SR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
@ -215,4 +215,4 @@
#define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */
#define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_DAC_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DAC_H */

456
arch/arm/src/stm32f0l0/hardware/stm32_dma.h Normal file
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@ -0,0 +1,456 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_dma.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DMA_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DMA_H
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* 12 Channels Total: 7 DMA1 Channels(1-7) (and 5 DMA2 channels (1-5) if STM32F09x) */
#define DMA1 0
#define DMA2 1
#define DMA3 2
#define DMA4 3
#define DMA5 4
#define DMA6 5
#define DMA7 6
/* Register Offsets *****************************************************************/
#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
#define STM32_DMACHAN_OFFSET(n) (0x0014*(n))
#define STM32_DMACHAN1_OFFSET 0x0000
#define STM32_DMACHAN2_OFFSET 0x0014
#define STM32_DMACHAN3_OFFSET 0x0028
#define STM32_DMACHAN4_OFFSET 0x003c
#define STM32_DMACHAN5_OFFSET 0x0050
#define STM32_DMACHAN6_OFFSET 0x0064
#define STM32_DMACHAN7_OFFSET 0x0078
#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */
#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */
#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET + STM32_DMACHAN_OFFSET(n))
#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET + STM32_DMACHAN_OFFSET(n))
#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET + STM32_DMACHAN_OFFSET(n))
#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET + STM32_DMACHAN_OFFSET(n))
#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
#define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */
/* Register Addresses ***************************************************************/
#define STM32_DMA1_ISRC (STM32_DMA1_BASE + STM32_DMA_ISR_OFFSET)
#define STM32_DMA1_IFCR (STM32_DMA1_BASE + STM32_DMA_IFCR_OFFSET)
#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE + STM32_DMA_CCR_OFFSET(n))
#define STM32_DMA1_CCR1 (STM32_DMA1_BASE + STM32_DMA_CCR1_OFFSET)
#define STM32_DMA1_CCR2 (STM32_DMA1_BASE + STM32_DMA_CCR2_OFFSET)
#define STM32_DMA1_CCR3 (STM32_DMA1_BASE + STM32_DMA_CCR3_OFFSET)
#define STM32_DMA1_CCR4 (STM32_DMA1_BASE + STM32_DMA_CCR4_OFFSET)
#define STM32_DMA1_CCR5 (STM32_DMA1_BASE + STM32_DMA_CCR5_OFFSET)
#define STM32_DMA1_CCR6 (STM32_DMA1_BASE + STM32_DMA_CCR6_OFFSET)
#define STM32_DMA1_CCR7 (STM32_DMA1_BASE + STM32_DMA_CCR7_OFFSET)
#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE + STM32_DMA_CNDTR_OFFSET(n))
#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE + STM32_DMA_CNDTR1_OFFSET)
#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE + STM32_DMA_CNDTR2_OFFSET)
#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE + STM32_DMA_CNDTR3_OFFSET)
#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE + STM32_DMA_CNDTR4_OFFSET)
#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE + STM32_DMA_CNDTR5_OFFSET)
#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE + STM32_DMA_CNDTR6_OFFSET)
#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE + STM32_DMA_CNDTR7_OFFSET)
#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE + STM32_DMA_CPAR_OFFSET(n))
#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE + STM32_DMA_CPAR1_OFFSET)
#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE + STM32_DMA_CPAR2_OFFSET)
#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE + STM32_DMA_CPAR3_OFFSET)
#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE + STM32_DMA_CPAR4_OFFSET)
#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE + STM32_DMA_CPAR5_OFFSET)
#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE + STM32_DMA_CPAR6_OFFSET)
#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE + STM32_DMA_CPAR7_OFFSET)
#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE + STM32_DMA_CMAR_OFFSET(n))
#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE + STM32_DMA_CMAR1_OFFSET)
#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE + STM32_DMA_CMAR2_OFFSET)
#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE + STM32_DMA_CMAR3_OFFSET)
#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE + STM32_DMA_CMAR4_OFFSET)
#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE + STM32_DMA_CMAR5_OFFSET)
#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE + STM32_DMA_CMAR6_OFFSET)
#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE + STM32_DMA_CMAR7_OFFSET)
#define STM32_DMA2_ISRC (STM32_DMA2_BASE + STM32_DMA_ISR_OFFSET)
#define STM32_DMA2_IFCR (STM32_DMA2_BASE + STM32_DMA_IFCR_OFFSET)
#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE + STM32_DMA_CCR_OFFSET(n))
#define STM32_DMA2_CCR1 (STM32_DMA2_BASE + STM32_DMA_CCR1_OFFSET)
#define STM32_DMA2_CCR2 (STM32_DMA2_BASE + STM32_DMA_CCR2_OFFSET)
#define STM32_DMA2_CCR3 (STM32_DMA2_BASE + STM32_DMA_CCR3_OFFSET)
#define STM32_DMA2_CCR4 (STM32_DMA2_BASE + STM32_DMA_CCR4_OFFSET)
#define STM32_DMA2_CCR5 (STM32_DMA2_BASE + STM32_DMA_CCR5_OFFSET)
#define STM32_DMA2_CCR6 (STM32_DMA2_BASE + STM32_DMA_CCR6_OFFSET)
#define STM32_DMA2_CCR7 (STM32_DMA2_BASE + STM32_DMA_CCR7_OFFSET)
#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE + STM32_DMA_CNDTR_OFFSET(n))
#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE + STM32_DMA_CNDTR1_OFFSET)
#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE + STM32_DMA_CNDTR2_OFFSET)
#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE + STM32_DMA_CNDTR3_OFFSET)
#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE + STM32_DMA_CNDTR4_OFFSET)
#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE + STM32_DMA_CNDTR5_OFFSET)
#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE + STM32_DMA_CNDTR6_OFFSET)
#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE + STM32_DMA_CNDTR7_OFFSET)
#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE + STM32_DMA_CPAR_OFFSET(n))
#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE + STM32_DMA_CPAR1_OFFSET)
#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE + STM32_DMA_CPAR2_OFFSET)
#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE + STM32_DMA_CPAR3_OFFSET)
#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE + STM32_DMA_CPAR4_OFFSET)
#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE + STM32_DMA_CPAR5_OFFSET)
#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE + STM32_DMA_CPAR6_OFFSET)
#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE + STM32_DMA_CPAR7_OFFSET)
#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE + STM32_DMA_CMAR_OFFSET(n))
#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE + STM32_DMA_CMAR1_OFFSET)
#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE + STM32_DMA_CMAR2_OFFSET)
#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE + STM32_DMA_CMAR3_OFFSET)
#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE + STM32_DMA_CMAR4_OFFSET)
#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE + STM32_DMA_CMAR5_OFFSET)
#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE + STM32_DMA_CMAR6_OFFSET)
#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE + STM32_DMA_CMAR7_OFFSET)
/* Register Bitfield Definitions ****************************************************/
#define DMA_CHAN_SHIFT(n) ((n) << 2)
#define DMA_CHAN_MASK 0x0f
#define DMA_CHAN_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */
#define DMA_CHAN_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */
#define DMA_CHAN_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */
#define DMA_CHAN_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */
/* DMA interrupt status register */
#define DMA_ISR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
#define DMA_ISR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_ISR_CHAN_SHIFT(n))
#define DMA_ISR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */
#define DMA_ISR_CHAN1_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN1_SHIFT)
#define DMA_ISR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */
#define DMA_ISR_CHAN2_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN2_SHIFT)
#define DMA_ISR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */
#define DMA_ISR_CHAN3_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN3_SHIFT)
#define DMA_ISR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */
#define DMA_ISR_CHAN4_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN4_SHIFT)
#define DMA_ISR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */
#define DMA_ISR_CHAN5_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN5_SHIFT)
#define DMA_ISR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */
#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT)
#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */
#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT)
#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n))
#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n))
#define DMA_ISR_HTIF(n) (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n))
#define DMA_ISR_TEIF(n) (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n))
/* DMA interrupt flag clear register */
#define DMA_IFCR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
#define DMA_IFCR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_IFCR_CHAN_SHIFT(n))
#define DMA_IFCR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt flag clear */
#define DMA_IFCR_CHAN1_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN1_SHIFT)
#define DMA_IFCR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt flag clear */
#define DMA_IFCR_CHAN2_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN2_SHIFT)
#define DMA_IFCR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt flag clear */
#define DMA_IFCR_CHAN3_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN3_SHIFT)
#define DMA_IFCR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt flag clear */
#define DMA_IFCR_CHAN4_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN4_SHIFT)
#define DMA_IFCR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt flag clear */
#define DMA_IFCR_CHAN5_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN5_SHIFT)
#define DMA_IFCR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt flag clear */
#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT)
#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */
#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT)
#define DMA_IFCR_ALLCHANNELS (0x0fffffff)
#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
#define DMA_IFCR_CHTIF(n) (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
#define DMA_IFCR_CTEIF(n) (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
/* DMA channel configuration register */
#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */
#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */
#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */
#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */
#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */
#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */
#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */
#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */
#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 8-9: Peripheral size */
#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT)
# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */
# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */
# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */
#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 10-11: Memory size */
#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT)
# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */
# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */
# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */
#define DMA_CCR_PL_SHIFT (12) /* Bits 12-13: Channel Priority level */
#define DMA_CCR_PL_MASK (3 << DMA_CCR_PL_SHIFT)
# define DMA_CCR_PRILO (0 << DMA_CCR_PL_SHIFT) /* 00: Low */
# define DMA_CCR_PRIMED (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */
# define DMA_CCR_PRIHI (2 << DMA_CCR_PL_SHIFT) /* 10: High */
# define DMA_CCR_PRIVERYHI (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */
#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */
#define DMA_CCR_ALLINTS (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE)
/* DMA channel number of data register */
#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT)
/* DMA Channel mapping. Each DMA channel has a mapping to one of several
* possible sources/sinks of data. The requests from peripherals assigned to a
* channel are multiplexed together before entering the DMA block. This means
* that only one request on a given channel can be enabled at once.
*
* Alternative DMA channel selections are provided with a numeric suffix like _1,
* _2, etc. Drivers, however, will use the pin selection without the numeric suffix.
* Additional definitions are required in the board.h file.
*/
/* REVISE IT: based on STM32L4 DMA Header */
#define STM32_DMA1_CHAN1 (0)
#define STM32_DMA1_CHAN2 (1)
#define STM32_DMA1_CHAN3 (2)
#define STM32_DMA1_CHAN4 (3)
#define STM32_DMA1_CHAN5 (4)
#define STM32_DMA1_CHAN6 (5)
#define STM32_DMA1_CHAN7 (6)
#define STM32_DMA2_CHAN1 (7)
#define STM32_DMA2_CHAN2 (8)
#define STM32_DMA2_CHAN3 (9)
#define STM32_DMA2_CHAN4 (10)
#define STM32_DMA2_CHAN5 (11)
#define DMACHAN_SETTING(chan, sel) ((((sel) & 0xff) << 8) | ((chan) & 0xff))
#define DMACHAN_SETTING_CHANNEL_MASK 0x00FF
#define DMACHAN_SETTING_CHANNEL_SHIFT (0)
#define DMACHAN_SETTING_FUNCTION_MASK 0xFF00
#define DMACHAN_SETTING_FUNCTION_SHIFT (8)
/* ADC */
#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0)
#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 0)
#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0)
#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 0)
#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0)
#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 0)
/* AES */
#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 6)
#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 6)
#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 6)
#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 6)
/* DAC */
#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6)
#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5)
#define DMACHAN_DAC1_3 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3)
#define DMACHAN_DAC2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3)
/* I2C */
#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 3)
#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 5)
#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 3)
#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 5)
#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN5, 3)
#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 3)
#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2)
#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 3)
/* QUADSPI */
#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 5)
#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 3)
/* SPI */
#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 1)
#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 4)
#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 0)
#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 4)
#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32_DMA1_CHAN4, 1)
#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32_DMA1_CHAN5, 1)
#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 3)
#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 3)
/* TIM */
#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 7)
#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 7)
#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 7)
#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN4, 7)
#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32_DMA1_CHAN4, 7)
#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN4, 7)
#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32_DMA1_CHAN6, 7)
#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4)
#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4)
#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 4)
#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4)
#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 4)
#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5)
#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5)
#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5)
#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN6, 5)
#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32_DMA1_CHAN3, 5)
#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 6)
#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 6)
#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN5, 6)
#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32_DMA1_CHAN7, 6)
#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 5)
#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 5)
#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN2, 5)
#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN1, 5)
#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32_DMA2_CHAN1, 5)
#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN1, 5)
#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32_DMA2_CHAN2, 5)
#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6)
#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3)
#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5)
#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3)
#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN6, 7)
#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 7)
#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN1, 7)
#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN2, 7)
#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32_DMA2_CHAN2, 7)
#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN2, 7)
#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32_DMA2_CHAN1, 7)
#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4)
#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4)
#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4)
#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4)
#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5)
#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5)
#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5)
#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5)
/* USARTs */
#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2)
#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 2)
#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2)
#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 2)
#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32_DMA1_CHAN6, 2)
#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32_DMA1_CHAN7, 2)
#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 1)
#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 2)
#define DMACHAN_USART4_RX DMACHAN_SETTING(STM32_DMA2_CHAN5, 2)
#define DMACHAN_USART4_TX DMACHAN_SETTING(STM32_DMA2_CHAN3, 2)
#define DMACHAN_USART5_RX DMACHAN_SETTING(STM32_DMA2_CHAN2, 2)
#define DMACHAN_USART5_TX DMACHAN_SETTING(STM32_DMA2_CHAN1, 2)
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DMA_H */

131
arch/arm/src/stm32f0l0/hardware/stm32_exti.h Normal file
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@ -0,0 +1,131 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_exti.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_EXTI_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_EXTI_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#define STM32_NEXTI 31
#define STM32_EXTI_MASK 0xffffffff
#define STM32_EXTI_BIT(n) (1 << (n))
/* Register Offsets *****************************************************************/
#define STM32_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */
#define STM32_EXTI_EMR_OFFSET 0x0004 /* Event mask register */
#define STM32_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */
#define STM32_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */
#define STM32_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */
#define STM32_EXTI_PR_OFFSET 0x0014 /* Pending register */
/* Register Addresses ***************************************************************/
#define STM32_EXTI_IMR (STM32_EXTI_BASE + STM32_EXTI_IMR_OFFSET)
#define STM32_EXTI_EMR (STM32_EXTI_BASE + STM32_EXTI_EMR_OFFSET)
#define STM32_EXTI_RTSR (STM32_EXTI_BASE + STM32_EXTI_RTSR_OFFSET)
#define STM32_EXTI_FTSR (STM32_EXTI_BASE + STM32_EXTI_FTSR_OFFSET)
#define STM32_EXTI_SWIER (STM32_EXTI_BASE + STM32_EXTI_SWIER_OFFSET)
#define STM32_EXTI_PR (STM32_EXTI_BASE + STM32_EXTI_PR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* EXTI lines > 15 are associated with internal devices: */
#define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */
#define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */
#define EXTI_USB_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB wake up event */
#define EXTI_RTC_TAMPER (1 << 19) /* EXTI line 19 is connected to the RTC Tamper and TimeStamp events */
#define EXTI_RTC_WAKEUP (1 << 20) /* EXTI line 20 is connected to the RTC Wakeup event */
#define EXTI_COMP1 (1 << 21) /* EXTI line 21 is connected to the COMP1 (comparator) output */
#define EXTI_COMP2 (1 << 22) /* EXTI line 22 is connected to the COMP2 (comparator) output */
#define EXTI_I2C1 (1 << 23) /* EXTI line 23 is connected to the I2C1 wakeup */
/* EXTI line 24 is reserved (internally held low) */
#define EXTI_USART1 (1 << 25) /* EXTI line 25 is connected to the USART1 wakeup */
#define EXTI_USART2 (1 << 26) /* EXTI line 26 is connected to the USART2 wakeup */
#define EXTI_CEC (1 << 27) /* EXTI line 27 is connected to the CEC wakeup */
#define EXTI_USART3 (1 << 28) /* EXTI line 28 is connected to the USART3 wakeup */
/* EXTI line 29 is reserved (internally held low) */
/* EXTI line 30 is reserved (internally held low) */
#define EXTI_VDDIO2 (1 << 31) /* EXTI line 31 is connected to the Vddio2 supply comparator */
/* Interrupt mask register */
#define EXTI_IMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Interrupt request from line x is not masked */
#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */
#define EXTI_IMR_MASK STM32_EXTI_MASK
/* Event mask register */
#define EXTI_EMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Event request from line x is not mask */
#define EXTI_EMR_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */
#define EXTI_EMR_MASK STM32_EXTI_MASK
/* Rising Trigger selection register */
#define EXTI_RTSR_BIT(n) STM32_EXTI_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */
#define EXTI_RTSR_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */
#define EXTI_RTSR_MASK STM32_EXTI_MASK
/* Falling Trigger selection register */
#define EXTI_FTSR_BIT(n) STM32_EXTI_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */
#define EXTI_FTSR_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */
#define EXTI_FTSR_MASK STM32_EXTI_MASK
/* Software interrupt event register */
#define EXTI_SWIER_BIT(n) STM32_EXTI_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */
#define EXTI_SWIER_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */
#define EXTI_SWIER_MASK STM32_EXTI_MASK
/* Pending register */
#define EXTI_PR_BIT(n) STM32_EXTI_BIT(n) /* 1=Selected trigger request occurred */
#define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
#define EXTI_PR_MASK STM32_EXTI_MASK
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_EXTI_H */

40
arch/arm/src/stm32f0/chip/stm32f0_flash.h → arch/arm/src/stm32f0l0/hardware/stm32_flash.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32/chip/stm32f0_flash.h
* arch/arm/src/stm32f0l0/hardware/stm32_flash.h
*
* Copyright (C) 20017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_FLASH_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_FLASH_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_FLASH_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_FLASH_H
/************************************************************************************
* Included Files
@ -50,25 +50,25 @@
/* Register Offsets *****************************************************************/
#define STM32_FLASH_ACR_OFFSET 0x0000
#define STM32_FLASH_KEYR_OFFSET 0x0004
#define STM32_FLASH_OPTKEYR_OFFSET 0x0008
#define STM32_FLASH_SR_OFFSET 0x000c
#define STM32_FLASH_CR_OFFSET 0x0010
#define STM32_FLASH_AR_OFFSET 0x0014
#define STM32_FLASH_OBR_OFFSET 0x001c
#define STM32_FLASH_WRPR_OFFSET 0x0020
#define STM32_FLASH_ACR_OFFSET 0x0000
#define STM32_FLASH_KEYR_OFFSET 0x0004
#define STM32_FLASH_OPTKEYR_OFFSET 0x0008
#define STM32_FLASH_SR_OFFSET 0x000c
#define STM32_FLASH_CR_OFFSET 0x0010
#define STM32_FLASH_AR_OFFSET 0x0014
#define STM32_FLASH_OBR_OFFSET 0x001c
#define STM32_FLASH_WRPR_OFFSET 0x0020
/* Register Addresses ***************************************************************/
#define STM32_FLASH_ACR (STM32F0_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET)
#define STM32_FLASH_KEYR (STM32F0_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET)
#define STM32_FLASH_OPTKEYR (STM32F0_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET)
#define STM32_FLASH_SR (STM32F0_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
#define STM32_FLASH_CR (STM32F0_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)
#define STM32_FLASH_AR (STM32F0_FLASHIF_BASE+STM32_FLASH_AR_OFFSET)
#define STM32_FLASH_OBR (STM32F0_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET)
#define STM32_FLASH_WRPR (STM32F0_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET)
#define STM32_FLASH_ACR (STM32_FLASHIF_BASE + STM32_FLASH_ACR_OFFSET)
#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE + STM32_FLASH_KEYR_OFFSET)
#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE + STM32_FLASH_OPTKEYR_OFFSET)
#define STM32_FLASH_SR (STM32_FLASHIF_BASE + STM32_FLASH_SR_OFFSET)
#define STM32_FLASH_CR (STM32_FLASHIF_BASE + STM32_FLASH_CR_OFFSET)
#define STM32_FLASH_AR (STM32_FLASHIF_BASE + STM32_FLASH_AR_OFFSET)
#define STM32_FLASH_OBR (STM32_FLASHIF_BASE + STM32_FLASH_OBR_OFFSET)
#define STM32_FLASH_WRPR (STM32_FLASHIF_BASE + STM32_FLASH_WRPR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* Flash Access Control Register (ACR) */
@ -112,4 +112,4 @@
void stm32_flash_lock(void);
void stm32_flash_unlock(void);
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_FLASH_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_FLASH_H */

164
arch/arm/src/stm32f0/chip/stm32f0_gpio.h → arch/arm/src/stm32f0l0/hardware/stm32_gpio.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f0_gpio.h
* arch/arm/src/stm32f0l0/hardware/stm32_gpio.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_GPIO_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_GPIO_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_GPIO_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_GPIO_H
/************************************************************************************
* Pre-processor Definitions
@ -43,96 +43,96 @@
/* Register Offsets *****************************************************************/
#define STM32F0_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
#define STM32F0_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
#define STM32F0_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
#define STM32F0_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
#define STM32F0_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
#define STM32F0_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
#define STM32F0_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
#define STM32F0_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
#define STM32F0_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
#define STM32F0_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
#define STM32F0_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
/* Register Addresses ***************************************************************/
#if STM32F0_NPORTS > 0
# define STM32F0_GPIOA_MODER (STM32F0_GPIOA_BASE+STM32F0_GPIO_MODER_OFFSET)
# define STM32F0_GPIOA_OTYPER (STM32F0_GPIOA_BASE+STM32F0_GPIO_OTYPER_OFFSET)
# define STM32F0_GPIOA_OSPEED (STM32F0_GPIOA_BASE+STM32F0_GPIO_OSPEED_OFFSET)
# define STM32F0_GPIOA_PUPDR (STM32F0_GPIOA_BASE+STM32F0_GPIO_PUPDR_OFFSET)
# define STM32F0_GPIOA_IDR (STM32F0_GPIOA_BASE+STM32F0_GPIO_IDR_OFFSET)
# define STM32F0_GPIOA_ODR (STM32F0_GPIOA_BASE+STM32F0_GPIO_ODR_OFFSET)
# define STM32F0_GPIOA_BSRR (STM32F0_GPIOA_BASE+STM32F0_GPIO_BSRR_OFFSET)
# define STM32F0_GPIOA_LCKR (STM32F0_GPIOA_BASE+STM32F0_GPIO_LCKR_OFFSET)
# define STM32F0_GPIOA_AFRL (STM32F0_GPIOA_BASE+STM32F0_GPIO_AFRL_OFFSET)
# define STM32F0_GPIOA_AFRH (STM32F0_GPIOA_BASE+STM32F0_GPIO_AFRH_OFFSET)
#if STM32_NPORTS > 0
# define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOA_IDR (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOA_ODR (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET)
#endif
#if STM32F0_NPORTS > 1
# define STM32F0_GPIOB_MODER (STM32F0_GPIOB_BASE+STM32F0_GPIO_MODER_OFFSET)
# define STM32F0_GPIOB_OTYPER (STM32F0_GPIOB_BASE+STM32F0_GPIO_OTYPER_OFFSET)
# define STM32F0_GPIOB_OSPEED (STM32F0_GPIOB_BASE+STM32F0_GPIO_OSPEED_OFFSET)
# define STM32F0_GPIOB_PUPDR (STM32F0_GPIOB_BASE+STM32F0_GPIO_PUPDR_OFFSET)
# define STM32F0_GPIOB_IDR (STM32F0_GPIOB_BASE+STM32F0_GPIO_IDR_OFFSET)
# define STM32F0_GPIOB_ODR (STM32F0_GPIOB_BASE+STM32F0_GPIO_ODR_OFFSET)
# define STM32F0_GPIOB_BSRR (STM32F0_GPIOB_BASE+STM32F0_GPIO_BSRR_OFFSET)
# define STM32F0_GPIOB_LCKR (STM32F0_GPIOB_BASE+STM32F0_GPIO_LCKR_OFFSET)
# define STM32F0_GPIOB_AFRL (STM32F0_GPIOB_BASE+STM32F0_GPIO_AFRL_OFFSET)
# define STM32F0_GPIOB_AFRH (STM32F0_GPIOB_BASE+STM32F0_GPIO_AFRH_OFFSET)
#if STM32_NPORTS > 1
# define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOB_IDR (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOB_ODR (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET)
#endif
#if STM32F0_NPORTS > 2
# define STM32F0_GPIOC_MODER (STM32F0_GPIOC_BASE+STM32F0_GPIO_MODER_OFFSET)
# define STM32F0_GPIOC_OTYPER (STM32F0_GPIOC_BASE+STM32F0_GPIO_OTYPER_OFFSET)
# define STM32F0_GPIOC_OSPEED (STM32F0_GPIOC_BASE+STM32F0_GPIO_OSPEED_OFFSET)
# define STM32F0_GPIOC_PUPDR (STM32F0_GPIOC_BASE+STM32F0_GPIO_PUPDR_OFFSET)
# define STM32F0_GPIOC_IDR (STM32F0_GPIOC_BASE+STM32F0_GPIO_IDR_OFFSET)
# define STM32F0_GPIOC_ODR (STM32F0_GPIOC_BASE+STM32F0_GPIO_ODR_OFFSET)
# define STM32F0_GPIOC_BSRR (STM32F0_GPIOC_BASE+STM32F0_GPIO_BSRR_OFFSET)
# define STM32F0_GPIOC_LCKR (STM32F0_GPIOC_BASE+STM32F0_GPIO_LCKR_OFFSET)
# define STM32F0_GPIOC_AFRL (STM32F0_GPIOC_BASE+STM32F0_GPIO_AFRL_OFFSET)
# define STM32F0_GPIOC_AFRH (STM32F0_GPIOC_BASE+STM32F0_GPIO_AFRH_OFFSET)
#if STM32_NPORTS > 2
# define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOC_IDR (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOC_ODR (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET)
#endif
#if STM32F0_NPORTS > 3
# define STM32F0_GPIOD_MODER (STM32F0_GPIOD_BASE+STM32F0_GPIO_MODER_OFFSET)
# define STM32F0_GPIOD_OTYPER (STM32F0_GPIOD_BASE+STM32F0_GPIO_OTYPER_OFFSET)
# define STM32F0_GPIOD_OSPEED (STM32F0_GPIOD_BASE+STM32F0_GPIO_OSPEED_OFFSET)
# define STM32F0_GPIOD_PUPDR (STM32F0_GPIOD_BASE+STM32F0_GPIO_PUPDR_OFFSET)
# define STM32F0_GPIOD_IDR (STM32F0_GPIOD_BASE+STM32F0_GPIO_IDR_OFFSET)
# define STM32F0_GPIOD_ODR (STM32F0_GPIOD_BASE+STM32F0_GPIO_ODR_OFFSET)
# define STM32F0_GPIOD_BSRR (STM32F0_GPIOD_BASE+STM32F0_GPIO_BSRR_OFFSET)
# define STM32F0_GPIOD_LCKR (STM32F0_GPIOD_BASE+STM32F0_GPIO_LCKR_OFFSET)
# define STM32F0_GPIOD_AFRL (STM32F0_GPIOD_BASE+STM32F0_GPIO_AFRL_OFFSET)
# define STM32F0_GPIOD_AFRH (STM32F0_GPIOD_BASE+STM32F0_GPIO_AFRH_OFFSET)
#if STM32_NPORTS > 3
# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOD_IDR (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOD_ODR (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET)
#endif
#if STM32F0_NPORTS > 4
# define STM32F0_GPIOE_MODER (STM32F0_GPIOE_BASE+STM32F0_GPIO_MODER_OFFSET)
# define STM32F0_GPIOE_OTYPER (STM32F0_GPIOE_BASE+STM32F0_GPIO_OTYPER_OFFSET)
# define STM32F0_GPIOE_OSPEED (STM32F0_GPIOE_BASE+STM32F0_GPIO_OSPEED_OFFSET)
# define STM32F0_GPIOE_PUPDR (STM32F0_GPIOE_BASE+STM32F0_GPIO_PUPDR_OFFSET)
# define STM32F0_GPIOE_IDR (STM32F0_GPIOE_BASE+STM32F0_GPIO_IDR_OFFSET)
# define STM32F0_GPIOE_ODR (STM32F0_GPIOE_BASE+STM32F0_GPIO_ODR_OFFSET)
# define STM32F0_GPIOE_BSRR (STM32F0_GPIOE_BASE+STM32F0_GPIO_BSRR_OFFSET)
# define STM32F0_GPIOE_LCKR (STM32F0_GPIOE_BASE+STM32F0_GPIO_LCKR_OFFSET)
# define STM32F0_GPIOE_AFRL (STM32F0_GPIOE_BASE+STM32F0_GPIO_AFRL_OFFSET)
# define STM32F0_GPIOE_AFRH (STM32F0_GPIOE_BASE+STM32F0_GPIO_AFRH_OFFSET)
#if STM32_NPORTS > 4
# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOE_IDR (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOE_ODR (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE + STM32_GPIO_AFRH_OFFSET)
#endif
#if STM32F0_NPORTS > 5
# define STM32F0_GPIOF_MODER (STM32F0_GPIOF_BASE+STM32F0_GPIO_MODER_OFFSET)
# define STM32F0_GPIOF_OTYPER (STM32F0_GPIOF_BASE+STM32F0_GPIO_OTYPER_OFFSET)
# define STM32F0_GPIOF_OSPEED (STM32F0_GPIOF_BASE+STM32F0_GPIO_OSPEED_OFFSET)
# define STM32F0_GPIOF_PUPDR (STM32F0_GPIOF_BASE+STM32F0_GPIO_PUPDR_OFFSET)
# define STM32F0_GPIOF_IDR (STM32F0_GPIOF_BASE+STM32F0_GPIO_IDR_OFFSET)
# define STM32F0_GPIOF_ODR (STM32F0_GPIOF_BASE+STM32F0_GPIO_ODR_OFFSET)
# define STM32F0_GPIOF_BSRR (STM32F0_GPIOF_BASE+STM32F0_GPIO_BSRR_OFFSET)
# define STM32F0_GPIOF_LCKR (STM32F0_GPIOF_BASE+STM32F0_GPIO_LCKR_OFFSET)
# define STM32F0_GPIOF_AFRL (STM32F0_GPIOF_BASE+STM32F0_GPIO_AFRL_OFFSET)
# define STM32F0_GPIOF_AFRH (STM32F0_GPIOF_BASE+STM32F0_GPIO_AFRH_OFFSET)
#if STM32_NPORTS > 5
# define STM32_GPIOF_MODER (STM32_GPIOF_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOF_IDR (STM32_GPIOF_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOF_ODR (STM32_GPIOF_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE + STM32_GPIO_AFRH_OFFSET)
#endif
/* Register Bitfield Definitions ****************************************************/
@ -280,7 +280,7 @@
/* GPIO port bit set/reset register */
#define GPIO_BSRR_SET(n) (1 << (n))
#define GPIO_BSRR_RESET(n) (1 << ((n)+16))
#define GPIO_BSRR_RESET(n) (1 << ((n) + 16))
/* GPIO port configuration lock register */
@ -330,4 +330,4 @@
#define GPIO_BRR(n) (1 << (n))
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_GPIO_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_GPIO_H */

78
arch/arm/src/stm32f0/chip/stm32f0_i2c.h → arch/arm/src/stm32f0l0/hardware/stm32_i2c.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f0_i2c.h
* arch/arm/src/stm32f0l0/hardware/stm32_i2c.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_I2C_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_I2C_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_I2C_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_I2C_H
/************************************************************************************
* Pre-processor Definitions
@ -43,46 +43,46 @@
/* Register Offsets *****************************************************************/
#define STM32F0_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */
#define STM32F0_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */
#define STM32F0_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
#define STM32F0_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
#define STM32F0_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */
#define STM32F0_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */
#define STM32F0_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */
#define STM32F0_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */
#define STM32F0_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */
#define STM32F0_I2C_RXDR_OFFSET 0x0024 /* Receive data register */
#define STM32F0_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */
#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */
#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */
#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */
#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */
#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */
#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */
#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */
#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */
#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */
/* Register Addresses ***************************************************************/
#if STM32F0_NI2C > 0
# define STM32F0_I2C1_CR1 (STM32F0_I2C1_BASE+STM32F0_I2C_CR1_OFFSET)
# define STM32F0_I2C1_CR2 (STM32F0_I2C1_BASE+STM32F0_I2C_CR2_OFFSET)
# define STM32F0_I2C1_OAR1 (STM32F0_I2C1_BASE+STM32F0_I2C_OAR1_OFFSET)
# define STM32F0_I2C1_OAR2 (STM32F0_I2C1_BASE+STM32F0_I2C_OAR2_OFFSET)
# define STM32F0_I2C1_TIMINGR (STM32F0_I2C1_BASE+STM32F0_I2C_TIMINGR_OFFSET)
# define STM32F0_I2C1_TIMEOUTR (STM32F0_I2C1_BASE+STM32F0_I2C_TIMEOUTR_OFFSET)
# define STM32F0_I2C1_ISR (STM32F0_I2C1_BASE+STM32F0_I2C_ISR_OFFSET)
# define STM32F0_I2C1_ICR (STM32F0_I2C1_BASE+STM32F0_I2C_ICR_OFFSET)
# define STM32F0_I2C1_PECR (STM32F0_I2C1_BASE+STM32F0_I2C_PECR_OFFSET)
# define STM32F0_I2C1_RXDR (STM32F0_I2C1_BASE+STM32F0_I2C_RXDR_OFFSET)
# define STM32F0_I2C1_TXDR (STM32F0_I2C1_BASE+STM32F0_I2C_TXDR_OFFSET)
#if STM32_NI2C > 0
# define STM32_I2C1_CR1 (STM32_I2C1_BASE + STM32_I2C_CR1_OFFSET)
# define STM32_I2C1_CR2 (STM32_I2C1_BASE + STM32_I2C_CR2_OFFSET)
# define STM32_I2C1_OAR1 (STM32_I2C1_BASE + STM32_I2C_OAR1_OFFSET)
# define STM32_I2C1_OAR2 (STM32_I2C1_BASE + STM32_I2C_OAR2_OFFSET)
# define STM32_I2C1_TIMINGR (STM32_I2C1_BASE + STM32_I2C_TIMINGR_OFFSET)
# define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE + STM32_I2C_TIMEOUTR_OFFSET)
# define STM32_I2C1_ISR (STM32_I2C1_BASE + STM32_I2C_ISR_OFFSET)
# define STM32_I2C1_ICR (STM32_I2C1_BASE + STM32_I2C_ICR_OFFSET)
# define STM32_I2C1_PECR (STM32_I2C1_BASE + STM32_I2C_PECR_OFFSET)
# define STM32_I2C1_RXDR (STM32_I2C1_BASE + STM32_I2C_RXDR_OFFSET)
# define STM32_I2C1_TXDR (STM32_I2C1_BASE + STM32_I2C_TXDR_OFFSET)
#endif
#if STM32F0_NI2C > 1
# define STM32F0_I2C2_CR1 (STM32F0_I2C2_BASE+STM32F0_I2C_CR1_OFFSET)
# define STM32F0_I2C2_CR2 (STM32F0_I2C2_BASE+STM32F0_I2C_CR2_OFFSET)
# define STM32F0_I2C2_OAR1 (STM32F0_I2C2_BASE+STM32F0_I2C_OAR1_OFFSET)
# define STM32F0_I2C2_OAR2 (STM32F0_I2C2_BASE+STM32F0_I2C_OAR2_OFFSET)
# define STM32F0_I2C2_TIMINGR (STM32F0_I2C2_BASE+STM32F0_I2C_TIMINGR_OFFSET)
# define STM32F0_I2C2_TIMEOUTR (STM32F0_I2C2_BASE+STM32F0_I2C_TIMEOUTR_OFFSET)
# define STM32F0_I2C2_ISR (STM32F0_I2C2_BASE+STM32F0_I2C_ISR_OFFSET)
# define STM32F0_I2C2_ICR (STM32F0_I2C2_BASE+STM32F0_I2C_ICR_OFFSET)
# define STM32F0_I2C2_PECR (STM32F0_I2C2_BASE+STM32F0_I2C_PECR_OFFSET)
# define STM32F0_I2C2_RXDR (STM32F0_I2C2_BASE+STM32F0_I2C_RXDR_OFFSET)
# define STM32F0_I2C2_TXDR (STM32F0_I2C2_BASE+STM32F0_I2C_TXDR_OFFSET)
#if STM32_NI2C > 1
# define STM32_I2C2_CR1 (STM32_I2C2_BASE + STM32_I2C_CR1_OFFSET)
# define STM32_I2C2_CR2 (STM32_I2C2_BASE + STM32_I2C_CR2_OFFSET)
# define STM32_I2C2_OAR1 (STM32_I2C2_BASE + STM32_I2C_OAR1_OFFSET)
# define STM32_I2C2_OAR2 (STM32_I2C2_BASE + STM32_I2C_OAR2_OFFSET)
# define STM32_I2C2_TIMINGR (STM32_I2C2_BASE + STM32_I2C_TIMINGR_OFFSET)
# define STM32_I2C2_TIMEOUTR (STM32_I2C2_BASE + STM32_I2C_TIMEOUTR_OFFSET)
# define STM32_I2C2_ISR (STM32_I2C2_BASE + STM32_I2C_ISR_OFFSET)
# define STM32_I2C2_ICR (STM32_I2C2_BASE + STM32_I2C_ICR_OFFSET)
# define STM32_I2C2_PECR (STM32_I2C2_BASE + STM32_I2C_PECR_OFFSET)
# define STM32_I2C2_RXDR (STM32_I2C2_BASE + STM32_I2C_RXDR_OFFSET)
# define STM32_I2C2_TXDR (STM32_I2C2_BASE + STM32_I2C_TXDR_OFFSET)
#endif
/* Register Bitfield Definitions ****************************************************/
@ -235,4 +235,4 @@
#define I2C_TXDR_MASK (0xff)
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_I2C_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_I2C_H */

14
arch/arm/src/stm32f0/chip/stm32f0_memorymap.h → arch/arm/src/stm32f0l0/hardware/stm32_memorymap.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f0_memorymap.h
* arch/arm/src/stm32f0l0/hardware/stm32_memorymap.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_MEMORYMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_MEMORYMAP_H
/************************************************************************************
* Included Files
@ -44,11 +44,11 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F0_STM32F05X) || defined(CONFIG_STM32F0_STM32F07X) \
|| defined(CONFIG_STM32F0_STM32F09X)
# include "chip/stm32f05xf07xf09x_memorymap.h"
#if defined(CONFIG_STM32F0L0_STM32F05X) || defined(CONFIG_STM32F0L0_STM32F07X) || \
defined(CONFIG_STM32F0L0_STM32F09X)
# include "hardware/stm32f05xf07xf09x_memorymap.h"
#else
# error "Unsupported STM32 memory map"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_MEMORYMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_MEMORYMAP_H */

21
arch/arm/src/stm32f0/chip/stm32f0_pinmap.h → arch/arm/src/stm32f0l0/hardware/stm32_pinmap.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f0_pinmap.h
* arch/arm/src/stm32f0l0/hardware/stm32_pinmap.h
*
* Copyright (C) 2015 Sebastien Lorquet. All rights reserved.
* Author: Sebastien Lorquet <sebastien@lorquet.fr>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_PINMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PINMAP_H
/************************************************************************************
* Included Files
@ -43,15 +43,14 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F0_STM32F05X)
# include "chip/stm32f05x_pinmap.h"
#elif defined(CONFIG_STM32F0_STM32F07X)
# include "chip/stm32f07x_pinmap.h"
#elif defined(CONFIG_STM32F0_STM32F09X)
# include "chip/stm32f09x_pinmap.h"
#if defined(CONFIG_STM32F0L0_STM32F05X)
# include "hardware/stm32f05x_pinmap.h"
#elif defined(CONFIG_STM32F0L0_STM32F07X)
# include "hardware/stm32f07x_pinmap.h"
#elif defined(CONFIG_STM32F0L0_STM32F09X)
# include "hardware/stm32f09x_pinmap.h"
#else
# error "Unsupported STM32F0 pin map"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_PINMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PINMAP_H */

72
arch/arm/src/stm32f0/chip/stm32f0_pwr.h → arch/arm/src/stm32f0l0/hardware/stm32_pwr.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f0_pwr.h
* arch/arm/src/stm32f0l0/hardware/stm32_pwr.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_PWR_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_PWR_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_PWR_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_PWR_H
/************************************************************************************
* Included Files
@ -50,49 +50,49 @@
/* Register Offsets *****************************************************************/
#define STM32F0_PWR_CR_OFFSET 0x0000 /* Power control register */
#define STM32F0_PWR_CSR_OFFSET 0x0004 /* Power control/status register */
#define STM32_PWR_CR_OFFSET 0x0000 /* Power control register */
#define STM32_PWR_CSR_OFFSET 0x0004 /* Power control/status register */
/* Register Addresses ***************************************************************/
#define STM32F0_PWR_CR (STM32F0_PWR_BASE+STM32F0_PWR_CR_OFFSET)
#define STM32F0_PWR_CSR (STM32F0_PWR_BASE+STM32F0_PWR_CSR_OFFSET)
#define STM32_PWR_CR (STM32_PWR_BASE + STM32_PWR_CR_OFFSET)
#define STM32_PWR_CSR (STM32_PWR_BASE + STM32_PWR_CSR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* Power control register */
#define PWR_CR_LPDS (1 << 0) /* Bit 0: Low-Power Deepsleep/sleep; low power run */
#define PWR_CR_PDDS (1 << 1) /* Bit 1: Power Down Deepsleep */
#define PWR_CR_CWUF (1 << 2) /* Bit 2: Clear Wakeup Flag */
#define PWR_CR_CSBF (1 << 3) /* Bit 3: Clear Standby Flag */
#define PWR_CR_PVDE (1 << 4) /* Bit 4: Power Voltage Detector Enable */
#define PWR_CR_PLS_SHIFT (5) /* Bits 7-5: PVD Level Selection */
#define PWR_CR_PLS_MASK (7 << PWR_CR_PLS_SHIFT)
# define PWR_CR_2p2V (0 << PWR_CR_PLS_SHIFT) /* 000: 2.2V */
# define PWR_CR_2p3V (1 << PWR_CR_PLS_SHIFT) /* 001: 2.3V */
# define PWR_CR_2p4V (2 << PWR_CR_PLS_SHIFT) /* 010: 2.4V */
# define PWR_CR_2p5V (3 << PWR_CR_PLS_SHIFT) /* 011: 2.5V */
# define PWR_CR_2p6V (4 << PWR_CR_PLS_SHIFT) /* 100: 2.6V */
# define PWR_CR_2p7V (5 << PWR_CR_PLS_SHIFT) /* 101: 2.7V */
# define PWR_CR_2p8V (6 << PWR_CR_PLS_SHIFT) /* 110: 2.8V */
# define PWR_CR_2p9V (7 << PWR_CR_PLS_SHIFT) /* 111: 2.9V */
#define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */
#define PWR_CR_LPDS (1 << 0) /* Bit 0: Low-Power Deepsleep/sleep; low power run */
#define PWR_CR_PDDS (1 << 1) /* Bit 1: Power Down Deepsleep */
#define PWR_CR_CWUF (1 << 2) /* Bit 2: Clear Wakeup Flag */
#define PWR_CR_CSBF (1 << 3) /* Bit 3: Clear Standby Flag */
#define PWR_CR_PVDE (1 << 4) /* Bit 4: Power Voltage Detector Enable */
#define PWR_CR_PLS_SHIFT (5) /* Bits 7-5: PVD Level Selection */
#define PWR_CR_PLS_MASK (7 << PWR_CR_PLS_SHIFT)
# define PWR_CR_2p2V (0 << PWR_CR_PLS_SHIFT) /* 000: 2.2V */
# define PWR_CR_2p3V (1 << PWR_CR_PLS_SHIFT) /* 001: 2.3V */
# define PWR_CR_2p4V (2 << PWR_CR_PLS_SHIFT) /* 010: 2.4V */
# define PWR_CR_2p5V (3 << PWR_CR_PLS_SHIFT) /* 011: 2.5V */
# define PWR_CR_2p6V (4 << PWR_CR_PLS_SHIFT) /* 100: 2.6V */
# define PWR_CR_2p7V (5 << PWR_CR_PLS_SHIFT) /* 101: 2.7V */
# define PWR_CR_2p8V (6 << PWR_CR_PLS_SHIFT) /* 110: 2.8V */
# define PWR_CR_2p9V (7 << PWR_CR_PLS_SHIFT) /* 111: 2.9V */
#define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */
/* Power control/status register */
#define PWR_CSR_WUF (1 << 0) /* Bit 0: Wakeup Flag */
#define PWR_CSR_SBF (1 << 1) /* Bit 1: Standby Flag */
#define PWR_CSR_PVDO (1 << 2) /* Bit 2: PVD Output */
#define PWR_CSR_VREFINTRDY (1 << 3) /* Bit 3: Internal voltage reference (VREFINT) ready flag */
#define PWR_CSR_EWUP1 (1 << 8) /* Bit 8: Enable WKUP1 pin */
#define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */
#define PWR_CSR_EWUP3 (1 << 10) /* Bit 10: Enable WKUP3 pin */
#define PWR_CSR_EWUP4 (1 << 11) /* Bit 11: Enable WKUP4 pin */
#define PWR_CSR_EWUP5 (1 << 12) /* Bit 12: Enable WKUP5 pin */
#define PWR_CSR_EWUP6 (1 << 13) /* Bit 13: Enable WKUP6 pin */
#define PWR_CSR_EWUP7 (1 << 14) /* Bit 14: Enable WKUP7 pin */
#define PWR_CSR_EWUP8 (1 << 15) /* Bit 15: Enable WKUP8 pin */
#define PWR_CSR_WUF (1 << 0) /* Bit 0: Wakeup Flag */
#define PWR_CSR_SBF (1 << 1) /* Bit 1: Standby Flag */
#define PWR_CSR_PVDO (1 << 2) /* Bit 2: PVD Output */
#define PWR_CSR_VREFINTRDY (1 << 3) /* Bit 3: Internal voltage reference (VREFINT) ready flag */
#define PWR_CSR_EWUP1 (1 << 8) /* Bit 8: Enable WKUP1 pin */
#define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */
#define PWR_CSR_EWUP3 (1 << 10) /* Bit 10: Enable WKUP3 pin */
#define PWR_CSR_EWUP4 (1 << 11) /* Bit 11: Enable WKUP4 pin */
#define PWR_CSR_EWUP5 (1 << 12) /* Bit 12: Enable WKUP5 pin */
#define PWR_CSR_EWUP6 (1 << 13) /* Bit 13: Enable WKUP6 pin */
#define PWR_CSR_EWUP7 (1 << 14) /* Bit 14: Enable WKUP7 pin */
#define PWR_CSR_EWUP8 (1 << 15) /* Bit 15: Enable WKUP8 pin */
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_PWR_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_PWR_H */

54
arch/arm/src/stm32f0l0/hardware/stm32_rcc.h Normal file
View file

@ -0,0 +1,54 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_rcc.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RCC_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RCC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F0L0_STM32F05X) || defined(CONFIG_STM32F0L0_STM32F07X) || \
defined(CONFIG_STM32F0L0_STM32F09X)
# include "hardware/stm32f0_rcc.h"
#else
# error "Unsupported STM32 RCC"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RCC_H */

98
arch/arm/src/stm32f0/chip/stm32f0_rtcc.h → arch/arm/src/stm32f0l0/hardware/stm32_rtcc.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f0_rtcc.h.h
* arch/arm/src/stm32f0l0/hardware/stm32_rtcc.h.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_RTCC_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_RTCC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RTCC_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RTCC_H
/************************************************************************************
* Pre-processor Definitions
@ -43,57 +43,57 @@
/* Register Offsets *****************************************************************/
#define STM32F0_RTC_TR_OFFSET 0x0000 /* RTC time register */
#define STM32F0_RTC_DR_OFFSET 0x0004 /* RTC date register */
#define STM32F0_RTC_CR_OFFSET 0x0008 /* RTC control register */
#define STM32F0_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */
#define STM32F0_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */
#define STM32F0_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */
#define STM32F0_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */
#define STM32F0_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */
#define STM32F0_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */
#define STM32F0_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */
#define STM32F0_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */
#define STM32F0_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */
#define STM32F0_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */
#define STM32F0_RTC_CALR_OFFSET 0x003c /* RTC calibration register */
#define STM32F0_RTC_TAFCR_OFFSET 0x0040 /* RTC tamper and alternate function configuration register */
#define STM32F0_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */
#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */
#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */
#define STM32_RTC_CR_OFFSET 0x0008 /* RTC control register */
#define STM32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */
#define STM32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */
#define STM32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */
#define STM32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */
#define STM32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */
#define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */
#define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */
#define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */
#define STM32_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */
#define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */
#define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */
#define STM32_RTC_TAFCR_OFFSET 0x0040 /* RTC tamper and alternate function configuration register */
#define STM32_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */
#define STM32F0_RTC_BKR_OFFSET(n) (0x0050+((n)<<2))
#define STM32F0_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */
#define STM32F0_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */
#define STM32F0_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */
#define STM32F0_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */
#define STM32F0_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */
#define STM32_RTC_BKR_OFFSET(n) (0x0050 + ((n) << 2))
#define STM32_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */
#define STM32_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */
#define STM32_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */
#define STM32_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */
#define STM32_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */
/* Register Addresses ***************************************************************/
#define STM32F0_RTC_TR (STM32F0_RTC_BASE+STM32F0_RTC_TR_OFFSET)
#define STM32F0_RTC_DR (STM32F0_RTC_BASE+STM32F0_RTC_DR_OFFSET)
#define STM32F0_RTC_CR (STM32F0_RTC_BASE+STM32F0_RTC_CR_OFFSET)
#define STM32F0_RTC_ISR (STM32F0_RTC_BASE+STM32F0_RTC_ISR_OFFSET)
#define STM32F0_RTC_PRER (STM32F0_RTC_BASE+STM32F0_RTC_PRER_OFFSET)
#define STM32F0_RTC_WUTR (STM32F0_RTC_BASE+STM32F0_RTC_WUTR_OFFSET)
#define STM32F0_RTC_ALRMAR (STM32F0_RTC_BASE+STM32F0_RTC_ALRMAR_OFFSET)
#define STM32F0_RTC_WPR (STM32F0_RTC_BASE+STM32F0_RTC_WPR_OFFSET)
#define STM32F0_RTC_SSR (STM32F0_RTC_BASE+STM32F0_RTC_SSR_OFFSET)
#define STM32F0_RTC_SHIFTR (STM32F0_RTC_BASE+STM32F0_RTC_SHIFTR_OFFSET)
#define STM32F0_RTC_TSTR (STM32F0_RTC_BASE+STM32F0_RTC_TSTR_OFFSET)
#define STM32F0_RTC_TSDR (STM32F0_RTC_BASE+STM32F0_RTC_TSDR_OFFSET)
#define STM32F0_RTC_TSSSR (STM32F0_RTC_BASE+STM32F0_RTC_TSSSR_OFFSET)
#define STM32F0_RTC_CALR (STM32F0_RTC_BASE+STM32F0_RTC_CALR_OFFSET)
#define STM32F0_RTC_TAFCR (STM32F0_RTC_BASE+STM32F0_RTC_TAFCR_OFFSET)
#define STM32F0_RTC_ALRMASSR (STM32F0_RTC_BASE+STM32F0_RTC_ALRMASSR_OFFSET)
#define STM32_RTC_TR (STM32_RTC_BASE + STM32_RTC_TR_OFFSET)
#define STM32_RTC_DR (STM32_RTC_BASE + STM32_RTC_DR_OFFSET)
#define STM32_RTC_CR (STM32_RTC_BASE + STM32_RTC_CR_OFFSET)
#define STM32_RTC_ISR (STM32_RTC_BASE + STM32_RTC_ISR_OFFSET)
#define STM32_RTC_PRER (STM32_RTC_BASE + STM32_RTC_PRER_OFFSET)
#define STM32_RTC_WUTR (STM32_RTC_BASE + STM32_RTC_WUTR_OFFSET)
#define STM32_RTC_ALRMAR (STM32_RTC_BASE + STM32_RTC_ALRMAR_OFFSET)
#define STM32_RTC_WPR (STM32_RTC_BASE + STM32_RTC_WPR_OFFSET)
#define STM32_RTC_SSR (STM32_RTC_BASE + STM32_RTC_SSR_OFFSET)
#define STM32_RTC_SHIFTR (STM32_RTC_BASE + STM32_RTC_SHIFTR_OFFSET)
#define STM32_RTC_TSTR (STM32_RTC_BASE + STM32_RTC_TSTR_OFFSET)
#define STM32_RTC_TSDR (STM32_RTC_BASE + STM32_RTC_TSDR_OFFSET)
#define STM32_RTC_TSSSR (STM32_RTC_BASE + STM32_RTC_TSSSR_OFFSET)
#define STM32_RTC_CALR (STM32_RTC_BASE + STM32_RTC_CALR_OFFSET)
#define STM32_RTC_TAFCR (STM32_RTC_BASE + STM32_RTC_TAFCR_OFFSET)
#define STM32_RTC_ALRMASSR (STM32_RTC_BASE + STM32_RTC_ALRMASSR_OFFSET)
#define STM32F0_RTC_BKR(n) (STM32F0_RTC_BASE+STM32F0_RTC_BKR_OFFSET(n))
#define STM32F0_RTC_BK0R (STM32F0_RTC_BASE+STM32F0_RTC_BK0R_OFFSET)
#define STM32F0_RTC_BK1R (STM32F0_RTC_BASE+STM32F0_RTC_BK1R_OFFSET)
#define STM32F0_RTC_BK2R (STM32F0_RTC_BASE+STM32F0_RTC_BK2R_OFFSET)
#define STM32F0_RTC_BK3R (STM32F0_RTC_BASE+STM32F0_RTC_BK3R_OFFSET)
#define STM32F0_RTC_BK4R (STM32F0_RTC_BASE+STM32F0_RTC_BK4R_OFFSET)
#define STM32_RTC_BKR(n) (STM32_RTC_BASE + STM32_RTC_BKR_OFFSET(n))
#define STM32_RTC_BK0R (STM32_RTC_BASE + STM32_RTC_BK0R_OFFSET)
#define STM32_RTC_BK1R (STM32_RTC_BASE + STM32_RTC_BK1R_OFFSET)
#define STM32_RTC_BK2R (STM32_RTC_BASE + STM32_RTC_BK2R_OFFSET)
#define STM32_RTC_BK3R (STM32_RTC_BASE + STM32_RTC_BK3R_OFFSET)
#define STM32_RTC_BK4R (STM32_RTC_BASE + STM32_RTC_BK4R_OFFSET)
#define STM32F0_RTC_BKCOUNT 5
#define STM32_RTC_BKCOUNT 5
/* Register Bitfield Definitions ****************************************************/
@ -321,4 +321,4 @@
#define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */
#define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_RTCC_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RTCC_H */

144
arch/arm/src/stm32f0/chip/stm32f0_spi.h → arch/arm/src/stm32f0l0/hardware/stm32_spi.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f0_spi.h
* arch/arm/src/stm32f0l0/hardware/stm32_spi.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_SPI_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_SPI_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SPI_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SPI_H
/************************************************************************************
* Included Files
@ -49,90 +49,90 @@
/* Maximum allowed speed as per data sheet for all SPIs (both pclk1 and pclk2)*/
#define STM32F0_SPI_CLK_MAX 50000000UL
#define STM32_SPI_CLK_MAX 50000000UL
/* Register Offsets *****************************************************************/
#define STM32F0_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
#define STM32F0_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
#define STM32F0_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
#define STM32F0_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
#define STM32F0_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
#define STM32F0_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
#define STM32F0_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
#define STM32F0_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */
#define STM32F0_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */
#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
#define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */
#define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */
/* Register Addresses ***************************************************************/
#if STM32F0_NSPI > 0
# define STM32F0_SPI1_CR1 (STM32F0_SPI1_BASE+STM32F0_SPI_CR1_OFFSET)
# define STM32F0_SPI1_CR2 (STM32F0_SPI1_BASE+STM32F0_SPI_CR2_OFFSET)
# define STM32F0_SPI1_SR (STM32F0_SPI1_BASE+STM32F0_SPI_SR_OFFSET)
# define STM32F0_SPI1_DR (STM32F0_SPI1_BASE+STM32F0_SPI_DR_OFFSET)
# define STM32F0_SPI1_CRCPR (STM32F0_SPI1_BASE+STM32F0_SPI_CRCPR_OFFSET)
# define STM32F0_SPI1_RXCRCR (STM32F0_SPI1_BASE+STM32F0_SPI_RXCRCR_OFFSET)
# define STM32F0_SPI1_TXCRCR (STM32F0_SPI1_BASE+STM32F0_SPI_TXCRCR_OFFSET)
#if STM32_NSPI > 0
# define STM32_SPI1_CR1 (STM32_SPI1_BASE + STM32_SPI_CR1_OFFSET)
# define STM32_SPI1_CR2 (STM32_SPI1_BASE + STM32_SPI_CR2_OFFSET)
# define STM32_SPI1_SR (STM32_SPI1_BASE + STM32_SPI_SR_OFFSET)
# define STM32_SPI1_DR (STM32_SPI1_BASE + STM32_SPI_DR_OFFSET)
# define STM32_SPI1_CRCPR (STM32_SPI1_BASE + STM32_SPI_CRCPR_OFFSET)
# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET)
#endif
#if STM32F0_NSPI > 1
# define STM32F0_SPI2_CR1 (STM32F0_SPI2_BASE+STM32F0_SPI_CR1_OFFSET)
# define STM32F0_SPI2_CR2 (STM32F0_SPI2_BASE+STM32F0_SPI_CR2_OFFSET)
# define STM32F0_SPI2_SR (STM32F0_SPI2_BASE+STM32F0_SPI_SR_OFFSET)
# define STM32F0_SPI2_DR (STM32F0_SPI2_BASE+STM32F0_SPI_DR_OFFSET)
# define STM32F0_SPI2_CRCPR (STM32F0_SPI2_BASE+STM32F0_SPI_CRCPR_OFFSET)
# define STM32F0_SPI2_RXCRCR (STM32F0_SPI2_BASE+STM32F0_SPI_RXCRCR_OFFSET)
# define STM32F0_SPI2_TXCRCR (STM32F0_SPI2_BASE+STM32F0_SPI_TXCRCR_OFFSET)
# define STM32F0_SPI2_I2SCFGR (STM32F0_SPI2_BASE+STM32F0_SPI_I2SCFGR_OFFSET)
# define STM32F0_SPI2_I2SPR (STM32F0_SPI2_BASE+STM32F0_SPI_I2SPR_OFFSET)
#if STM32_NSPI > 1
# define STM32_SPI2_CR1 (STM32_SPI2_BASE + STM32_SPI_CR1_OFFSET)
# define STM32_SPI2_CR2 (STM32_SPI2_BASE + STM32_SPI_CR2_OFFSET)
# define STM32_SPI2_SR (STM32_SPI2_BASE + STM32_SPI_SR_OFFSET)
# define STM32_SPI2_DR (STM32_SPI2_BASE + STM32_SPI_DR_OFFSET)
# define STM32_SPI2_CRCPR (STM32_SPI2_BASE + STM32_SPI_CRCPR_OFFSET)
# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE + STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE + STM32_SPI_TXCRCR_OFFSET)
# define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE + STM32_SPI_I2SCFGR_OFFSET)
# define STM32_SPI2_I2SPR (STM32_SPI2_BASE + STM32_SPI_I2SPR_OFFSET)
#endif
#if STM32F0_NSPI > 2
# define STM32F0_SPI3_CR1 (STM32F0_SPI3_BASE+STM32F0_SPI_CR1_OFFSET)
# define STM32F0_SPI3_CR2 (STM32F0_SPI3_BASE+STM32F0_SPI_CR2_OFFSET)
# define STM32F0_SPI3_SR (STM32F0_SPI3_BASE+STM32F0_SPI_SR_OFFSET)
# define STM32F0_SPI3_DR (STM32F0_SPI3_BASE+STM32F0_SPI_DR_OFFSET)
# define STM32F0_SPI3_CRCPR (STM32F0_SPI3_BASE+STM32F0_SPI_CRCPR_OFFSET)
# define STM32F0_SPI3_RXCRCR (STM32F0_SPI3_BASE+STM32F0_SPI_RXCRCR_OFFSET)
# define STM32F0_SPI3_TXCRCR (STM32F0_SPI3_BASE+STM32F0_SPI_TXCRCR_OFFSET)
# define STM32F0_SPI3_I2SCFGR (STM32F0_SPI3_BASE+STM32F0_SPI_I2SCFGR_OFFSET)
# define STM32F0_SPI3_I2SPR (STM32F0_SPI3_BASE+STM32F0_SPI_I2SPR_OFFSET)
#if STM32_NSPI > 2
# define STM32_SPI3_CR1 (STM32_SPI3_BASE + STM32_SPI_CR1_OFFSET)
# define STM32_SPI3_CR2 (STM32_SPI3_BASE + STM32_SPI_CR2_OFFSET)
# define STM32_SPI3_SR (STM32_SPI3_BASE + STM32_SPI_SR_OFFSET)
# define STM32_SPI3_DR (STM32_SPI3_BASE + STM32_SPI_DR_OFFSET)
# define STM32_SPI3_CRCPR (STM32_SPI3_BASE + STM32_SPI_CRCPR_OFFSET)
# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE + STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE + STM32_SPI_TXCRCR_OFFSET)
# define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE + STM32_SPI_I2SCFGR_OFFSET)
# define STM32_SPI3_I2SPR (STM32_SPI3_BASE + STM32_SPI_I2SPR_OFFSET)
#endif
#if STM32F0_NSPI > 3
# define STM32F0_SPI4_CR1 (STM32F0_SPI4_BASE+STM32F0_SPI_CR1_OFFSET)
# define STM32F0_SPI4_CR2 (STM32F0_SPI4_BASE+STM32F0_SPI_CR2_OFFSET)
# define STM32F0_SPI4_SR (STM32F0_SPI4_BASE+STM32F0_SPI_SR_OFFSET)
# define STM32F0_SPI4_DR (STM32F0_SPI4_BASE+STM32F0_SPI_DR_OFFSET)
# define STM32F0_SPI4_CRCPR (STM32F0_SPI4_BASE+STM32F0_SPI_CRCPR_OFFSET)
# define STM32F0_SPI4_RXCRCR (STM32F0_SPI4_BASE+STM32F0_SPI_RXCRCR_OFFSET)
# define STM32F0_SPI4_TXCRCR (STM32F0_SPI4_BASE+STM32F0_SPI_TXCRCR_OFFSET)
# define STM32F0_SPI4_I2SCFGR (STM32F0_SPI4_BASE+STM32F0_SPI_I2SCFGR_OFFSET)
# define STM32F0_SPI4_I2SPR (STM32F0_SPI4_BASE+STM32F0_SPI_I2SPR_OFFSET)
#if STM32_NSPI > 3
# define STM32_SPI4_CR1 (STM32_SPI4_BASE + STM32_SPI_CR1_OFFSET)
# define STM32_SPI4_CR2 (STM32_SPI4_BASE + STM32_SPI_CR2_OFFSET)
# define STM32_SPI4_SR (STM32_SPI4_BASE + STM32_SPI_SR_OFFSET)
# define STM32_SPI4_DR (STM32_SPI4_BASE + STM32_SPI_DR_OFFSET)
# define STM32_SPI4_CRCPR (STM32_SPI4_BASE + STM32_SPI_CRCPR_OFFSET)
# define STM32_SPI4_RXCRCR (STM32_SPI4_BASE + STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI4_TXCRCR (STM32_SPI4_BASE + STM32_SPI_TXCRCR_OFFSET)
# define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE + STM32_SPI_I2SCFGR_OFFSET)
# define STM32_SPI4_I2SPR (STM32_SPI4_BASE + STM32_SPI_I2SPR_OFFSET)
#endif
#if STM32F0_NSPI > 4
# define STM32F0_SPI5_CR1 (STM32F0_SPI5_BASE+STM32F0_SPI_CR1_OFFSET)
# define STM32F0_SPI5_CR2 (STM32F0_SPI5_BASE+STM32F0_SPI_CR2_OFFSET)
# define STM32F0_SPI5_SR (STM32F0_SPI5_BASE+STM32F0_SPI_SR_OFFSET)
# define STM32F0_SPI5_DR (STM32F0_SPI5_BASE+STM32F0_SPI_DR_OFFSET)
# define STM32F0_SPI5_CRCPR (STM32F0_SPI5_BASE+STM32F0_SPI_CRCPR_OFFSET)
# define STM32F0_SPI5_RXCRCR (STM32F0_SPI5_BASE+STM32F0_SPI_RXCRCR_OFFSET)
# define STM32F0_SPI5_TXCRCR (STM32F0_SPI5_BASE+STM32F0_SPI_TXCRCR_OFFSET)
# define STM32F0_SPI5_I2SCFGR (STM32F0_SPI5_BASE+STM32F0_SPI_I2SCFGR_OFFSET)
# define STM32F0_SPI5_I2SPR (STM32F0_SPI5_BASE+STM32F0_SPI_I2SPR_OFFSET)
#if STM32_NSPI > 4
# define STM32_SPI5_CR1 (STM32_SPI5_BASE + STM32_SPI_CR1_OFFSET)
# define STM32_SPI5_CR2 (STM32_SPI5_BASE + STM32_SPI_CR2_OFFSET)
# define STM32_SPI5_SR (STM32_SPI5_BASE + STM32_SPI_SR_OFFSET)
# define STM32_SPI5_DR (STM32_SPI5_BASE + STM32_SPI_DR_OFFSET)
# define STM32_SPI5_CRCPR (STM32_SPI5_BASE + STM32_SPI_CRCPR_OFFSET)
# define STM32_SPI5_RXCRCR (STM32_SPI5_BASE + STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI5_TXCRCR (STM32_SPI5_BASE + STM32_SPI_TXCRCR_OFFSET)
# define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE + STM32_SPI_I2SCFGR_OFFSET)
# define STM32_SPI5_I2SPR (STM32_SPI5_BASE + STM32_SPI_I2SPR_OFFSET)
#endif
#if STM32F0_NSPI > 5
# define STM32F0_SPI6_CR1 (STM32F0_SPI6_BASE+STM32F0_SPI_CR1_OFFSET)
# define STM32F0_SPI6_CR2 (STM32F0_SPI6_BASE+STM32F0_SPI_CR2_OFFSET)
# define STM32F0_SPI6_SR (STM32F0_SPI6_BASE+STM32F0_SPI_SR_OFFSET)
# define STM32F0_SPI6_DR (STM32F0_SPI6_BASE+STM32F0_SPI_DR_OFFSET)
# define STM32F0_SPI6_CRCPR (STM32F0_SPI6_BASE+STM32F0_SPI_CRCPR_OFFSET)
# define STM32F0_SPI6_RXCRCR (STM32F0_SPI6_BASE+STM32F0_SPI_RXCRCR_OFFSET)
# define STM32F0_SPI6_TXCRCR (STM32F0_SPI6_BASE+STM32F0_SPI_TXCRCR_OFFSET)
# define STM32F0_SPI6_I2SCFGR (STM32F0_SPI6_BASE+STM32F0_SPI_I2SCFGR_OFFSET)
# define STM32F0_SPI6_I2SPR (STM32F0_SPI6_BASE+STM32F0_SPI_I2SPR_OFFSET)
#if STM32_NSPI > 5
# define STM32_SPI6_CR1 (STM32_SPI6_BASE + STM32_SPI_CR1_OFFSET)
# define STM32_SPI6_CR2 (STM32_SPI6_BASE + STM32_SPI_CR2_OFFSET)
# define STM32_SPI6_SR (STM32_SPI6_BASE + STM32_SPI_SR_OFFSET)
# define STM32_SPI6_DR (STM32_SPI6_BASE + STM32_SPI_DR_OFFSET)
# define STM32_SPI6_CRCPR (STM32_SPI6_BASE + STM32_SPI_CRCPR_OFFSET)
# define STM32_SPI6_RXCRCR (STM32_SPI6_BASE + STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI6_TXCRCR (STM32_SPI6_BASE + STM32_SPI_TXCRCR_OFFSET)
# define STM32_SPI6_I2SCFGR (STM32_SPI6_BASE + STM32_SPI_I2SCFGR_OFFSET)
# define STM32_SPI6_I2SPR (STM32_SPI6_BASE + STM32_SPI_I2SPR_OFFSET)
#endif
/* Register Bitfield Definitions ****************************************************/
@ -249,4 +249,4 @@
#define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */
#define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_SPI_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SPI_H */

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arch/arm/src/stm32f0l0/hardware/stm32_syscfg.h Normal file
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@ -0,0 +1,391 @@
/****************************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_syscfg.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SYSCFG_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SYSCFG_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* Register Offsets *********************************************************************************/
#define STM32_SYSCFG_CFGR1_OFFSET 0x0000 /* SYSCFG configuration register 1 */
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
#define STM32_SYSCFG_CFGR2_OFFSET 0x0018 /* SYSCFG configuration register 2 */
#define STM32_SYSCFG_ITLINE0_OFFSET 0x0080 /* SYSCFG interrupt line 0 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE1_OFFSET 0x0084 /* SYSCFG interrupt line 1 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE2_OFFSET 0x0088 /* SYSCFG interrupt line 2 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE3_OFFSET 0x008c /* SYSCFG interrupt line 3 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE4_OFFSET 0x0090 /* SYSCFG interrupt line 4 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE5_OFFSET 0x0094 /* SYSCFG interrupt line 5 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE6_OFFSET 0x0098 /* SYSCFG interrupt line 6 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE7_OFFSET 0x009c /* SYSCFG interrupt line 7 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE8_OFFSET 0x00a0 /* SYSCFG interrupt line 8 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE9_OFFSET 0x00a4 /* SYSCFG interrupt line 9 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE10_OFFSET 0x00a8 /* SYSCFG interrupt line 10 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE11_OFFSET 0x00ac /* SYSCFG interrupt line 11 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE12_OFFSET 0x00b0 /* SYSCFG interrupt line 12 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE13_OFFSET 0x00b4 /* SYSCFG interrupt line 13 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE14_OFFSET 0x00b8 /* SYSCFG interrupt line 14 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE15_OFFSET 0x00bc /* SYSCFG interrupt line 15 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE16_OFFSET 0x00c0 /* SYSCFG interrupt line 16 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE17_OFFSET 0x00c4 /* SYSCFG interrupt line 17 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE18_OFFSET 0x00c8 /* SYSCFG interrupt line 18 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE19_OFFSET 0x00cc /* SYSCFG interrupt line 19 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE20_OFFSET 0x00d0 /* SYSCFG interrupt line 20 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE21_OFFSET 0x00d4 /* SYSCFG interrupt line 21 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE22_OFFSET 0x00d8 /* SYSCFG interrupt line 22 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE23_OFFSET 0x00dc /* SYSCFG interrupt line 23 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE24_OFFSET 0x00e0 /* SYSCFG interrupt line 24 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE25_OFFSET 0x00e4 /* SYSCFG interrupt line 25 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE26_OFFSET 0x00e8 /* SYSCFG interrupt line 26 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE27_OFFSET 0x00ec /* SYSCFG interrupt line 27 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE28_OFFSET 0x00f0 /* SYSCFG interrupt line 28 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE29_OFFSET 0x00f4 /* SYSCFG interrupt line 29 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE30_OFFSET 0x00f8 /* SYSCFG interrupt line 30 status register (STM32F09x) */
/* Register Addresses *******************************************************************************/
#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET)
#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR_OFFSET(p))
#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR1_OFFSET)
#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR2_OFFSET)
#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR3_OFFSET)
#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR4_OFFSET)
#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR2_OFFSET)
#define STM32_SYSCFG_ITLINE0 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE0_OFFSET)
#define STM32_SYSCFG_ITLINE1 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE1_OFFSET)
#define STM32_SYSCFG_ITLINE2 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE2_OFFSET)
#define STM32_SYSCFG_ITLINE3 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE3_OFFSET)
#define STM32_SYSCFG_ITLINE4 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE4_OFFSET)
#define STM32_SYSCFG_ITLINE5 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE5_OFFSET)
#define STM32_SYSCFG_ITLINE6 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE6_OFFSET)
#define STM32_SYSCFG_ITLINE7 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE7_OFFSET)
#define STM32_SYSCFG_ITLINE8 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE8_OFFSET)
#define STM32_SYSCFG_ITLINE9 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE9_OFFSET)
#define STM32_SYSCFG_ITLINE10 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE10_OFFSET)
#define STM32_SYSCFG_ITLINE11 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE11_OFFSET)
#define STM32_SYSCFG_ITLINE12 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE12_OFFSET)
#define STM32_SYSCFG_ITLINE13 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE13_OFFSET)
#define STM32_SYSCFG_ITLINE14 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE14_OFFSET)
#define STM32_SYSCFG_ITLINE15 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE15_OFFSET)
#define STM32_SYSCFG_ITLINE16 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE16_OFFSET)
#define STM32_SYSCFG_ITLINE17 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE17_OFFSET)
#define STM32_SYSCFG_ITLINE18 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE18_OFFSET)
#define STM32_SYSCFG_ITLINE19 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE19_OFFSET)
#define STM32_SYSCFG_ITLINE20 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE20_OFFSET)
#define STM32_SYSCFG_ITLINE21 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE21_OFFSET)
#define STM32_SYSCFG_ITLINE22 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE22_OFFSET)
#define STM32_SYSCFG_ITLINE23 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE23_OFFSET)
#define STM32_SYSCFG_ITLINE24 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE24_OFFSET)
#define STM32_SYSCFG_ITLINE25 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE25_OFFSET)
#define STM32_SYSCFG_ITLINE26 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE26_OFFSET)
#define STM32_SYSCFG_ITLINE27 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE27_OFFSET)
#define STM32_SYSCFG_ITLINE28 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE28_OFFSET)
#define STM32_SYSCFG_ITLINE29 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE29_OFFSET)
#define STM32_SYSCFG_ITLINE30 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE30_OFFSET)
/* Register Bitfield Definitions ********************************************************************/
/* SYSCFG memory remap register */
#define SYSCFG_CFGR1_MEMMODE_SHIFT (0) /* Bits 1:0 MEM_MODE: Memory mapping selection */
#define SYSCFG_CFGR1_MEMMODE_MASK (3 << SYSCFG_CFGR1_MEMMODE_SHIFT)
# define SYSCFG_CFGR1_MEMMODE_FLASH (0 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 00: Main Flash at 0x00000000 */
# define SYSCFG_CFGR1_MEMMODE_SYSTEM (1 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 01: System Flash at 0x00000000 */
# define SYSCFG_CFGR1_MEMMODE_SRAM (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 11: Embedded SRAM at 0x00000000 */
#define SYSCFG_CFGR1_PA11_PA12_RMP (1 << 4) /* Bit 4: PA11 and PA12 remapping bit for small packages */
#define SYSCFG_CFGR1_IRMOD_SHIFT (6) /* Bits 6-7: IR Modulation Envelope signal selection */
#define SYSCFG_CFGR1_IRMOD_MASK (3 << SYSCFG_CFGR1_IRMOD_SHIFT)
# define SYSCFG_CFGR1_IRMOD_TIM16 (0 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 00: TIM16 selected */
# define SYSCFG_CFGR1_IRMOD_USART1 (1 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 01: USART1 selected */
# define SYSCFG_CFGR1_IRMOD_USART4 (2 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 10: USART1 selected */
#define SYSCFG_CFGR1_ADC_DMARMP (1 << 8) /* Bit 8: ADC DMA remapping bit. Only STM32F03x/F04x/F05x/F07x */
#define SYSCFG_CFGR1_USART1_TXDMARMP (1 << 9) /* Bit 9: USART1_TX_DMA request remapping bit. Only STM32F03x/F04x/F05x/F07x */
#define SYSCFG_CFGR1_USART1_RXDMARMP (1 << 10) /* Bit 10: USART1_TX_DMA request remapping bit. Only STM32F03x/F04x/F05x/F07x */
#define SYSCFG_CFGR1_TIM16_DMARMP (1 << 11) /* Bit 11: TIM16 DMA request remapping bit */
#define SYSCFG_CFGR1_TIM17_DMARMP (1 << 12) /* Bit 12: TIM17 DMA request remapping bit */
#define SYSCFG_CFGR1_TIM16_DMARMP2 (1 << 13) /* Bit 13: TIM16 alternate DMA request remapping bit */
#define SYSCFG_CFGR1_TIM17_DMARMP2 (1 << 14) /* Bit 14: TIM17 alternate DMA request remapping bit */
#define SYSCFG_CFGR1_I2C_PBXFMP_SHIFT (16) /* Bits 16-19: Fast Mode Plus (FM+) driving capability */
#define SYSCFG_CFGR1_I2C_PBXFMP_MASK (15 << SYSCFG_CFGR1_I2C_PBXFMP_SHIFT)
#define SYSCFG_CFGR1_I2C1_FMP (1 << 20) /* Bit 20: I2C1 fast mode Plus driving capability */
#define SYSCFG_CFGR1_I2C2_FMP (1 << 21) /* Bit 21: I2C2 fast mode Plus driving capability */
#define SYSCFG_CFGR1_I2C_PAXFMP_SHIFT (22) /* Bits 22-23: Fast Mode Plus (FM+) driving capability */
#define SYSCFG_CFGR1_I2C_PAXFMP_MASK (3 << SYSCFG_CFGR1_I2C_PAXFMP_SHIFT)
#define SYSCFG_CFGR1_SPI2_DMARMP (1 << 24) /* Bit 24: SPI2 DMA request remapping bit. */
#define SYSCFG_CFGR1_USART2_DMARMP (1 << 25) /* Bit 25: USART2 DMA request remapping bit. */
#define SYSCFG_CFGR1_USART3_DMARMP (1 << 26) /* Bit 26: USART3 DMA request remapping bit. */
#define SYSCFG_CFGR1_I2C1_DMARMP (1 << 27) /* Bit 27: I2C1 DMA request remapping bit. */
#define SYSCFG_CFGR1_TIM1_DMARMP (1 << 28) /* Bit 28: TIM1 DMA request remapping bit. */
#define SYSCFG_CFGR1_TIM2_DMARMP (1 << 29) /* Bit 29: TIM2 DMA request remapping bit. */
#define SYSCFG_CFGR1_TIM3_DMARMP (1 << 30) /* Bit 30: TIM3 DMA request remapping bit. */
/* SYSCFG external interrupt configuration register 1-4 */
#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */
#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */
#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */
#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[x] pin */
#define SYSCFG_EXTICR_PORT_MASK (15)
#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 coinfiguration */
#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 coinfiguration */
#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 coinfiguration */
#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 coinfiguration */
#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 coinfiguration */
#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 coinfiguration */
#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 coinfiguration */
#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 coinfiguration */
#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 coinfiguration */
#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 coinfiguration */
#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 coinfiguration */
#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 coinfiguration */
#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 coinfiguration */
#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 coinfiguration */
#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 coinfiguration */
#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 coinfiguration */
#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
/* SYSCFG configuration register 2 */
#define SYSCFG_CFGR2_LOCKUPLOCK (1 << 0) /* Bit 0: Cortex-M0 Hardfault output bit enable */
#define SYSCFG_CFGR2_SRAM_PARITYLOCK (1 << 1) /* Bit 1: RAM parity lock */
#define SYSCFG_CFGR2_PVDLOCK (1 << 2) /* Bit 2: PVD lock enable */
#define SYSCFG_CFGR2_SRAM_PEF (1 << 8) /* Bit 8: SRAM parity error */
/* SYSCFG interrupt line 0 status register */
#define SYSCFG_ITLINE0_WWDG (1 << 0) /* Bit 0: Window Watchdog interrupt pending flag */
/* SYSCFG interrupt line 1 status register */
#define SYSCFG_ITLINE1_PVDOUT (1 << 0) /* Bit 0: PVD supply monitoring interrupt request pending (EXTI line 16) */
#define SYSCFG_ITLINE1_VDDIO2 (1 << 0) /* Bit 1: VDDIO2 supply monitoring interrupt request pending (EXTI line 31) */
/* SYSCFG interrupt line 2 status register */
#define SYSCFG_ITLINE2_RTC_WAKEUP (1 << 0) /* Bit 0: RTC Wake Up interrupt request pending (EXTI line 20) */
#define SYSCFG_ITLINE2_RTC_TSTAMP (1 << 1) /* Bit 1: RTC Tamper and TimeStamp interrupt request pending (EXTI line 19) */
#define SYSCFG_ITLINE2_RTC_ALRA (1 << 2) /* Bit 2: RTC Alarm interrupt request pending (EXTI line 17) */
/* SYSCFG interrupt line 3 status register */
#define SYSCFG_ITLINE3_FLASH_ITF (1 << 0) /* Bit 0: Flash interface interrupt request pending */
/* SYSCFG interrupt line 4 status register */
#define SYSCFG_ITLINE4_RCC (1 << 0) /* Bit 0: Reset and clock control interrupt request pending */
#define SYSCFG_ITLINE4_CRS (1 << 1) /* Bit 1: Clock recovery system interrupt request pending */
/* SYSCFG interrupt line 5 status register */
#define SYSCFG_ITLINE5_EXTI0 (1 << 0) /* Bit 0: EXTI line 0 interrupt request pending */
#define SYSCFG_ITLINE5_EXTI1 (1 << 1) /* Bit 1: EXTI line 1 interrupt request pending */
/* SYSCFG interrupt line 6 status register */
#define SYSCFG_ITLINE6_EXTI2 (1 << 0) /* Bit 0: EXTI line 2 interrupt request pending */
#define SYSCFG_ITLINE6_EXTI3 (1 << 1) /* Bit 1: EXTI line 3 interrupt request pending */
/* SYSCFG interrupt line 7 status register */
#define SYSCFG_ITLINE7_EXTI4 (1 << 0) /* Bit 0: EXTI line 4 interrupt request pending */
#define SYSCFG_ITLINE7_EXTI5 (1 << 1) /* Bit 1: EXTI line 5 interrupt request pending */
#define SYSCFG_ITLINE7_EXTI6 (1 << 2) /* Bit 2: EXTI line 6 interrupt request pending */
#define SYSCFG_ITLINE7_EXTI7 (1 << 3) /* Bit 3: EXTI line 7 interrupt request pending */
#define SYSCFG_ITLINE7_EXTI8 (1 << 4) /* Bit 4: EXTI line 8 interrupt request pending */
#define SYSCFG_ITLINE7_EXTI9 (1 << 5) /* Bit 5: EXTI line 9 interrupt request pending */
#define SYSCFG_ITLINE7_EXTI10 (1 << 6) /* Bit 6: EXTI line 10 interrupt request pending */
#define SYSCFG_ITLINE7_EXTI11 (1 << 7) /* Bit 7: EXTI line 11 interrupt request pending */
#define SYSCFG_ITLINE7_EXTI12 (1 << 8) /* Bit 8: EXTI line 12 interrupt request pending */
#define SYSCFG_ITLINE7_EXTI13 (1 << 9) /* Bit 9: EXTI line 13 interrupt request pending */
#define SYSCFG_ITLINE7_EXTI14 (1 << 10) /* Bit 10: EXTI line 14 interrupt request pending */
#define SYSCFG_ITLINE7_EXTI15 (1 << 11) /* Bit 11: EXTI line 15 interrupt request pending */
/* SYSCFG interrupt line 8 status register */
#define SYSCFG_ITLINE8_TCS_MCE (1 << 0) /* Bit 0: Touch sensing controller max count error interrupt request pending */
#define SYSCFG_ITLINE8_TCS_EOA (1 << 1) /* Bit 1: Touch sensing controller end of acquisition interrupt request pending */
/* SYSCFG interrupt line 9 status register */
#define SYSCFG_ITLINE9_DMA1_CH1 (1 << 0) /* Bit 0: DMA1 channel 1 interrupt request pending */
/* SYSCFG interrupt line 10 status register */
#define SYSCFG_ITLINE10_DMA1_CH2 (1 << 0) /* Bit 0: DMA1 channel 2 interrupt request pending */
#define SYSCFG_ITLINE10_DMA1_CH3 (1 << 1) /* Bit 1: DMA1 channel 3 interrupt request pending */
#define SYSCFG_ITLINE10_DMA2_CH1 (1 << 2) /* Bit 0: DMA2 channel 1 interrupt request pending */
#define SYSCFG_ITLINE10_DMA2_CH2 (1 << 3) /* Bit 1: DMA2 channel 2 interrupt request pending */
/* SYSCFG interrupt line 11 status register */
#define SYSCFG_ITLINE11_DMA1_CH4 (1 << 0) /* Bit 0: DMA1 channel 4 interrupt request pending */
#define SYSCFG_ITLINE11_DMA1_CH5 (1 << 1) /* Bit 1: DMA1 channel 5 interrupt request pending */
#define SYSCFG_ITLINE11_DMA1_CH6 (1 << 2) /* Bit 2: DMA1 channel 6 interrupt request pending */
#define SYSCFG_ITLINE11_DMA1_CH7 (1 << 3) /* Bit 3: DMA1 channel 7 interrupt request pending */
#define SYSCFG_ITLINE11_DMA2_CH3 (1 << 4) /* Bit 4: DMA2 channel 3 interrupt request pending */
#define SYSCFG_ITLINE11_DMA2_CH4 (1 << 5) /* Bit 5: DMA2 channel 4 interrupt request pending */
#define SYSCFG_ITLINE11_DMA2_CH5 (1 << 6) /* Bit 6: DMA2 channel 5 interrupt request pending */
/* SYSCFG interrupt line 12 status register */
#define SYSCFG_ITLINE12_ADC (1 << 0) /* Bit 0: ADC interrupt request pending */
#define SYSCFG_ITLINE12_COMP1 (1 << 1) /* Bit 1: Comparator 1 interrupt request pending */
#define SYSCFG_ITLINE12_COMP2 (1 << 2) /* Bit 2: Comparator 2 interrupt request pending */
/* SYSCFG interrupt line 13 status register */
#define SYSCFG_ITLINE13_TIM1_CCU (1 << 0) /* Bit 0: TIM1 commutation interrupt request pending */
#define SYSCFG_ITLINE13_TIM1_TRG (1 << 1) /* Bit 1: TIM1 triggerinterrupt request pending */
#define SYSCFG_ITLINE13_TIM1_UPD (1 << 2) /* Bit 2: TIM1 update interrupt request pending */
#define SYSCFG_ITLINE13_TIM1_BRK (1 << 3) /* Bit 3: TIM1 break interrupt request pending */
/* SYSCFG interrupt line 14 status register */
#define SYSCFG_ITLINE14_TIM1_CC (1 << 0) /* Bit 0: TIM1 capture compare interrupt request pending */
/* SYSCFG interrupt line 15 status register */
#define SYSCFG_ITLINE15_TIM2 (1 << 0) /* Bit 0: Timer 2 interrupt request pending */
/* SYSCFG interrupt line 16 status register */
#define SYSCFG_ITLINE16_TIM3 (1 << 0) /* Bit 0: Timer 3 interrupt request pending */
/* SYSCFG interrupt line 17 status register */
#define SYSCFG_ITLINE17_TIM6 (1 << 0) /* Bit 0: Timer 6 interrupt request pending */
#define SYSCFG_ITLINE17_DAC (1 << 1) /* Bit 1: DAC underrun interrupt request pending */
/* SYSCFG interrupt line 18 status register */
#define SYSCFG_ITLINE18_TIM7 (1 << 0) /* Bit 0: Timer 7 interrupt request pending */
/* SYSCFG interrupt line 19 status register */
#define SYSCFG_ITLINE19_TIM14 (1 << 0) /* Bit 0: Timer 14 interrupt request pending */
/* SYSCFG interrupt line 20 status register */
#define SYSCFG_ITLINE20_TIM15 (1 << 0) /* Bit 0: Timer 15 interrupt request pending */
/* SYSCFG interrupt line 21 status register */
#define SYSCFG_ITLINE21_TIM16 (1 << 0) /* Bit 0: Timer 16 interrupt request pending */
/* SYSCFG interrupt line 22 status register */
#define SYSCFG_ITLINE22_TIM17 (1 << 0) /* Bit 0: Timer 17 interrupt request pending */
/* SYSCFG interrupt line 23 status register */
#define SYSCFG_ITLINE23_I2C1 (1 << 0) /* Bit 0: I2C1 interrupt request pending, combined with EXTI line 23 */
/* SYSCFG interrupt line 24 status register */
#define SYSCFG_ITLINE24_I2C2 (1 << 0) /* Bit 0: I2C2 interrupt request pending */
/* SYSCFG interrupt line 25 status register */
#define SYSCFG_ITLINE25_SPI1 (1 << 0) /* Bit 0: SPI1 interrupt request pending */
/* SYSCFG interrupt line 26 status register */
#define SYSCFG_ITLINE26_SPI2 (1 << 0) /* Bit 0: SPI2 interrupt request pending */
/* SYSCFG interrupt line 27 status register */
#define SYSCFG_ITLINE27_USART1 (1 << 0) /* Bit 0: USART1 interrupt request pending */
/* SYSCFG interrupt line 28 status register */
#define SYSCFG_ITLINE28_USART2 (1 << 0) /* Bit 0: USART2 interrupt request pending */
/* SYSCFG interrupt line 29 status register */
#define SYSCFG_ITLINE29_USART3 (1 << 0) /* Bit 0: USART3 interrupt request pending */
#define SYSCFG_ITLINE29_USART4 (1 << 1) /* Bit 1: USART4 interrupt request pending */
#define SYSCFG_ITLINE29_USART5 (1 << 2) /* Bit 2: USART5 interrupt request pending */
#define SYSCFG_ITLINE29_USART6 (1 << 3) /* Bit 3: USART6 interrupt request pending */
#define SYSCFG_ITLINE29_USART7 (1 << 4) /* Bit 4: USART7 interrupt request pending */
#define SYSCFG_ITLINE29_USART8 (1 << 5) /* Bit 5: USART8 interrupt request pending */
/* SYSCFG interrupt line 30 status register */
#define SYSCFG_ITLINE30_CEC (1 << 0) /* Bit 0: CEC interrupt request pending, combined with EXTI line 27 */
#define SYSCFG_ITLINE30_CAN (1 << 1) /* Bit 1: CAN interrupt request pending */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SYSCFG_H */

8
arch/arm/src/stm32f0/chip/stm32f0_tim.h → arch/arm/src/stm32f0l0/hardware/stm32_tim.h
View file

@ -1,5 +1,5 @@
/****************************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f0_tim.h
* arch/arm/src/stm32f0l0/hardware/stm32_tim.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_TIM_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_TIM_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_TIM_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_TIM_H
/****************************************************************************************************
* Pre-processor Definitions
@ -49,4 +49,4 @@
/* Register Bitfield Definitions ********************************************************************/
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_TIM_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_TIM_H */

150
arch/arm/src/stm32f0/chip/stm32f0_uart.h → arch/arm/src/stm32f0l0/hardware/stm32_uart.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f0_uart.h
* arch/arm/src/stm32f0l0/hardware/stm32_uart.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_UART_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_UART_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_UART_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_UART_H
/************************************************************************************
* Included Files
@ -51,88 +51,88 @@
/* Register Offsets *****************************************************************/
#define STM32F0_USART_CR1_OFFSET 0x0000 /* Control register 1 */
#define STM32F0_USART_CR2_OFFSET 0x0004 /* Control register 2 */
#define STM32F0_USART_CR3_OFFSET 0x0008 /* Control register 3 */
#define STM32F0_USART_BRR_OFFSET 0x000c /* Baud Rate register */
#define STM32F0_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */
#define STM32F0_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */
#define STM32F0_USART_RQR_OFFSET 0x0018 /* Request register */
#define STM32F0_USART_ISR_OFFSET 0x001c /* Interrupot and status register */
#define STM32F0_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */
#define STM32F0_USART_RDR_OFFSET 0x0024 /* Receive Data register */
#define STM32F0_USART_TDR_OFFSET 0x0028 /* Transmit Data register */
#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */
#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */
#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */
#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */
#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */
#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */
#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */
#define STM32_USART_ISR_OFFSET 0x001c /* Interrupot and status register */
#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */
#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */
#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */
/* Register Addresses ***************************************************************/
#if STM32F0_NUSART > 0
# define STM32F0_USART1_CR1 (STM32F0_USART1_BASE+STM32F0_USART_CR1_OFFSET)
# define STM32F0_USART1_CR2 (STM32F0_USART1_BASE+STM32F0_USART_CR2_OFFSET)
# define STM32F0_USART1_CR3 (STM32F0_USART1_BASE+STM32F0_USART_CR3_OFFSET)
# define STM32F0_USART1_BRR (STM32F0_USART1_BASE+STM32F0_USART_BRR_OFFSET)
# define STM32F0_USART1_GTPR (STM32F0_USART1_BASE+STM32F0_USART_GTPR_OFFSET)
# define STM32F0_USART1_RTOR (STM32F0_USART1_BASE+STM32F0_USART_RTOR_OFFSET)
# define STM32F0_USART1_RQR (STM32F0_USART1_BASE+STM32F0_USART_RQR_OFFSET)
# define STM32F0_USART1_ISR (STM32F0_USART1_BASE+STM32F0_USART_ISR_OFFSET)
# define STM32F0_USART1_ICR (STM32F0_USART1_BASE+STM32F0_USART_ICR_OFFSET)
# define STM32F0_USART1_RDR (STM32F0_USART1_BASE+STM32F0_USART_RDR_OFFSET)
# define STM32F0_USART1_TDR (STM32F0_USART1_BASE+STM32F0_USART_TDR_OFFSET)
#if STM32_NUSART > 0
# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET)
#endif
#if STM32F0_NUSART > 1
# define STM32F0_USART2_CR1 (STM32F0_USART2_BASE+STM32F0_USART_CR1_OFFSET)
# define STM32F0_USART2_CR2 (STM32F0_USART2_BASE+STM32F0_USART_CR2_OFFSET)
# define STM32F0_USART2_CR3 (STM32F0_USART2_BASE+STM32F0_USART_CR3_OFFSET)
# define STM32F0_USART2_BRR (STM32F0_USART2_BASE+STM32F0_USART_BRR_OFFSET)
# define STM32F0_USART2_GTPR (STM32F0_USART2_BASE+STM32F0_USART_GTPR_OFFSET)
# define STM32F0_USART2_RTOR (STM32F0_USART2_BASE+STM32F0_USART_RTOR_OFFSET)
# define STM32F0_USART2_RQR (STM32F0_USART2_BASE+STM32F0_USART_RQR_OFFSET)
# define STM32F0_USART2_ISR (STM32F0_USART2_BASE+STM32F0_USART_ISR_OFFSET)
# define STM32F0_USART2_ICR (STM32F0_USART2_BASE+STM32F0_USART_ICR_OFFSET)
# define STM32F0_USART2_RDR (STM32F0_USART2_BASE+STM32F0_USART_RDR_OFFSET)
# define STM32F0_USART2_TDR (STM32F0_USART2_BASE+STM32F0_USART_TDR_OFFSET)
#if STM32_NUSART > 1
# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET)
#endif
#if STM32F0_NUSART > 2
# define STM32F0_USART3_CR1 (STM32F0_USART3_BASE+STM32F0_USART_CR1_OFFSET)
# define STM32F0_USART3_CR2 (STM32F0_USART3_BASE+STM32F0_USART_CR2_OFFSET)
# define STM32F0_USART3_CR3 (STM32F0_USART3_BASE+STM32F0_USART_CR3_OFFSET)
# define STM32F0_USART3_BRR (STM32F0_USART3_BASE+STM32F0_USART_BRR_OFFSET)
# define STM32F0_USART3_GTPR (STM32F0_USART3_BASE+STM32F0_USART_GTPR_OFFSET)
# define STM32F0_USART3_RTOR (STM32F0_USART3_BASE+STM32F0_USART_RTOR_OFFSET)
# define STM32F0_USART3_RQR (STM32F0_USART3_BASE+STM32F0_USART_RQR_OFFSET)
# define STM32F0_USART3_ISR (STM32F0_USART3_BASE+STM32F0_USART_ISR_OFFSET)
# define STM32F0_USART3_ICR (STM32F0_USART3_BASE+STM32F0_USART_ICR_OFFSET)
# define STM32F0_USART3_RDR (STM32F0_USART3_BASE+STM32F0_USART_RDR_OFFSET)
# define STM32F0_USART3_TDR (STM32F0_USART3_BASE+STM32F0_USART_TDR_OFFSET)
#if STM32_NUSART > 2
# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET)
#endif
#if STM32F0_NUSART > 3
# define STM32F0_USART4_CR1 (STM32F0_USART4_BASE+STM32F0_USART_CR1_OFFSET)
# define STM32F0_USART4_CR2 (STM32F0_USART4_BASE+STM32F0_USART_CR2_OFFSET)
# define STM32F0_USART4_CR3 (STM32F0_USART4_BASE+STM32F0_USART_CR3_OFFSET)
# define STM32F0_USART4_BRR (STM32F0_USART4_BASE+STM32F0_USART_BRR_OFFSET)
# define STM32F0_USART4_GTPR (STM32F0_USART4_BASE+STM32F0_USART_GTPR_OFFSET)
# define STM32F0_USART4_RTOR (STM32F0_USART4_BASE+STM32F0_USART_RTOR_OFFSET)
# define STM32F0_USART4_RQR (STM32F0_USART4_BASE+STM32F0_USART_RQR_OFFSET)
# define STM32F0_USART4_ISR (STM32F0_USART4_BASE+STM32F0_USART_ISR_OFFSET)
# define STM32F0_USART4_ICR (STM32F0_USART4_BASE+STM32F0_USART_ICR_OFFSET)
# define STM32F0_USART4_RDR (STM32F0_USART4_BASE+STM32F0_USART_RDR_OFFSET)
# define STM32F0_USART4_TDR (STM32F0_USART4_BASE+STM32F0_USART_TDR_OFFSET)
#if STM32_NUSART > 3
# define STM32_USART4_CR1 (STM32_USART4_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART4_CR2 (STM32_USART4_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART4_CR3 (STM32_USART4_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART4_BRR (STM32_USART4_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART4_GTPR (STM32_USART4_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART4_RTOR (STM32_USART4_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART4_RQR (STM32_USART4_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART4_ISR (STM32_USART4_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART4_ICR (STM32_USART4_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART4_RDR (STM32_USART4_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART4_TDR (STM32_USART4_BASE + STM32_USART_TDR_OFFSET)
#endif
#if STM32F0_NUSART > 4
# define STM32F0_USART5_CR1 (STM32F0_USART5_BASE+STM32F0_USART_CR1_OFFSET)
# define STM32F0_USART5_CR2 (STM32F0_USART5_BASE+STM32F0_USART_CR2_OFFSET)
# define STM32F0_USART5_CR3 (STM32F0_USART5_BASE+STM32F0_USART_CR3_OFFSET)
# define STM32F0_USART5_BRR (STM32F0_USART5_BASE+STM32F0_USART_BRR_OFFSET)
# define STM32F0_USART5_GTPR (STM32F0_USART5_BASE+STM32F0_USART_GTPR_OFFSET)
# define STM32F0_USART5_RTOR (STM32F0_USART5_BASE+STM32F0_USART_RTOR_OFFSET)
# define STM32F0_USART5_RQR (STM32F0_USART5_BASE+STM32F0_USART_RQR_OFFSET)
# define STM32F0_USART5_ISR (STM32F0_USART5_BASE+STM32F0_USART_ISR_OFFSET)
# define STM32F0_USART5_ICR (STM32F0_USART5_BASE+STM32F0_USART_ICR_OFFSET)
# define STM32F0_USART5_RDR (STM32F0_USART5_BASE+STM32F0_USART_RDR_OFFSET)
# define STM32F0_USART5_TDR (STM32F0_USART5_BASE+STM32F0_USART_TDR_OFFSET)
#if STM32_NUSART > 4
# define STM32_USART5_CR1 (STM32_USART5_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART5_CR2 (STM32_USART5_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART5_CR3 (STM32_USART5_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART5_BRR (STM32_USART5_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART5_GTPR (STM32_USART5_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART5_RTOR (STM32_USART5_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART5_RQR (STM32_USART5_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART5_ISR (STM32_USART5_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART5_ICR (STM32_USART5_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART5_RDR (STM32_USART5_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART5_TDR (STM32_USART5_BASE + STM32_USART_TDR_OFFSET)
#endif
/* Register Bitfield Definitions ****************************************************/
@ -313,4 +313,4 @@
#define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */
#define USART_TDR_MASK (0xff << USART_TDR_SHIFT)
#endif /* __ARCH_ARM_STC_STM32F0_CHIP_STM32F0_UART_H */
#endif /* __ARCH_ARM_STC_STM32F0L0_CHIP_STM32_UART_H */

106
arch/arm/src/stm32f0/chip/stm32f0_usbdev.h → arch/arm/src/stm32f0l0/hardware/stm32_usbdev.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f0_usbdev.h
* arch/arm/src/stm32f0l0/hardware/stm32_usbdev.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_USBDEV_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_USBDEV_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_USBDEV_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_USBDEV_H
/************************************************************************************
* Included Files
@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include <chip.h>
#ifdef CONFIG_STM32F0_HAVE_USBDEV
#ifdef CONFIG_STM32F0L0_HAVE_USBDEV
/************************************************************************************
* Pre-processor Definitions
@ -53,70 +53,70 @@
/* Endpoint Registers */
#define STM32F0_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */
#define STM32F0_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */
#define STM32F0_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */
#define STM32F0_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */
#define STM32F0_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */
#define STM32F0_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */
#define STM32F0_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */
#define STM32F0_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */
#define STM32F0_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */
#define STM32_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */
#define STM32_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */
#define STM32_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */
#define STM32_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */
#define STM32_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */
#define STM32_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */
#define STM32_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */
#define STM32_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */
#define STM32_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */
/* Common Registers */
#define STM32F0_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */
#define STM32F0_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */
#define STM32F0_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */
#define STM32F0_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */
#define STM32F0_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */
#define STM32F0_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register (16-bits) */
#define STM32F0_USB_BCDR_OFFSET 0x0058 /* Battery charging detector (16-bits) */
#define STM32_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */
#define STM32_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */
#define STM32_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */
#define STM32_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */
#define STM32_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */
#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register (16-bits) */
#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector (16-bits) */
/* Buffer Descriptor Table (Relatative to BTABLE address) */
#define STM32F0_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */
#define STM32F0_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */
#define STM32F0_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */
#define STM32F0_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */
#define STM32_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */
#define STM32_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */
#define STM32_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */
#define STM32_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */
#define STM32F0_USB_BTABLE_RADDR(ep,o) ((((uint32_t)getreg16(STM32F0_USB_BTABLE) + ((ep) << 3)) + (o)) << 1)
#define STM32F0_USB_ADDR_TX_OFFSET(ep) STM32F0_USB_BTABLE_RADDR(ep,STM32F0_USB_ADDR_TX_WOFFSET)
#define STM32F0_USB_COUNT_TX_OFFSET(ep) STM32F0_USB_BTABLE_RADDR(ep,STM32F0_USB_COUNT_TX_WOFFSET)
#define STM32F0_USB_ADDR_RX_OFFSET(ep) STM32F0_USB_BTABLE_RADDR(ep,STM32F0_USB_ADDR_RX_WOFFSET)
#define STM32F0_USB_COUNT_RX_OFFSET(ep) STM32F0_USB_BTABLE_RADDR(ep,STM32F0_USB_COUNT_RX_WOFFSET)
#define STM32_USB_BTABLE_RADDR(ep,o) ((((uint32_t)getreg16(STM32_USB_BTABLE) + ((ep) << 3)) + (o)) << 1)
#define STM32_USB_ADDR_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_TX_WOFFSET)
#define STM32_USB_COUNT_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_TX_WOFFSET)
#define STM32_USB_ADDR_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_RX_WOFFSET)
#define STM32_USB_COUNT_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_RX_WOFFSET)
/* Register Addresses ***************************************************************/
/* Endpoint Registers */
#define STM32F0_USB_EPR(n) (STM32F0_USB_BASE+STM32F0_USB_EPR_OFFSET(n))
#define STM32F0_USB_EP0R (STM32F0_USB_BASE+STM32F0_USB_EP0R_OFFSET)
#define STM32F0_USB_EP1R (STM32F0_USB_BASE+STM32F0_USB_EP1R_OFFSET)
#define STM32F0_USB_EP2R (STM32F0_USB_BASE+STM32F0_USB_EP2R_OFFSET)
#define STM32F0_USB_EP3R (STM32F0_USB_BASE+STM32F0_USB_EP3R_OFFSET)
#define STM32F0_USB_EP4R (STM32F0_USB_BASE+STM32F0_USB_EP4R_OFFSET)
#define STM32F0_USB_EP5R (STM32F0_USB_BASE+STM32F0_USB_EP5R_OFFSET)
#define STM32F0_USB_EP6R (STM32F0_USB_BASE+STM32F0_USB_EP6R_OFFSET)
#define STM32F0_USB_EP7R (STM32F0_USB_BASE+STM32F0_USB_EP7R_OFFSET)
#define STM32_USB_EPR(n) (STM32_USB_BASE + STM32_USB_EPR_OFFSET(n))
#define STM32_USB_EP0R (STM32_USB_BASE + STM32_USB_EP0R_OFFSET)
#define STM32_USB_EP1R (STM32_USB_BASE + STM32_USB_EP1R_OFFSET)
#define STM32_USB_EP2R (STM32_USB_BASE + STM32_USB_EP2R_OFFSET)
#define STM32_USB_EP3R (STM32_USB_BASE + STM32_USB_EP3R_OFFSET)
#define STM32_USB_EP4R (STM32_USB_BASE + STM32_USB_EP4R_OFFSET)
#define STM32_USB_EP5R (STM32_USB_BASE + STM32_USB_EP5R_OFFSET)
#define STM32_USB_EP6R (STM32_USB_BASE + STM32_USB_EP6R_OFFSET)
#define STM32_USB_EP7R (STM32_USB_BASE + STM32_USB_EP7R_OFFSET)
/* Common Registers */
#define STM32F0_USB_CNTR (STM32F0_USB_BASE+STM32F0_USB_CNTR_OFFSET)
#define STM32F0_USB_ISTR (STM32F0_USB_BASE+STM32F0_USB_ISTR_OFFSET)
#define STM32F0_USB_FNR (STM32F0_USB_BASE+STM32F0_USB_FNR_OFFSET)
#define STM32F0_USB_DADDR (STM32F0_USB_BASE+STM32F0_USB_DADDR_OFFSET)
#define STM32F0_USB_BTABLE (STM32F0_USB_BASE+STM32F0_USB_BTABLE_OFFSET)
#define STM32F0_USB_LPMCSR (STM32F0_USB_BASE+STM32F0_USB_LPMCSR_OFFSET)
#define STM32F0_USB_BCDR (STM32F0_USB_BASE+STM32F0_USB_BCDR_OFFSET)
#define STM32_USB_CNTR (STM32_USB_BASE + STM32_USB_CNTR_OFFSET)
#define STM32_USB_ISTR (STM32_USB_BASE + STM32_USB_ISTR_OFFSET)
#define STM32_USB_FNR (STM32_USB_BASE + STM32_USB_FNR_OFFSET)
#define STM32_USB_DADDR (STM32_USB_BASE + STM32_USB_DADDR_OFFSET)
#define STM32_USB_BTABLE (STM32_USB_BASE + STM32_USB_BTABLE_OFFSET)
#define STM32_USB_LPMCSR (STM32_USB_BASE + STM32_USB_LPMCSR_OFFSET)
#define STM32_USB_BCDR (STM32_USB_BASE + STM32_USB_BCDR_OFFSET)
/* Buffer Descriptor Table (Relatative to BTABLE address) */
/* Buffer Descriptor Table (Relative to BTABLE address) */
#define STM32F0_USB_BTABLE_ADDR(ep,o) (STM32F0_USBRAM_BASE+STM32F0_USB_BTABLE_RADDR(ep,o))
#define STM32F0_USB_ADDR_TX(ep) STM32F0_USB_BTABLE_ADDR(ep,STM32F0_USB_ADDR_TX_WOFFSET)
#define STM32F0_USB_COUNT_TX(ep) STM32F0_USB_BTABLE_ADDR(ep,STM32F0_USB_COUNT_TX_WOFFSET)
#define STM32F0_USB_ADDR_RX(ep) STM32F0_USB_BTABLE_ADDR(ep,STM32F0_USB_ADDR_RX_WOFFSET)
#define STM32F0_USB_COUNT_RX(ep) STM32F0_USB_BTABLE_ADDR(ep,STM32F0_USB_COUNT_RX_WOFFSET)
#define STM32_USB_BTABLE_ADDR(ep,o) (STM32_USBRAM_BASE + STM32_USB_BTABLE_RADDR(ep,o))
#define STM32_USB_ADDR_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_TX_WOFFSET)
#define STM32_USB_COUNT_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_TX_WOFFSET)
#define STM32_USB_ADDR_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_RX_WOFFSET)
#define STM32_USB_COUNT_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_RX_WOFFSET)
/* Register Bitfield Definitions ****************************************************/
@ -260,5 +260,5 @@
#define USB_COUNT_RX_SHIFT (0) /* Bits 9-0: Reception Byte Count */
#define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT)
#endif /* CONFIG_STM32F0_HAVE_USBDEV */
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_USBDEV_H */
#endif /* CONFIG_STM32F0L0_HAVE_USBDEV */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_USBDEV_H */

142
arch/arm/src/stm32f0l0/hardware/stm32_wdt.h Normal file
View file

@ -0,0 +1,142 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32_wdt.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_WDG_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_WDG_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */
#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */
#define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */
#define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */
#define STM32_IWDG_WINR_OFFSET 0x0010 /* Window register (32-bit) */
#define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */
#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */
#define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */
/* Register Addresses ***************************************************************/
#define STM32_IWDG_KR (STM32_IWDG_BASE + STM32_IWDG_KR_OFFSET)
#define STM32_IWDG_PR (STM32_IWDG_BASE + STM32_IWDG_PR_OFFSET)
#define STM32_IWDG_RLR (STM32_IWDG_BASE + STM32_IWDG_RLR_OFFSET)
#define STM32_IWDG_SR (STM32_IWDG_BASE + STM32_IWDG_SR_OFFSET)
#define STM32_IWDG_WINR (STM32_IWDG_BASE + STM32_IWDG_WINR_OFFSET)
#define STM32_WWDG_CR (STM32_WWDG_BASE + STM32_WWDG_CR_OFFSET)
#define STM32_WWDG_CFR (STM32_WWDG_BASE + STM32_WWDG_CFR_OFFSET)
#define STM32_WWDG_SR (STM32_WWDG_BASE + STM32_WWDG_SR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* Key register (32-bit) */
#define IWDG_KR_KEY_SHIFT (0) /* Bits 15-0: Key value (write only, read 0000h) */
#define IWDG_KR_KEY_MASK (0xffff << IWDG_KR_KEY_SHIFT)
#define IWDG_KR_KEY_ENABLE (0x5555) /* Enable register access */
#define IWDG_KR_KEY_DISABLE (0x0000) /* Disable register access */
#define IWDG_KR_KEY_RELOAD (0xaaaa) /* Reload the counter */
#define IWDG_KR_KEY_START (0xcccc) /* Start the watchdog */
/* Prescaler register (32-bit) */
#define IWDG_PR_SHIFT (0) /* Bits 2-0: Prescaler divider */
#define IWDG_PR_MASK (7 << IWDG_PR_SHIFT)
# define IWDG_PR_DIV4 (0 << IWDG_PR_SHIFT) /* 000: divider /4 */
# define IWDG_PR_DIV8 (1 << IWDG_PR_SHIFT) /* 001: divider /8 */
# define IWDG_PR_DIV16 (2 << IWDG_PR_SHIFT) /* 010: divider /16 */
# define IWDG_PR_DIV32 (3 << IWDG_PR_SHIFT) /* 011: divider /32 */
# define IWDG_PR_DIV64 (4 << IWDG_PR_SHIFT) /* 100: divider /64 */
# define IWDG_PR_DIV128 (5 << IWDG_PR_SHIFT) /* 101: divider /128 */
# define IWDG_PR_DIV256 (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */
/* Reload register (32-bit) */
#define IWDG_RLR_RL_SHIFT (0) /* Bits11:0 RL[11:0]: Watchdog counter reload value */
#define IWDG_RLR_RL_MASK (0x0fff << IWDG_RLR_RL_SHIFT)
#define IWDG_RLR_MAX (0xfff)
/* Status register (32-bit) */
#define IWDG_SR_PVU (1 << 0) /* Bit 0: Watchdog prescaler value update */
#define IWDG_SR_RVU (1 << 1) /* Bit 1: Watchdog counter reload value update */
#define IWDG_SR_WVU (1 << 2) /* Bit 2: Watchdog counter window value update */
/* Window register (32-bit) */
#define IWDG_WINR_SHIFT (0)
#define IWDG_WINR_MASK (0x0fff << IWDG_WINR_SHIFT)
/* Control Register (32-bit) */
#define WWDG_CR_T_SHIFT (0) /* Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) */
#define WWDG_CR_T_MASK (0x7f << WWDG_CR_T_SHIFT)
# define WWDG_CR_T_MAX (0x3f << WWDG_CR_T_SHIFT)
# define WWDG_CR_T_RESET (0x40 << WWDG_CR_T_SHIFT)
#define WWDG_CR_WDGA (1 << 7) /* Bit 7: Activation bit */
/* Configuration register (32-bit) */
#define WWDG_CFR_W_SHIFT (0) /* Bits 6:0 W[6:0] 7-bit window value */
#define WWDG_CFR_W_MASK (0x7f << WWDG_CFR_W_SHIFT)
#define WWDG_CFR_WDGTB_SHIFT (7) /* Bits 8:7 [1:0]: Timer Base */
#define WWDG_CFR_WDGTB_MASK (3 << WWDG_CFR_WDGTB_SHIFT)
# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */
# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */
# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */
# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */
#define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */
/* Status register (32-bit) */
#define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_WDG_H */

10
arch/arm/src/stm32f0/chip/stm32f05x_pinmap.h → arch/arm/src/stm32f0l0/hardware/stm32f05x_pinmap.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f05x_pinmap.h
* arch/arm/src/stm32f0l0/hardware/stm32f05x_pinmap.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F05X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F05X_PINMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F05X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F05X_PINMAP_H
/************************************************************************************
* Included Files
@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include "stm32f0_gpio.h"
#include "stm32_gpio.h"
/************************************************************************************
* Pre-processor Definitions
@ -133,4 +133,4 @@
#define GPIO_I2C2_SCL (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN10)
#define GPIO_I2C2_SDA (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN11)
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F05X_PINMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F05X_PINMAP_H */

157
arch/arm/src/stm32f0l0/hardware/stm32f05xf07xf09x_memorymap.h Normal file
View file

@ -0,0 +1,157 @@
/************************************************************************************
* arch/arm/src/stm32f0l0/hardware/stm32f05xf07xf09x_memorymap.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_ST32F05XF07XF09X_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_ST32F05XF07XF09X_MEMORYMAP_H
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* ST32F05XF07X Address Blocks ******************************************************/
#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
/* 0x60000000-0xdfffffff: Reserved */
#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
#define STM32_REGION_MASK 0xf0000000
#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
/* Code Base Addresses **************************************************************/
#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
/* 0x00100000-0x07ffffff: Reserved */
#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */
/* 0x08100000-0x0fffffff: Reserved */
#define STM32_CCMRAM_BASE 0x10000000 /* 0x10000000-0x1000ffff: 64Kb CCM data RAM */
/* 0x10010000-0x1ffeffff: Reserved */
#define STM32_SYSMEM_BASE 0x1fffd800 /* 0x1fff0000-0x1fff7a0f: System memory */
/* 0x1fff7a10-0x1fff7fff: Reserved */
#define STM32_OPTION_BASE 0x1ffff800 /* 0x1fffc000-0x1fffc007: Option bytes */
/* 0x1fffc008-0x1fffffff: Reserved */
/* System Memory Addresses **********************************************************/
#define STM32_SYSMEM_UID 0x1ffff7ac /* The 96-bit unique device identifier */
#define STM32_SYSMEM_FSIZE 0x1ffff7cc /* This bitfield indicates the size of
* the device Flash memory expressed in
* Kbytes. Example: 0x040 corresponds
* to 64 Kbytes
*/
/* Peripheral Base Addresses ********************************************************/
#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40009fff: APB1 */
/* 0x4000a000-0x4000ffff: Reserved */
#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40006bff: APB2 */
/* 0x40016c00-0x4001ffff: Reserved */
#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */
/* 0x40024400-0x4007ffff: Reserved */
#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x480017ff: AHB2 */
/* 0x48001800-0x4fffFfff: Reserved */
#define STM32_AHB3_BASE 0x50000000 /* 0x50000000-0x500007ff: AHB3 */
/* APB1 Base Addresses **************************************************************/
#define STM32_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff TIM2 */
#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff TIM3 */
#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */
#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */
#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff TIM14 */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */
#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff SPI2, or */
#define STM32_I2S2_BASE 0x40003800 /* 0x40003800-0x40003bff I2S2 */
#define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff USART2 */
#define STM32_USART3_BASE 0x40004800 /* 0x40004800-0x40004bff USART3 */
#define STM32_USART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff USART4 */
#define STM32_USART5_BASE 0x40005000 /* 0x40005000-0x400053ff USART5 */
#define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff I2C1 */
#define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff I2C2 */
#define STM32_USB_BASE 0x40005c00 /* 0x40005c00-0x40005fff USB device FS */
#define STM32_USBRAM_BASE 0x40006000 /* 0x40006000-0x400063ff USB SRAM 512B */
#define STM32_CAN_BASE 0x40006400 /* 0x40006400-0x400067ff bxCAN */
#define STM32_CRS_BASE 0x40006c00 /* 0x40006c00-0x40006fff CRS */
#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */
#define STM32_DAC_BASE 0x40007400 /* 0x40007400-0x400077ff DAC */
#define STM32_CEC_BASE 0x40007800 /* 0x40007800-0x40007bff HDMI CEC */
/* APB2 Base Addresses **************************************************************/
#define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103ff SYSCFG + COMP + OPAMP */
#define STM32_EXTI_BASE 0x40010400 /* 0x40010400-0x400107ff EXTI */
#define STM32_USART6_BASE 0x40011400 /* 0x40011400-0x400117ff USART6 */
#define STM32_USART7_BASE 0x40011800 /* 0x40011800-0x40011bff USART7 */
#define STM32_USART8_BASE 0x40011c00 /* 0x40011c00-0x40011fff USART8 */
#define STM32_ADC_BASE 0x40012400 /* 0x40012400-0x400127ff ADC */
#define STM32_TIM1_BASE 0x40012c00 /* 0x40012c00-0x40012fff TIM1 */
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */
#define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */
#define STM32_TIM15_BASE 0x40014000 /* 0x40014000-0x400143ff TIM15 */
#define STM32_TIM16_BASE 0x40014400 /* 0x40014400-0x400147ff TIM16 */
#define STM32_TIM17_BASE 0x40014800 /* 0x40014800-0x40014bff TIM17 */
#define STM32_DBGMCU_BASE 0x40015800 /* 0x40015800-0x40015bff DBGMCU */
/* AHB1 Base Addresses **************************************************************/
#define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */
#define STM32_DMA2_BASE 0x40020400 /* 0x40020400-0x400207ff: DMA2 */
#define STM32_RCC_BASE 0x40021000 /* 0x40021000-0x400213ff: Reset and Clock control RCC */
#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000-0x400223ff: Flash memory interface */
#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */
#define STM32_TSC_BASE 0x40024000 /* 0x40024000-0x400243ff: TSC */
/* AHB2 Base Addresses **************************************************************/
#define STM32_GPIOA_BASE 0x48000000 /* 0x48000000-0x480003ff: GPIO Port A */
#define STM32_GPIOB_BASE 0x48000400 /* 0x48000400-0x480007ff: GPIO Port B */
#define STM32_GPIOC_BASE 0x48000800 /* 0x48000800-0x48000bff: GPIO Port C */
#define STM32_GPIOD_BASE 0X48000C00 /* 0x48000c00-0x48000fff: GPIO Port D */
#define STM32_GPIOE_BASE 0x48001000 /* 0x48001000-0x480013ff: GPIO Port E */
#define STM32_GPIOF_BASE 0x48001400 /* 0x48001400-0x480017ff: GPIO Port F */
/* Cortex-M4 Base Addresses *********************************************************/
/* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in this
* address range
*/
#define STM32_SCS_BASE 0xe000e000
#define STM32_DEBUGMCU_BASE 0xe0042000
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_ST32F05XF07XF09X_MEMORYMAP_H */

10
arch/arm/src/stm32f0/chip/stm32f07x_pinmap.h → arch/arm/src/stm32f0l0/hardware/stm32f07x_pinmap.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f07x_pinmap.h
* arch/arm/src/stm32f0l0/hardware/stm32f07x_pinmap.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F07X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F07X_PINMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F07X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F07X_PINMAP_H
/************************************************************************************
* Included Files
@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include "stm32f0_gpio.h"
#include "stm32_gpio.h"
/************************************************************************************
* Pre-processor Definitions
@ -397,4 +397,4 @@
#define GPIO_USB_NOE (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN13)
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F07X_PINMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F07X_PINMAP_H */

10
arch/arm/src/stm32f0/chip/stm32f09x_pinmap.h → arch/arm/src/stm32f0l0/hardware/stm32f09x_pinmap.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f09x_pinmap.h
* arch/arm/src/stm32f0l0/hardware/stm32f09x_pinmap.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F09X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F09X_PINMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F09X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F09X_PINMAP_H
/************************************************************************************
* Included Files
@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include "stm32f0_gpio.h"
#include "stm32_gpio.h"
/************************************************************************************
* Pre-processor Definitions
@ -427,4 +427,4 @@
#define GPIO_USART8_RX_3 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN13)
#define GPIO_USART8_CK_RST (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN14)
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F09X_PINMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F09X_PINMAP_H */

64
arch/arm/src/stm32f0/chip/stm32f0_rcc.h → arch/arm/src/stm32f0l0/hardware/stm32f0_rcc.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f0_rcc.h
* arch/arm/src/stm32f0l0/hardware/stm32f0_rcc.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_RCC_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_RCC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_RCC_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_RCC_H
/************************************************************************************
* Pre-processor Definitions
@ -43,37 +43,37 @@
/* Register Offsets *****************************************************************/
#define STM32F0_RCC_CR_OFFSET 0x0000 /* Clock control register */
#define STM32F0_RCC_CFGR_OFFSET 0x0004 /* Clock configuration register */
#define STM32F0_RCC_CIR_OFFSET 0x0008 /* Clock interrupt register */
#define STM32F0_RCC_APB2RSTR_OFFSET 0x000c /* APB2 Peripheral reset register */
#define STM32F0_RCC_APB1RSTR_OFFSET 0x0010 /* APB1 Peripheral reset register */
#define STM32F0_RCC_AHBENR_OFFSET 0x0014 /* AHB Peripheral Clock enable register */
#define STM32F0_RCC_APB2ENR_OFFSET 0x0018 /* APB2 Peripheral Clock enable register */
#define STM32F0_RCC_APB1ENR_OFFSET 0x001c /* APB1 Peripheral Clock enable register */
#define STM32F0_RCC_BDCR_OFFSET 0x0020 /* Backup domain control register */
#define STM32F0_RCC_CSR_OFFSET 0x0024 /* Control/status register */
#define STM32F0_RCC_AHBRSTR_OFFSET 0x0028 /* AHB Reset register */
#define STM32F0_RCC_CFGR2_OFFSET 0x002c /* Clock configuration register 2 */
#define STM32F0_RCC_CFGR3_OFFSET 0x0030 /* Clock configuration register 3 */
#define STM32F0_RCC_CR2_OFFSET 0x0034 /* Clock control register 2 */
#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */
#define STM32_RCC_CFGR_OFFSET 0x0004 /* Clock configuration register */
#define STM32_RCC_CIR_OFFSET 0x0008 /* Clock interrupt register */
#define STM32_RCC_APB2RSTR_OFFSET 0x000c /* APB2 Peripheral reset register */
#define STM32_RCC_APB1RSTR_OFFSET 0x0010 /* APB1 Peripheral reset register */
#define STM32_RCC_AHBENR_OFFSET 0x0014 /* AHB Peripheral Clock enable register */
#define STM32_RCC_APB2ENR_OFFSET 0x0018 /* APB2 Peripheral Clock enable register */
#define STM32_RCC_APB1ENR_OFFSET 0x001c /* APB1 Peripheral Clock enable register */
#define STM32_RCC_BDCR_OFFSET 0x0020 /* Backup domain control register */
#define STM32_RCC_CSR_OFFSET 0x0024 /* Control/status register */
#define STM32_RCC_AHBRSTR_OFFSET 0x0028 /* AHB Reset register */
#define STM32_RCC_CFGR2_OFFSET 0x002c /* Clock configuration register 2 */
#define STM32_RCC_CFGR3_OFFSET 0x0030 /* Clock configuration register 3 */
#define STM32_RCC_CR2_OFFSET 0x0034 /* Clock control register 2 */
/* Register Addresses ***************************************************************/
#define STM32F0_RCC_CR (STM32F0_RCC_BASE+STM32F0_RCC_CR_OFFSET)
#define STM32F0_RCC_CFGR (STM32F0_RCC_BASE+STM32F0_RCC_CFGR_OFFSET)
#define STM32F0_RCC_CIR (STM32F0_RCC_BASE+STM32F0_RCC_CIR_OFFSET)
#define STM32F0_RCC_APB2RSTR (STM32F0_RCC_BASE+STM32F0_RCC_APB2RSTR_OFFSET)
#define STM32F0_RCC_APB1RSTR (STM32F0_RCC_BASE+STM32F0_RCC_APB1RSTR_OFFSET)
#define STM32F0_RCC_AHBENR (STM32F0_RCC_BASE+STM32F0_RCC_AHBENR_OFFSET)
#define STM32F0_RCC_APB2ENR (STM32F0_RCC_BASE+STM32F0_RCC_APB2ENR_OFFSET)
#define STM32F0_RCC_APB1ENR (STM32F0_RCC_BASE+STM32F0_RCC_APB1ENR_OFFSET)
#define STM32F0_RCC_BDCR (STM32F0_RCC_BASE+STM32F0_RCC_BDCR_OFFSET)
#define STM32F0_RCC_CSR (STM32F0_RCC_BASE+STM32F0_RCC_CSR_OFFSET)
#define STM32F0_RCC_AHBRSTR (STM32F0_RCC_BASE+STM32F0_RCC_AHBRSTR_OFFSET)
#define STM32F0_RCC_CFGR2 (STM32F0_RCC_BASE+STM32F0_RCC_CFGR2_OFFSET)
#define STM32F0_RCC_CFGR3 (STM32F0_RCC_BASE+STM32F0_RCC_CFGR3_OFFSET)
#define STM32F0_RCC_CR2 (STM32F0_RCC_BASE+STM32F0_RCC_CR2_OFFSET)
#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET)
#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET)
#define STM32_RCC_CIR (STM32_RCC_BASE+STM32_RCC_CIR_OFFSET)
#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET)
#define STM32_RCC_APB1RSTR (STM32_RCC_BASE+STM32_RCC_APB1RSTR_OFFSET)
#define STM32_RCC_AHBENR (STM32_RCC_BASE+STM32_RCC_AHBENR_OFFSET)
#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
#define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET)
#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
#define STM32_RCC_AHBRSTR (STM32_RCC_BASE+STM32_RCC_AHBRSTR_OFFSET)
#define STM32_RCC_CFGR2 (STM32_RCC_BASE+STM32_RCC_CFGR2_OFFSET)
#define STM32_RCC_CFGR3 (STM32_RCC_BASE+STM32_RCC_CFGR3_OFFSET)
#define STM32_RCC_CR2 (STM32_RCC_BASE+STM32_RCC_CR2_OFFSET)
/* Register Bitfield Definitions ****************************************************/
@ -391,4 +391,4 @@
#define RCC_CR2_HSI48CAL_SHIFT (24) /* Bits 24-31: HSI48 factory clock calibration */
#define RCC_CR2_HSI48CAL_MASK (0xff << RCC_CR2_HSI48CAL_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_RCC_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_RCC_H */

56
arch/arm/src/stm32f0/stm32f0_clockconfig.c → arch/arm/src/stm32f0l0/stm32_clockconfig.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0/stm32f0_clockconfig.c
* arch/arm/src/stm32f0l0/stm32_clockconfig.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -48,18 +48,18 @@
#include "up_arch.h"
#include "up_internal.h"
#include "stm32f0_rcc.h"
#include "stm32f0_clockconfig.h"
#include "chip/stm32f0_syscfg.h"
#include "chip/stm32f0_flash.h"
#include "chip/stm32f0_gpio.h"
#include "stm32_rcc.h"
#include "stm32_clockconfig.h"
#include "hardware/stm32_syscfg.h"
#include "hardware/stm32_flash.h"
#include "hardware/stm32_gpio.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32f0_clockconfig
* Name: stm32_clockconfig
*
* Description:
* Called to initialize the STM32F0xx. This does whatever setup is needed
@ -68,29 +68,29 @@
*
****************************************************************************/
void stm32f0_clockconfig(void)
void stm32_clockconfig(void)
{
uint32_t regval;
/* Verify if PLL is already setup. If so configure to use HSI mode */
if ((getreg32(STM32F0_RCC_CFGR) & RCC_CFGR_SWS_MASK) == RCC_CFGR_SWS_PLL)
if ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) == RCC_CFGR_SWS_PLL)
{
/* Select HSI mode */
regval = getreg32(STM32F0_RCC_CFGR);
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_SW_MASK;
putreg32(regval, STM32F0_RCC_CFGR);
putreg32(regval, STM32_RCC_CFGR);
while ((getreg32(STM32F0_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_HSI);
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_HSI);
}
/* Disable the PLL */
regval = getreg32(STM32F0_RCC_CR);
regval = getreg32(STM32_RCC_CR);
regval &= ~RCC_CR_PLLON;
putreg32(regval, STM32F0_RCC_CR);
while ((getreg32(STM32F0_RCC_CR) & RCC_CR_PLLRDY) != 0);
putreg32(regval, STM32_RCC_CR);
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) != 0);
/* Enable FLASH prefetch buffer and set flash latency */
@ -101,16 +101,16 @@ void stm32f0_clockconfig(void)
/* Set HCLK = SYSCLK */
regval = getreg32(STM32F0_RCC_CFGR);
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_HPRE_MASK;
regval |= RCC_CFGR_HPRE_SYSCLK;
putreg32(regval, STM32F0_RCC_CFGR);
putreg32(regval, STM32_RCC_CFGR);
/* Set PCLK = HCLK */
regval &= ~RCC_CFGR_PPRE1_MASK;
regval |= RCC_CFGR_PPRE1_HCLK;
putreg32(regval, STM32F0_RCC_CFGR);
putreg32(regval, STM32_RCC_CFGR);
/* Configure the PLL to generate the system clock
*
@ -120,28 +120,28 @@ void stm32f0_clockconfig(void)
*/
regval &= ~(RCC_CFGR_PLLSRC_MASK | RCC_CFGR_PLLXTPRE_MASK | RCC_CFGR_PLLMUL_MASK);
regval |= (RCC_CFGR_PLLSRC_HSId2 | RCC_CFGR_PLLXTPRE_DIV1 | STM32F0_CFGR_PLLMUL);
putreg32(regval, STM32F0_RCC_CFGR);
regval |= (RCC_CFGR_PLLSRC_HSId2 | RCC_CFGR_PLLXTPRE_DIV1 | STM32_CFGR_PLLMUL);
putreg32(regval, STM32_RCC_CFGR);
/* Enable the PLL */
regval = getreg32(STM32F0_RCC_CR);
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLON;
putreg32(regval, STM32F0_RCC_CR);
while ((getreg32(STM32F0_RCC_CR) & RCC_CR_PLLRDY) == 0);
putreg32(regval, STM32_RCC_CR);
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
/* Configure to use the PLL */
regval = getreg32(STM32F0_RCC_CFGR);
regval = getreg32(STM32_RCC_CFGR);
regval |= RCC_CFGR_SW_PLL;
putreg32(regval, STM32F0_RCC_CFGR);
while ((getreg32(STM32F0_RCC_CFGR) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL);
putreg32(regval, STM32_RCC_CFGR);
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL);
/* Enable basic peripheral support */
/* Enable all GPIO modules */
regval = getreg32(STM32F0_RCC_AHBENR);
regval = getreg32(STM32_RCC_AHBENR);
regval |= RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPBEN | RCC_AHBENR_IOPCEN |\
RCC_AHBENR_IOPDEN | RCC_AHBENR_IOPEEN | RCC_AHBENR_IOPFEN;
putreg32(regval, STM32F0_RCC_AHBENR);
putreg32(regval, STM32_RCC_AHBENR);
}

12
arch/arm/src/stm32f0/stm32f0_clockconfig.h → arch/arm/src/stm32f0l0/stm32_clockconfig.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/stm32f0_clockconfig.h
* arch/arm/src/stm32f0l0/stm32_clockconfig.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_CLOCKCONFIG_H
#define __ARCH_ARM_SRC_STM32F0_STM32F0_CLOCKCONFIG_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_CLOCKCONFIG_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_CLOCKCONFIG_H
/************************************************************************************
* Included Files
@ -58,7 +58,7 @@ extern "C"
************************************************************************************/
/************************************************************************************
* Name: stm32f0_clockconfig
* Name: stm32_clockconfig
*
* Description:
* Called to initialize the STM32F0XX. This does whatever setup is needed to put
@ -67,11 +67,11 @@ extern "C"
*
************************************************************************************/
void stm32f0_clockconfig(void);
void stm32_clockconfig(void);
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_CLOCKCONFIG_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_CLOCKCONFIG_H */

94
arch/arm/src/stm32f0/stm32f0_gpio.c → arch/arm/src/stm32f0l0/stm32_gpio.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0/stm32f0_gpio.c
* arch/arm/src/stm32f0l0/stm32_gpio.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -47,39 +47,39 @@
#include <debug.h>
#include <arch/irq.h>
#include <arch/stm32f0/chip.h>
#include <arch/stm32f0l0/chip.h>
#include "up_arch.h"
#include "chip.h"
#include "stm32f0_gpio.h"
#include "stm32_gpio.h"
#include "chip/stm32f0_syscfg.h"
#include "hardware/stm32_syscfg.h"
/****************************************************************************
* Public Data
****************************************************************************/
/* Base addresses for each GPIO block */
const uint32_t g_gpiobase[STM32F0_NPORTS] =
const uint32_t g_gpiobase[STM32_NPORTS] =
{
#if STM32F0_NPORTS > 0
STM32F0_GPIOA_BASE,
#if STM32_NPORTS > 0
STM32_GPIOA_BASE,
#endif
#if STM32F0_NPORTS > 1
STM32F0_GPIOB_BASE,
#if STM32_NPORTS > 1
STM32_GPIOB_BASE,
#endif
#if STM32F0_NPORTS > 2
STM32F0_GPIOC_BASE,
#if STM32_NPORTS > 2
STM32_GPIOC_BASE,
#endif
#if STM32F0_NPORTS > 3
STM32F0_GPIOD_BASE,
#if STM32_NPORTS > 3
STM32_GPIOD_BASE,
#endif
#if STM32F0_NPORTS > 4
STM32F0_GPIOE_BASE,
#if STM32_NPORTS > 4
STM32_GPIOE_BASE,
#endif
#if STM32F0_NPORTS > 5
STM32F0_GPIOF_BASE,
#if STM32_NPORTS > 5
STM32_GPIOF_BASE,
#endif
};
@ -88,13 +88,13 @@ const uint32_t g_gpiobase[STM32F0_NPORTS] =
****************************************************************************/
/****************************************************************************
* Function: stm32f0_gpioinit
* Function: stm32_gpioinit
*
* Description:
* Based on configuration within the .config file, it does:
* - Remaps positions of alternative functions.
*
* Typically called from stm32f0_start().
* Typically called from stm32_start().
*
* Assumptions:
* This function is called early in the initialization sequence so that
@ -102,17 +102,17 @@ const uint32_t g_gpiobase[STM32F0_NPORTS] =
*
****************************************************************************/
void stm32f0_gpioinit(void)
void stm32_gpioinit(void)
{
}
/****************************************************************************
* Name: stm32f0_configgpio
* Name: stm32_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
* function, it must be unconfigured with stm32f0_unconfiggpio() with
* function, it must be unconfigured with stm32_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
* Returned Value:
@ -123,7 +123,7 @@ void stm32f0_gpioinit(void)
* To-Do: Auto Power Enable
****************************************************************************/
int stm32f0_configgpio(uint32_t cfgset)
int stm32_configgpio(uint32_t cfgset)
{
uintptr_t base;
uint32_t regval;
@ -138,7 +138,7 @@ int stm32f0_configgpio(uint32_t cfgset)
/* Verify that this hardware supports the select GPIO port */
port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
if (port >= STM32F0_NPORTS)
if (port >= STM32_NPORTS)
{
return -EINVAL;
}
@ -163,7 +163,7 @@ int stm32f0_configgpio(uint32_t cfgset)
break;
case GPIO_OUTPUT: /* General purpose output mode */
stm32f0_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); /* Set the initial output value */
stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); /* Set the initial output value */
pinmode = GPIO_MODER_OUTPUT;
break;
@ -184,10 +184,10 @@ int stm32f0_configgpio(uint32_t cfgset)
/* Now apply the configuration to the mode register */
regval = getreg32(base + STM32F0_GPIO_MODER_OFFSET);
regval = getreg32(base + STM32_GPIO_MODER_OFFSET);
regval &= ~GPIO_MODER_MASK(pin);
regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin));
putreg32(regval, base + STM32F0_GPIO_MODER_OFFSET);
putreg32(regval, base + STM32_GPIO_MODER_OFFSET);
/* Set up the pull-up/pull-down configuration (all but analog pins) */
@ -210,10 +210,10 @@ int stm32f0_configgpio(uint32_t cfgset)
}
}
regval = getreg32(base + STM32F0_GPIO_PUPDR_OFFSET);
regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET);
regval &= ~GPIO_PUPDR_MASK(pin);
regval |= (setting << GPIO_PUPDR_SHIFT(pin));
putreg32(regval, base + STM32F0_GPIO_PUPDR_OFFSET);
putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET);
/* Set the alternate function (Only alternate function pins) */
@ -228,12 +228,12 @@ int stm32f0_configgpio(uint32_t cfgset)
if (pin < 8)
{
regoffset = STM32F0_GPIO_AFRL_OFFSET;
regoffset = STM32_GPIO_AFRL_OFFSET;
pos = pin;
}
else
{
regoffset = STM32F0_GPIO_AFRH_OFFSET;
regoffset = STM32_GPIO_AFRH_OFFSET;
pos = pin - 8;
}
@ -267,14 +267,14 @@ int stm32f0_configgpio(uint32_t cfgset)
setting = 0;
}
regval = getreg32(base + STM32F0_GPIO_OSPEED_OFFSET);
regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET);
regval &= ~GPIO_OSPEED_MASK(pin);
regval |= (setting << GPIO_OSPEED_SHIFT(pin));
putreg32(regval, base + STM32F0_GPIO_OSPEED_OFFSET);
putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET);
/* Set push-pull/open-drain (Only outputs and alternate function pins) */
regval = getreg32(base + STM32F0_GPIO_OTYPER_OFFSET);
regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET);
setting = GPIO_OTYPER_OD(pin);
if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) &&
@ -287,7 +287,7 @@ int stm32f0_configgpio(uint32_t cfgset)
regval &= ~setting;
}
putreg32(regval, base + STM32F0_GPIO_OTYPER_OFFSET);
putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET);
/* Otherwise, it is an input pin. Should it configured as an EXTI interrupt? */
@ -309,7 +309,7 @@ int stm32f0_configgpio(uint32_t cfgset)
/* Set the bits in the SYSCFG EXTICR register */
regaddr = STM32F0_SYSCFG_EXTICR(pin);
regaddr = STM32_SYSCFG_EXTICR(pin);
regval = getreg32(regaddr);
shift = SYSCFG_EXTICR_EXTI_SHIFT(pin);
regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift);
@ -324,7 +324,7 @@ int stm32f0_configgpio(uint32_t cfgset)
}
/****************************************************************************
* Name: stm32f0_unconfiggpio
* Name: stm32_unconfiggpio
*
* Description:
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set it
@ -343,7 +343,7 @@ int stm32f0_configgpio(uint32_t cfgset)
* To-Do: Auto Power Disable
****************************************************************************/
int stm32f0_unconfiggpio(uint32_t cfgset)
int stm32_unconfiggpio(uint32_t cfgset)
{
/* Reuse port and pin number and set it to default HiZ INPUT */
@ -352,18 +352,18 @@ int stm32f0_unconfiggpio(uint32_t cfgset)
/* To-Do: Mark its unuse for automatic power saving options */
return stm32f0_configgpio(cfgset);
return stm32_configgpio(cfgset);
}
/****************************************************************************
* Name: stm32f0_gpiowrite
* Name: stm32_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void stm32f0_gpiowrite(uint32_t pinset, bool value)
void stm32_gpiowrite(uint32_t pinset, bool value)
{
uint32_t base;
uint32_t bit;
@ -371,7 +371,7 @@ void stm32f0_gpiowrite(uint32_t pinset, bool value)
unsigned int pin;
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
if (port < STM32F0_NPORTS)
if (port < STM32_NPORTS)
{
/* Get the port base address */
@ -392,27 +392,27 @@ void stm32f0_gpiowrite(uint32_t pinset, bool value)
bit = GPIO_BSRR_RESET(pin);
}
putreg32(bit, base + STM32F0_GPIO_BSRR_OFFSET);
putreg32(bit, base + STM32_GPIO_BSRR_OFFSET);
}
}
/****************************************************************************
* Name: stm32f0_gpioread
* Name: stm32_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool stm32f0_gpioread(uint32_t pinset)
bool stm32_gpioread(uint32_t pinset)
{
uint32_t base;
unsigned int port;
unsigned int pin;
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
if (port < STM32F0_NPORTS)
if (port < STM32_NPORTS)
{
/* Get the port base address */
@ -421,7 +421,7 @@ bool stm32f0_gpioread(uint32_t pinset)
/* Get the pin number and return the input state of that pin */
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
return ((getreg32(base + STM32F0_GPIO_IDR_OFFSET) & (1 << pin)) != 0);
return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0);
}
return 0;

52
arch/arm/src/stm32f0/stm32f0_gpio.h → arch/arm/src/stm32f0l0/stm32_gpio.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/stm32f0_gpio.h
* arch/arm/src/stm32f0l0/stm32_gpio.h
*
* Copyright (C) 2009, 2011-2012, 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2015-2016 Sebastien Lorquet. All rights reserved.
@ -36,8 +36,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_GPIO_H
#define __ARCH_ARM_SRC_STM32F0_STM32F0_GPIO_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_GPIO_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_GPIO_H
/************************************************************************************
* Included Files
@ -51,16 +51,16 @@
#endif
#include <nuttx/irq.h>
#include <arch/stm32f0/chip.h>
#include <arch/stm32f0l0/chip.h>
#include "chip.h"
#include "chip/stm32f0_pinmap.h"
#include "hardware/stm32_pinmap.h"
/************************************************************************************
* Pre-Processor Declarations
************************************************************************************/
/* Bit-encoded input to stm32f0_configgpio() */
/* Bit-encoded input to stm32_configgpio() */
/* Each port bit of the general-purpose I/O (GPIO) ports can be individually configured
* by software in several modes:
@ -241,19 +241,19 @@ extern "C"
/* Base addresses for each GPIO block */
EXTERN const uint32_t g_gpiobase[STM32F0_NPORTS];
EXTERN const uint32_t g_gpiobase[STM32_NPORTS];
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/************************************************************************************
* Name: stm32f0_configgpio
* Name: stm32_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
* function, it must be unconfigured with stm32f0_unconfiggpio() with
* function, it must be unconfigured with stm32_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
* Returned Value:
@ -262,10 +262,10 @@ EXTERN const uint32_t g_gpiobase[STM32F0_NPORTS];
*
************************************************************************************/
int stm32f0_configgpio(uint32_t cfgset);
int stm32_configgpio(uint32_t cfgset);
/************************************************************************************
* Name: stm32f0_unconfiggpio
* Name: stm32_unconfiggpio
*
* Description:
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set it
@ -283,30 +283,30 @@ int stm32f0_configgpio(uint32_t cfgset);
*
************************************************************************************/
int stm32f0_unconfiggpio(uint32_t cfgset);
int stm32_unconfiggpio(uint32_t cfgset);
/************************************************************************************
* Name: stm32f0_gpiowrite
* Name: stm32_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
************************************************************************************/
void stm32f0_gpiowrite(uint32_t pinset, bool value);
void stm32_gpiowrite(uint32_t pinset, bool value);
/************************************************************************************
* Name: stm32f0_gpioread
* Name: stm32_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
************************************************************************************/
bool stm32f0_gpioread(uint32_t pinset);
bool stm32_gpioread(uint32_t pinset);
/************************************************************************************
* Name: stm32f0_gpiosetevent
* Name: stm32_gpiosetevent
*
* Description:
* Sets/clears GPIO based event and interrupt triggers.
@ -325,11 +325,11 @@ bool stm32f0_gpioread(uint32_t pinset);
*
************************************************************************************/
int stm32f0_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
bool event, xcpt_t func, void *arg);
int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
bool event, xcpt_t func, void *arg);
/************************************************************************************
* Function: stm32f0_dumpgpio
* Function: stm32_dumpgpio
*
* Description:
* Dump all GPIO registers associated with the provided base address
@ -337,23 +337,23 @@ int stm32f0_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
************************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
int stm32f0_dumpgpio(uint32_t pinset, const char *msg);
int stm32_dumpgpio(uint32_t pinset, const char *msg);
#else
# define stm32f0_dumpgpio(p,m)
# define stm32_dumpgpio(p,m)
#endif
/************************************************************************************
* Function: stm32f0_gpioinit
* Function: stm32_gpioinit
*
* Description:
* Based on configuration within the .config file, it does:
* - Remaps positions of alternative functions.
*
* Typically called from stm32f0_start().
* Typically called from stm32_start().
*
************************************************************************************/
void stm32f0_gpioinit(void);
void stm32_gpioinit(void);
#undef EXTERN
#if defined(__cplusplus)
@ -361,4 +361,4 @@ void stm32f0_gpioinit(void);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_GPIO_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_GPIO_H */

46
arch/arm/src/stm32f0/stm32f0_hsi48.c → arch/arm/src/stm32f0l0/stm32_hsi48.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0/stm32f0_hsi48.c
* arch/arm/src/stm32f0l0/stm32_hsi48.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -41,17 +41,17 @@
#include "up_arch.h"
#include "chip.h"
#include "chip/stm32f0_rcc.h"
#include "chip/stm32f0_crs.h"
#include "hardware/stm32_rcc.h"
#include "hardware/stm32_crs.h"
#include "stm32f0_hsi48.h"
#include "stm32_hsi48.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32f0_enable_hsi48
* Name: stm32_enable_hsi48
*
* Description:
* On STM32F04x, STM32F07x and STM32F09x devices only, the HSI48 clock
@ -77,7 +77,7 @@
*
****************************************************************************/
void stm32f0_enable_hsi48(enum syncsrc_e syncsrc)
void stm32_enable_hsi48(enum syncsrc_e syncsrc)
{
uint32_t regval;
@ -93,22 +93,22 @@ void stm32f0_enable_hsi48(enum syncsrc_e syncsrc)
* enabled.
*/
regval = getreg32(STM32F0_RCC_CR2);
regval = getreg32(STM32_RCC_CR2);
regval |= RCC_CR2_HSI48ON;
putreg32(regval, STM32F0_RCC_CR2);
putreg32(regval, STM32_RCC_CR2);
if (syncsrc == SYNCSRC_USB)
{
/* Select the HSI48 as the USB clock source */
regval = getreg32(STM32F0_RCC_CFGR3);
regval = getreg32(STM32_RCC_CFGR3);
regval &= ~RCC_CFGR3_USBSW;
putreg32(regval, STM32F0_RCC_CFGR3);
putreg32(regval, STM32_RCC_CFGR3);
}
/* Wait for the HSI48 clock to stabilize */
while ((getreg32(STM32F0_RCC_CR2) & RCC_CR2_HSI48RDY) == 0);
while ((getreg32(STM32_RCC_CR2) & RCC_CR2_HSI48RDY) == 0);
/* The CRS synchronization (SYNC) source, selectable through the CRS_CFGR
@ -116,7 +116,7 @@ void stm32f0_enable_hsi48(enum syncsrc_e syncsrc)
* clock or the USB SOF signal.
*/
regval = getreg32(STM32F0_CRS_CFGR);
regval = getreg32(STM32_CRS_CFGR);
regval &= ~CRS_CFGR_SYNCSRC_MASK;
switch (syncsrc)
@ -135,20 +135,20 @@ void stm32f0_enable_hsi48(enum syncsrc_e syncsrc)
break;
}
putreg32(regval, STM32F0_CRS_CFGR);
putreg32(regval, STM32_CRS_CFGR);
/* Set the AUTOTRIMEN bit the CRS_CR register to enables the automatic
* hardware adjustment of TRIM bits according to the measured frequency
* error between the selected SYNC event.
*/
regval = getreg32(STM32F0_CRS_CR);
regval = getreg32(STM32_CRS_CR);
regval |= CRS_CR_AUTOTRIMEN;
putreg32(regval, STM32F0_CRS_CR);
putreg32(regval, STM32_CRS_CR);
}
/****************************************************************************
* Name: stm32f0_disable_hsi48
* Name: stm32_disable_hsi48
*
* Description:
* Disable the HSI48 clock.
@ -161,23 +161,23 @@ void stm32f0_enable_hsi48(enum syncsrc_e syncsrc)
*
****************************************************************************/
void stm32f0_disable_hsi48(void)
void stm32_disable_hsi48(void)
{
uint32_t regval;
/* Disable the HSI48 clock */
regval = getreg32(STM32F0_RCC_CR2);
regval = getreg32(STM32_RCC_CR2);
regval &= ~RCC_CR2_HSI48ON;
putreg32(regval, STM32F0_RCC_CR2);
putreg32(regval, STM32_RCC_CR2);
/* Set other registers to the default settings. */
regval = getreg32(STM32F0_CRS_CFGR);
regval = getreg32(STM32_CRS_CFGR);
regval &= ~CRS_CFGR_SYNCSRC_MASK;
putreg32(regval, STM32F0_CRS_CFGR);
putreg32(regval, STM32_CRS_CFGR);
regval = getreg32(STM32F0_CRS_CR);
regval = getreg32(STM32_CRS_CR);
regval &= ~CRS_CR_AUTOTRIMEN;
putreg32(regval, STM32F0_CRS_CR);
putreg32(regval, STM32_CRS_CR);
}

20
arch/arm/src/stm32f0/stm32f0_hsi48.h → arch/arm/src/stm32f0l0/stm32_hsi48.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/stm32f0_rcc.h
* arch/arm/src/stm32f0l0/stm32_rcc.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.orgr>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_HSI48_H
#define __ARCH_ARM_SRC_STM32F0_STM32F0_HSI48_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_HSI48_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_HSI48_H
/************************************************************************************
* Included Files
@ -43,7 +43,7 @@
#include <nuttx/config.h>
#ifdef CONFIG_STM32F0_HAVE_HSI48
#ifdef CONFIG_STM32F0L0_HAVE_HSI48
/************************************************************************************
* Public Types
@ -61,7 +61,7 @@ enum syncsrc_e
************************************************************************************/
/****************************************************************************
* Name: stm32f0_enable_hsi48
* Name: stm32_enable_hsi48
*
* Description:
* On STM32F04x, STM32F07x and STM32F09x devices only, the HSI48 clock
@ -87,10 +87,10 @@ enum syncsrc_e
*
****************************************************************************/
void stm32f0_enable_hsi48(enum syncsrc_e syncsrc);
void stm32_enable_hsi48(enum syncsrc_e syncsrc);
/****************************************************************************
* Name: stm32f0_disable_hsi48
* Name: stm32_disable_hsi48
*
* Description:
* Disable the HSI48 clock.
@ -103,7 +103,7 @@ void stm32f0_enable_hsi48(enum syncsrc_e syncsrc);
*
****************************************************************************/
void stm32f0_disable_hsi48(void);
void stm32_disable_hsi48(void);
#endif /* CONFIG_STM32F0_HAVE_HSI48 */
#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_HSI48_H */
#endif /* CONFIG_STM32F0L0_HAVE_HSI48 */
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_HSI48_H */

610
arch/arm/src/stm32f0/stm32f0_i2c.c → arch/arm/src/stm32f0l0/stm32_i2c.c
View file

File diff suppressed because it is too large Load diff

28
arch/arm/src/stm32f0/stm32f0_i2c.h → arch/arm/src/stm32f0l0/stm32_i2c.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0/stm32f0_i2c.h
* arch/arm/src/stm32f0l0/stm32_i2c.h
*
* Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_I2C_H
#define __ARCH_ARM_SRC_STM32F0_STM32F0_I2C_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_I2C_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_I2C_H
/****************************************************************************
* Included Files
@ -44,7 +44,7 @@
#include <nuttx/i2c/i2c_master.h>
#include "chip.h"
#include "chip/stm32f0_i2c.h"
#include "hardware/stm32_i2c.h"
/****************************************************************************
* Pre-processor Definitions
@ -54,10 +54,10 @@
* seconds per byte value must be provided as well.
*/
#ifdef CONFIG_STM32F0_I2C_DYNTIMEO
# if CONFIG_STM32F0_I2C_DYNTIMEO_USECPERBYTE < 1
# warning "Ignoring CONFIG_STM32F0_I2C_DYNTIMEO because of CONFIG_STM32F0_I2C_DYNTIMEO_USECPERBYTE"
# undef CONFIG_STM32F0_I2C_DYNTIMEO
#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO
# if CONFIG_STM32F0L0_I2C_DYNTIMEO_USECPERBYTE < 1
# warning "Ignoring CONFIG_STM32F0L0_I2C_DYNTIMEO because of CONFIG_STM32F0L0_I2C_DYNTIMEO_USECPERBYTE"
# undef CONFIG_STM32F0L0_I2C_DYNTIMEO
# endif
#endif
@ -66,7 +66,7 @@
****************************************************************************/
/****************************************************************************
* Name: stm32f0_i2cbus_initialize
* Name: stm32_i2cbus_initialize
*
* Description:
* Initialize the selected I2C port. And return a unique instance of struct
@ -82,16 +82,16 @@
*
****************************************************************************/
FAR struct i2c_master_s *stm32f0_i2cbus_initialize(int port);
FAR struct i2c_master_s *stm32_i2cbus_initialize(int port);
/****************************************************************************
* Name: stm32f0_i2cbus_uninitialize
* Name: stm32_i2cbus_uninitialize
*
* Description:
* De-initialize the selected I2C port, and power down the device.
*
* Input Parameters:
* Device structure as returned by the stm32f0_i2cbus_initialize()
* Device structure as returned by the stm32_i2cbus_initialize()
*
* Returned Value:
* OK on success, ERROR when internal reference count mismatch or dev
@ -99,6 +99,6 @@ FAR struct i2c_master_s *stm32f0_i2cbus_initialize(int port);
*
****************************************************************************/
int stm32f0_i2cbus_uninitialize(FAR struct i2c_master_s *dev);
int stm32_i2cbus_uninitialize(FAR struct i2c_master_s *dev);
#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_I2C_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_I2C_H */

4
arch/arm/src/stm32f0/stm32f0_idle.c → arch/arm/src/stm32f0l0/stm32_idle.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0/stm32f0_idle.c
* arch/arm/src/stm32f0l0/stm32_idle.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -97,7 +97,7 @@ void up_idle(void)
* disabled in order to save power."
*/
#ifdef CONFIG_STM32F0_GPDMA
#ifdef CONFIG_STM32F0L0_GPDMA
if (g_dma_inprogress == 0)
#endif
{

62
arch/arm/src/stm32f0/stm32f0_irq.c → arch/arm/src/stm32f0l0/stm32_irq.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0/stm32f0_irq.c
* arch/arm/src/stm32f0l0/stm32_irq.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -51,7 +51,7 @@
#include "up_arch.h"
#include "up_internal.h"
//#include "stm32f0_irq.h"
//#include "stm32_irq.h"
/****************************************************************************
* Pre-processor Definitions
@ -80,7 +80,7 @@ volatile uint32_t *g_current_regs[1];
****************************************************************************/
/****************************************************************************
* Name: stm32f0_dumpnvic
* Name: stm32_dumpnvic
*
* Description:
* Dump some interesting NVIC registers
@ -88,7 +88,7 @@ volatile uint32_t *g_current_regs[1];
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void stm32f0_dumpnvic(const char *msg, int irq)
static void stm32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
@ -120,12 +120,12 @@ static void stm32f0_dumpnvic(const char *msg, int irq)
}
#else
# define stm32f0_dumpnvic(msg, irq)
# define stm32_dumpnvic(msg, irq)
#endif
/****************************************************************************
* Name: stm32f0_nmi, stm32f0_busfault, stm32f0_usagefault, stm32f0_pendsv,
* stm32f0_dbgmonitor, stm32f0_pendsv, stm32f0_reserved
* Name: stm32_nmi, stm32_busfault, stm32_usagefault, stm32_pendsv,
* stm32_dbgmonitor, stm32_pendsv, stm32_reserved
*
* Description:
* Handlers for various execptions. None are handled and all are fatal
@ -135,7 +135,7 @@ static void stm32f0_dumpnvic(const char *msg, int irq)
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
static int stm32f0_nmi(int irq, FAR void *context, FAR void *arg)
static int stm32_nmi(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! NMI received\n");
@ -143,7 +143,7 @@ static int stm32f0_nmi(int irq, FAR void *context, FAR void *arg)
return 0;
}
static int stm32f0_pendsv(int irq, FAR void *context, FAR void *arg)
static int stm32_pendsv(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! PendSV received\n");
@ -151,7 +151,7 @@ static int stm32f0_pendsv(int irq, FAR void *context, FAR void *arg)
return 0;
}
static int stm32f0_reserved(int irq, FAR void *context, FAR void *arg)
static int stm32_reserved(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
@ -161,14 +161,14 @@ static int stm32f0_reserved(int irq, FAR void *context, FAR void *arg)
#endif
/****************************************************************************
* Name: stm32f0_clrpend
* Name: stm32_clrpend
*
* Description:
* Clear a pending interrupt at the NVIC.
*
****************************************************************************/
static inline void stm32f0_clrpend(int irq)
static inline void stm32_clrpend(int irq)
{
/* This will be called on each interrupt exit whether the interrupt can be
* enambled or not. So this assertion is necessarily lame.
@ -178,13 +178,13 @@ static inline void stm32f0_clrpend(int irq)
/* Check for an external interrupt */
if (irq >= STM32F0_IRQ_EXTINT && irq < (STM32F0_IRQ_EXTINT + 32))
if (irq >= STM32_IRQ_EXTINT && irq < (STM32_IRQ_EXTINT + 32))
{
/* Set the appropriate bit in the ISER register to enable the
* interrupt
*/
putreg32((1 << (irq - STM32F0_IRQ_EXTINT)), ARMV6M_NVIC_ICPR);
putreg32((1 << (irq - STM32_IRQ_EXTINT)), ARMV6M_NVIC_ICPR);
}
}
@ -228,25 +228,25 @@ void up_irqinitialize(void)
* under certain conditions.
*/
irq_attach(STM32F0_IRQ_SVCALL, up_svcall, NULL);
irq_attach(STM32F0_IRQ_HARDFAULT, up_hardfault, NULL);
irq_attach(STM32_IRQ_SVCALL, up_svcall, NULL);
irq_attach(STM32_IRQ_HARDFAULT, up_hardfault, NULL);
/* Attach all other processor exceptions (except reset and sys tick) */
#ifdef CONFIG_DEBUG_FEATURES
irq_attach(STM32F0_IRQ_NMI, stm32f0_nmi, NULL);
irq_attach(STM32F0_IRQ_PENDSV, stm32f0_pendsv, NULL);
irq_attach(STM32F0_IRQ_RESERVED, stm32f0_reserved, NULL);
irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL);
irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL);
irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL);
#endif
stm32f0_dumpnvic("initial", NR_IRQS);
stm32_dumpnvic("initial", NR_IRQS);
/* Initialize logic to support a second level of interrupt decoding for
* configured pin interrupts.
*/
#ifdef CONFIG_STM32F0_GPIOIRQ
stm32f0_gpioirqinitialize();
#ifdef CONFIG_STM32F0L0_GPIOIRQ
stm32_gpioirqinitialize();
#endif
#ifndef CONFIG_SUPPRESS_INTERRUPTS
@ -271,23 +271,23 @@ void up_disable_irq(int irq)
/* Check for an external interrupt */
if (irq >= STM32F0_IRQ_EXTINT && irq < (STM32F0_IRQ_EXTINT + 32))
if (irq >= STM32_IRQ_EXTINT && irq < (STM32_IRQ_EXTINT + 32))
{
/* Set the appropriate bit in the ICER register to disable the
* interrupt
*/
putreg32((1 << (irq - STM32F0_IRQ_EXTINT)), ARMV6M_NVIC_ICER);
putreg32((1 << (irq - STM32_IRQ_EXTINT)), ARMV6M_NVIC_ICER);
}
/* Handle processor exceptions. Only SysTick can be disabled */
else if (irq == STM32F0_IRQ_SYSTICK)
else if (irq == STM32_IRQ_SYSTICK)
{
modifyreg32(ARMV6M_SYSTICK_CSR, SYSTICK_CSR_ENABLE, 0);
}
stm32f0_dumpnvic("disable", irq);
stm32_dumpnvic("disable", irq);
}
/****************************************************************************
@ -308,23 +308,23 @@ void up_enable_irq(int irq)
/* Check for external interrupt */
if (irq >= STM32F0_IRQ_EXTINT && irq < (STM32F0_IRQ_EXTINT + 32))
if (irq >= STM32_IRQ_EXTINT && irq < (STM32_IRQ_EXTINT + 32))
{
/* Set the appropriate bit in the ISER register to enable the
* interrupt
*/
putreg32((1 << (irq - STM32F0_IRQ_EXTINT)), ARMV6M_NVIC_ISER);
putreg32((1 << (irq - STM32_IRQ_EXTINT)), ARMV6M_NVIC_ISER);
}
/* Handle processor exceptions. Only SysTick can be disabled */
else if (irq == STM32F0_IRQ_SYSTICK)
else if (irq == STM32_IRQ_SYSTICK)
{
modifyreg32(ARMV6M_SYSTICK_CSR, 0, SYSTICK_CSR_ENABLE);
}
stm32f0_dumpnvic("enable", irq);
stm32_dumpnvic("enable", irq);
}
/****************************************************************************
@ -337,5 +337,5 @@ void up_enable_irq(int irq)
void up_ack_irq(int irq)
{
stm32f0_clrpend(irq);
stm32_clrpend(irq);
}

222
arch/arm/src/stm32f0/stm32f0_lowputc.c → arch/arm/src/stm32f0l0/stm32_lowputc.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0/stm32f0_lowputc.c
* arch/arm/src/stm32f0l0/stm32_lowputc.c
*
* Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -49,9 +49,9 @@
#include "chip.h"
#include "stm32f0_rcc.h"
#include "stm32f0_gpio.h"
#include "stm32f0_uart.h"
#include "stm32_rcc.h"
#include "stm32_gpio.h"
#include "stm32_uart.h"
/****************************************************************************
* Pre-processor Definitions
@ -61,88 +61,88 @@
#ifdef HAVE_CONSOLE
# if defined(CONFIG_USART1_SERIAL_CONSOLE)
# define STM32F0_CONSOLE_BASE STM32F0_USART1_BASE
# define STM32F0_APBCLOCK STM32F0_PCLK2_FREQUENCY
# define STM32F0_CONSOLE_BAUD CONFIG_USART1_BAUD
# define STM32F0_CONSOLE_BITS CONFIG_USART1_BITS
# define STM32F0_CONSOLE_PARITY CONFIG_USART1_PARITY
# define STM32F0_CONSOLE_2STOP CONFIG_USART1_2STOP
# define STM32_CONSOLE_BASE STM32_USART1_BASE
# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY
# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART1_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY
# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP
# ifdef CONFIG_USART1_RS485
# define STM32F0_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
# define STM32F0_CONSOLE_RS485_DIR_POLARITY false
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32F0_CONSOLE_RS485_DIR_POLARITY true
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART2_SERIAL_CONSOLE)
# define STM32F0_CONSOLE_BASE STM32F0_USART2_BASE
# define STM32F0_APBCLOCK STM32F0_PCLK1_FREQUENCY
# define STM32F0_CONSOLE_BAUD CONFIG_USART2_BAUD
# define STM32F0_CONSOLE_BITS CONFIG_USART2_BITS
# define STM32F0_CONSOLE_PARITY CONFIG_USART2_PARITY
# define STM32F0_CONSOLE_2STOP CONFIG_USART2_2STOP
# define STM32_CONSOLE_BASE STM32_USART2_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART2_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY
# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP
# ifdef CONFIG_USART2_RS485
# define STM32F0_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
# define STM32F0_CONSOLE_RS485_DIR_POLARITY false
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32F0_CONSOLE_RS485_DIR_POLARITY true
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART3_SERIAL_CONSOLE)
# define STM32F0_CONSOLE_BASE STM32F0_USART3_BASE
# define STM32F0_APBCLOCK STM32F0_PCLK1_FREQUENCY
# define STM32F0_CONSOLE_BAUD CONFIG_USART3_BAUD
# define STM32F0_CONSOLE_BITS CONFIG_USART3_BITS
# define STM32F0_CONSOLE_PARITY CONFIG_USART3_PARITY
# define STM32F0_CONSOLE_2STOP CONFIG_USART3_2STOP
# define STM32_CONSOLE_BASE STM32_USART3_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART3_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY
# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP
# ifdef CONFIG_USART3_RS485
# define STM32F0_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR
# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR
# if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
# define STM32F0_CONSOLE_RS485_DIR_POLARITY false
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32F0_CONSOLE_RS485_DIR_POLARITY true
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART4_SERIAL_CONSOLE)
# define STM32F0_CONSOLE_BASE STM32F0_USART4_BASE
# define STM32F0_APBCLOCK STM32F0_PCLK1_FREQUENCY
# define STM32F0_CONSOLE_BAUD CONFIG_USART4_BAUD
# define STM32F0_CONSOLE_BITS CONFIG_USART4_BITS
# define STM32F0_CONSOLE_PARITY CONFIG_USART4_PARITY
# define STM32F0_CONSOLE_2STOP CONFIG_USART4_2STOP
# define STM32_CONSOLE_BASE STM32_USART4_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_BAUD CONFIG_USART4_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART4_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART4_PARITY
# define STM32_CONSOLE_2STOP CONFIG_USART4_2STOP
# ifdef CONFIG_USART4_RS485
# define STM32F0_CONSOLE_RS485_DIR GPIO_USART4_RS485_DIR
# define STM32_CONSOLE_RS485_DIR GPIO_USART4_RS485_DIR
# if (CONFIG_USART4_RS485_DIR_POLARITY == 0)
# define STM32F0_CONSOLE_RS485_DIR_POLARITY false
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32F0_CONSOLE_RS485_DIR_POLARITY true
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART5_SERIAL_CONSOLE)
# define STM32F0_CONSOLE_BASE STM32F0_USART5_BASE
# define STM32F0_APBCLOCK STM32F0_PCLK1_FREQUENCY
# define STM32F0_CONSOLE_BAUD CONFIG_USART5_BAUD
# define STM32F0_CONSOLE_BITS CONFIG_USART5_BITS
# define STM32F0_CONSOLE_PARITY CONFIG_USART5_PARITY
# define STM32F0_CONSOLE_2STOP CONFIG_USART5_2STOP
# define STM32_CONSOLE_BASE STM32_USART5_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_BAUD CONFIG_USART5_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART5_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART5_PARITY
# define STM32_CONSOLE_2STOP CONFIG_USART5_2STOP
# ifdef CONFIG_USART5_RS485
# define STM32F0_CONSOLE_RS485_DIR GPIO_USART5_RS485_DIR
# define STM32_CONSOLE_RS485_DIR GPIO_USART5_RS485_DIR
# if (CONFIG_USART5_RS485_DIR_POLARITY == 0)
# define STM32F0_CONSOLE_RS485_DIR_POLARITY false
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32F0_CONSOLE_RS485_DIR_POLARITY true
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# endif
/* CR1 settings */
# if STM32F0_CONSOLE_BITS == 9
# if STM32_CONSOLE_BITS == 9
# define USART_CR1_M0_VALUE USART_CR1_M0
# define USART_CR1_M1_VALUE 0
# elif STM32F0_CONSOLE_BITS == 7
# elif STM32_CONSOLE_BITS == 7
# define USART_CR1_M0_VALUE 0
# define USART_CR1_M1_VALUE USART_CR1_M1
# else /* 8 bits */
@ -150,9 +150,9 @@
# define USART_CR1_M1_VALUE 0
# endif
# if STM32F0_CONSOLE_PARITY == 1 /* odd parity */
# if STM32_CONSOLE_PARITY == 1 /* odd parity */
# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS)
# elif STM32F0_CONSOLE_PARITY == 2 /* even parity */
# elif STM32_CONSOLE_PARITY == 2 /* even parity */
# define USART_CR1_PARITY_VALUE USART_CR1_PCE
# else /* no parity */
# define USART_CR1_PARITY_VALUE 0
@ -168,7 +168,7 @@
/* CR2 settings */
# if STM32F0_CONSOLE_2STOP != 0
# if STM32_CONSOLE_2STOP != 0
# define USART_CR2_STOP2_VALUE USART_CR2_STOP2
# else
# define USART_CR2_STOP2_VALUE 0
@ -210,19 +210,19 @@
* UARTDIV = 2 * fCK / baud
*/
# define STM32F0_USARTDIV8 \
(((STM32F0_APBCLOCK << 1) + (STM32F0_CONSOLE_BAUD >> 1)) / STM32F0_CONSOLE_BAUD)
# define STM32F0_USARTDIV16 \
((STM32F0_APBCLOCK + (STM32F0_CONSOLE_BAUD >> 1)) / STM32F0_CONSOLE_BAUD)
# define STM32_USARTDIV8 \
(((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
# define STM32_USARTDIV16 \
((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
/* Use oversamply by 8 only if the divisor is small. But what is small? */
# if STM32F0_USARTDIV8 > 100
# define STM32F0_BRR_VALUE STM32F0_USARTDIV16
# if STM32_USARTDIV8 > 100
# define STM32_BRR_VALUE STM32_USARTDIV16
# else
# define USE_OVER8 1
# define STM32F0_BRR_VALUE \
((STM32F0_USARTDIV8 & 0xfff0) | ((STM32F0_USARTDIV8 & 0x000f) >> 1))
# define STM32_BRR_VALUE \
((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1))
# endif
#endif /* HAVE_CONSOLE */
@ -244,25 +244,25 @@ void up_lowputc(char ch)
#ifdef HAVE_CONSOLE
/* Wait until the TX data register is empty */
while ((getreg32(STM32F0_CONSOLE_BASE + STM32F0_USART_ISR_OFFSET) & USART_ISR_TXE) == 0);
#ifdef STM32F0_CONSOLE_RS485_DIR
stm32f0_gpiowrite(STM32F0_CONSOLE_RS485_DIR, STM32F0_CONSOLE_RS485_DIR_POLARITY);
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0);
#ifdef STM32_CONSOLE_RS485_DIR
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY);
#endif
/* Then send the character */
putreg32((uint32_t)ch, STM32F0_CONSOLE_BASE + STM32F0_USART_TDR_OFFSET);
putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET);
#ifdef STM32F0_CONSOLE_RS485_DIR
while ((getreg32(STM32F0_CONSOLE_BASE + STM32F0_USART_ISR_OFFSET) & USART_ISR_TC) == 0);
stm32f0_gpiowrite(STM32F0_CONSOLE_RS485_DIR, !STM32F0_CONSOLE_RS485_DIR_POLARITY);
#ifdef STM32_CONSOLE_RS485_DIR
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0);
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
#endif
#endif /* HAVE_CONSOLE */
}
/****************************************************************************
* Name: stm32f0_lowsetup
* Name: stm32_lowsetup
*
* Description:
* This performs basic initialization of the USART used for the serial
@ -271,7 +271,7 @@ void up_lowputc(char ch)
*
****************************************************************************/
void stm32f0_lowsetup(void)
void stm32_lowsetup(void)
{
#if defined(HAVE_USART)
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
@ -280,83 +280,83 @@ void stm32f0_lowsetup(void)
/* Setup clocking and GPIO pins for all configured USARTs */
#ifdef CONFIG_STM32F0_USART1
#ifdef CONFIG_STM32F0L0_USART1
/* Enable USART APB2 clock */
modifyreg32(STM32F0_RCC_APB2ENR, 0, RCC_APB2ENR_USART1EN);
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_USART1EN);
/* Configure RX/TX pins */
stm32f0_configgpio(GPIO_USART1_TX);
stm32f0_configgpio(GPIO_USART1_RX);
stm32_configgpio(GPIO_USART1_TX);
stm32_configgpio(GPIO_USART1_RX);
#ifdef CONFIG_USART1_RS485
stm32f0_configgpio(GPIO_USART1_RS485_DIR);
stm32f0_gpiowrite(GPIO_USART1_RS485_DIR, !CONFIG_USART1_RS485_DIR_POLARITY);
stm32_configgpio(GPIO_USART1_RS485_DIR);
stm32_gpiowrite(GPIO_USART1_RS485_DIR, !CONFIG_USART1_RS485_DIR_POLARITY);
#endif
#endif
#ifdef CONFIG_STM32F0_USART2
#ifdef CONFIG_STM32F0L0_USART2
/* Enable USART APB1 clock */
modifyreg32(STM32F0_RCC_APB1ENR, 0, RCC_APB1ENR_USART2EN);
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART2EN);
/* Configure RX/TX pins */
stm32f0_configgpio(GPIO_USART2_TX);
stm32f0_configgpio(GPIO_USART2_RX);
stm32_configgpio(GPIO_USART2_TX);
stm32_configgpio(GPIO_USART2_RX);
#ifdef CONFIG_USART2_RS485
stm32f0_configgpio(GPIO_USART2_RS485_DIR);
stm32f0_gpiowrite(GPIO_USART2_RS485_DIR, !CONFIG_USART2_RS485_DIR_POLARITY);
stm32_configgpio(GPIO_USART2_RS485_DIR);
stm32_gpiowrite(GPIO_USART2_RS485_DIR, !CONFIG_USART2_RS485_DIR_POLARITY);
#endif
#endif
#ifdef CONFIG_STM32F0_USART3
#ifdef CONFIG_STM32F0L0_USART3
/* Enable USART APB1 clock */
modifyreg32(STM32F0_RCC_APB1ENR, 0, RCC_APB1ENR_USART3EN);
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART3EN);
/* Configure RX/TX pins */
stm32f0_configgpio(GPIO_USART3_TX);
stm32f0_configgpio(GPIO_USART3_RX);
stm32_configgpio(GPIO_USART3_TX);
stm32_configgpio(GPIO_USART3_RX);
#ifdef CONFIG_USART3_RS485
stm32f0_configgpio(GPIO_USART3_RS485_DIR);
stm32f0_gpiowrite(GPIO_USART3_RS485_DIR, !CONFIG_USART3_RS485_DIR_POLARITY);
stm32_configgpio(GPIO_USART3_RS485_DIR);
stm32_gpiowrite(GPIO_USART3_RS485_DIR, !CONFIG_USART3_RS485_DIR_POLARITY);
#endif
#endif
#ifdef CONFIG_STM32F0_USART4
#ifdef CONFIG_STM32F0L0_USART4
/* Enable USART APB1 clock */
modifyreg32(STM32F0_RCC_APB1ENR, 0, RCC_APB1ENR_USART4EN);
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART4EN);
/* Configure RX/TX pins */
stm32f0_configgpio(GPIO_USART4_TX);
stm32f0_configgpio(GPIO_USART4_RX);
stm32_configgpio(GPIO_USART4_TX);
stm32_configgpio(GPIO_USART4_RX);
#ifdef CONFIG_USART4_RS485
stm32f0_configgpio(GPIO_USART4_RS485_DIR);
stm32f0_gpiowrite(GPIO_USART4_RS485_DIR, !CONFIG_USART4_RS485_DIR_POLARITY);
stm32_configgpio(GPIO_USART4_RS485_DIR);
stm32_gpiowrite(GPIO_USART4_RS485_DIR, !CONFIG_USART4_RS485_DIR_POLARITY);
#endif
#endif
#ifdef CONFIG_STM32F0_USART5
#ifdef CONFIG_STM32F0L0_USART5
/* Enable USART APB1 clock */
modifyreg32(STM32F0_RCC_APB1ENR, 0, RCC_APB1ENR_USART5EN);
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART5EN);
/* Configure RX/TX pins */
stm32f0_configgpio(GPIO_USART5_TX);
stm32f0_configgpio(GPIO_USART5_RX);
stm32_configgpio(GPIO_USART5_TX);
stm32_configgpio(GPIO_USART5_RX);
#ifdef CONFIG_USART5_RS485
stm32f0_configgpio(GPIO_USART5_RS485_DIR);
stm32f0_gpiowrite(GPIO_USART5_RS485_DIR, !CONFIG_USART5_RS485_DIR_POLARITY);
stm32_configgpio(GPIO_USART5_RS485_DIR);
stm32_gpiowrite(GPIO_USART5_RS485_DIR, !CONFIG_USART5_RS485_DIR_POLARITY);
#endif
#endif
@ -365,41 +365,41 @@ void stm32f0_lowsetup(void)
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
/* Configure CR2 */
cr = getreg32(STM32F0_CONSOLE_BASE + STM32F0_USART_CR2_OFFSET);
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
cr &= ~USART_CR2_CLRBITS;
cr |= USART_CR2_SETBITS;
putreg32(cr, STM32F0_CONSOLE_BASE + STM32F0_USART_CR2_OFFSET);
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
/* Configure CR1 */
cr = getreg32(STM32F0_CONSOLE_BASE + STM32F0_USART_CR1_OFFSET);
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
cr &= ~USART_CR1_CLRBITS;
cr |= USART_CR1_SETBITS;
putreg32(cr, STM32F0_CONSOLE_BASE + STM32F0_USART_CR1_OFFSET);
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
/* Configure CR3 */
cr = getreg32(STM32F0_CONSOLE_BASE + STM32F0_USART_CR3_OFFSET);
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
cr &= ~USART_CR3_CLRBITS;
cr |= USART_CR3_SETBITS;
putreg32(cr, STM32F0_CONSOLE_BASE + STM32F0_USART_CR3_OFFSET);
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
/* Configure the USART Baud Rate */
putreg32(STM32F0_BRR_VALUE, STM32F0_CONSOLE_BASE + STM32F0_USART_BRR_OFFSET);
putreg32(STM32_BRR_VALUE, STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET);
/* Select oversampling by 8 */
cr = getreg32(STM32F0_CONSOLE_BASE + STM32F0_USART_CR1_OFFSET);
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
#ifdef USE_OVER8
cr |= USART_CR1_OVER8;
putreg32(cr, STM32F0_CONSOLE_BASE + STM32F0_USART_CR1_OFFSET);
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
#endif
/* Enable Rx, Tx, and the USART */
cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
putreg32(cr, STM32F0_CONSOLE_BASE + STM32F0_USART_CR1_OFFSET);
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
#endif /* HAVE_USART */

12
arch/arm/src/stm32f0/stm32f0_lowputc.h → arch/arm/src/stm32f0l0/stm32_lowputc.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/stm32f0_lowputc.h
* arch/arm/src/stm32f0l0/stm32_lowputc.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_LOWPUTC_H
#define __ARCH_ARM_SRC_STM32F0_STM32F0_LOWPUTC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_LOWPUTC_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_LOWPUTC_H
/************************************************************************************
* Included Files
@ -61,7 +61,7 @@ extern "C"
#endif
/************************************************************************************
* Name: stm32f0_lowsetup
* Name: stm32_lowsetup
*
* Description:
* Called at the very beginning of _start. Performs low level initialization
@ -69,7 +69,7 @@ extern "C"
*
************************************************************************************/
void stm32f0_lowsetup(void);
void stm32_lowsetup(void);
#undef EXTERN
#if defined(__cplusplus)
@ -77,4 +77,4 @@ void stm32f0_lowsetup(void);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_LOWPUTC_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_LOWPUTC_H */

10
arch/arm/src/stm32f0/stm32f0_rcc.h → arch/arm/src/stm32f0l0/stm32_rcc.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/stm32f0_rcc.h
* arch/arm/src/stm32f0l0/stm32_rcc.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.orgr>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_RCC_H
#define __ARCH_ARM_SRC_STM32F0_STM32F0_RCC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_RCC_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_RCC_H
/************************************************************************************
* Included Files
@ -46,6 +46,6 @@
#include "up_arch.h"
#include "chip.h"
#include "chip/stm32f0_rcc.h"
#include "hardware/stm32_rcc.h"
#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_RCC_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_RCC_H */

662
arch/arm/src/stm32f0/stm32f0_serial.c → arch/arm/src/stm32f0l0/stm32_serial.c
View file

File diff suppressed because it is too large Load diff

8
arch/arm/src/stm32f0/stm32f0_serial.h → arch/arm/src/stm32f0l0/stm32_serial.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/stm32f0_serial.h
* arch/arm/src/stm32f0l0/stm32_serial.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_SERIAL_H
#define __ARCH_ARM_SRC_STM32F0_STM32F0_SERIAL_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_SERIAL_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_SERIAL_H
/************************************************************************************
* Included Files
@ -47,4 +47,4 @@
* Pre-processor Definitions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_SERIAL_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_SERIAL_H */

16
arch/arm/src/stm32f0/stm32f0_start.c → arch/arm/src/stm32f0l0/stm32_start.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0/stm32f0_start.c
* arch/arm/src/stm32f0l0/stm32_start.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -50,9 +50,9 @@
#include "up_arch.h"
#include "up_internal.h"
#include "stm32f0_clockconfig.h"
#include "stm32f0_lowputc.h"
#include "stm32f0_start.h"
#include "stm32_clockconfig.h"
#include "stm32_lowputc.h"
#include "stm32_start.h"
/****************************************************************************
* Pre-processor Definitions
@ -104,8 +104,8 @@ void __start(void)
/* Configure the uart so that we can get debug output as soon as possible */
stm32f0_clockconfig();
stm32f0_lowsetup();
stm32_clockconfig();
stm32_lowsetup();
showprogress('A');
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
@ -146,13 +146,13 @@ void __start(void)
*/
#ifdef CONFIG_BUILD_PROTECTED
stm32f0_userspace();
stm32_userspace();
showprogress('E');
#endif
/* Initialize onboard resources */
stm32f0_boardinitialize();
stm32_boardinitialize();
showprogress('F');
/* Then start NuttX */

14
arch/arm/src/stm32f0/stm32f0_start.h → arch/arm/src/stm32f0l0/stm32_start.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/stm32f0_start.h
* arch/arm/src/stm32f0l0/stm32_start.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_START_H
#define __ARCH_ARM_SRC_STM32F0_STM32F0_START_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_START_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_START_H
/************************************************************************************
* Included Files
@ -57,20 +57,20 @@ extern "C"
************************************************************************************/
/************************************************************************************
* Name: stm32f0_boardinitialize
* Name: stm32_boardinitialize
*
* Description:
* All STM32 architectures must provide the following entry point. This entry
* point is called early in the intitialization -- after all memory has been
* point is called early in the initialization -- after all memory has been
* configured and mapped but before any devices have been initialized.
*
************************************************************************************/
void stm32f0_boardinitialize(void);
void stm32_boardinitialize(void);
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_START_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_START_H */

20
arch/arm/src/stm32f0/stm32f0_timerisr.c → arch/arm/src/stm32f0l0/stm32_timerisr.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f0/stm32f0_timerisr.c
* arch/arm/src/stm32f0l0/stm32_timerisr.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -62,10 +62,10 @@
* (when CLKSOURCE = 0). ..."
*/
#if defined(CONFIG_STM32F0_SYSTICK_CORECLK)
# define SYSTICK_CLOCK STM32F0_SYSCLK_FREQUENCY /* Core clock */
#elif defined(CONFIG_STM32F0_SYSTICK_CORECLK_DIV16)
# define SYSTICK_CLOCK (STM32F0_SYSCLK_FREQUENCY / 16) /* Core clock divided by 16 */
#if defined(CONFIG_STM32F0L0_SYSTICK_CORECLK)
# define SYSTICK_CLOCK STM32_SYSCLK_FREQUENCY /* Core clock */
#elif defined(CONFIG_STM32F0L0_SYSTICK_CORECLK_DIV16)
# define SYSTICK_CLOCK (STM32_SYSCLK_FREQUENCY / 16) /* Core clock divided by 16 */
#endif
/* The desired timer interrupt frequency is provided by the definition
@ -99,7 +99,7 @@
****************************************************************************/
/****************************************************************************
* Function: stm32f0_timerisr
* Function: stm32_timerisr
*
* Description:
* The timer ISR will perform a variety of services for various portions
@ -107,7 +107,7 @@
*
****************************************************************************/
static int stm32f0_timerisr(int irq, uint32_t *regs, FAR void *arg)
static int stm32_timerisr(int irq, uint32_t *regs, FAR void *arg)
{
/* Process timer interrupt */
@ -145,14 +145,14 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
(void)irq_attach(STM32F0_IRQ_SYSTICK, (xcpt_t)stm32f0_timerisr, NULL);
(void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL);
/* Enable SysTick interrupts. "The CLKSOURCE bit in SysTick Control and
* Status register selects either the core clock (when CLKSOURCE = 1) or
* a divide-by-16 of the core clock (when CLKSOURCE = 0). ..."
*/
#ifdef CONFIG_STM32F0_SYSTICK_CORECLK
#ifdef CONFIG_STM32F0L0_SYSTICK_CORECLK
putreg32((SYSTICK_CSR_CLKSOURCE | SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE),
ARMV6M_SYSTICK_CSR);
#else
@ -161,5 +161,5 @@ void arm_timer_initialize(void)
/* And enable the timer interrupt */
up_enable_irq(STM32F0_IRQ_SYSTICK);
up_enable_irq(STM32_IRQ_SYSTICK);
}

254
arch/arm/src/stm32f0/stm32f0_uart.h → arch/arm/src/stm32f0l0/stm32_uart.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32/stm32f0_uart.h
* arch/arm/src/stm32f0l0/stm32_uart.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_STC_STM32F0_STM32F0_UART_H
#define __ARCH_ARM_STC_STM32F0_STM32F0_UART_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_UART_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_UART_H
/************************************************************************************
* Included Files
@ -45,7 +45,7 @@
#include "chip.h"
#include "chip/stm32f0_uart.h"
#include "hardware/stm32_uart.h"
/************************************************************************************
* Pre-processor Definitions
@ -54,29 +54,29 @@
* device.
*/
#if STM32F0_NUSART < 8 || !defined(CONFIG_STM32F0_HAVE_USART8)
# undef CONFIG_STM32F0_USART8
#if STM32_NUSART < 8 || !defined(CONFIG_STM32F0L0_HAVE_USART8)
# undef CONFIG_STM32F0L0_USART8
#endif
#if STM32F0_NUSART < 7 || !defined(CONFIG_STM32F0_HAVE_USART7)
# undef CONFIG_STM32F0_USART7
#if STM32_NUSART < 7 || !defined(CONFIG_STM32F0L0_HAVE_USART7)
# undef CONFIG_STM32F0L0_USART7
#endif
#if STM32F0_NUSART < 6 || !defined(CONFIG_STM32F0_HAVE_USART6)
# undef CONFIG_STM32F0_USART6
#if STM32_NUSART < 6 || !defined(CONFIG_STM32F0L0_HAVE_USART6)
# undef CONFIG_STM32F0L0_USART6
#endif
#if STM32F0_NUSART < 5 || !defined(CONFIG_STM32F0_HAVE_USART5)
# undef CONFIG_STM32F0_USART5
#if STM32_NUSART < 5 || !defined(CONFIG_STM32F0L0_HAVE_USART5)
# undef CONFIG_STM32F0L0_USART5
#endif
#if STM32F0_NUSART < 4 || !defined(CONFIG_STM32F0_HAVE_USART4)
# undef CONFIG_STM32F0_USART4
#if STM32_NUSART < 4 || !defined(CONFIG_STM32F0L0_HAVE_USART4)
# undef CONFIG_STM32F0L0_USART4
#endif
#if STM32F0_NUSART < 3 || !defined(CONFIG_STM32F0_HAVE_USART3)
# undef CONFIG_STM32F0_USART3
#if STM32_NUSART < 3 || !defined(CONFIG_STM32F0L0_HAVE_USART3)
# undef CONFIG_STM32F0L0_USART3
#endif
#if STM32F0_NUSART < 2
# undef CONFIG_STM32F0_USART2
#if STM32_NUSART < 2
# undef CONFIG_STM32F0L0_USART2
#endif
#if STM32F0_NUSART < 1
# undef CONFIG_STM32F0_USART1
#if STM32_NUSART < 1
# undef CONFIG_STM32F0L0_USART1
#endif
/* USART 3-8 are multiplexed to the same interrupt. Current interrupt
@ -85,128 +85,128 @@
* issue in the future.
*/
#if defined(CONFIG_STM32F0_USART3)
# undef CONFIG_STM32F0_USART4
# undef CONFIG_STM32F0_USART5
# undef CONFIG_STM32F0_USART6
# undef CONFIG_STM32F0_USART7
# undef CONFIG_STM32F0_USART8
#elif defined(CONFIG_STM32F0_USART4)
# undef CONFIG_STM32F0_USART5
# undef CONFIG_STM32F0_USART6
# undef CONFIG_STM32F0_USART7
# undef CONFIG_STM32F0_USART8
#elif defined(CONFIG_STM32F0_USART5)
# undef CONFIG_STM32F0_USART6
# undef CONFIG_STM32F0_USART7
# undef CONFIG_STM32F0_USART8
#elif defined(CONFIG_STM32F0_USART6)
# undef CONFIG_STM32F0_USART7
# undef CONFIG_STM32F0_USART8
#elif defined(CONFIG_STM32F0_USART7)
# undef CONFIG_STM32F0_USART8
#if defined(CONFIG_STM32F0L0_USART3)
# undef CONFIG_STM32F0L0_USART4
# undef CONFIG_STM32F0L0_USART5
# undef CONFIG_STM32F0L0_USART6
# undef CONFIG_STM32F0L0_USART7
# undef CONFIG_STM32F0L0_USART8
#elif defined(CONFIG_STM32F0L0_USART4)
# undef CONFIG_STM32F0L0_USART5
# undef CONFIG_STM32F0L0_USART6
# undef CONFIG_STM32F0L0_USART7
# undef CONFIG_STM32F0L0_USART8
#elif defined(CONFIG_STM32F0L0_USART5)
# undef CONFIG_STM32F0L0_USART6
# undef CONFIG_STM32F0L0_USART7
# undef CONFIG_STM32F0L0_USART8
#elif defined(CONFIG_STM32F0L0_USART6)
# undef CONFIG_STM32F0L0_USART7
# undef CONFIG_STM32F0L0_USART8
#elif defined(CONFIG_STM32F0L0_USART7)
# undef CONFIG_STM32F0L0_USART8
#endif
/* Is there a USART enabled? */
#if defined(CONFIG_STM32F0_USART1) || defined(CONFIG_STM32F0_USART2) || \
defined(CONFIG_STM32F0_USART3) || defined(CONFIG_STM32F0_USART4) || \
defined(CONFIG_STM32F0_USART5) || defined(CONFIG_STM32F0_USART6) || \
defined(CONFIG_STM32F0_USART7) || defined(CONFIG_STM32F0_USART8)
#if defined(CONFIG_STM32F0L0_USART1) || defined(CONFIG_STM32F0L0_USART2) || \
defined(CONFIG_STM32F0L0_USART3) || defined(CONFIG_STM32F0L0_USART4) || \
defined(CONFIG_STM32F0L0_USART5) || defined(CONFIG_STM32F0L0_USART6) || \
defined(CONFIG_STM32F0L0_USART7) || defined(CONFIG_STM32F0L0_USART8)
# define HAVE_USART 1
#endif
/* Sanity checks */
#if !defined(CONFIG_STM32F0_USART1)
# undef CONFIG_STM32F0_USART1_SERIALDRIVER
# undef CONFIG_STM32F0_USART1_1WIREDRIVER
#if !defined(CONFIG_STM32F0L0_USART1)
# undef CONFIG_STM32F0L0_USART1_SERIALDRIVER
# undef CONFIG_STM32F0L0_USART1_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32F0_USART2)
# undef CONFIG_STM32F0_USART2_SERIALDRIVER
# undef CONFIG_STM32F0_USART2_1WIREDRIVER
#if !defined(CONFIG_STM32F0L0_USART2)
# undef CONFIG_STM32F0L0_USART2_SERIALDRIVER
# undef CONFIG_STM32F0L0_USART2_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32F0_USART3)
# undef CONFIG_STM32F0_USART3_SERIALDRIVER
# undef CONFIG_STM32F0_USART3_1WIREDRIVER
#if !defined(CONFIG_STM32F0L0_USART3)
# undef CONFIG_STM32F0L0_USART3_SERIALDRIVER
# undef CONFIG_STM32F0L0_USART3_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32F0_USART4)
# undef CONFIG_STM32F0_USART4_SERIALDRIVER
# undef CONFIG_STM32F0_USART4_1WIREDRIVER
#if !defined(CONFIG_STM32F0L0_USART4)
# undef CONFIG_STM32F0L0_USART4_SERIALDRIVER
# undef CONFIG_STM32F0L0_USART4_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32F0_USART5)
# undef CONFIG_STM32F0_USART5_SERIALDRIVER
# undef CONFIG_STM32F0_USART5_1WIREDRIVER
#if !defined(CONFIG_STM32F0L0_USART5)
# undef CONFIG_STM32F0L0_USART5_SERIALDRIVER
# undef CONFIG_STM32F0L0_USART5_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32F0_USART6)
# undef CONFIG_STM32F0_USART6_SERIALDRIVER
# undef CONFIG_STM32F0_USART6_1WIREDRIVER
#if !defined(CONFIG_STM32F0L0_USART6)
# undef CONFIG_STM32F0L0_USART6_SERIALDRIVER
# undef CONFIG_STM32F0L0_USART6_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32F0_USART7)
# undef CONFIG_STM32F0_USART7_SERIALDRIVER
# undef CONFIG_STM32F0_USART7_1WIREDRIVER
#if !defined(CONFIG_STM32F0L0_USART7)
# undef CONFIG_STM32F0L0_USART7_SERIALDRIVER
# undef CONFIG_STM32F0L0_USART7_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32F0_USART8)
# undef CONFIG_STM32F0_USART8_SERIALDRIVER
# undef CONFIG_STM32F0_USART8_1WIREDRIVER
#if !defined(CONFIG_STM32F0L0_USART8)
# undef CONFIG_STM32F0L0_USART8_SERIALDRIVER
# undef CONFIG_STM32F0L0_USART8_1WIREDRIVER
#endif
/* Check 1-Wire and U(S)ART conflicts */
#if defined(CONFIG_STM32F0_USART1_1WIREDRIVER) && defined(CONFIG_STM32F0_USART1_SERIALDRIVER)
# error Both CONFIG_STM32F0_USART1_1WIREDRIVER and CONFIG_STM32F0_USART1_SERIALDRIVER defined
# undef CONFIG_STM32F0_USART1_1WIREDRIVER
#if defined(CONFIG_STM32F0L0_USART1_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART1_SERIALDRIVER)
# error Both CONFIG_STM32F0L0_USART1_1WIREDRIVER and CONFIG_STM32F0L0_USART1_SERIALDRIVER defined
# undef CONFIG_STM32F0L0_USART1_1WIREDRIVER
#endif
#if defined(CONFIG_STM32F0_USART2_1WIREDRIVER) && defined(CONFIG_STM32F0_USART2_SERIALDRIVER)
# error Both CONFIG_STM32F0_USART2_1WIREDRIVER and CONFIG_STM32F0_USART2_SERIALDRIVER defined
# undef CONFIG_STM32F0_USART2_1WIREDRIVER
#if defined(CONFIG_STM32F0L0_USART2_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART2_SERIALDRIVER)
# error Both CONFIG_STM32F0L0_USART2_1WIREDRIVER and CONFIG_STM32F0L0_USART2_SERIALDRIVER defined
# undef CONFIG_STM32F0L0_USART2_1WIREDRIVER
#endif
#if defined(CONFIG_STM32F0_USART3_1WIREDRIVER) && defined(CONFIG_STM32F0_USART3_SERIALDRIVER)
# error Both CONFIG_STM32F0_USART3_1WIREDRIVER and CONFIG_STM32F0_USART3_SERIALDRIVER defined
# undef CONFIG_STM32F0_USART3_1WIREDRIVER
#if defined(CONFIG_STM32F0L0_USART3_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART3_SERIALDRIVER)
# error Both CONFIG_STM32F0L0_USART3_1WIREDRIVER and CONFIG_STM32F0L0_USART3_SERIALDRIVER defined
# undef CONFIG_STM32F0L0_USART3_1WIREDRIVER
#endif
#if defined(CONFIG_STM32F0_USART4_1WIREDRIVER) && defined(CONFIG_STM32F0_USART4_SERIALDRIVER)
# error Both CONFIG_STM32F0_USART4_1WIREDRIVER and CONFIG_STM32F0_USART4_SERIALDRIVER defined
# undef CONFIG_STM32F0_USART4_1WIREDRIVER
#if defined(CONFIG_STM32F0L0_USART4_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART4_SERIALDRIVER)
# error Both CONFIG_STM32F0L0_USART4_1WIREDRIVER and CONFIG_STM32F0L0_USART4_SERIALDRIVER defined
# undef CONFIG_STM32F0L0_USART4_1WIREDRIVER
#endif
#if defined(CONFIG_STM32F0_USART5_1WIREDRIVER) && defined(CONFIG_STM32F0_USART5_SERIALDRIVER)
# error Both CONFIG_STM32F0_USART5_1WIREDRIVER and CONFIG_STM32F0_USART5_SERIALDRIVER defined
# undef CONFIG_STM32F0_USART5_1WIREDRIVER
#if defined(CONFIG_STM32F0L0_USART5_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART5_SERIALDRIVER)
# error Both CONFIG_STM32F0L0_USART5_1WIREDRIVER and CONFIG_STM32F0L0_USART5_SERIALDRIVER defined
# undef CONFIG_STM32F0L0_USART5_1WIREDRIVER
#endif
#if defined(CONFIG_STM32F0_USART6_1WIREDRIVER) && defined(CONFIG_STM32F0_USART6_SERIALDRIVER)
# error Both CONFIG_STM32F0_USART6_1WIREDRIVER and CONFIG_STM32F0_USART6_SERIALDRIVER defined
# undef CONFIG_STM32F0_USART6_1WIREDRIVER
#if defined(CONFIG_STM32F0L0_USART6_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART6_SERIALDRIVER)
# error Both CONFIG_STM32F0L0_USART6_1WIREDRIVER and CONFIG_STM32F0L0_USART6_SERIALDRIVER defined
# undef CONFIG_STM32F0L0_USART6_1WIREDRIVER
#endif
#if defined(CONFIG_STM32F0_USART7_1WIREDRIVER) && defined(CONFIG_STM32F0_USART7_SERIALDRIVER)
# error Both CONFIG_STM32F0_USART7_1WIREDRIVER and CONFIG_STM32F0_USART7_SERIALDRIVER defined
# undef CONFIG_STM32F0_USART7_1WIREDRIVER
#if defined(CONFIG_STM32F0L0_USART7_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART7_SERIALDRIVER)
# error Both CONFIG_STM32F0L0_USART7_1WIREDRIVER and CONFIG_STM32F0L0_USART7_SERIALDRIVER defined
# undef CONFIG_STM32F0L0_USART7_1WIREDRIVER
#endif
#if defined(CONFIG_STM32F0_USART8_1WIREDRIVER) && defined(CONFIG_STM32F0_USART8_SERIALDRIVER)
# error Both CONFIG_STM32F0_USART8_1WIREDRIVER and CONFIG_STM32F0_USART8_SERIALDRIVER defined
# undef CONFIG_STM32F0_USART8_1WIREDRIVER
#if defined(CONFIG_STM32F0L0_USART8_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART8_SERIALDRIVER)
# error Both CONFIG_STM32F0L0_USART8_1WIREDRIVER and CONFIG_STM32F0L0_USART8_SERIALDRIVER defined
# undef CONFIG_STM32F0L0_USART8_1WIREDRIVER
#endif
/* Is the serial driver enabled? */
#if defined(CONFIG_STM32F0_USART1_SERIALDRIVER) || defined(CONFIG_STM32F0_USART2_SERIALDRIVER) || \
defined(CONFIG_STM32F0_USART3_SERIALDRIVER) || defined(CONFIG_STM32F0_USART4_SERIALDRIVER) || \
defined(CONFIG_STM32F0_USART5_SERIALDRIVER) || defined(CONFIG_STM32F0_USART6_SERIALDRIVER) || \
defined(CONFIG_STM32F0_USART7_SERIALDRIVER) || defined(CONFIG_STM32F0_USART8_SERIALDRIVER)
#if defined(CONFIG_STM32F0L0_USART1_SERIALDRIVER) || defined(CONFIG_STM32F0L0_USART2_SERIALDRIVER) || \
defined(CONFIG_STM32F0L0_USART3_SERIALDRIVER) || defined(CONFIG_STM32F0L0_USART4_SERIALDRIVER) || \
defined(CONFIG_STM32F0L0_USART5_SERIALDRIVER) || defined(CONFIG_STM32F0L0_USART6_SERIALDRIVER) || \
defined(CONFIG_STM32F0L0_USART7_SERIALDRIVER) || defined(CONFIG_STM32F0L0_USART8_SERIALDRIVER)
# define HAVE_SERIALDRIVER 1
#endif
/* Is the 1-Wire driver? */
#if defined(CONFIG_STM32F0_USART1_1WIREDRIVER) || defined(CONFIG_STM32F0_USART2_1WIREDRIVER) || \
defined(CONFIG_STM32F0_USART3_1WIREDRIVER) || defined(CONFIG_STM32F0_USART4_1WIREDRIVER) || \
defined(CONFIG_STM32F0_USART5_1WIREDRIVER) || defined(CONFIG_STM32F0_USART6_1WIREDRIVER) || \
defined(CONFIG_STM32F0_USART7_1WIREDRIVER) || defined(CONFIG_STM32F0_USART8_1WIREDRIVER)
#if defined(CONFIG_STM32F0L0_USART1_1WIREDRIVER) || defined(CONFIG_STM32F0L0_USART2_1WIREDRIVER) || \
defined(CONFIG_STM32F0L0_USART3_1WIREDRIVER) || defined(CONFIG_STM32F0L0_USART4_1WIREDRIVER) || \
defined(CONFIG_STM32F0L0_USART5_1WIREDRIVER) || defined(CONFIG_STM32F0L0_USART6_1WIREDRIVER) || \
defined(CONFIG_STM32F0L0_USART7_1WIREDRIVER) || defined(CONFIG_STM32F0L0_USART8_1WIREDRIVER)
# define HAVE_1WIREDRIVER 1
#endif
/* Is there a serial console? */
#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F0_USART1_SERIALDRIVER)
#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART1_SERIALDRIVER)
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_USART4_SERIAL_CONSOLE
@ -216,7 +216,7 @@
# undef CONFIG_USART8_SERIAL_CONSOLE
# define CONSOLE_USART 1
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F0_USART2_SERIALDRIVER)
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART2_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_USART4_SERIAL_CONSOLE
@ -226,7 +226,7 @@
# undef CONFIG_USART8_SERIAL_CONSOLE
# define CONSOLE_USART 2
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F0_USART3_SERIALDRIVER)
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART3_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART4_SERIAL_CONSOLE
@ -236,7 +236,7 @@
# undef CONFIG_USART8_SERIAL_CONSOLE
# define CONSOLE_USART 3
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F0_USART4_SERIALDRIVER)
#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART4_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -246,7 +246,7 @@
# undef CONFIG_USART8_SERIAL_CONSOLE
# define CONSOLE_USART 4
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART5_SERIAL_CONSOLE) && defined(CONFIG_STM32F0_USART5_SERIALDRIVER)
#elif defined(CONFIG_USART5_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART5_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -256,7 +256,7 @@
# undef CONFIG_USART8_SERIAL_CONSOLE
# define CONSOLE_USART 5
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32F0_USART6_SERIALDRIVER)
#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART6_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -266,7 +266,7 @@
# undef CONFIG_USART8_SERIAL_CONSOLE
# define CONSOLE_USART 6
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART7_SERIAL_CONSOLE) && defined(CONFIG_STM32F0_USART7_SERIALDRIVER)
#elif defined(CONFIG_USART7_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART7_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -277,7 +277,7 @@
# undef CONFIG_USART8_SERIAL_CONSOLE
# define CONSOLE_USART 7
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART8_SERIAL_CONSOLE) && defined(CONFIG_STM32F0_USART8_SERIALDRIVER)
#elif defined(CONFIG_USART8_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART8_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -315,35 +315,35 @@
/* Disable the DMA configuration on all unused USARTs */
#ifndef CONFIG_STM32F0_USART1_SERIALDRIVER
#ifndef CONFIG_STM32F0L0_USART1_SERIALDRIVER
# undef CONFIG_USART1_RXDMA
#endif
#ifndef CONFIG_STM32F0_USART2_SERIALDRIVER
#ifndef CONFIG_STM32F0L0_USART2_SERIALDRIVER
# undef CONFIG_USART2_RXDMA
#endif
#ifndef CONFIG_STM32F0_USART3_SERIALDRIVER
#ifndef CONFIG_STM32F0L0_USART3_SERIALDRIVER
# undef CONFIG_USART3_RXDMA
#endif
#ifndef CONFIG_STM32F0_USART4_SERIALDRIVER
#ifndef CONFIG_STM32F0L0_USART4_SERIALDRIVER
# undef CONFIG_USART4_RXDMA
#endif
#ifndef CONFIG_STM32F0_USART5_SERIALDRIVER
#ifndef CONFIG_STM32F0L0_USART5_SERIALDRIVER
# undef CONFIG_USART5_RXDMA
#endif
#ifndef CONFIG_STM32F0_USART6_SERIALDRIVER
#ifndef CONFIG_STM32F0L0_USART6_SERIALDRIVER
# undef CONFIG_USART6_RXDMA
#endif
#ifndef CONFIG_STM32F0_USART7_SERIALDRIVER
#ifndef CONFIG_STM32F0L0_USART7_SERIALDRIVER
# undef CONFIG_USART7_RXDMA
#endif
#ifndef CONFIG_STM32F0_USART8_SERIALDRIVER
#ifndef CONFIG_STM32F0L0_USART8_SERIALDRIVER
# undef CONFIG_USART8_RXDMA
#endif
@ -381,21 +381,21 @@
/* Is DMA used on all (enabled) USARTs */
#define SERIAL_HAVE_ONLY_DMA 1
#if defined(CONFIG_STM32F0_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA)
#if defined(CONFIG_STM32F0L0_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32F0_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA)
#elif defined(CONFIG_STM32F0L0_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32F0_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA)
#elif defined(CONFIG_STM32F0L0_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32F0_USART4_SERIALDRIVER) && !defined(CONFIG_USART4_RXDMA)
#elif defined(CONFIG_STM32F0L0_USART4_SERIALDRIVER) && !defined(CONFIG_USART4_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32F0_USART5_SERIALDRIVER) && !defined(CONFIG_USART5_RXDMA)
#elif defined(CONFIG_STM32F0L0_USART5_SERIALDRIVER) && !defined(CONFIG_USART5_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32F0_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA)
#elif defined(CONFIG_STM32F0L0_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32F0_USART7_SERIALDRIVER) && !defined(CONFIG_USART7_RXDMA)
#elif defined(CONFIG_STM32F0L0_USART7_SERIALDRIVER) && !defined(CONFIG_USART7_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32F0_USART8_SERIALDRIVER) && !defined(CONFIG_USART8_RXDMA)
#elif defined(CONFIG_STM32F0L0_USART8_SERIALDRIVER) && !defined(CONFIG_USART8_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#endif
@ -438,7 +438,7 @@ extern "C"
************************************************************************************/
/************************************************************************************
* Name: stm32f0_serial_dma_poll
* Name: stm32_serial_dma_poll
*
* Description:
* Must be called periodically if any STM32 USART is configured for DMA. The DMA
@ -451,7 +451,7 @@ extern "C"
************************************************************************************/
#ifdef SERIAL_HAVE_DMA
void stm32f0_serial_dma_poll(void);
void stm32_serial_dma_poll(void);
#endif
#undef EXTERN
@ -460,4 +460,4 @@ void stm32f0_serial_dma_poll(void);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_STC_STM32F0_STM32F0_UART_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_UART_H */

1578
arch/arm/src/stm32f0/stm32f0_usbdev.c → arch/arm/src/stm32f0l0/stm32_usbdev.c
View file

File diff suppressed because it is too large Load diff

22
arch/arm/src/stm32f0/stm32f0_usbdev.h → arch/arm/src/stm32f0l0/stm32_usbdev.h
View file

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/stm32f0_usbdev.h
* arch/arm/src/stm32f0l0/stm32_usbdev.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_USBDEV_H
#define __ARCH_ARM_SRC_STM32F0_STM32F0_USBDEV_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_USBDEV_H
#define __ARCH_ARM_SRC_STM32F0L0_STM32_USBDEV_H
/************************************************************************************
* Included Files
@ -45,7 +45,7 @@
#include <stdint.h>
#include "chip.h"
#include "chip/stm32f0_usbdev.h"
#include "hardware/stm32_usbdev.h"
/************************************************************************************
* Public Functions
@ -63,29 +63,29 @@ extern "C"
#endif
/************************************************************************************
* Name: stm32f0_usbpullup
* Name: stm32_usbpullup
*
* Description:
* If USB is supported and the board supports a pullup via GPIO (for USB software
* connect and disconnect), then the board software must provide stm32f0_pullup.
* connect and disconnect), then the board software must provide stm32_pullup.
* See include/nuttx/usb/usbdev.h for additional description of this method.
*
************************************************************************************/
int stm32f0_usbpullup(FAR struct usbdev_s *dev, bool enable);
int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable);
/************************************************************************************
* Name: stm32f0_usbsuspend
* Name: stm32_usbsuspend
*
* Description:
* Board logic must provide the stm32f0_usbsuspend logic if the USBDEV driver is
* Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is
* used. This function is called whenever the USB enters or leaves suspend mode.
* This is an opportunity for the board logic to shutdown clocks, power, etc.
* while the USB is suspended.
*
************************************************************************************/
void stm32f0_usbsuspend(FAR struct usbdev_s *dev, bool resume);
void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume);
#undef EXTERN
#if defined(__cplusplus)
@ -93,4 +93,4 @@ void stm32f0_usbsuspend(FAR struct usbdev_s *dev, bool resume);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_USBDEV_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_USBDEV_H */

82
configs/nucleo-f072rb/include/board.h
View file

@ -72,14 +72,14 @@
* Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins.
*/
#define STM32F0_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/
#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/
#define STM32F0_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */
#define STM32F0_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */
#define STM32F0_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */
#define STM32F0_HSE_FREQUENCY STM32F0_BOARD_XTAL
#define STM32F0_LSI_FREQUENCY 40000 /* Approximately 40KHz */
#define STM32F0_LSE_FREQUENCY 32768 /* X2 on board */
#define STM32_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */
#define STM32_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */
#define STM32_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
#define STM32_LSI_FREQUENCY 40000 /* Approximately 40KHz */
#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
/* PLL Configuration
*
@ -93,7 +93,7 @@
* If the USB interface is used in the application, it requires a precise
* 48MHz clock which can be generated from either the (1) the internal
* main PLL with the HSE clock source using an HSE crystal oscillator. In
* this case, the PLL VCO clock (defined by STM32F0_CFGR_PLLMUL) must be
* this case, the PLL VCO clock (defined by STM32_CFGR_PLLMUL) must be
* programmed to output a 96 MHz frequency. This is required to provide a
* 48MHz clock to the (USBCLK = PLLVCO/2). Or (2) by using the internal
* 48MHz oscillator in automatic trimming mode. The synchronization for
@ -111,63 +111,63 @@
* PLL source).
*/
#define STM32F0_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */
#define STM32F0_PLLSRC_FREQUENCY (STM32F0_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */
#ifdef CONFIG_STM32F0_USB
# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */
# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
# define STM32F0_PLL_FREQUENCY (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */
#define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */
#ifdef CONFIG_STM32F0L0_USB
# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */
# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
#else
# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */
# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
# define STM32F0_PLL_FREQUENCY (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */
# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
#endif
/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output
* frequency (STM32F0_PLL_FREQUENCY divided by the PLLDIV value).
* frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value).
*/
#define STM32F0_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */
#define STM32F0_SYSCLK_SWS RCC_CFGR_SWS_PLL
#ifdef CONFIG_STM32F0_USB
# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */
#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
#ifdef CONFIG_STM32F0L0_USB
# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
#else
# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
#endif
#define STM32F0_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32F0_HCLK_FREQUENCY STM32F0_SYSCLK_FREQUENCY
#define STM32F0_BOARD_HCLK STM32F0_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK (48MHz) */
#define STM32F0_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK
#define STM32F0_PCLK1_FREQUENCY (STM32F0_HCLK_FREQUENCY)
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY)
/* APB2 clock (PCLK2) is HCLK (48MHz) */
#define STM32F0_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
#define STM32F0_PCLK2_FREQUENCY STM32F0_HCLK_FREQUENCY
#define STM32F0_APB2_CLKIN (STM32F0_PCLK2_FREQUENCY)
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY)
/* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */
#define STM32F0_APB1_TIM1_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM2_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM3_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32_APB1_TIM1_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM6_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM7_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM14_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM15_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM16_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM17_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM15_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM16_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM17_CLKIN (STM32_PCLK1_FREQUENCY)
/* LED definitions ******************************************************************/
/* LEDs
*
* The Nucleo-64 board has one user controlable LED, User LD2. This green
* The Nucleo-64 board has one user controllable LED, User LD2. This green
* LED is a user LED connected to Arduino signal D13 corresponding to STM32
* I/O PA5 (PB13 on other some other Nucleo-64 boards).
*

4
configs/nucleo-f072rb/nsh/defconfig
View file

@ -48,8 +48,8 @@ CONFIG_START_DAY=19
CONFIG_START_MONTH=5
CONFIG_START_YEAR=2013
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_STM32F0_PWR=y
CONFIG_STM32F0_USART2=y
CONFIG_STM32F0L0_PWR=y
CONFIG_STM32F0L0_USART2=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536

20
configs/nucleo-f072rb/src/nucleo-f072rb.h
View file

@ -45,7 +45,7 @@
#include <nuttx/compiler.h>
#include <stdint.h>
#include "stm32f0_gpio.h"
#include "stm32_gpio.h"
/****************************************************************************
* Pre-processor Definitions
@ -54,15 +54,15 @@
/* Configuration ************************************************************/
/* How many SPI modules does this chip support? */
#if STM32F0_NSPI < 1
# undef CONFIG_STM32F0_SPI1
# undef CONFIG_STM32F0_SPI2
# undef CONFIG_STM32F0_SPI3
#elif STM32F0_NSPI < 2
# undef CONFIG_STM32F0_SPI2
# undef CONFIG_STM32F0_SPI3
#elif STM32F0_NSPI < 3
# undef CONFIG_STM32F0_SPI3
#if STM32_NSPI < 1
# undef CONFIG_STM32F0L0_SPI1
# undef CONFIG_STM32F0L0_SPI2
# undef CONFIG_STM32F0L0_SPI3
#elif STM32_NSPI < 2
# undef CONFIG_STM32F0L0_SPI2
# undef CONFIG_STM32F0L0_SPI3
#elif STM32_NSPI < 3
# undef CONFIG_STM32F0L0_SPI3
#endif
/* Nucleo-F072RB GPIOs ******************************************************/

8
configs/nucleo-f072rb/src/stm32_autoleds.c
View file

@ -49,7 +49,7 @@
#include "chip.h"
#include "up_arch.h"
#include "up_internal.h"
#include "stm32f0_gpio.h"
#include "stm32_gpio.h"
#include "nucleo-f072rb.h"
#ifdef CONFIG_ARCH_LEDS
@ -66,7 +66,7 @@ void board_autoled_initialize(void)
{
/* Configure LD2 GPIO for output */
stm32f0_configgpio(GPIO_LD2);
stm32_configgpio(GPIO_LD2);
}
/****************************************************************************
@ -77,7 +77,7 @@ void board_autoled_on(int led)
{
if (led == 1)
{
stm32f0_gpiowrite(GPIO_LD2, true);
stm32_gpiowrite(GPIO_LD2, true);
}
}
@ -89,7 +89,7 @@ void board_autoled_off(int led)
{
if (led == 1)
{
stm32f0_gpiowrite(GPIO_LD2, false);
stm32_gpiowrite(GPIO_LD2, false);
}
}

8
configs/nucleo-f072rb/src/stm32_boot.c
View file

@ -1,5 +1,5 @@
/************************************************************************************
* configs/nucleo-f072rb/src/stm32f0_boot.c
* configs/nucleo-f072rb/src/stm32f072rb_boot.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -53,16 +53,16 @@
************************************************************************************/
/************************************************************************************
* Name: stm32f0_boardinitialize
* Name: stm32_boardinitialize
*
* Description:
* All STM32 architectures must provide the following entry point. This entry point
* is called early in the intitialization -- after all memory has been configured
* is called early in the initialization -- after all memory has been configured
* and mapped but before any devices have been initialized.
*
************************************************************************************/
void stm32f0_boardinitialize(void)
void stm32_boardinitialize(void)
{
#ifdef CONFIG_ARCH_LEDS
/* Configure on-board LEDs if LED support has been selected. */

6
configs/nucleo-f072rb/src/stm32_bringup.c
View file

@ -45,7 +45,7 @@
#include <nuttx/i2c/i2c_master.h>
#include "stm32f0_i2c.h"
#include "stm32_i2c.h"
#include "nucleo-f072rb.h"
/****************************************************************************
@ -53,7 +53,7 @@
****************************************************************************/
#undef HAVE_I2C_DRIVER
#if defined(CONFIG_STM32F0_I2C1) && defined(CONFIG_I2C_DRIVER)
#if defined(CONFIG_STM32F0L0_I2C1) && defined(CONFIG_I2C_DRIVER)
# define HAVE_I2C_DRIVER 1
#endif
@ -95,7 +95,7 @@ int stm32_bringup(void)
#ifdef HAVE_I2C_DRIVER
/* Get the I2C lower half instance */
i2c = stm32f0_i2cbus_initialize(1);
i2c = stm32_i2cbus_initialize(1);
if (i2c == NULL)
{
i2cerr("ERROR: Inialize I2C1: %d\n", ret);

8
configs/nucleo-f072rb/src/stm32_buttons.c
View file

@ -47,7 +47,7 @@
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "stm32f0_gpio.h"
#include "stm32_gpio.h"
#include "nucleo-f072rb.h"
#ifdef CONFIG_ARCH_BUTTONS
@ -73,7 +73,7 @@ void board_button_initialize(void)
* also configured for the pin.
*/
stm32f0_configgpio(GPIO_BTN_USER);
stm32_configgpio(GPIO_BTN_USER);
}
/****************************************************************************
@ -86,7 +86,7 @@ uint32_t board_buttons(void)
* pressed.
*/
bool released = stm32f0_gpioread(GPIO_BTN_USER);
bool released = stm32_gpioread(GPIO_BTN_USER);
return !released;
}
@ -119,7 +119,7 @@ int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg)
if (id == BUTTON_USER)
{
ret = stm32f0_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg);
ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg);
}
return ret;

12
configs/nucleo-f072rb/src/stm32_userleds.c
View file

@ -49,7 +49,7 @@
#include "chip.h"
#include "up_arch.h"
#include "up_internal.h"
#include "stm32f0_gpio.h"
#include "stm32_gpio.h"
#include "nucleo-f072rb.h"
#ifndef CONFIG_ARCH_LEDS
@ -172,7 +172,7 @@ void board_userled_initialize(void)
{
/* Configure LD2 GPIO for output */
stm32f0_configgpio(GPIO_LD2);
stm32_configgpio(GPIO_LD2);
}
/****************************************************************************
@ -183,7 +183,7 @@ void board_userled(int led, bool ledon)
{
if (led == BOARD_LD2)
{
stm32f0_gpiowrite(GPIO_LD2, ledon);
stm32_gpiowrite(GPIO_LD2, ledon);
}
}
@ -193,15 +193,15 @@ void board_userled(int led, bool ledon)
void board_userled_all(uint8_t ledset)
{
stm32f0_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0);
stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0);
}
/****************************************************************************
* Name: stm32f0_led_pminitialize
* Name: stm32_led_pminitialize
****************************************************************************/
#ifdef CONFIG_PM
void stm32f0_led_pminitialize(void)
void stm32_led_pminitialize(void)
{
/* Register to receive power management callbacks */

80
configs/nucleo-f091rc/include/board.h
View file

@ -72,14 +72,14 @@
* Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins.
*/
#define STM32F0_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/
#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/
#define STM32F0_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */
#define STM32F0_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */
#define STM32F0_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */
#define STM32F0_HSE_FREQUENCY STM32F0_BOARD_XTAL
#define STM32F0_LSI_FREQUENCY 40000 /* Approximately 40KHz */
#define STM32F0_LSE_FREQUENCY 32768 /* X2 on board */
#define STM32_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */
#define STM32_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */
#define STM32_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
#define STM32_LSI_FREQUENCY 40000 /* Approximately 40KHz */
#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
/* PLL Configuration
*
@ -93,7 +93,7 @@
* If the USB interface is used in the application, it requires a precise
* 48MHz clock which can be generated from either the (1) the internal
* main PLL with the HSE clock source using an HSE crystal oscillator. In
* this case, the PLL VCO clock (defined by STM32F0_CFGR_PLLMUL) must be
* this case, the PLL VCO clock (defined by STM32_CFGR_PLLMUL) must be
* programmed to output a 96 MHz frequency. This is required to provide a
* 48MHz clock to the (USBCLK = PLLVCO/2). Or (2) by using the internal
* 48MHz oscillator in automatic trimming mode. The synchronization for
@ -111,58 +111,58 @@
* PLL source).
*/
#define STM32F0_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */
#define STM32F0_PLLSRC_FREQUENCY (STM32F0_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */
#ifdef CONFIG_STM32F0_USB
# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */
# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
# define STM32F0_PLL_FREQUENCY (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */
#define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */
#ifdef CONFIG_STM32F0L0_USB
# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */
# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
#else
# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */
# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
# define STM32F0_PLL_FREQUENCY (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */
# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
#endif
/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output
* frequency (STM32F0_PLL_FREQUENCY divided by the PLLDIV value).
* frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value).
*/
#define STM32F0_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */
#define STM32F0_SYSCLK_SWS RCC_CFGR_SWS_PLL
#ifdef CONFIG_STM32F0_USB
# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */
#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
#ifdef CONFIG_STM32F0L0_USB
# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
#else
# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
#endif
#define STM32F0_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32F0_HCLK_FREQUENCY STM32F0_SYSCLK_FREQUENCY
#define STM32F0_BOARD_HCLK STM32F0_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK (48MHz) */
#define STM32F0_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK
#define STM32F0_PCLK1_FREQUENCY (STM32F0_HCLK_FREQUENCY)
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY)
/* APB2 clock (PCLK2) is HCLK (48MHz) */
#define STM32F0_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
#define STM32F0_PCLK2_FREQUENCY STM32F0_HCLK_FREQUENCY
#define STM32F0_APB2_CLKIN (STM32F0_PCLK2_FREQUENCY)
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY)
/* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */
#define STM32F0_APB1_TIM1_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM2_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM3_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32_APB1_TIM1_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM6_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM7_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM14_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM15_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM16_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM17_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM15_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM16_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM17_CLKIN (STM32_PCLK1_FREQUENCY)
/* LED definitions ******************************************************************/
/* LEDs

4
configs/nucleo-f091rc/nsh/defconfig
View file

@ -51,8 +51,8 @@ CONFIG_START_DAY=19
CONFIG_START_MONTH=5
CONFIG_START_YEAR=2013
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_STM32F0_PWR=y
CONFIG_STM32F0_USART2=y
CONFIG_STM32F0L0_PWR=y
CONFIG_STM32F0L0_USART2=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
CONFIG_USART2_SERIAL_CONSOLE=y

20
configs/nucleo-f091rc/src/nucleo-f091rc.h
View file

@ -45,7 +45,7 @@
#include <nuttx/compiler.h>
#include <stdint.h>
#include "stm32f0_gpio.h"
#include "stm32_gpio.h"
/****************************************************************************
* Pre-processor Definitions
@ -54,15 +54,15 @@
/* Configuration ************************************************************/
/* How many SPI modules does this chip support? */
#if STM32F0_NSPI < 1
# undef CONFIG_STM32F0_SPI1
# undef CONFIG_STM32F0_SPI2
# undef CONFIG_STM32F0_SPI3
#elif STM32F0_NSPI < 2
# undef CONFIG_STM32F0_SPI2
# undef CONFIG_STM32F0_SPI3
#elif STM32F0_NSPI < 3
# undef CONFIG_STM32F0_SPI3
#if STM32_NSPI < 1
# undef CONFIG_STM32F0L0_SPI1
# undef CONFIG_STM32F0L0_SPI2
# undef CONFIG_STM32F0L0_SPI3
#elif STM32_NSPI < 2
# undef CONFIG_STM32F0L0_SPI2
# undef CONFIG_STM32F0L0_SPI3
#elif STM32_NSPI < 3
# undef CONFIG_STM32F0L0_SPI3
#endif
/* Nucleo-F091RC GPIOs ******************************************************/

8
configs/nucleo-f091rc/src/stm32_autoleds.c
View file

@ -49,7 +49,7 @@
#include "chip.h"
#include "up_arch.h"
#include "up_internal.h"
#include "stm32f0_gpio.h"
#include "stm32_gpio.h"
#include "nucleo-f091rc.h"
#ifdef CONFIG_ARCH_LEDS
@ -66,7 +66,7 @@ void board_autoled_initialize(void)
{
/* Configure LD2 GPIO for output */
stm32f0_configgpio(GPIO_LD2);
stm32_configgpio(GPIO_LD2);
}
/****************************************************************************
@ -77,7 +77,7 @@ void board_autoled_on(int led)
{
if (led == 1)
{
stm32f0_gpiowrite(GPIO_LD2, true);
stm32_gpiowrite(GPIO_LD2, true);
}
}
@ -89,7 +89,7 @@ void board_autoled_off(int led)
{
if (led == 1)
{
stm32f0_gpiowrite(GPIO_LD2, false);
stm32_gpiowrite(GPIO_LD2, false);
}
}

6
configs/nucleo-f091rc/src/stm32_boot.c
View file

@ -1,5 +1,5 @@
/************************************************************************************
* configs/nucleo-f091rc/src/stm32f0_boot.c
* configs/nucleo-f091rc/src/stm32_boot.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -53,7 +53,7 @@
************************************************************************************/
/************************************************************************************
* Name: stm32f0_boardinitialize
* Name: stm32_boardinitialize
*
* Description:
* All STM32 architectures must provide the following entry point. This entry point
@ -62,7 +62,7 @@
*
************************************************************************************/
void stm32f0_boardinitialize(void)
void stm32_boardinitialize(void)
{
#ifdef CONFIG_ARCH_LEDS
/* Configure on-board LEDs if LED support has been selected. */

8
configs/nucleo-f091rc/src/stm32_buttons.c
View file

@ -47,7 +47,7 @@
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "stm32f0_gpio.h"
#include "stm32_gpio.h"
#include "nucleo-f091rc.h"
#ifdef CONFIG_ARCH_BUTTONS
@ -73,7 +73,7 @@ void board_button_initialize(void)
* also configured for the pin.
*/
stm32f0_configgpio(GPIO_BTN_USER);
stm32_configgpio(GPIO_BTN_USER);
}
/****************************************************************************
@ -86,7 +86,7 @@ uint32_t board_buttons(void)
* pressed.
*/
bool released = stm32f0_gpioread(GPIO_BTN_USER);
bool released = stm32_gpioread(GPIO_BTN_USER);
return !released;
}
@ -119,7 +119,7 @@ int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg)
if (id == BUTTON_USER)
{
ret = stm32f0_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg);
ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg);
}
return ret;

12
configs/nucleo-f091rc/src/stm32_userleds.c
View file

@ -49,7 +49,7 @@
#include "chip.h"
#include "up_arch.h"
#include "up_internal.h"
#include "stm32f0_gpio.h"
#include "stm32_gpio.h"
#include "nucleo-f091rc.h"
#ifndef CONFIG_ARCH_LEDS
@ -172,7 +172,7 @@ void board_userled_initialize(void)
{
/* Configure LD2 GPIO for output */
stm32f0_configgpio(GPIO_LD2);
stm32_configgpio(GPIO_LD2);
}
/****************************************************************************
@ -183,7 +183,7 @@ void board_userled(int led, bool ledon)
{
if (led == BOARD_LD2)
{
stm32f0_gpiowrite(GPIO_LD2, ledon);
stm32_gpiowrite(GPIO_LD2, ledon);
}
}
@ -193,15 +193,15 @@ void board_userled(int led, bool ledon)
void board_userled_all(uint8_t ledset)
{
stm32f0_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0);
stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0);
}
/****************************************************************************
* Name: stm32f0_led_pminitialize
* Name: stm32_led_pminitialize
****************************************************************************/
#ifdef CONFIG_PM
void stm32f0_led_pminitialize(void)
void stm32_led_pminitialize(void)
{
/* Register to receive power management callbacks */

80
configs/stm32f051-discovery/include/board.h
View file

@ -72,14 +72,14 @@
* Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins.
*/
#define STM32F0_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/
#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/
#define STM32F0_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */
#define STM32F0_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */
#define STM32F0_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */
#define STM32F0_HSE_FREQUENCY STM32F0_BOARD_XTAL
#define STM32F0_LSI_FREQUENCY 40000 /* Approximately 40KHz */
#define STM32F0_LSE_FREQUENCY 32768 /* X2 on board */
#define STM32_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */
#define STM32_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */
#define STM32_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
#define STM32_LSI_FREQUENCY 40000 /* Approximately 40KHz */
#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
/* PLL Configuration
*
@ -93,7 +93,7 @@
* If the USB interface is used in the application, it requires a precise
* 48MHz clock which can be generated from either the (1) the internal
* main PLL with the HSE clock source using an HSE crystal oscillator. In
* this case, the PLL VCO clock (defined by STM32F0_CFGR_PLLMUL) must be
* this case, the PLL VCO clock (defined by STM32_CFGR_PLLMUL) must be
* programmed to output a 96 MHz frequency. This is required to provide a
* 48MHz clock to the (USBCLK = PLLVCO/2). Or (2) by using the internal
* 48MHz oscillator in automatic trimming mode. The synchronization for
@ -111,58 +111,58 @@
* PLL source).
*/
#define STM32F0_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */
#define STM32F0_PLLSRC_FREQUENCY (STM32F0_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */
#ifdef CONFIG_STM32F0_USB
# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */
# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
# define STM32F0_PLL_FREQUENCY (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */
#define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */
#ifdef CONFIG_STM32F0L0_USB
# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */
# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
#else
# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */
# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
# define STM32F0_PLL_FREQUENCY (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */
# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
#endif
/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output
* frequency (STM32F0_PLL_FREQUENCY divided by the PLLDIV value).
* frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value).
*/
#define STM32F0_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */
#define STM32F0_SYSCLK_SWS RCC_CFGR_SWS_PLL
#ifdef CONFIG_STM32F0_USB
# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */
#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
#ifdef CONFIG_STM32F0L0_USB
# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
#else
# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
#endif
#define STM32F0_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32F0_HCLK_FREQUENCY STM32F0_SYSCLK_FREQUENCY
#define STM32F0_BOARD_HCLK STM32F0_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK (48MHz) */
#define STM32F0_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK
#define STM32F0_PCLK1_FREQUENCY (STM32F0_HCLK_FREQUENCY)
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY)
/* APB2 clock (PCLK2) is HCLK (48MHz) */
#define STM32F0_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
#define STM32F0_PCLK2_FREQUENCY STM32F0_HCLK_FREQUENCY
#define STM32F0_APB2_CLKIN (STM32F0_PCLK2_FREQUENCY)
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY)
/* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */
#define STM32F0_APB1_TIM1_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM2_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM3_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32_APB1_TIM1_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM6_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM7_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM14_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM15_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM16_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM17_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM15_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM16_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM17_CLKIN (STM32_PCLK1_FREQUENCY)
/* LED definitions ******************************************************************/
/* The STM32F0-Discovery board has four LEDs. Two of these are controlled by

4
configs/stm32f051-discovery/nsh/defconfig
View file

@ -44,8 +44,8 @@ CONFIG_START_DAY=19
CONFIG_START_MONTH=5
CONFIG_START_YEAR=2013
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_STM32F0_PWR=y
CONFIG_STM32F0_USART1=y
CONFIG_STM32F0L0_PWR=y
CONFIG_STM32F0L0_USART1=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536

2
configs/stm32f051-discovery/src/Makefile
View file

@ -49,7 +49,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y)
CSRCS += stm32_buttons.c
endif
ifeq ($(CONFIG_STM32F0_SPI),y)
ifeq ($(CONFIG_STM32F0L0_SPI),y)
CSRCS += stm32_spi.c
endif

12
configs/stm32f051-discovery/src/stm32_autoleds.c
View file

@ -86,8 +86,8 @@ void board_autoled_initialize(void)
{
/* Configure LED1-2 GPIOs for output */
stm32f0_configgpio(GPIO_LED1);
stm32f0_configgpio(GPIO_LED2);
stm32_configgpio(GPIO_LED1);
stm32_configgpio(GPIO_LED2);
}
/****************************************************************************
@ -117,8 +117,8 @@ void board_autoled_on(int led)
break;
}
stm32f0_gpiowrite(GPIO_LED1, led1on);
stm32f0_gpiowrite(GPIO_LED2, led2on);
stm32_gpiowrite(GPIO_LED1, led1on);
stm32_gpiowrite(GPIO_LED2, led2on);
}
/****************************************************************************
@ -129,8 +129,8 @@ void board_autoled_off(int led)
{
if (led != 2)
{
stm32f0_gpiowrite(GPIO_LED1, false);
stm32f0_gpiowrite(GPIO_LED2, false);
stm32_gpiowrite(GPIO_LED1, false);
stm32_gpiowrite(GPIO_LED2, false);
}
}

6
configs/stm32f051-discovery/src/stm32_boot.c
View file

@ -1,5 +1,5 @@
/************************************************************************************
* configs/stm32f051-discovery/src/stm32f0_boot.c
* configs/stm32f051-discovery/src/stm32_boot.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -53,7 +53,7 @@
************************************************************************************/
/************************************************************************************
* Name: stm32f0_boardinitialize
* Name: stm32_boardinitialize
*
* Description:
* All STM32 architectures must provide the following entry point. This entry point
@ -62,7 +62,7 @@
*
************************************************************************************/
void stm32f0_boardinitialize(void)
void stm32_boardinitialize(void)
{
#ifdef CONFIG_ARCH_LEDS
/* Configure on-board LEDs if LED support has been selected. */

20
configs/stm32f051-discovery/src/stm32f051-discovery.h
View file

@ -45,7 +45,7 @@
#include <nuttx/compiler.h>
#include <stdint.h>
#include "stm32f0_gpio.h"
#include "stm32_gpio.h"
/****************************************************************************************************
* Pre-processor Definitions
@ -54,15 +54,15 @@
/* Configuration ************************************************************************************/
/* How many SPI modules does this chip support? */
#if STM32F0_NSPI < 1
# undef CONFIG_STM32F0_SPI1
# undef CONFIG_STM32F0_SPI2
# undef CONFIG_STM32F0_SPI3
#elif STM32F0_NSPI < 2
# undef CONFIG_STM32F0_SPI2
# undef CONFIG_STM32F0_SPI3
#elif STM32F0_NSPI < 3
# undef CONFIG_STM32F0_SPI3
#if STM32_NSPI < 1
# undef CONFIG_STM32F0L0_SPI1
# undef CONFIG_STM32F0L0_SPI2
# undef CONFIG_STM32F0L0_SPI3
#elif STM32_NSPI < 2
# undef CONFIG_STM32F0L0_SPI2
# undef CONFIG_STM32F0L0_SPI3
#elif STM32_NSPI < 3
# undef CONFIG_STM32F0L0_SPI3
#endif
/* STM32F0Discovery GPIOs ***************************************************************************/

80
configs/stm32f072-discovery/include/board.h
View file

@ -72,14 +72,14 @@
* Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins.
*/
#define STM32F0_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/
#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/
#define STM32F0_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */
#define STM32F0_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */
#define STM32F0_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */
#define STM32F0_HSE_FREQUENCY STM32F0_BOARD_XTAL
#define STM32F0_LSI_FREQUENCY 40000 /* Approximately 40KHz */
#define STM32F0_LSE_FREQUENCY 32768 /* X2 on board */
#define STM32_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */
#define STM32_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */
#define STM32_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
#define STM32_LSI_FREQUENCY 40000 /* Approximately 40KHz */
#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
/* PLL Configuration
*
@ -93,7 +93,7 @@
* If the USB interface is used in the application, it requires a precise
* 48MHz clock which can be generated from either the (1) the internal
* main PLL with the HSE clock source using an HSE crystal oscillator. In
* this case, the PLL VCO clock (defined by STM32F0_CFGR_PLLMUL) must be
* this case, the PLL VCO clock (defined by STM32_CFGR_PLLMUL) must be
* programmed to output a 96 MHz frequency. This is required to provide a
* 48MHz clock to the (USBCLK = PLLVCO/2). Or (2) by using the internal
* 48MHz oscillator in automatic trimming mode. The synchronization for
@ -111,58 +111,58 @@
* PLL source).
*/
#define STM32F0_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */
#define STM32F0_PLLSRC_FREQUENCY (STM32F0_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */
#ifdef CONFIG_STM32F0_USB
# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */
# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
# define STM32F0_PLL_FREQUENCY (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */
#define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */
#ifdef CONFIG_STM32F0L0_USB
# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */
# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
#else
# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */
# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
# define STM32F0_PLL_FREQUENCY (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */
# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
#endif
/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output
* frequency (STM32F0_PLL_FREQUENCY divided by the PLLDIV value).
* frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value).
*/
#define STM32F0_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */
#define STM32F0_SYSCLK_SWS RCC_CFGR_SWS_PLL
#ifdef CONFIG_STM32F0_USB
# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */
#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
#ifdef CONFIG_STM32F0L0_USB
# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
#else
# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
#endif
#define STM32F0_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32F0_HCLK_FREQUENCY STM32F0_SYSCLK_FREQUENCY
#define STM32F0_BOARD_HCLK STM32F0_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK (48MHz) */
#define STM32F0_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK
#define STM32F0_PCLK1_FREQUENCY (STM32F0_HCLK_FREQUENCY)
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY)
/* APB2 clock (PCLK2) is HCLK (48MHz) */
#define STM32F0_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
#define STM32F0_PCLK2_FREQUENCY STM32F0_HCLK_FREQUENCY
#define STM32F0_APB2_CLKIN (STM32F0_PCLK2_FREQUENCY)
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY)
/* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */
#define STM32F0_APB1_TIM1_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM2_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM3_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32_APB1_TIM1_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM6_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM7_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM14_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM15_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM16_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM17_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM15_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM16_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM17_CLKIN (STM32_PCLK1_FREQUENCY)
/* LED definitions ******************************************************************/
/* The STM32F0-Discovery board has four LEDs. Two of these are controlled by

4
configs/stm32f072-discovery/nsh/defconfig
View file

@ -44,8 +44,8 @@ CONFIG_START_DAY=19
CONFIG_START_MONTH=5
CONFIG_START_YEAR=2013
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_STM32F0_PWR=y
CONFIG_STM32F0_USART1=y
CONFIG_STM32F0L0_PWR=y
CONFIG_STM32F0L0_USART1=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536

2
configs/stm32f072-discovery/src/Makefile
View file

@ -49,7 +49,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y)
CSRCS += stm32_buttons.c
endif
ifeq ($(CONFIG_STM32F0_SPI),y)
ifeq ($(CONFIG_STM32F0L0_SPI),y)
CSRCS += stm32_spi.c
endif

12
configs/stm32f072-discovery/src/stm32_autoleds.c
View file

@ -86,8 +86,8 @@ void board_autoled_initialize(void)
{
/* Configure LED1-2 GPIOs for output */
stm32f0_configgpio(GPIO_LED1);
stm32f0_configgpio(GPIO_LED2);
stm32_configgpio(GPIO_LED1);
stm32_configgpio(GPIO_LED2);
}
/****************************************************************************
@ -117,8 +117,8 @@ void board_autoled_on(int led)
break;
}
stm32f0_gpiowrite(GPIO_LED1, led1on);
stm32f0_gpiowrite(GPIO_LED2, led2on);
stm32_gpiowrite(GPIO_LED1, led1on);
stm32_gpiowrite(GPIO_LED2, led2on);
}
/****************************************************************************
@ -129,8 +129,8 @@ void board_autoled_off(int led)
{
if (led != 2)
{
stm32f0_gpiowrite(GPIO_LED1, false);
stm32f0_gpiowrite(GPIO_LED2, false);
stm32_gpiowrite(GPIO_LED1, false);
stm32_gpiowrite(GPIO_LED2, false);
}
}

6
configs/stm32f072-discovery/src/stm32_boot.c
View file

@ -1,5 +1,5 @@
/************************************************************************************
* configs/stm32f072-discovery/src/stm32f0_boot.c
* configs/stm32f072-discovery/src/stm32f072_boot.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -53,7 +53,7 @@
************************************************************************************/
/************************************************************************************
* Name: stm32f0_boardinitialize
* Name: stm32_boardinitialize
*
* Description:
* All STM32 architectures must provide the following entry point. This entry point
@ -62,7 +62,7 @@
*
************************************************************************************/
void stm32f0_boardinitialize(void)
void stm32_boardinitialize(void)
{
#ifdef CONFIG_ARCH_LEDS
/* Configure on-board LEDs if LED support has been selected. */

20
configs/stm32f072-discovery/src/stm32f072-discovery.h
View file

@ -45,7 +45,7 @@
#include <nuttx/compiler.h>
#include <stdint.h>
#include "stm32f0_gpio.h"
#include "stm32_gpio.h"
/****************************************************************************************************
* Pre-processor Definitions
@ -54,15 +54,15 @@
/* Configuration ************************************************************************************/
/* How many SPI modules does this chip support? */
#if STM32F0_NSPI < 1
# undef CONFIG_STM32F0_SPI1
# undef CONFIG_STM32F0_SPI2
# undef CONFIG_STM32F0_SPI3
#elif STM32F0_NSPI < 2
# undef CONFIG_STM32F0_SPI2
# undef CONFIG_STM32F0_SPI3
#elif STM32F0_NSPI < 3
# undef CONFIG_STM32F0_SPI3
#if STM32_NSPI < 1
# undef CONFIG_STM32F0L0_SPI1
# undef CONFIG_STM32F0L0_SPI2
# undef CONFIG_STM32F0L0_SPI3
#elif STM32_NSPI < 2
# undef CONFIG_STM32F0L0_SPI2
# undef CONFIG_STM32F0L0_SPI3
#elif STM32_NSPI < 3
# undef CONFIG_STM32F0L0_SPI3
#endif
/* STM32F0Discovery GPIOs ***************************************************************************/