From b4ab6bc7f2ac3640ba79bfb231eb0fa6b4f62e19 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 16 Dec 2018 10:50:16 -0600 Subject: [PATCH] Squashed commit of the following: arch/arm/src/stm32f0l0: Some fixes for a clean build. Still have a problem with lots of error messages coming from kconfig-mconf, but the configuation looks fine. Sometimes kconfig errors are difficult to spot. I would appreciate it anyone can spot the issue. arch/arm/src/stm32f0l0/hardware: Rename the chip directory to hardware. This will hopefully eliminate some problems that I have seen with the chip include paths not being unique in more complex configuartions. configs/nucleo-f072rb, configs/nucleo-f091rc, configs/stm32f051-discovery, and configs/stm32f072-discovery: Update for all of the naming changes made in arch/arm/src/stm32f0l0 arch/arm/include/stm32f0l0: Rename stm32f0 to stm32f0l0 to make a speace for STM32 L0. Rename files, functions and defines, removeing the f0_ from the names in order to make them MCU agnostic. arch/arm/src/stm32f0l0: Rename stm32f0 to stm32f0l0 to make a speace for STM32 L0. Rename files, functions and defines, removeing the f0_ from the names in order to make them MCU agnostic. --- arch/arm/Kconfig | 15 +- arch/arm/include/stm32f0/chip.h | 264 --- arch/arm/include/stm32f0l0/chip.h | 264 +++ arch/arm/include/{stm32f0 => stm32f0l0}/irq.h | 74 +- arch/arm/include/stm32f0l0/stm32f0_irq.h | 123 ++ arch/arm/src/stm32f0/Kconfig | 1510 ---------------- .../chip/stm32f05xf07xf09x_memorymap.h | 157 -- arch/arm/src/stm32f0/chip/stm32f0_adc.h | 195 -- arch/arm/src/stm32f0/chip/stm32f0_dma.h | 456 ----- arch/arm/src/stm32f0/chip/stm32f0_exti.h | 131 -- arch/arm/src/stm32f0/chip/stm32f0_syscfg.h | 391 ---- arch/arm/src/stm32f0/chip/stm32f0_wdt.h | 142 -- arch/arm/src/stm32f0l0/Kconfig | 1522 ++++++++++++++++ arch/arm/src/{stm32f0 => stm32f0l0}/Make.defs | 40 +- arch/arm/src/{stm32f0 => stm32f0l0}/chip.h | 12 +- arch/arm/src/stm32f0l0/hardware/stm32_adc.h | 195 ++ .../hardware/stm32_can.h} | 266 +-- .../hardware/stm32_comp.h} | 12 +- .../hardware/stm32_crc.h} | 58 +- .../hardware/stm32_crs.h} | 24 +- .../hardware/stm32_dac.h} | 64 +- arch/arm/src/stm32f0l0/hardware/stm32_dma.h | 456 +++++ arch/arm/src/stm32f0l0/hardware/stm32_exti.h | 131 ++ .../hardware/stm32_flash.h} | 40 +- .../hardware/stm32_gpio.h} | 164 +- .../hardware/stm32_i2c.h} | 78 +- .../hardware/stm32_memorymap.h} | 14 +- .../hardware/stm32_pinmap.h} | 21 +- .../hardware/stm32_pwr.h} | 72 +- arch/arm/src/stm32f0l0/hardware/stm32_rcc.h | 54 + .../hardware/stm32_rtcc.h} | 98 +- .../hardware/stm32_spi.h} | 144 +- .../arm/src/stm32f0l0/hardware/stm32_syscfg.h | 391 ++++ .../hardware/stm32_tim.h} | 8 +- .../hardware/stm32_uart.h} | 150 +- .../hardware/stm32_usbdev.h} | 106 +- arch/arm/src/stm32f0l0/hardware/stm32_wdt.h | 142 ++ .../hardware}/stm32f05x_pinmap.h | 10 +- .../hardware/stm32f05xf07xf09x_memorymap.h | 157 ++ .../hardware}/stm32f07x_pinmap.h | 10 +- .../hardware}/stm32f09x_pinmap.h | 10 +- .../chip => stm32f0l0/hardware}/stm32f0_rcc.h | 64 +- .../stm32_clockconfig.c} | 56 +- .../stm32_clockconfig.h} | 12 +- .../stm32f0_gpio.c => stm32f0l0/stm32_gpio.c} | 94 +- .../stm32f0_gpio.h => stm32f0l0/stm32_gpio.h} | 52 +- .../stm32_hsi48.c} | 46 +- .../stm32_hsi48.h} | 20 +- .../stm32f0_i2c.c => stm32f0l0/stm32_i2c.c} | 610 +++---- .../stm32f0_i2c.h => stm32f0l0/stm32_i2c.h} | 28 +- .../stm32f0_idle.c => stm32f0l0/stm32_idle.c} | 4 +- .../stm32f0_irq.c => stm32f0l0/stm32_irq.c} | 62 +- .../stm32_lowputc.c} | 222 +-- .../stm32_lowputc.h} | 12 +- .../stm32f0_rcc.h => stm32f0l0/stm32_rcc.h} | 10 +- .../stm32_serial.c} | 662 +++---- .../stm32_serial.h} | 8 +- .../stm32_start.c} | 16 +- .../stm32_start.h} | 14 +- .../stm32_timerisr.c} | 20 +- .../stm32f0_uart.h => stm32f0l0/stm32_uart.h} | 254 +-- .../stm32_usbdev.c} | 1578 ++++++++--------- .../stm32_usbdev.h} | 22 +- configs/nucleo-f072rb/include/board.h | 82 +- configs/nucleo-f072rb/nsh/defconfig | 4 +- configs/nucleo-f072rb/src/nucleo-f072rb.h | 20 +- configs/nucleo-f072rb/src/stm32_autoleds.c | 8 +- configs/nucleo-f072rb/src/stm32_boot.c | 8 +- configs/nucleo-f072rb/src/stm32_bringup.c | 6 +- configs/nucleo-f072rb/src/stm32_buttons.c | 8 +- configs/nucleo-f072rb/src/stm32_userleds.c | 12 +- configs/nucleo-f091rc/include/board.h | 80 +- configs/nucleo-f091rc/nsh/defconfig | 4 +- configs/nucleo-f091rc/src/nucleo-f091rc.h | 20 +- configs/nucleo-f091rc/src/stm32_autoleds.c | 8 +- configs/nucleo-f091rc/src/stm32_boot.c | 6 +- configs/nucleo-f091rc/src/stm32_buttons.c | 8 +- configs/nucleo-f091rc/src/stm32_userleds.c | 12 +- configs/stm32f051-discovery/include/board.h | 80 +- configs/stm32f051-discovery/nsh/defconfig | 4 +- configs/stm32f051-discovery/src/Makefile | 2 +- .../stm32f051-discovery/src/stm32_autoleds.c | 12 +- configs/stm32f051-discovery/src/stm32_boot.c | 6 +- .../src/stm32f051-discovery.h | 20 +- configs/stm32f072-discovery/include/board.h | 80 +- configs/stm32f072-discovery/nsh/defconfig | 4 +- configs/stm32f072-discovery/src/Makefile | 2 +- .../stm32f072-discovery/src/stm32_autoleds.c | 12 +- configs/stm32f072-discovery/src/stm32_boot.c | 6 +- .../src/stm32f072-discovery.h | 20 +- 90 files changed, 6373 insertions(+), 6198 deletions(-) delete mode 100644 arch/arm/include/stm32f0/chip.h create mode 100644 arch/arm/include/stm32f0l0/chip.h rename arch/arm/include/{stm32f0 => stm32f0l0}/irq.h (52%) create mode 100644 arch/arm/include/stm32f0l0/stm32f0_irq.h delete mode 100644 arch/arm/src/stm32f0/Kconfig delete mode 100644 arch/arm/src/stm32f0/chip/stm32f05xf07xf09x_memorymap.h delete mode 100644 arch/arm/src/stm32f0/chip/stm32f0_adc.h delete mode 100644 arch/arm/src/stm32f0/chip/stm32f0_dma.h delete mode 100644 arch/arm/src/stm32f0/chip/stm32f0_exti.h delete mode 100644 arch/arm/src/stm32f0/chip/stm32f0_syscfg.h delete mode 100644 arch/arm/src/stm32f0/chip/stm32f0_wdt.h create mode 100644 arch/arm/src/stm32f0l0/Kconfig rename arch/arm/src/{stm32f0 => stm32f0l0}/Make.defs (81%) rename arch/arm/src/{stm32f0 => stm32f0l0}/chip.h (90%) create mode 100644 arch/arm/src/stm32f0l0/hardware/stm32_adc.h rename arch/arm/src/{stm32f0/chip/stm32f0_can.h => stm32f0l0/hardware/stm32_can.h} (60%) rename arch/arm/src/{stm32f0/chip/stm32f0_comp.h => stm32f0l0/hardware/stm32_comp.h} (96%) rename arch/arm/src/{stm32f0/chip/stm32f0_crc.h => stm32f0l0/hardware/stm32_crc.h} (52%) rename arch/arm/src/{stm32f0/chip/stm32f0_crs.h => stm32f0l0/hardware/stm32_crs.h} (88%) rename arch/arm/src/{stm32f0/chip/stm32f0_dac.h => stm32f0l0/hardware/stm32_dac.h} (81%) create mode 100644 arch/arm/src/stm32f0l0/hardware/stm32_dma.h create mode 100644 arch/arm/src/stm32f0l0/hardware/stm32_exti.h rename arch/arm/src/{stm32f0/chip/stm32f0_flash.h => stm32f0l0/hardware/stm32_flash.h} (79%) rename arch/arm/src/{stm32f0/chip/stm32f0_gpio.h => stm32f0l0/hardware/stm32_gpio.h} (62%) rename arch/arm/src/{stm32f0/chip/stm32f0_i2c.h => stm32f0l0/hardware/stm32_i2c.h} (80%) rename arch/arm/src/{stm32f0/chip/stm32f0_memorymap.h => stm32f0l0/hardware/stm32_memorymap.h} (84%) rename arch/arm/src/{stm32f0/chip/stm32f0_pinmap.h => stm32f0l0/hardware/stm32_pinmap.h} (81%) rename arch/arm/src/{stm32f0/chip/stm32f0_pwr.h => stm32f0l0/hardware/stm32_pwr.h} (50%) create mode 100644 arch/arm/src/stm32f0l0/hardware/stm32_rcc.h rename arch/arm/src/{stm32f0/chip/stm32f0_rtcc.h => stm32f0l0/hardware/stm32_rtcc.h} (82%) rename arch/arm/src/{stm32f0/chip/stm32f0_spi.h => stm32f0l0/hardware/stm32_spi.h} (66%) create mode 100644 arch/arm/src/stm32f0l0/hardware/stm32_syscfg.h rename arch/arm/src/{stm32f0/chip/stm32f0_tim.h => stm32f0l0/hardware/stm32_tim.h} (92%) rename arch/arm/src/{stm32f0/chip/stm32f0_uart.h => stm32f0l0/hardware/stm32_uart.h} (71%) rename arch/arm/src/{stm32f0/chip/stm32f0_usbdev.h => stm32f0l0/hardware/stm32_usbdev.h} (73%) create mode 100644 arch/arm/src/stm32f0l0/hardware/stm32_wdt.h rename arch/arm/src/{stm32f0/chip => stm32f0l0/hardware}/stm32f05x_pinmap.h (96%) create mode 100644 arch/arm/src/stm32f0l0/hardware/stm32f05xf07xf09x_memorymap.h rename arch/arm/src/{stm32f0/chip => stm32f0l0/hardware}/stm32f07x_pinmap.h (98%) rename arch/arm/src/{stm32f0/chip => stm32f0l0/hardware}/stm32f09x_pinmap.h (99%) rename arch/arm/src/{stm32f0/chip => stm32f0l0/hardware}/stm32f0_rcc.h (92%) rename arch/arm/src/{stm32f0/stm32f0_clockconfig.c => stm32f0l0/stm32_clockconfig.c} (77%) rename arch/arm/src/{stm32f0/stm32f0_clockconfig.h => stm32f0l0/stm32_clockconfig.h} (91%) rename arch/arm/src/{stm32f0/stm32f0_gpio.c => stm32f0l0/stm32_gpio.c} (85%) rename arch/arm/src/{stm32f0/stm32f0_gpio.h => stm32f0l0/stm32_gpio.h} (92%) rename arch/arm/src/{stm32f0/stm32f0_hsi48.c => stm32f0l0/stm32_hsi48.c} (86%) rename arch/arm/src/{stm32f0/stm32f0_hsi48.h => stm32f0l0/stm32_hsi48.h} (91%) rename arch/arm/src/{stm32f0/stm32f0_i2c.c => stm32f0l0/stm32_i2c.c} (72%) rename arch/arm/src/{stm32f0/stm32f0_i2c.h => stm32f0l0/stm32_i2c.h} (83%) rename arch/arm/src/{stm32f0/stm32f0_idle.c => stm32f0l0/stm32_idle.c} (98%) rename arch/arm/src/{stm32f0/stm32f0_irq.c => stm32f0l0/stm32_irq.c} (85%) rename arch/arm/src/{stm32f0/stm32f0_lowputc.c => stm32f0l0/stm32_lowputc.c} (57%) rename arch/arm/src/{stm32f0/stm32f0_lowputc.h => stm32f0l0/stm32_lowputc.h} (91%) rename arch/arm/src/{stm32f0/stm32f0_rcc.h => stm32f0l0/stm32_rcc.h} (90%) rename arch/arm/src/{stm32f0/stm32f0_serial.c => stm32f0l0/stm32_serial.c} (77%) rename arch/arm/src/{stm32f0/stm32f0_serial.h => stm32f0l0/stm32_serial.h} (92%) rename arch/arm/src/{stm32f0/stm32f0_start.c => stm32f0l0/stm32_start.c} (95%) rename arch/arm/src/{stm32f0/stm32f0_start.h => stm32f0l0/stm32_start.h} (89%) rename arch/arm/src/{stm32f0/stm32f0_timerisr.c => stm32f0l0/stm32_timerisr.c} (90%) rename arch/arm/src/{stm32f0/stm32f0_uart.h => stm32f0l0/stm32_uart.h} (60%) rename arch/arm/src/{stm32f0/stm32f0_usbdev.c => stm32f0l0/stm32_usbdev.c} (66%) rename arch/arm/src/{stm32f0/stm32f0_usbdev.h => stm32f0l0/stm32_usbdev.h} (86%) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d5a17acc30f..728173fd780 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -304,7 +304,13 @@ config ARCH_CHIP_STM32F0 bool "STMicro STM32 F0" select ARCH_CORTEXM0 ---help--- - STMicro STM32 architectures (ARM Cortex-M0). + STMicro STM32F0 architectures (ARM Cortex-M0). + +config ARCH_CHIP_STM32L0 + bool "STMicro STM32 L0" + select ARCH_CORTEXM0 + ---help--- + STMicro STM32L0 architectures (ARM Cortex-M0). config ARCH_CHIP_STM32F7 bool "STMicro STM32 F7" @@ -616,7 +622,7 @@ config ARCH_CHIP default "sam34" if ARCH_CHIP_SAM34 default "samv7" if ARCH_CHIP_SAMV7 default "stm32" if ARCH_CHIP_STM32 - default "stm32f0" if ARCH_CHIP_STM32F0 + default "stm32f0l0" if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 default "stm32f7" if ARCH_CHIP_STM32F7 default "stm32h7" if ARCH_CHIP_STM32H7 default "stm32l4" if ARCH_CHIP_STM32L4 @@ -871,7 +877,10 @@ if ARCH_CHIP_STM32 source arch/arm/src/stm32/Kconfig endif if ARCH_CHIP_STM32F0 -source arch/arm/src/stm32f0/Kconfig +source arch/arm/src/stm32f0l0/Kconfig +endif +if ARCH_CHIP_STM32L0 +source arch/arm/src/stm32f0l0/Kconfig endif if ARCH_CHIP_STM32F7 source arch/arm/src/stm32f7/Kconfig diff --git a/arch/arm/include/stm32f0/chip.h b/arch/arm/include/stm32f0/chip.h deleted file mode 100644 index 892755e4716..00000000000 --- a/arch/arm/include/stm32f0/chip.h +++ /dev/null @@ -1,264 +0,0 @@ -/************************************************************************************ - * arch/arm/include/stm32f0/chip.h - * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Alan Carvalho de Assis - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_INCLUDE_STM32F0_CHIP_H -#define __ARCH_ARM_INCLUDE_STM32F0_CHIP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Get customizations for each supported chip */ - -#if defined(CONFIG_ARCH_CHIP_STM32F051R8) -# define STM32F051x 1 /* STM32F051x family */ -# undef STM32F072x /* Not STM32F072x family */ -# undef STM32F091x /* Not STM32F091x family */ - -# define STM32F0_FLASH_SIZE (64*1024) /* 64Kb */ -# define STM32F0_SRAM_SIZE (8*1024) /* 8Kb */ - -# define STM32F0_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32F0_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32F0_NI2C 2 /* Two I2C modules */ -# define STM32F0_NUSART 2 /* Two USARTs modules */ -# define STM32F0_NCAN 0 /* No CAN controllers */ -# define STM32F0_NUSBDEV 1 /* One USB device controller */ -# define STM32F0_NDAC 1 /* One DAC module */ -# define STM32F0_NDACCHAN 1 /* One DAC channels */ -# define STM32F0_NCOMP 2 /* Two Analog Comparators */ -# define STM32F0_NCAP 13 /* Capacitive sensing channels (14 on UFQFPN32)) */ -# define STM32F0_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F072C8) || defined(CONFIG_ARCH_CHIP_STM32F072CB) -# undef STM32F051x /* Not STM32F051x family */ -# define STM32F072x 1 /* STM32F072x family */ -# undef STM32F091x /* Not STM32F091x family */ - -# ifdef CONFIG_ARCH_CHIP_STM32F072C8 -# define STM32F0_FLASH_SIZE (64*1024) /* 64Kb */ -# else -# define STM32F0_FLASH_SIZE (128*1024) /* 128Kb */ -# endif -# define STM32F0_SRAM_SIZE (16*1024) /* 16Kb */ - -# define STM32F0_NATIM 1 /* One advanced timer TIM1 */ -# define STM32F0_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ -# define STM32F0_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ -# define STM32F0_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ -# define STM32F0_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32F0_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32F0_NI2C 2 /* Two I2C modules */ -# define STM32F0_NUSART 4 /* Four USARTs module */ -# define STM32F0_NCAN 1 /* One CAN controller */ -# define STM32F0_NUSBDEV 1 /* One USB device controller */ -# define STM32F0_NCEC 1 /* One HDMI-CEC controller */ -# define STM32F0_NADC12 1 /* One 12-bit module */ -# define STM32F0_NADCCHAN 10 /* Ten external channels */ -# define STM32F0_NADCINT 3 /* Three internal channels */ -# define STM32F0_NDAC 1 /* One DAC module */ -# define STM32F0_NDACCHAN 2 /* Two DAC channels */ -# define STM32F0_NCOMP 2 /* Two Analog Comparators */ -# define STM32F0_NCAP 17 /* Capacitive sensing channels */ -# define STM32F0_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F072R8) || defined(CONFIG_ARCH_CHIP_STM32F072RB) -# undef STM32F051x /* Not STM32F051x family */ -# define STM32F072x 1 /* STM32F072x family */ -# undef STM32F091x /* Not STM32F091x family */ - -# ifdef CONFIG_ARCH_CHIP_STM32F072R8 -# define STM32F0_FLASH_SIZE (64*1024) /* 64Kb */ -# else -# define STM32F0_FLASH_SIZE (128*1024) /* 128Kb */ -# endif -# define STM32F0_SRAM_SIZE (16*1024) /* 16Kb */ - -# define STM32F0_NATIM 1 /* One advanced timer TIM1 */ -# define STM32F0_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ -# define STM32F0_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ -# define STM32F0_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ -# define STM32F0_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32F0_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32F0_NI2C 2 /* Two I2C modules */ -# define STM32F0_NUSART 4 /* Four USARTs module */ -# define STM32F0_NCAN 1 /* One CAN controller */ -# define STM32F0_NUSBDEV 1 /* One USB device controller */ -# define STM32F0_NCEC 1 /* One HDMI-CEC controller */ -# define STM32F0_NADC12 1 /* One 12-bit module */ -# define STM32F0_NADCCHAN 16 /* 16 external channels */ -# define STM32F0_NADCINT 3 /* Three internal channels */ -# define STM32F0_NDAC 1 /* One DAC module */ -# define STM32F0_NDACCHAN 2 /* Two DAC channels */ -# define STM32F0_NCOMP 2 /* Two Analog Comparators */ -# define STM32F0_NCAP 18 /* Capacitive sensing channels */ -# define STM32F0_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F072V8) || defined(CONFIG_ARCH_CHIP_STM32F072VB) -# undef STM32F051x /* Not STM32F051x family */ -# define STM32F072x 1 /* STM32F072x family */ -# undef STM32F091x /* Not STM32F091x family */ - -# ifdef CONFIG_ARCH_CHIP_STM32F072V8 -# define STM32F0_FLASH_SIZE (64*1024) /* 64Kb */ -# else -# define STM32F0_FLASH_SIZE (128*1024) /* 128Kb */ -# endif -# define STM32F0_SRAM_SIZE (16*1024) /* 16Kb */ - -# define STM32F0_NATIM 1 /* One advanced timer TIM1 */ -# define STM32F0_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ -# define STM32F0_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ -# define STM32F0_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ -# define STM32F0_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32F0_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32F0_NI2C 2 /* Two I2C modules */ -# define STM32F0_NUSART 4 /* Four USARTs module */ -# define STM32F0_NCAN 1 /* One CAN controller */ -# define STM32F0_NUSBDEV 1 /* One USB device controller */ -# define STM32F0_NCEC 1 /* One HDMI-CEC controller */ -# define STM32F0_NADC12 1 /* One 12-bit module */ -# define STM32F0_NADCCHAN 16 /* 16 external channels */ -# define STM32F0_NADCINT 3 /* Three internal channels */ -# define STM32F0_NDAC 1 /* One DAC module */ -# define STM32F0_NDACCHAN 2 /* Two DAC channels */ -# define STM32F0_NCOMP 2 /* Two Analog Comparators */ -# define STM32F0_NCAP 24 /* Capacitive sensing channels */ -# define STM32F0_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F091CB) || defined(CONFIG_ARCH_CHIP_STM32F091CC) -# undef STM32F051x /* Not STM32F051x family */ -# undef STM32F072x /* Not STM32F072x family */ -# define STM32F091x 1 /* STM32F091x family */ - -# ifdef CONFIG_ARCH_CHIP_STM32F091CB -# define STM32F0_FLASH_SIZE (128*1024) /* 128Kb */ -# else -# define STM32F0_FLASH_SIZE (256*1024) /* 256Kb */ -# endif -# define STM32F0_SRAM_SIZE (32*1024) /* 32Kb */ - -# define STM32F0_NATIM 1 /* One advanced timer TIM1 */ -# define STM32F0_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ -# define STM32F0_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ -# define STM32F0_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ -# define STM32F0_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32F0_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32F0_NI2C 2 /* Two I2C modules */ -# define STM32F0_NUSART 6 /* Six USARTs modules */ -# define STM32F0_NCAN 1 /* One CAN controller */ -# define STM32F0_NUSBDEV 0 /* No USB device controller */ -# define STM32F0_NCEC 1 /* One HDMI-CEC controller */ -# define STM32F0_NADC12 1 /* One 12-bit module */ -# define STM32F0_NADCCHAN 10 /* 10 external channels */ -# define STM32F0_NADCINT 3 /* Three internal channels */ -# define STM32F0_NDAC 1 /* One DAC module */ -# define STM32F0_NDACCHAN 2 /* Two DAC channels */ -# define STM32F0_NCOMP 2 /* Two Analog Comparators */ -# define STM32F0_NCAP 17 /* Capacitive sensing channels */ -# define STM32F0_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091RC) \ - || defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC) -# undef STM32F051x /* Not STM32F051x family */ -# undef STM32F072x /* Not STM32F072x family */ -# define STM32F091x 1 /* STM32F091x family */ - -# if defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091VB) -# define STM32F0_FLASH_SIZE (128*1024) /* 128Kb */ -# else -# define STM32F0_FLASH_SIZE (256*1024) /* 256Kb */ -# endif -# define STM32F0_SRAM_SIZE (32*1024) /* 32Kb */ - -# define STM32F0_NATIM 1 /* One advanced timer TIM1 */ -# define STM32F0_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ -# define STM32F0_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ -# define STM32F0_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ -# define STM32F0_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32F0_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32F0_NI2C 2 /* Two I2C modules */ -# define STM32F0_NUSART 8 /* Eight USARTs modules */ -# define STM32F0_NCAN 1 /* One CAN controller */ -# define STM32F0_NUSBDEV 0 /* No USB device controller */ -# define STM32F0_NCEC 1 /* One HDMI-CEC controller */ -# define STM32F0_NADC12 1 /* One 12-bit module */ -# define STM32F0_NADCCHAN 16 /* 16 external channels */ -# define STM32F0_NADCINT 3 /* Three internal channels */ -# define STM32F0_NDAC 1 /* One DAC module */ -# define STM32F0_NDACCHAN 2 /* Two DAC channels */ -# define STM32F0_NCOMP 2 /* Two Analog Comparators */ -# if defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC) -# define STM32F0_NCAP 24 /* Capacitive sensing channels */ -# else -# define STM32F0_NCAP 18 /* Capacitive sensing channels */ -# endif -# define STM32F0_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#else -# error "Unsupported STM32F0xx chip" -#endif - -/* NVIC priority levels *************************************************************/ -/* Each priority field holds a priority value, 0-31. The lower the value, the greater - * the priority of the corresponding interrupt. The processor implements only - * bits[7:6] of each field, bits[5:0] read as zero and ignore writes. - */ - -#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ -#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_INCLUDE_STM32F0_CHIP_H */ diff --git a/arch/arm/include/stm32f0l0/chip.h b/arch/arm/include/stm32f0l0/chip.h new file mode 100644 index 00000000000..06a41f1e2bc --- /dev/null +++ b/arch/arm/include/stm32f0l0/chip.h @@ -0,0 +1,264 @@ +/************************************************************************************ + * arch/arm/include/stm32f0l0/chip.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32F0L0_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_CHIP_STM32F051R8) +# define STM32F051x 1 /* STM32F051x family */ +# undef STM32F072x /* Not STM32F072x family */ +# undef STM32F091x /* Not STM32F091x family */ + +# define STM32_FLASH_SIZE (64*1024) /* 64Kb */ +# define STM32_SRAM_SIZE (8*1024) /* 8Kb */ + +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NUSART 2 /* Two USARTs modules */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NUSBDEV 1 /* One USB device controller */ +# define STM32_NDAC 1 /* One DAC module */ +# define STM32_NDACCHAN 1 /* One DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCAP 13 /* Capacitive sensing channels (14 on UFQFPN32)) */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F072C8) || defined(CONFIG_ARCH_CHIP_STM32F072CB) +# undef STM32F051x /* Not STM32F051x family */ +# define STM32F072x 1 /* STM32F072x family */ +# undef STM32F091x /* Not STM32F091x family */ + +# ifdef CONFIG_ARCH_CHIP_STM32F072C8 +# define STM32_FLASH_SIZE (64*1024) /* 64Kb */ +# else +# define STM32_FLASH_SIZE (128*1024) /* 128Kb */ +# endif +# define STM32_SRAM_SIZE (16*1024) /* 16Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ +# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NUSART 4 /* Four USARTs module */ +# define STM32_NCAN 1 /* One CAN controller */ +# define STM32_NUSBDEV 1 /* One USB device controller */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC12 1 /* One 12-bit module */ +# define STM32_NADCCHAN 10 /* Ten external channels */ +# define STM32_NADCINT 3 /* Three internal channels */ +# define STM32_NDAC 1 /* One DAC module */ +# define STM32_NDACCHAN 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCAP 17 /* Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F072R8) || defined(CONFIG_ARCH_CHIP_STM32F072RB) +# undef STM32F051x /* Not STM32F051x family */ +# define STM32F072x 1 /* STM32F072x family */ +# undef STM32F091x /* Not STM32F091x family */ + +# ifdef CONFIG_ARCH_CHIP_STM32F072R8 +# define STM32_FLASH_SIZE (64*1024) /* 64Kb */ +# else +# define STM32_FLASH_SIZE (128*1024) /* 128Kb */ +# endif +# define STM32_SRAM_SIZE (16*1024) /* 16Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ +# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NUSART 4 /* Four USARTs module */ +# define STM32_NCAN 1 /* One CAN controller */ +# define STM32_NUSBDEV 1 /* One USB device controller */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC12 1 /* One 12-bit module */ +# define STM32_NADCCHAN 16 /* 16 external channels */ +# define STM32_NADCINT 3 /* Three internal channels */ +# define STM32_NDAC 1 /* One DAC module */ +# define STM32_NDACCHAN 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCAP 18 /* Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F072V8) || defined(CONFIG_ARCH_CHIP_STM32F072VB) +# undef STM32F051x /* Not STM32F051x family */ +# define STM32F072x 1 /* STM32F072x family */ +# undef STM32F091x /* Not STM32F091x family */ + +# ifdef CONFIG_ARCH_CHIP_STM32F072V8 +# define STM32_FLASH_SIZE (64*1024) /* 64Kb */ +# else +# define STM32_FLASH_SIZE (128*1024) /* 128Kb */ +# endif +# define STM32_SRAM_SIZE (16*1024) /* 16Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ +# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NUSART 4 /* Four USARTs module */ +# define STM32_NCAN 1 /* One CAN controller */ +# define STM32_NUSBDEV 1 /* One USB device controller */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC12 1 /* One 12-bit module */ +# define STM32_NADCCHAN 16 /* 16 external channels */ +# define STM32_NADCINT 3 /* Three internal channels */ +# define STM32_NDAC 1 /* One DAC module */ +# define STM32_NDACCHAN 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCAP 24 /* Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F091CB) || defined(CONFIG_ARCH_CHIP_STM32F091CC) +# undef STM32F051x /* Not STM32F051x family */ +# undef STM32F072x /* Not STM32F072x family */ +# define STM32F091x 1 /* STM32F091x family */ + +# ifdef CONFIG_ARCH_CHIP_STM32F091CB +# define STM32_FLASH_SIZE (128*1024) /* 128Kb */ +# else +# define STM32_FLASH_SIZE (256*1024) /* 256Kb */ +# endif +# define STM32_SRAM_SIZE (32*1024) /* 32Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ +# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NUSART 6 /* Six USARTs modules */ +# define STM32_NCAN 1 /* One CAN controller */ +# define STM32_NUSBDEV 0 /* No USB device controller */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC12 1 /* One 12-bit module */ +# define STM32_NADCCHAN 10 /* 10 external channels */ +# define STM32_NADCINT 3 /* Three internal channels */ +# define STM32_NDAC 1 /* One DAC module */ +# define STM32_NDACCHAN 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCAP 17 /* Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091RC) \ + || defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC) +# undef STM32F051x /* Not STM32F051x family */ +# undef STM32F072x /* Not STM32F072x family */ +# define STM32F091x 1 /* STM32F091x family */ + +# if defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091VB) +# define STM32_FLASH_SIZE (128*1024) /* 128Kb */ +# else +# define STM32_FLASH_SIZE (256*1024) /* 256Kb */ +# endif +# define STM32_SRAM_SIZE (32*1024) /* 32Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ +# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NUSART 8 /* Eight USARTs modules */ +# define STM32_NCAN 1 /* One CAN controller */ +# define STM32_NUSBDEV 0 /* No USB device controller */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC12 1 /* One 12-bit module */ +# define STM32_NADCCHAN 16 /* 16 external channels */ +# define STM32_NADCINT 3 /* Three internal channels */ +# define STM32_NDAC 1 /* One DAC module */ +# define STM32_NDACCHAN 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# if defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC) +# define STM32_NCAP 24 /* Capacitive sensing channels */ +# else +# define STM32_NCAP 18 /* Capacitive sensing channels */ +# endif +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#else +# error "Unsupported STM32F0xx chip" +#endif + +/* NVIC priority levels *************************************************************/ +/* Each priority field holds a priority value, 0-31. The lower the value, the greater + * the priority of the corresponding interrupt. The processor implements only + * bits[7:6] of each field, bits[5:0] read as zero and ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_CHIP_H */ diff --git a/arch/arm/include/stm32f0/irq.h b/arch/arm/include/stm32f0l0/irq.h similarity index 52% rename from arch/arm/include/stm32f0/irq.h rename to arch/arm/include/stm32f0l0/irq.h index e01fb47be7e..12a274667de 100644 --- a/arch/arm/include/stm32f0/irq.h +++ b/arch/arm/include/stm32f0l0/irq.h @@ -38,8 +38,8 @@ * through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_STM32F0_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32F0_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F0L0_IRQ_H /**************************************************************************** * Included Files @@ -48,11 +48,12 @@ #ifndef __ASSEMBLY__ # include #endif -#include +#include /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* IRQ numbers. The IRQ number corresponds vector number and hence map * directly to bits in the NVIC. This does, however, waste several words of * memory in the IRQ to handle mapping tables. @@ -60,55 +61,32 @@ /* Common Processor Exceptions (vectors 0-15) */ -#define STM32F0_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define STM32F0_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define STM32F0_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ - /* Vectors 4-10: Reserved */ -#define STM32F0_IRQ_SVCALL (11) /* Vector 11: SVC call */ - /* Vector 12-13: Reserved */ -#define STM32F0_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define STM32F0_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ + /* Vectors 4-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ + /* Vector 12-13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* External interrupts (vectors >= 16) */ -#define STM32F0_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ +#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ -#define STM32F0_IRQ_WWDG (16) /* Vector 16: WWDG */ -#define STM32F0_IRQ_PVD_VDDIO2 (17) /* Vector 17: PVD_VDDIO2 */ -#define STM32F0_IRQ_RTC (18) /* Vector 18: RTC */ -#define STM32F0_IRQ_FLASH (19) /* Vector 19: FLASH */ -#define STM32F0_IRQ_RCC_CRS (20) /* Vector 20: RCC and CRS */ -#define STM32F0_IRQ_EXTI0_1 (21) /* Vector 21: EXTI0_1 */ -#define STM32F0_IRQ_EXTI2_3 (22) /* Vector 22: EXTI2_3 */ -#define STM32F0_IRQ_EXTI4_15 (23) /* Vector 23: EXTI4_15 */ -#define STM32F0_IRQ_TSC (24) /* Vector 24: TSC */ -#define STM32F0_IRQ_DMA_CH1 (25) /* Vector 25: DMA_CH1 */ -#define STM32F0_IRQ_DMA_CH23 (26) /* Vector 26: DMA_CH2_3 and DMA2_CH1_2 */ -#define STM32F0_IRQ_DMA_CH4567 (27) /* Vector 27: DMA_CH4_5_6_7 and DMA2_CH3_4_5 */ -#define STM32F0_IRQ_ADC_COMP (28) /* Vector 28: ADC_COMP */ -#define STM32F0_IRQ_TIM1_BRK (29) /* Vector 29: TIM1_BRK_UP_TRG_COM */ -#define STM32F0_IRQ_TIM1_CC (30) /* Vector 30: TIM1_CC */ -#define STM32F0_IRQ_TIM2 (31) /* Vector 31: TIM2 */ -#define STM32F0_IRQ_TIM3 (32) /* Vector 32: TIM3 */ -#define STM32F0_IRQ_TIM6_DAC (33) /* Vector 33: TIM6 and DAC */ -#define STM32F0_IRQ_TIM7 (34) /* Vector 34: TIM7 */ -#define STM32F0_IRQ_TIM14 (35) /* Vector 35: TIM14 */ -#define STM32F0_IRQ_TIM15 (36) /* Vector 36: TIM15 */ -#define STM32F0_IRQ_TIM16 (37) /* Vector 37: TIM16 */ -#define STM32F0_IRQ_TIM17 (38) /* Vector 38: TIM17 */ -#define STM32F0_IRQ_I2C1 (39) /* Vector 39: I2C1 */ -#define STM32F0_IRQ_I2C2 (40) /* Vector 40: I2C2 */ -#define STM32F0_IRQ_SPI1 (41) /* Vector 41: SPI1 */ -#define STM32F0_IRQ_SPI2 (42) /* Vector 42: SPI2 */ -#define STM32F0_IRQ_USART1 (43) /* Vector 43: USART1 */ -#define STM32F0_IRQ_USART2 (44) /* Vector 44: USART2 */ -#define STM32F0_IRQ_USART345678 (45) /* Vector 45: USART3_4_5_6_7_8 */ -#define STM32F0_IRQ_CEC_CAN (46) /* Vector 46: HDMI CEC and CAN */ -#define STM32F0_IRQ_USB (47) /* Vector 47: USB */ +/* Include MCU-specific external interrupt definitions */ -#define NR_IRQS (48) /* 32 interrupts plus 16 exceptions */ +#if defined(CONFIG_STM32F0L0_STM32F0) +# include +#elif defined(CONFIG_STM32F0L0_STM32L0) +# include +#else +# error Unrecognized STM32 Cortex M0 family +#endif + +#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINT) /**************************************************************************** * Public Types @@ -139,4 +117,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_INCLUDE_STM32F0_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_IRQ_H */ diff --git a/arch/arm/include/stm32f0l0/stm32f0_irq.h b/arch/arm/include/stm32f0l0/stm32f0_irq.h new file mode 100644 index 00000000000..e6d53fa1837 --- /dev/null +++ b/arch/arm/include/stm32f0l0/stm32f0_irq.h @@ -0,0 +1,123 @@ +/**************************************************************************** + * arch/arm/include/stm32f0l0/stm32f0_irq.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_STM32F0_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F0L0_STM32F0_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +#endif +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Include STM32F0-specific external interrupt definitions */ + +#define STM32_IRQ_WWDG (16) /* Vector 16: WWDG */ +#define STM32_IRQ_PVD_VDDIO2 (17) /* Vector 17: PVD_VDDIO2 */ +#define STM32_IRQ_RTC (18) /* Vector 18: RTC */ +#define STM32_IRQ_FLASH (19) /* Vector 19: FLASH */ +#define STM32_IRQ_RCC_CRS (20) /* Vector 20: RCC and CRS */ +#define STM32_IRQ_EXTI0_1 (21) /* Vector 21: EXTI0_1 */ +#define STM32_IRQ_EXTI2_3 (22) /* Vector 22: EXTI2_3 */ +#define STM32_IRQ_EXTI4_15 (23) /* Vector 23: EXTI4_15 */ +#define STM32_IRQ_TSC (24) /* Vector 24: TSC */ +#define STM32_IRQ_DMA_CH1 (25) /* Vector 25: DMA_CH1 */ +#define STM32_IRQ_DMA_CH23 (26) /* Vector 26: DMA_CH2_3 and DMA2_CH1_2 */ +#define STM32_IRQ_DMA_CH4567 (27) /* Vector 27: DMA_CH4_5_6_7 and DMA2_CH3_4_5 */ +#define STM32_IRQ_ADC_COMP (28) /* Vector 28: ADC_COMP */ +#define STM32_IRQ_TIM1_BRK (29) /* Vector 29: TIM1_BRK_UP_TRG_COM */ +#define STM32_IRQ_TIM1_CC (30) /* Vector 30: TIM1_CC */ +#define STM32_IRQ_TIM2 (31) /* Vector 31: TIM2 */ +#define STM32_IRQ_TIM3 (32) /* Vector 32: TIM3 */ +#define STM32_IRQ_TIM6_DAC (33) /* Vector 33: TIM6 and DAC */ +#define STM32_IRQ_TIM7 (34) /* Vector 34: TIM7 */ +#define STM32_IRQ_TIM14 (35) /* Vector 35: TIM14 */ +#define STM32_IRQ_TIM15 (36) /* Vector 36: TIM15 */ +#define STM32_IRQ_TIM16 (37) /* Vector 37: TIM16 */ +#define STM32_IRQ_TIM17 (38) /* Vector 38: TIM17 */ +#define STM32_IRQ_I2C1 (39) /* Vector 39: I2C1 */ +#define STM32_IRQ_I2C2 (40) /* Vector 40: I2C2 */ +#define STM32_IRQ_SPI1 (41) /* Vector 41: SPI1 */ +#define STM32_IRQ_SPI2 (42) /* Vector 42: SPI2 */ +#define STM32_IRQ_USART1 (43) /* Vector 43: USART1 */ +#define STM32_IRQ_USART2 (44) /* Vector 44: USART2 */ +#define STM32_IRQ_USART345678 (45) /* Vector 45: USART3_4_5_6_7_8 */ +#define STM32_IRQ_CEC_CAN (46) /* Vector 46: HDMI CEC and CAN */ +#define STM32_IRQ_USB (47) /* Vector 47: USB */ + +#define STM32_IRQ_NEXTINT (32) /* 32 external interrupts */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +typedef void (*vic_vector_t)(uint32_t *regs); + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_STM32F0_IRQ_H */ diff --git a/arch/arm/src/stm32f0/Kconfig b/arch/arm/src/stm32f0/Kconfig deleted file mode 100644 index 1cdfc18401c..00000000000 --- a/arch/arm/src/stm32f0/Kconfig +++ /dev/null @@ -1,1510 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -comment "STM32F0xx Configuration Options" - -choice - prompt "ST STM32F0XX Chip Selection" - default ARCH_CHIP_STM32F051R8 - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F030C6 - bool "STM32F030C6" - select STM32F0_STM32F03X - select STM32F0_VALUELINE - -config ARCH_CHIP_STM32F030C8 - bool "STM32F030C8" - select STM32F0_STM32F03X - select STM32F0_VALUELINE - -config ARCH_CHIP_STM32F030CC - bool "STM32F030CC" - select STM32F0_STM32F03X - select STM32F0_VALUELINE - -config ARCH_CHIP_STM32F030F4 - bool "STM32F030F4" - select STM32F0_STM32F03X - select STM32F0_VALUELINE - -config ARCH_CHIP_STM32F030K6 - bool "STM32F030K6" - select STM32F0_STM32F03X - select STM32F0_VALUELINE - -config ARCH_CHIP_STM32F030R8 - bool "STM32F030R8" - select STM32F0_STM32F03X - select STM32F0_VALUELINE - -config ARCH_CHIP_STM32F030RC - bool "STM32F030RC" - select STM32F0_STM32F03X - select STM32F0_VALUELINE - -config ARCH_CHIP_STM32F031C4 - bool "STM32F031C4" - select STM32F0_STM32F03X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F031C6 - bool "STM32F031C6" - select STM32F0_STM32F03X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F031E6 - bool "STM32F031E6" - select STM32F0_STM32F03X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F031F4 - bool "STM32F031F4" - select STM32F0_STM32F03X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F031F6 - bool "STM32F031F6" - select STM32F0_STM32F03X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F031G4 - bool "STM32F031G4" - select STM32F0_STM32F03X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F031G6 - bool "STM32F031G6" - select STM32F0_STM32F03X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F031K4 - bool "STM32F031K4" - select STM32F0_STM32F03X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F031K6 - bool "STM32F031K6" - select STM32F0_STM32F03X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F038C6 - bool "STM32F038C6" - select STM32F0_STM32F03X - select STM32F0_LOWVOLTLINE - -config ARCH_CHIP_STM32F038E6 - bool "STM32F038E6" - select STM32F0_STM32F03X - select STM32F0_LOWVOLTLINE - -config ARCH_CHIP_STM32F038F6 - bool "STM32F038F6" - select STM32F0_STM32F03X - select STM32F0_LOWVOLTLINE - -config ARCH_CHIP_STM32F038G6 - bool "STM32F038G6" - select STM32F0_STM32F03X - select STM32F0_LOWVOLTLINE - -config ARCH_CHIP_STM32F038K6 - bool "STM32F038K6" - select STM32F0_STM32F03X - select STM32F0_LOWVOLTLINE - -config ARCH_CHIP_STM32F042C4 - bool "STM32F042C4" - select STM32F0_STM32F04X - select STM32F0_USBLINE - -config ARCH_CHIP_STM32F042C6 - bool "STM32F042C6" - select STM32F0_STM32F04X - select STM32F0_USBLINE - -config ARCH_CHIP_STM32F042F4 - bool "STM32F042F4" - select STM32F0_STM32F04X - select STM32F0_USBLINE - -config ARCH_CHIP_STM32F042F6 - bool "STM32F042F6" - select STM32F0_STM32F04X - select STM32F0_USBLINE - -config ARCH_CHIP_STM32F042G4 - bool "STM32F042G4" - select STM32F0_STM32F04X - select STM32F0_USBLINE - -config ARCH_CHIP_STM32F042G6 - bool "STM32F042G6" - select STM32F0_STM32F04X - select STM32F0_USBLINE - -config ARCH_CHIP_STM32F042K4 - bool "STM32F042K4" - select STM32F0_STM32F04X - select STM32F0_USBLINE - -config ARCH_CHIP_STM32F042K6 - bool "STM32F042K6" - select STM32F0_STM32F04X - select STM32F0_USBLINE - -config ARCH_CHIP_STM32F042T6 - bool "STM32F042T6" - select STM32F0_STM32F04X - select STM32F0_USBLINE - -config ARCH_CHIP_STM32F048C6 - bool "STM32F048C6" - select STM32F0_STM32F04X - select STM32F0_LOWVOLTLINE - -config ARCH_CHIP_STM32F048G6 - bool "STM32F048G6" - select STM32F0_STM32F04X - select STM32F0_LOWVOLTLINE - -config ARCH_CHIP_STM32F048T6 - bool "STM32F048T6" - select STM32F0_STM32F04X - select STM32F0_LOWVOLTLINE - -config ARCH_CHIP_STM32F051C4 - bool "STM32F051C4" - select STM32F0_STM32F05X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F051C6 - bool "STM32F051C6" - select STM32F0_STM32F05X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F051C8 - bool "STM32F051C8" - select STM32F0_STM32F05X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F051K4 - bool "STM32F051K4" - select STM32F0_STM32F05X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F051K6 - bool "STM32F051K6" - select STM32F0_STM32F05X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F051K8 - bool "STM32F051K8" - select STM32F0_STM32F05X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F051R4 - bool "STM32F051R4" - select STM32F0_STM32F05X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F051R6 - bool "STM32F051R6" - select STM32F0_STM32F05X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F051R8 - bool "STM32F051R8" - select STM32F0_STM32F05X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F051T8 - bool "STM32F051T8" - select STM32F0_STM32F05X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F058C8 - bool "STM32F058C8" - select STM32F0_STM32F05X - select STM32F0_LOWVOLTLINE - -config ARCH_CHIP_STM32F058R8 - bool "STM32F058R8" - select STM32F0_STM32F05X - select STM32F0_LOWVOLTLINE - -config ARCH_CHIP_STM32F058T8 - bool "STM32F058T8" - select STM32F0_STM32F05X - select STM32F0_LOWVOLTLINE - -config ARCH_CHIP_STM32F070C6 - bool "STM32F070C6" - select STM32F0_STM32F07X - select STM32F0_VALUELINE - -config ARCH_CHIP_STM32F070CB - bool "STM32F070CB" - select STM32F0_STM32F07X - select STM32F0_VALUELINE - -config ARCH_CHIP_STM32F070F6 - bool "STM32F070F6" - select STM32F0_STM32F07X - select STM32F0_VALUELINE - -config ARCH_CHIP_STM32F070RB - bool "STM32F070RB" - select STM32F0_STM32F07X - select STM32F0_VALUELINE - -config ARCH_CHIP_STM32F071C8 - bool "STM32F071C8" - select STM32F0_STM32F07X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F071CB - bool "STM32F071CB" - select STM32F0_STM32F07X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F071RB - bool "STM32F071RB" - select STM32F0_STM32F07X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F071V8 - bool "STM32F071V8" - select STM32F0_STM32F07X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F071VB - bool "STM32F071VB" - select STM32F0_STM32F07X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F072C8 - bool "STM32F072C8" - select STM32F0_STM32F07X - select STM32F0_USBLINE - -config ARCH_CHIP_STM32F072CB - bool "STM32F072CB" - select STM32F0_STM32F07X - select STM32F0_USBLINE - -config ARCH_CHIP_STM32F072R8 - bool "STM32F072R8" - select STM32F0_STM32F07X - select STM32F0_USBLINE - -config ARCH_CHIP_STM32F072RB - bool "STM32F072RB" - select STM32F0_STM32F07X - select STM32F0_USBLINE - -config ARCH_CHIP_STM32F072V8 - bool "STM32F072V8" - select STM32F0_STM32F07X - select STM32F0_USBLINE - -config ARCH_CHIP_STM32F072VB - bool "STM32F072VB" - select STM32F0_STM32F07X - select STM32F0_USBLINE - -config ARCH_CHIP_STM32F078CB - bool "STM32F078CB" - select STM32F0_STM32F07X - select STM32F0_LOWVOLTLINE - -config ARCH_CHIP_STM32F078RB - bool "STM32F078RB" - select STM32F0_STM32F07X - select STM32F0_LOWVOLTLINE - -config ARCH_CHIP_STM32F078VB - bool "STM32F078VB" - select STM32F0_STM32F07X - select STM32F0_LOWVOLTLINE - -config ARCH_CHIP_STM32F091CB - bool "STM32F091CB" - select STM32F0_STM32F09X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F091CC - bool "STM32F091CC" - select STM32F0_STM32F09X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F091RB - bool "STM32F091RB" - select STM32F0_STM32F09X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F091RC - bool "STM32F091RC" - select STM32F0_STM32F09X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F091VB - bool "STM32F091VB" - select STM32F0_STM32F09X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F091VC - bool "STM32F091VC" - select STM32F0_STM32F09X - select STM32F0_ACCESSLINE - -config ARCH_CHIP_STM32F098CC - bool "STM32F098CC" - select STM32F0_STM32F09X - select STM32F0_LOWVOLTLINE - -config ARCH_CHIP_STM32F098RC - bool "STM32F098RC" - select STM32F0_STM32F09X - select STM32F0_LOWVOLTLINE - -config ARCH_CHIP_STM32F098VC - bool "STM32F098VC" - select STM32F0_STM32F09X - select STM32F0_LOWVOLTLINE - -endchoice - -config ARCH_FAMILY_STM32F0XX - bool - -choice - prompt "Override Flash Size Designator" - default STM32F0_FLASH_CONFIG_DEFAULT - depends on ARCH_CHIP_STM32 - ---help--- - STM32F series parts numbering (sans the package type) ends with a number or letter - that designates the FLASH size. - - Designator Size in KiB - 4 16 - 6 32 - 8 64 - B 128 - C 256 - D 384 - E 512 - F 768 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32F407VE is chosen, the Flash configuration would be 'E', if a variant of - the part with a 2048 KiB Flash is released in the future one could simply select - the 'I' designator here. - - If an STM32F42xxx or Series parts is chosen the default Flash configuration will be 'G' - and can be set herein to 'I' to choose the larger FLASH part. - -config STM32F0_FLASH_CONFIG_DEFAULT - bool "Default" - -config STM32F0_FLASH_CONFIG_4 - bool "4 16KiB" - -config STM32F0_FLASH_CONFIG_6 - bool "6 32KiB" - -config STM32F0_FLASH_CONFIG_8 - bool "8 64KiB" - -config STM32F0_FLASH_CONFIG_B - bool "B 128KiB" - -config STM32F0_FLASH_CONFIG_C - bool "C 256KiB" - -config STM32F0_FLASH_CONFIG_D - bool "D 384KiB" - -config STM32F0_FLASH_CONFIG_E - bool "E 512KiB" - -config STM32F0_FLASH_CONFIG_F - bool "F 768KiB" - -config STM32F0_FLASH_CONFIG_G - bool "G 1024KiB" - -config STM32F0_FLASH_CONFIG_I - bool "I 2048KiB" - -endchoice - -config STM32F0_STM32F03X - bool - default n - -config STM32F0_STM32F04X - bool - default n - -config STM32F0_STM32F05X - bool - default n - -config STM32F0_STM32F07X - bool - default n - -config STM32F0_STM32F09X - bool - default n - select STM32F0_HAVE_HSI48 - -config STM32F0_VALUELINE - bool - default n - select STM32F0_HAVE_USART3 - select STM32F0_HAVE_USART4 - select STM32F0_HAVE_USART5 - select STM32F0_HAVE_TIM1 - select STM32F0_HAVE_TIM2 - select STM32F0_HAVE_TIM3 - select STM32F0_HAVE_TIM6 - select STM32F0_HAVE_TIM7 - select STM32F0_HAVE_TIM14 - select STM32F0_HAVE_TIM15 - select STM32F0_HAVE_TIM16 - select STM32F0_HAVE_TIM17 - select STM32F0_HAVE_SPI2 if STM32F0_HIGHDENSITY - select STM32F0_HAVE_SPI3 if STM32F0_HIGHDENSITY - -config STM32F0_ACCESSLINE - bool - default n - select STM32F0_HAVE_USART3 - select STM32F0_HAVE_USART4 - select STM32F0_HAVE_USART5 - select STM32F0_HAVE_TIM1 - select STM32F0_HAVE_TIM2 - select STM32F0_HAVE_TIM3 - select STM32F0_HAVE_TIM6 - select STM32F0_HAVE_TIM7 - select STM32F0_HAVE_TIM14 - select STM32F0_HAVE_TIM15 - select STM32F0_HAVE_TIM16 - select STM32F0_HAVE_TIM17 - select STM32F0_HAVE_ADC2 - select STM32F0_HAVE_CAN1 - select STM32F0_HAVE_SPI2 - select STM32F0_HAVE_SPI3 - -config STM32F0_LOWVOLTLINE - bool - default n - select STM32F0_HAVE_USART3 - select STM32F0_HAVE_USART4 - select STM32F0_HAVE_USART5 - select STM32F0_HAVE_TIM1 - select STM32F0_HAVE_TIM2 - select STM32F0_HAVE_TIM3 - select STM32F0_HAVE_TIM6 - select STM32F0_HAVE_TIM7 - select STM32F0_HAVE_TIM14 - select STM32F0_HAVE_TIM15 - select STM32F0_HAVE_TIM16 - select STM32F0_HAVE_TIM17 - select STM32F0_HAVE_ADC2 - select STM32F0_HAVE_CAN1 - select STM32F0_HAVE_SPI2 - select STM32F0_HAVE_SPI3 - -config STM32F0_USBLINE - bool - default n - select STM32F0_HAVE_HSI48 - select STM32F0_HAVE_USART3 - select STM32F0_HAVE_USART4 - select STM32F0_HAVE_TIM1 - select STM32F0_HAVE_TIM2 - select STM32F0_HAVE_TIM3 - select STM32F0_HAVE_TIM6 - select STM32F0_HAVE_TIM7 - select STM32F0_HAVE_TIM14 - select STM32F0_HAVE_TIM15 - select STM32F0_HAVE_TIM16 - select STM32F0_HAVE_TIM17 - select STM32F0_HAVE_ADC2 - select STM32F0_HAVE_CAN1 - select STM32F0_HAVE_SPI2 - select STM32F0_HAVE_SPI3 - select STM32F0_HAVE_USBDEV - -config STM32F0_DFU - bool "DFU bootloader" - default n - depends on !STM32F0_VALUELINE - ---help--- - Configure and position code for use with the STMicro DFU bootloader. Do - not select this option if you will load code using JTAG/SWM. - - -choice - prompt "SysTick clock source" - default STM32F0_SYSTICK_CORECLK - -config STM32F0_SYSTICK_CORECLK - bool "Cortex-M0 core clock" - -config STM32F0_SYSTICK_CORECLK_DIV16 - bool "Cortex-M0 core clock divided by 16" - -endchoice - - -menu "STM32 Peripheral Support" - -# These "hidden" settings determine is a peripheral option is available for the -# selection MCU - -config STM32F0_HAVE_CCM - bool - default n - -config STM32F0_HAVE_HSI48 - bool - default n - -config STM32F0_HAVE_USBDEV - bool - default n - -config STM32F0_HAVE_FSMC - bool - default n - -config STM32F0_HAVE_USART3 - bool - default n - -config STM32F0_HAVE_USART4 - bool - default n - -config STM32F0_HAVE_USART5 - bool - default n - -config STM32F0_HAVE_USART6 - bool - default n - -config STM32F0_HAVE_USART7 - bool - default n - -config STM32F0_HAVE_USART8 - bool - default n - -config STM32F0_HAVE_TIM1 - bool - default n - -config STM32F0_HAVE_TIM2 - bool - default n - -config STM32F0_HAVE_TIM3 - bool - default n - -config STM32F0_HAVE_TIM6 - bool - default n - -config STM32F0_HAVE_TIM7 - bool - default n - -config STM32F0_HAVE_TIM14 - bool - default n - -config STM32F0_HAVE_TIM15 - bool - default n - -config STM32F0_HAVE_TIM16 - bool - default n - -config STM32F0_HAVE_TIM17 - bool - default n - -config STM32F0_HAVE_TSC - bool - default n - -config STM32F0_HAVE_ADC2 - bool - default n - -config STM32F0_HAVE_ADC3 - bool - default n - -config STM32F0_HAVE_ADC4 - bool - default n - -config STM32F0_HAVE_ADC1_DMA - bool - default n - -config STM32F0_HAVE_ADC2_DMA - bool - default n - -config STM32F0_HAVE_ADC3_DMA - bool - default n - -config STM32F0_HAVE_ADC4_DMA - bool - default n - -config STM32F0_HAVE_SDADC1 - bool - default n - -config STM32F0_HAVE_SDADC2 - bool - default n - -config STM32F0_HAVE_SDADC3 - bool - default n - -config STM32F0_HAVE_SDADC1_DMA - bool - default n - -config STM32F0_HAVE_SDADC2_DMA - bool - default n - -config STM32F0_HAVE_SDADC3_DMA - bool - default n - -config STM32F0_HAVE_CAN1 - bool - default n - -config STM32F0_HAVE_COMP1 - bool - default n - -config STM32F0_HAVE_COMP2 - bool - default n - -config STM32F0_HAVE_COMP3 - bool - default n - -config STM32F0_HAVE_COMP4 - bool - default n - -config STM32F0_HAVE_COMP5 - bool - default n - -config STM32F0_HAVE_COMP6 - bool - default n - -config STM32F0_HAVE_COMP7 - bool - default n - -config STM32F0_HAVE_DAC1 - bool - default n - -config STM32F0_HAVE_DAC2 - bool - default n - -config STM32F0_HAVE_RNG - bool - default n - -config STM32F0_HAVE_I2C2 - bool - default n - -config STM32F0_HAVE_I2C3 - bool - default n - -config STM32F0_HAVE_SPI2 - bool - default n - -config STM32F0_HAVE_SPI3 - bool - default n - -config STM32F0_HAVE_SPI4 - bool - default n - -config STM32F0_HAVE_SPI5 - bool - default n - -config STM32F0_HAVE_SPI6 - bool - default n - -config STM32F0_HAVE_SAIPLL - bool - default n - -config STM32F0_HAVE_I2SPLL - bool - default n - -config STM32F0_HAVE_OPAMP1 - bool - default n - -config STM32F0_HAVE_OPAMP2 - bool - default n - -config STM32F0_HAVE_OPAMP3 - bool - default n - -config STM32F0_HAVE_OPAMP4 - bool - default n - -# These are the peripheral selections proper - -config STM32F0_ADC1 - bool "ADC1" - default n - select STM32F0_ADC - -config STM32F0_ADC2 - bool "ADC2" - default n - select STM32F0_ADC - depends on STM32F0_HAVE_ADC2 - -config STM32F0_ADC3 - bool "ADC3" - default n - select STM32F0_ADC - depends on STM32F0_HAVE_ADC3 - -config STM32F0_ADC4 - bool "ADC4" - default n - select STM32F0_ADC - depends on STM32F0_HAVE_ADC4 - -config STM32F0_SDADC1 - bool "SDADC1" - default n - select STM32F0_SDADC - depends on STM32F0_HAVE_SDADC1 - -config STM32F0_SDADC2 - bool "SDADC2" - default n - select STM32F0_SDADC - depends on STM32F0_HAVE_SDADC2 - -config STM32F0_SDADC3 - bool "SDADC3" - default n - select STM32F0_SDADC - depends on STM32F0_HAVE_SDADC3 - -config STM32F0_COMP - bool "COMP" - default n - -config STM32F0_COMP1 - bool "COMP1" - default n - depends on STM32F0_HAVE_COMP1 - -config STM32F0_COMP2 - bool "COMP2" - default n - depends on STM32F0_HAVE_COMP2 - -config STM32F0_COMP3 - bool "COMP3" - default n - depends on STM32F0_HAVE_COMP3 - -config STM32F0_COMP4 - bool "COMP4" - default n - depends on STM32F0_HAVE_COMP4 - -config STM32F0_COMP5 - bool "COMP5" - default n - depends on STM32F0_HAVE_COMP5 - -config STM32F0_COMP6 - bool "COMP6" - default n - depends on STM32F0_HAVE_COMP6 - -config STM32F0_COMP7 - bool "COMP7" - default n - depends on STM32F0_HAVE_COMP6 - -config STM32F0_BKP - bool "BKP" - default n - -config STM32F0_BKPSRAM - bool "Enable BKP RAM Domain" - default n - -config STM32F0_CAN1 - bool "CAN1" - default n - select CAN - select STM32F0_CAN - depends on STM32F0_HAVE_CAN1 - -config STM32F0_CEC - bool "CEC" - default n - depends on STM32F0_VALUELINE - -config STM32F0_CRC - bool "CRC" - default n - -config STM32F0_CRYP - bool "CRYP" - default n - depends on STM32F0_STM32F207 || STM32F0_STM32F40XX - -config STM32F0_DMA1 - bool "DMA1" - default n - select ARCH_DMA - -config STM32F0_DMA2 - bool "DMA2" - default n - select ARCH_DMA - depends on !STM32F0_VALUELINE || (STM32F0_VALUELINE && STM32F0_HIGHDENSITY) - -config STM32F0_DAC1 - bool "DAC1" - default n - depends on STM32F0_HAVE_DAC1 - select STM32F0_DAC - -config STM32F0_DAC2 - bool "DAC2" - default n - depends on STM32F0_HAVE_DAC2 - select STM32F0_DAC - -config STM32F0_FSMC - bool "FSMC" - default n - depends on STM32F0_HAVE_FSMC - -config STM32F0_HASH - bool "HASH" - default n - depends on STM32F0_STM32F207 || STM32F0_STM32F40XX - -config STM32F0_I2C1 - bool "I2C1" - default n - select STM32F0_I2C - -config STM32F0_I2C2 - bool "I2C2" - default n - depends on STM32F0_HAVE_I2C2 - select STM32F0_I2C - -config STM32F0_I2C3 - bool "I2C3" - default n - depends on STM32F0_HAVE_I2C3 - select STM32F0_I2C - -config STM32F0_PWR - bool "PWR" - default n - -config STM32F0_RNG - bool "RNG" - default n - depends on STM32F0_HAVE_RNG - select ARCH_HAVE_RNG - -config STM32F0_SDIO - bool "SDIO" - default n - depends on !STM32F0_CONNECTIVITYLINE && !STM32F0_VALUELINE - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - -config STM32F0_SPI1 - bool "SPI1" - default n - select SPI - select STM32F0_SPI - -config STM32F0_SPI2 - bool "SPI2" - default n - depends on STM32F0_HAVE_SPI2 - select SPI - select STM32F0_SPI - -config STM32F0_SPI3 - bool "SPI3" - default n - depends on STM32F0_HAVE_SPI3 - select SPI - select STM32F0_SPI - -config STM32F0_SPI4 - bool "SPI4" - default n - depends on STM32F0_HAVE_SPI4 - select SPI - select STM32F0_SPI - -config STM32F0_SPI5 - bool "SPI5" - default n - depends on STM32F0_HAVE_SPI5 - select SPI - select STM32F0_SPI - -config STM32F0_SPI6 - bool "SPI6" - default n - depends on STM32F0_HAVE_SPI6 - select SPI - select STM32F0_SPI - -config STM32F0_SYSCFG - bool "SYSCFG" - default y - -config STM32F0_TIM1 - bool "TIM1" - default n - depends on STM32F0_HAVE_TIM1 - -config STM32F0_TIM2 - bool "TIM2" - default n - -config STM32F0_TIM3 - bool "TIM3" - default n - depends on STM32F0_HAVE_TIM3 - -config STM32F0_TIM6 - bool "TIM6" - default n - depends on STM32F0_HAVE_TIM6 - -config STM32F0_TIM7 - bool "TIM7" - default n - depends on STM32F0_HAVE_TIM7 - -config STM32F0_TIM14 - bool "TIM14" - default n - depends on STM32F0_HAVE_TIM14 - -config STM32F0_TIM15 - bool "TIM15" - default n - depends on STM32F0_HAVE_TIM15 - -config STM32F0_TIM16 - bool "TIM16" - default n - depends on STM32F0_HAVE_TIM16 - -config STM32F0_TIM17 - bool "TIM17" - default n - depends on STM32F0_HAVE_TIM17 - -config STM32F0_TSC - bool "TSC" - default n - depends on STM32F0_HAVE_TSC - -config STM32F0_USART1 - bool "USART1" - default n - select STM32F0_USART - -config STM32F0_USART2 - bool "USART2" - default n - select STM32F0_USART - -config STM32F0_USART3 - bool "USART3" - default n - depends on STM32F0_HAVE_USART3 - select STM32F0_USART - -config STM32F0_USART4 - bool "USART4" - default n - depends on STM32F0_HAVE_USART4 - select STM32F0_USART - -config STM32F0_USART5 - bool "USART5" - default n - depends on STM32F0_HAVE_USART5 - select STM32F0_USART - -config STM32F0_USART6 - bool "USART6" - default n - depends on STM32F0_HAVE_USART6 - select STM32F0_USART - -config STM32F0_USART7 - bool "USART7" - default n - depends on STM32F0_HAVE_USART7 - select STM32F0_USART - -config STM32F0_USART8 - bool "USART8" - default n - depends on STM32F0_HAVE_USART8 - select STM32F0_USART - -config STM32F0_USB - bool "USB Device" - default n - depends on STM32F0_HAVE_USBDEV - select USBDEV - -config STM32F0_IWDG - bool "IWDG" - default n - select WATCHDOG - -config STM32F0_WWDG - bool "WWDG" - default n - select WATCHDOG - -endmenu - -config STM32F0_ADC - bool - -config STM32F0_SDADC - bool - -config STM32F0_DAC - bool - -config STM32F0_SPI - bool - -config STM32F0_I2C - bool - -config STM32F0_CAN - bool - -config STM32F0_USART - bool - -config STM32F0_SERIALDRIVER - bool - -config STM32F0_1WIREDRIVER - bool - -menu "U[S]ART Configuration" - depends on STM32F0_USART - -comment "U[S]ART Device Configuration" - -choice - prompt "USART1 Driver Configuration" - default STM32F0_USART1_SERIALDRIVER - depends on STM32F0_USART1 - -config STM32F0_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0_SERIALDRIVER - -config STM32F0_USART1_1WIREDRIVER - bool "1-Wire driver" - select STM32F0_1WIREDRIVER - -endchoice # USART1 Driver Configuration - -if STM32F0_USART1_SERIALDRIVER - -config USART1_RS485 - bool "RS-485 on USART1" - default n - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32F0_USART1_SERIALDRIVER - -choice - prompt "USART2 Driver Configuration" - default STM32F0_USART2_SERIALDRIVER - depends on STM32F0_USART2 - -config STM32F0_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0_SERIALDRIVER - -config STM32F0_USART2_1WIREDRIVER - bool "1-Wire driver" - select STM32F0_1WIREDRIVER - -endchoice # USART2 Driver Configuration - -if STM32F0_USART2_SERIALDRIVER - -config USART2_RS485 - bool "RS-485 on USART2" - default n - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32F0_USART2_SERIALDRIVER - -choice - prompt "USART3 Driver Configuration" - default STM32F0_USART3_SERIALDRIVER - depends on STM32F0_USART3 - -config STM32F0_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0_SERIALDRIVER - -config STM32F0_USART3_1WIREDRIVER - bool "1-Wire driver" - select STM32F0_1WIREDRIVER - -endchoice # USART3 Driver Configuration - -if STM32F0_USART3_SERIALDRIVER - -config USART3_RS485 - bool "RS-485 on USART3" - default n - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32F0_USART3_SERIALDRIVER - - -choice - prompt "USART4 Driver Configuration" - default STM32F0_USART4_SERIALDRIVER - depends on STM32F0_USART4 - -config STM32F0_USART4_SERIALDRIVER - bool "Standard serial driver" - select USART4_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0_SERIALDRIVER - -config STM32F0_USART4_1WIREDRIVER - bool "1-Wire driver" - select STM32F0_1WIREDRIVER - -endchoice # USART4 Driver Configuration - -if STM32F0_USART4_SERIALDRIVER - -config USART4_RS485 - bool "RS-485 on USART4" - default n - ---help--- - Enable RS-485 interface on USART4. Your board config will have to - provide GPIO_USART4_RS485_DIR pin definition. - -config USART4_RS485_DIR_POLARITY - int "USART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32F0_USART4_SERIALDRIVER - - -choice - prompt "USART5 Driver Configuration" - default STM32F0_USART5_SERIALDRIVER - depends on STM32F0_USART5 - -config STM32F0_USART5_SERIALDRIVER - bool "Standard serial driver" - select USART5_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0_SERIALDRIVER - -config STM32F0_USART5_1WIREDRIVER - bool "1-Wire driver" - select STM32F0_1WIREDRIVER - -endchoice # USART5 Driver Configuration - -if STM32F0_USART5_SERIALDRIVER - -config USART5_RS485 - bool "RS-485 on USART5" - default n - ---help--- - Enable RS-485 interface on USART5. Your board config will have to - provide GPIO_USART5_RS485_DIR pin definition. - -config USART5_RS485_DIR_POLARITY - int "USART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32F0_USART5_SERIALDRIVER - - -choice - prompt "USART6 Driver Configuration" - default STM32F0_USART6_SERIALDRIVER - depends on STM32F0_USART6 - -config STM32F0_USART6_SERIALDRIVER - bool "Standard serial driver" - select USART6_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0_SERIALDRIVER - -config STM32F0_USART6_1WIREDRIVER - bool "1-Wire driver" - select STM32F0_1WIREDRIVER - -endchoice # USART6 Driver Configuration - -if STM32F0_USART6_SERIALDRIVER - -config USART6_RS485 - bool "RS-485 on USART6" - default n - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART6_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32F0_USART6_SERIALDRIVER - -choice - prompt "USART7 Driver Configuration" - default STM32F0_USART7_SERIALDRIVER - depends on STM32F0_USART7 - -config STM32F0_USART7_SERIALDRIVER - bool "Standard serial driver" - select USART7_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0_SERIALDRIVER - -config STM32F0_USART7_1WIREDRIVER - bool "1-Wire driver" - select STM32F0_1WIREDRIVER - -endchoice # USART7 Driver Configuration - -if STM32F0_USART7_SERIALDRIVER - -config USART7_RS485 - bool "RS-485 on USART7" - default n - ---help--- - Enable RS-485 interface on USART7. Your board config will have to - provide GPIO_USART7_RS485_DIR pin definition. - -config USART7_RS485_DIR_POLARITY - int "USART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART7_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32F0_USART7_SERIALDRIVER - -choice - prompt "USART8 Driver Configuration" - default STM32F0_USART8_SERIALDRIVER - depends on STM32F0_USART8 - -config STM32F0_USART8_SERIALDRIVER - bool "Standard serial driver" - select USART8_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0_SERIALDRIVER - -config STM32F0_USART8_1WIREDRIVER - bool "1-Wire driver" - select STM32F0_1WIREDRIVER - -endchoice # USART8 Driver Configuration - -if STM32F0_USART8_SERIALDRIVER - -config USART8_RS485 - bool "RS-485 on USART8" - default n - ---help--- - Enable RS-485 interface on USART8. Your board config will have to - provide GPIO_USART8_RS485_DIR pin definition. - -config USART8_RS485_DIR_POLARITY - int "USART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART8_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32F0_USART8_SERIALDRIVER - -menu "Serial Driver Configuration" - depends on STM32F0_SERIALDRIVER - -config STM32F0_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some configs and a serial console in other configs, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32F0_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32F0_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32F0 serial driver. - -endmenu # Serial Driver Configuration - -if PM - -config STM32F0_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif - -endmenu diff --git a/arch/arm/src/stm32f0/chip/stm32f05xf07xf09x_memorymap.h b/arch/arm/src/stm32f0/chip/stm32f05xf07xf09x_memorymap.h deleted file mode 100644 index 84bb978aaf2..00000000000 --- a/arch/arm/src/stm32f0/chip/stm32f05xf07xf09x_memorymap.h +++ /dev/null @@ -1,157 +0,0 @@ -/************************************************************************************ - * arch/arm/src/stm32f0/chip/stm32f05xf07xf09x_memorymap.h - * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Alan Carvalho de Assis - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_ST32F05XF07XF09X_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_ST32F05XF07XF09X_MEMORYMAP_H - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* ST32F05XF07X Address Blocks ******************************************************/ - -#define STM32F0_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ -#define STM32F0_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */ -#define STM32F0_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ - /* 0x60000000-0xdfffffff: Reserved */ -#define STM32F0_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ - -#define STM32F0_REGION_MASK 0xf0000000 -#define STM32F0_IS_SRAM(a) ((((uint32_t)(a)) & STM32F0_REGION_MASK) == STM32F0_SRAM_BASE) - -/* Code Base Addresses **************************************************************/ - -#define STM32F0_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ - /* 0x00100000-0x07ffffff: Reserved */ -#define STM32F0_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ - /* 0x08100000-0x0fffffff: Reserved */ -#define STM32F0_CCMRAM_BASE 0x10000000 /* 0x10000000-0x1000ffff: 64Kb CCM data RAM */ - /* 0x10010000-0x1ffeffff: Reserved */ -#define STM32F0_SYSMEM_BASE 0x1fffd800 /* 0x1fff0000-0x1fff7a0f: System memory */ - /* 0x1fff7a10-0x1fff7fff: Reserved */ -#define STM32F0_OPTION_BASE 0x1ffff800 /* 0x1fffc000-0x1fffc007: Option bytes */ - /* 0x1fffc008-0x1fffffff: Reserved */ - -/* System Memory Addresses **********************************************************/ - -#define STM32F0_SYSMEM_UID 0x1ffff7ac /* The 96-bit unique device identifier */ -#define STM32F0_SYSMEM_FSIZE 0x1ffff7cc /* This bitfield indicates the size of - * the device Flash memory expressed in - * Kbytes. Example: 0x040 corresponds - * to 64 Kbytes - */ - -/* Peripheral Base Addresses ********************************************************/ - -#define STM32F0_APB1_BASE 0x40000000 /* 0x40000000-0x40009fff: APB1 */ - /* 0x4000a000-0x4000ffff: Reserved */ -#define STM32F0_APB2_BASE 0x40010000 /* 0x40010000-0x40006bff: APB2 */ - /* 0x40016c00-0x4001ffff: Reserved */ -#define STM32F0_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */ - /* 0x40024400-0x4007ffff: Reserved */ -#define STM32F0_AHB2_BASE 0x48000000 /* 0x48000000-0x480017ff: AHB2 */ - /* 0x48001800-0x4fffFfff: Reserved */ -#define STM32F0_AHB3_BASE 0x50000000 /* 0x50000000-0x500007ff: AHB3 */ - -/* APB1 Base Addresses **************************************************************/ - -#define STM32F0_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff TIM2 */ -#define STM32F0_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff TIM3 */ -#define STM32F0_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */ -#define STM32F0_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */ -#define STM32F0_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff TIM14 */ -#define STM32F0_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */ -#define STM32F0_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */ -#define STM32F0_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */ -#define STM32F0_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff SPI2, or */ -#define STM32F0_I2S2_BASE 0x40003800 /* 0x40003800-0x40003bff I2S2 */ -#define STM32F0_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff USART2 */ -#define STM32F0_USART3_BASE 0x40004800 /* 0x40004800-0x40004bff USART3 */ -#define STM32F0_USART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff USART4 */ -#define STM32F0_USART5_BASE 0x40005000 /* 0x40005000-0x400053ff USART5 */ -#define STM32F0_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff I2C1 */ -#define STM32F0_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff I2C2 */ -#define STM32F0_USB_BASE 0x40005c00 /* 0x40005c00-0x40005fff USB device FS */ -#define STM32F0_USBRAM_BASE 0x40006000 /* 0x40006000-0x400063ff USB SRAM 512B */ -#define STM32F0_CAN_BASE 0x40006400 /* 0x40006400-0x400067ff bxCAN */ -#define STM32F0_CRS_BASE 0x40006c00 /* 0x40006c00-0x40006fff CRS */ -#define STM32F0_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */ -#define STM32F0_DAC_BASE 0x40007400 /* 0x40007400-0x400077ff DAC */ -#define STM32F0_CEC_BASE 0x40007800 /* 0x40007800-0x40007bff HDMI CEC */ - -/* APB2 Base Addresses **************************************************************/ - -#define STM32F0_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103ff SYSCFG + COMP + OPAMP */ -#define STM32F0_EXTI_BASE 0x40010400 /* 0x40010400-0x400107ff EXTI */ -#define STM32F0_USART6_BASE 0x40011400 /* 0x40011400-0x400117ff USART6 */ -#define STM32F0_USART7_BASE 0x40011800 /* 0x40011800-0x40011bff USART7 */ -#define STM32F0_USART8_BASE 0x40011c00 /* 0x40011c00-0x40011fff USART8 */ -#define STM32F0_ADC_BASE 0x40012400 /* 0x40012400-0x400127ff ADC */ -#define STM32F0_TIM1_BASE 0x40012c00 /* 0x40012c00-0x40012fff TIM1 */ -#define STM32F0_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */ -#define STM32F0_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */ -#define STM32F0_TIM15_BASE 0x40014000 /* 0x40014000-0x400143ff TIM15 */ -#define STM32F0_TIM16_BASE 0x40014400 /* 0x40014400-0x400147ff TIM16 */ -#define STM32F0_TIM17_BASE 0x40014800 /* 0x40014800-0x40014bff TIM17 */ -#define STM32F0_DBGMCU_BASE 0x40015800 /* 0x40015800-0x40015bff DBGMCU */ - -/* AHB1 Base Addresses **************************************************************/ - -#define STM32F0_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */ -#define STM32F0_DMA2_BASE 0x40020400 /* 0x40020400-0x400207ff: DMA2 */ -#define STM32F0_RCC_BASE 0x40021000 /* 0x40021000-0x400213ff: Reset and Clock control RCC */ -#define STM32F0_FLASHIF_BASE 0x40022000 /* 0x40022000-0x400223ff: Flash memory interface */ -#define STM32F0_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */ -#define STM32F0_TSC_BASE 0x40024000 /* 0x40024000-0x400243ff: TSC */ - -/* AHB2 Base Addresses **************************************************************/ - -#define STM32F0_GPIOA_BASE 0x48000000 /* 0x48000000-0x480003ff: GPIO Port A */ -#define STM32F0_GPIOB_BASE 0x48000400 /* 0x48000400-0x480007ff: GPIO Port B */ -#define STM32F0_GPIOC_BASE 0x48000800 /* 0x48000800-0x48000bff: GPIO Port C */ -#define STM32F0_GPIOD_BASE 0X48000C00 /* 0x48000c00-0x48000fff: GPIO Port D */ -#define STM32F0_GPIOE_BASE 0x48001000 /* 0x48001000-0x480013ff: GPIO Port E */ -#define STM32F0_GPIOF_BASE 0x48001400 /* 0x48001400-0x480017ff: GPIO Port F */ - -/* Cortex-M4 Base Addresses *********************************************************/ -/* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in this - * address range - */ - -#define STM32F0_SCS_BASE 0xe000e000 -#define STM32F0_DEBUGMCU_BASE 0xe0042000 - -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_ST32F05XF07XF09X_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_adc.h b/arch/arm/src/stm32f0/chip/stm32f0_adc.h deleted file mode 100644 index 00ecab0d64f..00000000000 --- a/arch/arm/src/stm32f0/chip/stm32f0_adc.h +++ /dev/null @@ -1,195 +0,0 @@ -/******************************************************************************** - * arch/arm/src/stm32f0/chip/stm32f0_adc.h - * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Alan Carvalho de Assis - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ********************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_ADC_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_ADC_H - -/******************************************************************************** - * Included Files - ********************************************************************************/ - -#include - -#include "chip.h" - -/******************************************************************************** - * Pre-processor Definitions - ********************************************************************************/ - -/* Register Offsets *********************************************************************************/ - -#define STM32F0_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */ -#define STM32F0_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */ -#define STM32F0_ADC_CR_OFFSET 0x0008 /* ADC control register */ -#define STM32F0_ADC_CFGR1_OFFSET 0x000c /* ADC configuration register 1 */ -#define STM32F0_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */ -#define STM32F0_ADC_SMPR_OFFSET 0x0014 /* ADC sample time register */ -#define STM32F0_ADC_TR_OFFSET 0x0020 /* ADC watchdog threshold register */ -#define STM32F0_ADC_CHSELR_OFFSET 0x0028 /* ADC channel selection register */ -#define STM32F0_ADC_DR_OFFSET 0x0040 /* ADC regular data register */ -#define STM32F0_ADC_CCR_OFFSET 0x0308 /* ADC common configuration register */ - -/* Register Addresses *******************************************************************************/ - -#define STM32F0_ADC_ISR (STM32F0_ADC_BASE+STM32F0_ADC_ISR_OFFSET) -#define STM32F0_ADC_IER (STM32F0_ADC_BASE+STM32F0_ADC_IER_OFFSET) -#define STM32F0_ADC_CR (STM32F0_ADC_BASE+STM32F0_ADC_CR_OFFSET) -#define STM32F0_ADC_CFGR1 (STM32F0_ADC_BASE+STM32F0_ADC_CFGR1_OFFSET) -#define STM32F0_ADC_CFGR2 (STM32F0_ADC_BASE+STM32F0_ADC_CFGR2_OFFSET) -#define STM32F0_ADC_SMPR (STM32F0_ADC_BASE+STM32F0_ADC_SMPR_OFFSET) -#define STM32F0_ADC_TR (STM32F0_ADC_BASE+STM32F0_ADC_TR_OFFSET) -#define STM32F0_ADC_CHSELR (STM32F0_ADC_BASE+STM32F0_ADC_CHSELR_OFFSET) -#define STM32F0_ADC_DR (STM32F0_ADC_BASE+STM32F0_ADC_DR_OFFSET) -#define STM32F0_ADC_CCR (STM32F0_ADC_BASE+STM32F0_ADC_CCR_OFFSET) - -/* Register Bitfield Definitions ************************************************/ - -/* ADC interrupt and status register (ISR) and ADC interrupt enable register (IER) */ - -#define ADC_INT_ARDY (1 << 0) /* Bit 0: ADC ready */ -#define ADC_INT_EOSMP (1 << 1) /* Bit 1: End of sampling flag */ -#define ADC_INT_EOC (1 << 2) /* Bit 2: End of conversion */ -#define ADC_INT_EOS (1 << 3) /* Bit 3: End of regular sequence flag */ -#define ADC_INT_OVR (1 << 4) /* Bit 4: Overrun */ -#define ADC_INT_AWD (1 << 7) /* Bit 7: Analog watchdog flag */ - -/* ADC control register */ - -#define ADC_CR_ADEN (1 << 0) /* Bit 0: ADC enable control */ -#define ADC_CR_ADDIS (1 << 1) /* Bit 1: ADC disable command */ -#define ADC_CR_ADSTART (1 << 2) /* Bit 2: ADC start of regular conversion */ -#define ADC_CR_ADSTP (1 << 4) /* Bit 4: ADC stop of regular conversion command */ -#define ADC_CR_ADCAL (1 << 31) /* Bit 31: ADC calibration */ - -/* ADC configuration register 1 */ - -#define ADC_CFGR1_DMAEN (1 << 0) /* Bit 0: Direct memory access enable */ -#define ADC_CFGR1_DMACFG (1 << 1) /* Bit 1: Direct memory access configuration */ -#define ADC_CFGR1_SCANDIR (1 << 2) /* Bit 2: Scan sequence direction */ -#define ADC_CFGR1_RES_SHIFT (3) /* Bits 3-4: Data resolution */ -#define ADC_CFGR1_RES_MASK (3 << ADC_CFGR1_RES_SHIFT) -# define ADC_CFGR1_RES_12BIT (0 << ADC_CFGR1_RES_SHIFT) /* 15 ADCCLK clyes */ -# define ADC_CFGR1_RES_10BIT (1 << ADC_CFGR1_RES_SHIFT) /* 13 ADCCLK clyes */ -# define ADC_CFGR1_RES_8BIT (2 << ADC_CFGR1_RES_SHIFT) /* 11 ADCCLK clyes */ -# define ADC_CFGR1_RES_6BIT (3 << ADC_CFGR1_RES_SHIFT) /* 9 ADCCLK clyes */ -#define ADC_CFGR1_ALIGN (1 << 5) /* Bit 5: Data Alignment */ -#define ADC_CFGR1_EXTSEL_SHIFT (6) /* Bits 6-8: External trigger selection */ -#define ADC_CFGR1_EXTSEL_MASK (7 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_TRG0 (0 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_TRG1 (1 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_TRG2 (2 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_TRG3 (3 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_TRG4 (4 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_TRG5 (5 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_TRG6 (6 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_TRG7 (7 << ADC_CFGR1_EXTSEL_SHIFT) -#define ADC_CFGR1_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */ -#define ADC_CFGR1_EXTEN_MASK (3 << ADC_CFGR1_EXTEN_SHIFT) -# define ADC_CFGR1_EXTEN_NONE (0 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection disabled */ -# define ADC_CFGR1_EXTEN_RISING (1 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the rising edge */ -# define ADC_CFGR1_EXTEN_FALLING (2 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the falling edge */ -# define ADC_CFGR1_EXTEN_BOTH (3 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on both edges */ -#define ADC_CFGR1_OVRMOD (1 << 12) /* Bit 12: Overrun Mode */ -#define ADC_CFGR1_CONT (1 << 13) /* Bit 13: Continuous mode for regular conversions */ -#define ADC_CFGR1_WAIT (1 << 14) /* Bit 14: Wait convertion mode */ -#define ADC_CFGR1_AUTOFF (1 << 15) /* Bit 15: Auto-off mode */ -#define ADC_CFGR1_DISCEN (1 << 16) /* Bit 16: Discontinuous mode on regular channels */ -#define ADC_CFGR1_AWDSGL (1 << 22) /* Bit 22: Enable watchdog on single/all channels */ -#define ADC_CFGR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable */ -#define ADC_CFGR1_AWDCH_SHIFT (26) /* Bits 26-30: Analog watchdog 1 channel select bits */ -#define ADC_CFGR1_AWDCH_MASK (31 << ADC_CFGR1_AWDCH_SHIFT) -# define ADC_CFGR1_AWDCH_DISABLED (0 << ADC_CFGR1_AWDCH_SHIFT) - -/* ADC configuration register 2 */ - -#define ADC_CFGR2_CKMODE_SHIFT (30) /* Bits 30-31: ADC clock mode */ -#define ADC_CFGR2_CKMODE_MASK (3 << ADC_CFGR2_CKMODE_SHIFT) -# define ADC_CFGR2_CKMODE_ADCCLK (0 << ADC_CFGR2_CKMODE_SHIFT) /* 00: ADCCLK (Asynchronous) generated at product level */ -# define ADC_CFGR2_CKMODE_PCLKd2 (1 << ADC_CFGR2_CKMODE_SHIFT) /* 01: PCLK/2 (Synchronous clock mode) */ -# define ADC_CFGR2_CKMODE_PCLKd4 (2 << ADC_CFGR2_CKMODE_SHIFT) /* 10: PCLK/4 (Synchronous clock mode) */ - -/* ADC sample time register */ - -#define ADC_SMPR_SMP_SHIFT (0) /* Bits 0-2: Sampling time selection */ -#define ADC_SMPR_SMP_MASK (7 << ADC_SMPR_SMP_SHIFT) -#define ADC_SMPR_SMP_1p5 (0 << ADC_SMPR_SMP_SHIFT) /* 000: 1.5 cycles */ -#define ADC_SMPR_SMP_7p5 (1 << ADC_SMPR_SMP_SHIFT) /* 001: 7.5 cycles */ -#define ADC_SMPR_SMP_13p5 (2 << ADC_SMPR_SMP_SHIFT) /* 010: 13.5 cycles */ -#define ADC_SMPR_SMP_28p5 (3 << ADC_SMPR_SMP_SHIFT) /* 011: 28.5 cycles */ -#define ADC_SMPR_SMP_41p5 (4 << ADC_SMPR_SMP_SHIFT) /* 100: 41.5 cycles */ -#define ADC_SMPR_SMP_55p5 (5 << ADC_SMPR_SMP_SHIFT) /* 101: 55.5 cycles */ -#define ADC_SMPR_SMP_71p5 (6 << ADC_SMPR_SMP_SHIFT) /* 110: 71.5 cycles */ -#define ADC_SMPR_SMP_239p5 (7 << ADC_SMPR_SMP_SHIFT) /* 111: 239.5 cycles */ - -/* ADC watchdog threshold register */ - -#define ADC_TR_LT_SHIFT (0) /* Bits 0-11: Analog watchdog lower threshold */ -#define ADC_TR_LT_MASK (0x0fff << ADC_TR_LT_SHIFT) -#define ADC_TR_HT_SHIFT (16) /* Bits 16-27: Analog watchdog higher threshold */ -#define ADC_TR_HT_MASK (0x0fff << ADC_TR_HT_SHIFT) - -/* ADC channel selection register */ - -#define ADC_CHSELR_CHSEL0 (1 << 0) /* Select channel 0 */ -#define ADC_CHSELR_CHSEL1 (1 << 1) /* Select channel 1 */ -#define ADC_CHSELR_CHSEL2 (1 << 2) /* Select channel 2 */ -#define ADC_CHSELR_CHSEL3 (1 << 3) /* Select channel 3 */ -#define ADC_CHSELR_CHSEL4 (1 << 4) /* Select channel 4 */ -#define ADC_CHSELR_CHSEL5 (1 << 5) /* Select channel 5 */ -#define ADC_CHSELR_CHSEL6 (1 << 6) /* Select channel 6 */ -#define ADC_CHSELR_CHSEL7 (1 << 7) /* Select channel 7 */ -#define ADC_CHSELR_CHSEL8 (1 << 8) /* Select channel 8 */ -#define ADC_CHSELR_CHSEL9 (1 << 9) /* Select channel 9 */ -#define ADC_CHSELR_CHSEL10 (1 << 10) /* Select channel 10 */ -#define ADC_CHSELR_CHSEL11 (1 << 11) /* Select channel 11 */ -#define ADC_CHSELR_CHSEL12 (1 << 12) /* Select channel 12 */ -#define ADC_CHSELR_CHSEL13 (1 << 13) /* Select channel 13 */ -#define ADC_CHSELR_CHSEL14 (1 << 14) /* Select channel 14 */ -#define ADC_CHSELR_CHSEL15 (1 << 15) /* Select channel 15 */ -#define ADC_CHSELR_CHSEL16 (1 << 16) /* Select channel 16 */ -#define ADC_CHSELR_CHSEL17 (1 << 17) /* Select channel 17 */ -#define ADC_CHSELR_CHSEL18 (1 << 18) /* Select channel 18 */ - -#define ADC_DR_RDATA_SHIFT (0) -#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) - -/* Common configuration register */ - -#define ADC_CCR_VREFEN (1 << 22) /* Bit 22: VREFINT enable */ -#define ADC_CCR_TSEN (1 << 23) /* Bit 23: Temperature sensor enable */ -#define ADC_CCR_VBATEN (1 << 24) /* Bit 22: VBAT enable */ - -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_ADC_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_dma.h b/arch/arm/src/stm32f0/chip/stm32f0_dma.h deleted file mode 100644 index a0d82628fba..00000000000 --- a/arch/arm/src/stm32f0/chip/stm32f0_dma.h +++ /dev/null @@ -1,456 +0,0 @@ -/************************************************************************************ - * arch/arm/src/stm32f0/chip/stm32f0_dma.h - * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Alan Carvalho de Assis - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_DMA_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_DMA_H - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ -/* 12 Channels Total: 7 DMA1 Channels(1-7) (and 5 DMA2 channels (1-5) if STM32F09x) */ - -#define DMA1 0 -#define DMA2 1 -#define DMA3 2 -#define DMA4 3 -#define DMA5 4 -#define DMA6 5 -#define DMA7 6 - -/* Register Offsets *****************************************************************/ - -#define STM32F0_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32F0_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ - -#define STM32F0_DMACHAN_OFFSET(n) (0x0014*(n)) -#define STM32F0_DMACHAN1_OFFSET 0x0000 -#define STM32F0_DMACHAN2_OFFSET 0x0014 -#define STM32F0_DMACHAN3_OFFSET 0x0028 -#define STM32F0_DMACHAN4_OFFSET 0x003c -#define STM32F0_DMACHAN5_OFFSET 0x0050 -#define STM32F0_DMACHAN6_OFFSET 0x0064 -#define STM32F0_DMACHAN7_OFFSET 0x0078 - -#define STM32F0_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32F0_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32F0_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32F0_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ - -#define STM32F0_DMA_CCR_OFFSET(n) (STM32F0_DMACHAN_CCR_OFFSET+STM32F0_DMACHAN_OFFSET(n)) -#define STM32F0_DMA_CNDTR_OFFSET(n) (STM32F0_DMACHAN_CNDTR_OFFSET+STM32F0_DMACHAN_OFFSET(n)) -#define STM32F0_DMA_CPAR_OFFSET(n) (STM32F0_DMACHAN_CPAR_OFFSET+STM32F0_DMACHAN_OFFSET(n)) -#define STM32F0_DMA_CMAR_OFFSET(n) (STM32F0_DMACHAN_CMAR_OFFSET+STM32F0_DMACHAN_OFFSET(n)) - -#define STM32F0_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32F0_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32F0_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32F0_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32F0_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32F0_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32F0_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ - -#define STM32F0_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32F0_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32F0_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32F0_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32F0_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32F0_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32F0_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ - -#define STM32F0_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32F0_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32F0_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32F0_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32F0_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32F0_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32F0_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ - -#define STM32F0_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32F0_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32F0_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32F0_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32F0_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32F0_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32F0_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ - -#define STM32F0_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ - -/* Register Addresses ***************************************************************/ - -#define STM32F0_DMA1_ISRC (STM32F0_DMA1_BASE+STM32F0_DMA_ISR_OFFSET) -#define STM32F0_DMA1_IFCR (STM32F0_DMA1_BASE+STM32F0_DMA_IFCR_OFFSET) - -#define STM32F0_DMA1_CCR(n) (STM32F0_DMA1_BASE+STM32F0_DMA_CCR_OFFSET(n)) -#define STM32F0_DMA1_CCR1 (STM32F0_DMA1_BASE+STM32F0_DMA_CCR1_OFFSET) -#define STM32F0_DMA1_CCR2 (STM32F0_DMA1_BASE+STM32F0_DMA_CCR2_OFFSET) -#define STM32F0_DMA1_CCR3 (STM32F0_DMA1_BASE+STM32F0_DMA_CCR3_OFFSET) -#define STM32F0_DMA1_CCR4 (STM32F0_DMA1_BASE+STM32F0_DMA_CCR4_OFFSET) -#define STM32F0_DMA1_CCR5 (STM32F0_DMA1_BASE+STM32F0_DMA_CCR5_OFFSET) -#define STM32F0_DMA1_CCR6 (STM32F0_DMA1_BASE+STM32F0_DMA_CCR6_OFFSET) -#define STM32F0_DMA1_CCR7 (STM32F0_DMA1_BASE+STM32F0_DMA_CCR7_OFFSET) - -#define STM32F0_DMA1_CNDTR(n) (STM32F0_DMA1_BASE+STM32F0_DMA_CNDTR_OFFSET(n)) -#define STM32F0_DMA1_CNDTR1 (STM32F0_DMA1_BASE+STM32F0_DMA_CNDTR1_OFFSET) -#define STM32F0_DMA1_CNDTR2 (STM32F0_DMA1_BASE+STM32F0_DMA_CNDTR2_OFFSET) -#define STM32F0_DMA1_CNDTR3 (STM32F0_DMA1_BASE+STM32F0_DMA_CNDTR3_OFFSET) -#define STM32F0_DMA1_CNDTR4 (STM32F0_DMA1_BASE+STM32F0_DMA_CNDTR4_OFFSET) -#define STM32F0_DMA1_CNDTR5 (STM32F0_DMA1_BASE+STM32F0_DMA_CNDTR5_OFFSET) -#define STM32F0_DMA1_CNDTR6 (STM32F0_DMA1_BASE+STM32F0_DMA_CNDTR6_OFFSET) -#define STM32F0_DMA1_CNDTR7 (STM32F0_DMA1_BASE+STM32F0_DMA_CNDTR7_OFFSET) - -#define STM32F0_DMA1_CPAR(n) (STM32F0_DMA1_BASE+STM32F0_DMA_CPAR_OFFSET(n)) -#define STM32F0_DMA1_CPAR1 (STM32F0_DMA1_BASE+STM32F0_DMA_CPAR1_OFFSET) -#define STM32F0_DMA1_CPAR2 (STM32F0_DMA1_BASE+STM32F0_DMA_CPAR2_OFFSET) -#define STM32F0_DMA1_CPAR3 (STM32F0_DMA1_BASE+STM32F0_DMA_CPAR3_OFFSET) -#define STM32F0_DMA1_CPAR4 (STM32F0_DMA1_BASE+STM32F0_DMA_CPAR4_OFFSET) -#define STM32F0_DMA1_CPAR5 (STM32F0_DMA1_BASE+STM32F0_DMA_CPAR5_OFFSET) -#define STM32F0_DMA1_CPAR6 (STM32F0_DMA1_BASE+STM32F0_DMA_CPAR6_OFFSET) -#define STM32F0_DMA1_CPAR7 (STM32F0_DMA1_BASE+STM32F0_DMA_CPAR7_OFFSET) - -#define STM32F0_DMA1_CMAR(n) (STM32F0_DMA1_BASE+STM32F0_DMA_CMAR_OFFSET(n)) -#define STM32F0_DMA1_CMAR1 (STM32F0_DMA1_BASE+STM32F0_DMA_CMAR1_OFFSET) -#define STM32F0_DMA1_CMAR2 (STM32F0_DMA1_BASE+STM32F0_DMA_CMAR2_OFFSET) -#define STM32F0_DMA1_CMAR3 (STM32F0_DMA1_BASE+STM32F0_DMA_CMAR3_OFFSET) -#define STM32F0_DMA1_CMAR4 (STM32F0_DMA1_BASE+STM32F0_DMA_CMAR4_OFFSET) -#define STM32F0_DMA1_CMAR5 (STM32F0_DMA1_BASE+STM32F0_DMA_CMAR5_OFFSET) -#define STM32F0_DMA1_CMAR6 (STM32F0_DMA1_BASE+STM32F0_DMA_CMAR6_OFFSET) -#define STM32F0_DMA1_CMAR7 (STM32F0_DMA1_BASE+STM32F0_DMA_CMAR7_OFFSET) - -#define STM32F0_DMA2_ISRC (STM32F0_DMA2_BASE+STM32F0_DMA_ISR_OFFSET) -#define STM32F0_DMA2_IFCR (STM32F0_DMA2_BASE+STM32F0_DMA_IFCR_OFFSET) - -#define STM32F0_DMA2_CCR(n) (STM32F0_DMA2_BASE+STM32F0_DMA_CCR_OFFSET(n)) -#define STM32F0_DMA2_CCR1 (STM32F0_DMA2_BASE+STM32F0_DMA_CCR1_OFFSET) -#define STM32F0_DMA2_CCR2 (STM32F0_DMA2_BASE+STM32F0_DMA_CCR2_OFFSET) -#define STM32F0_DMA2_CCR3 (STM32F0_DMA2_BASE+STM32F0_DMA_CCR3_OFFSET) -#define STM32F0_DMA2_CCR4 (STM32F0_DMA2_BASE+STM32F0_DMA_CCR4_OFFSET) -#define STM32F0_DMA2_CCR5 (STM32F0_DMA2_BASE+STM32F0_DMA_CCR5_OFFSET) -#define STM32F0_DMA2_CCR6 (STM32F0_DMA2_BASE+STM32F0_DMA_CCR6_OFFSET) -#define STM32F0_DMA2_CCR7 (STM32F0_DMA2_BASE+STM32F0_DMA_CCR7_OFFSET) - -#define STM32F0_DMA2_CNDTR(n) (STM32F0_DMA2_BASE+STM32F0_DMA_CNDTR_OFFSET(n)) -#define STM32F0_DMA2_CNDTR1 (STM32F0_DMA2_BASE+STM32F0_DMA_CNDTR1_OFFSET) -#define STM32F0_DMA2_CNDTR2 (STM32F0_DMA2_BASE+STM32F0_DMA_CNDTR2_OFFSET) -#define STM32F0_DMA2_CNDTR3 (STM32F0_DMA2_BASE+STM32F0_DMA_CNDTR3_OFFSET) -#define STM32F0_DMA2_CNDTR4 (STM32F0_DMA2_BASE+STM32F0_DMA_CNDTR4_OFFSET) -#define STM32F0_DMA2_CNDTR5 (STM32F0_DMA2_BASE+STM32F0_DMA_CNDTR5_OFFSET) -#define STM32F0_DMA2_CNDTR6 (STM32F0_DMA2_BASE+STM32F0_DMA_CNDTR6_OFFSET) -#define STM32F0_DMA2_CNDTR7 (STM32F0_DMA2_BASE+STM32F0_DMA_CNDTR7_OFFSET) - -#define STM32F0_DMA2_CPAR(n) (STM32F0_DMA2_BASE+STM32F0_DMA_CPAR_OFFSET(n)) -#define STM32F0_DMA2_CPAR1 (STM32F0_DMA2_BASE+STM32F0_DMA_CPAR1_OFFSET) -#define STM32F0_DMA2_CPAR2 (STM32F0_DMA2_BASE+STM32F0_DMA_CPAR2_OFFSET) -#define STM32F0_DMA2_CPAR3 (STM32F0_DMA2_BASE+STM32F0_DMA_CPAR3_OFFSET) -#define STM32F0_DMA2_CPAR4 (STM32F0_DMA2_BASE+STM32F0_DMA_CPAR4_OFFSET) -#define STM32F0_DMA2_CPAR5 (STM32F0_DMA2_BASE+STM32F0_DMA_CPAR5_OFFSET) -#define STM32F0_DMA2_CPAR6 (STM32F0_DMA2_BASE+STM32F0_DMA_CPAR6_OFFSET) -#define STM32F0_DMA2_CPAR7 (STM32F0_DMA2_BASE+STM32F0_DMA_CPAR7_OFFSET) - -#define STM32F0_DMA2_CMAR(n) (STM32F0_DMA2_BASE+STM32F0_DMA_CMAR_OFFSET(n)) -#define STM32F0_DMA2_CMAR1 (STM32F0_DMA2_BASE+STM32F0_DMA_CMAR1_OFFSET) -#define STM32F0_DMA2_CMAR2 (STM32F0_DMA2_BASE+STM32F0_DMA_CMAR2_OFFSET) -#define STM32F0_DMA2_CMAR3 (STM32F0_DMA2_BASE+STM32F0_DMA_CMAR3_OFFSET) -#define STM32F0_DMA2_CMAR4 (STM32F0_DMA2_BASE+STM32F0_DMA_CMAR4_OFFSET) -#define STM32F0_DMA2_CMAR5 (STM32F0_DMA2_BASE+STM32F0_DMA_CMAR5_OFFSET) -#define STM32F0_DMA2_CMAR6 (STM32F0_DMA2_BASE+STM32F0_DMA_CMAR6_OFFSET) -#define STM32F0_DMA2_CMAR7 (STM32F0_DMA2_BASE+STM32F0_DMA_CMAR7_OFFSET) - -/* Register Bitfield Definitions ****************************************************/ - -#define DMA_CHAN_SHIFT(n) ((n) << 2) -#define DMA_CHAN_MASK 0x0f -#define DMA_CHAN_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */ -#define DMA_CHAN_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */ -#define DMA_CHAN_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */ -#define DMA_CHAN_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */ - -/* DMA interrupt status register */ - -#define DMA_ISR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n) -#define DMA_ISR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_ISR_CHAN_SHIFT(n)) -#define DMA_ISR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */ -#define DMA_ISR_CHAN1_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN1_SHIFT) -#define DMA_ISR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */ -#define DMA_ISR_CHAN2_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN2_SHIFT) -#define DMA_ISR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */ -#define DMA_ISR_CHAN3_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN3_SHIFT) -#define DMA_ISR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */ -#define DMA_ISR_CHAN4_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN4_SHIFT) -#define DMA_ISR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */ -#define DMA_ISR_CHAN5_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN5_SHIFT) -#define DMA_ISR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */ -#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT) -#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */ -#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT) - -#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n)) -#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n)) -#define DMA_ISR_HTIF(n) (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n)) -#define DMA_ISR_TEIF(n) (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n)) - -/* DMA interrupt flag clear register */ - -#define DMA_IFCR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n) -#define DMA_IFCR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_IFCR_CHAN_SHIFT(n)) -#define DMA_IFCR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt flag clear */ -#define DMA_IFCR_CHAN1_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN1_SHIFT) -#define DMA_IFCR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt flag clear */ -#define DMA_IFCR_CHAN2_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN2_SHIFT) -#define DMA_IFCR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt flag clear */ -#define DMA_IFCR_CHAN3_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN3_SHIFT) -#define DMA_IFCR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt flag clear */ -#define DMA_IFCR_CHAN4_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN4_SHIFT) -#define DMA_IFCR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt flag clear */ -#define DMA_IFCR_CHAN5_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN5_SHIFT) -#define DMA_IFCR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt flag clear */ -#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT) -#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */ -#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT) -#define DMA_IFCR_ALLCHANNELS (0x0fffffff) - -#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) -#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) -#define DMA_IFCR_CHTIF(n) (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) -#define DMA_IFCR_CTEIF(n) (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) - -/* DMA channel configuration register */ - -#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */ -#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */ -#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */ -#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */ -#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */ -#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */ -#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */ -#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */ -#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 8-9: Peripheral size */ -#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT) -# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */ -# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */ -# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */ -#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 10-11: Memory size */ -#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT) -# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */ -# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */ -# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */ -#define DMA_CCR_PL_SHIFT (12) /* Bits 12-13: Channel Priority level */ -#define DMA_CCR_PL_MASK (3 << DMA_CCR_PL_SHIFT) -# define DMA_CCR_PRILO (0 << DMA_CCR_PL_SHIFT) /* 00: Low */ -# define DMA_CCR_PRIMED (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */ -# define DMA_CCR_PRIHI (2 << DMA_CCR_PL_SHIFT) /* 10: High */ -# define DMA_CCR_PRIVERYHI (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */ -#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */ - -#define DMA_CCR_ALLINTS (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE) - -/* DMA channel number of data register */ - -#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */ -#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT) - -/* DMA Channel mapping. Each DMA channel has a mapping to one of several - * possible sources/sinks of data. The requests from peripherals assigned to a - * channel are multiplexed together before entering the DMA block. This means - * that only one request on a given channel can be enabled at once. - * - * Alternative DMA channel selections are provided with a numeric suffix like _1, - * _2, etc. Drivers, however, will use the pin selection without the numeric suffix. - * Additional definitions are required in the board.h file. - */ - -/* REVISE IT: based on STM32L4 DMA Header */ - -#define STM32F0_DMA1_CHAN1 (0) -#define STM32F0_DMA1_CHAN2 (1) -#define STM32F0_DMA1_CHAN3 (2) -#define STM32F0_DMA1_CHAN4 (3) -#define STM32F0_DMA1_CHAN5 (4) -#define STM32F0_DMA1_CHAN6 (5) -#define STM32F0_DMA1_CHAN7 (6) - -#define STM32F0_DMA2_CHAN1 (7) -#define STM32F0_DMA2_CHAN2 (8) -#define STM32F0_DMA2_CHAN3 (9) -#define STM32F0_DMA2_CHAN4 (10) -#define STM32F0_DMA2_CHAN5 (11) - -#define DMACHAN_SETTING(chan, sel) ( ( ( (sel) & 0xff) << 8) | ( (chan) & 0xff) ) -#define DMACHAN_SETTING_CHANNEL_MASK 0x00FF -#define DMACHAN_SETTING_CHANNEL_SHIFT (0) -#define DMACHAN_SETTING_FUNCTION_MASK 0xFF00 -#define DMACHAN_SETTING_FUNCTION_SHIFT (8) - -/* ADC */ - -#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN1, 0) -#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN3, 0) - -#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN1, 0) -#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN4, 0) - -#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN1, 0) -#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN5, 0) - -/* AES */ - -#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32F0_DMA2_CHAN1, 6) -#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN5, 6) -#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32F0_DMA2_CHAN2, 6) -#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN3, 6) - -/* DAC */ - -#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN3, 6) -#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32F0_DMA1_CHAN4, 5) -#define DMACHAN_DAC1_3 DMACHAN_SETTING(STM32F0_DMA2_CHAN4, 3) - -#define DMACHAN_DAC2 DMACHAN_SETTING(STM32F0_DMA2_CHAN5, 3) - -/* I2C */ - -#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN7, 3) -#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN6, 5) -#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN6, 3) -#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN7, 5) - -#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32F0_DMA1_CHAN5, 3) -#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32F0_DMA1_CHAN4, 3) - -#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32F0_DMA1_CHAN3, 2) -#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32F0_DMA1_CHAN2, 3) - -/* QUADSPI */ - -#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN5, 5) -#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN7, 3) - -/* SPI */ - -#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN2, 1) -#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN3, 4) -#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN3, 0) -#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN4, 4) - -#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32F0_DMA1_CHAN4, 1) -#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32F0_DMA1_CHAN5, 1) - -#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32F0_DMA2_CHAN1, 3) -#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32F0_DMA2_CHAN2, 3) - -/* TIM */ - -#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32F0_DMA1_CHAN2, 7) -#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32F0_DMA1_CHAN3, 7) -#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32F0_DMA1_CHAN7, 7) -#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32F0_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32F0_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32F0_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32F0_DMA1_CHAN6, 7) - -#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32F0_DMA1_CHAN5, 4) -#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32F0_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32F0_DMA1_CHAN1, 4) -#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32F0_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32F0_DMA1_CHAN2, 4) - -#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32F0_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32F0_DMA1_CHAN2, 5) -#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32F0_DMA1_CHAN3, 5) -#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32F0_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32F0_DMA1_CHAN3, 5) - -#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32F0_DMA1_CHAN1, 6) -#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32F0_DMA1_CHAN4, 6) -#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32F0_DMA1_CHAN5, 6) -#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32F0_DMA1_CHAN7, 6) - -#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32F0_DMA2_CHAN5, 5) -#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32F0_DMA2_CHAN4, 5) -#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32F0_DMA2_CHAN2, 5) -#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32F0_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32F0_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32F0_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32F0_DMA2_CHAN2, 5) - -#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN3, 6) -#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN4, 3) - -#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN4, 5) -#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN5, 3) - -#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32F0_DMA2_CHAN6, 7) -#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32F0_DMA2_CHAN7, 7) -#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32F0_DMA2_CHAN1, 7) -#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32F0_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32F0_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32F0_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32F0_DMA2_CHAN1, 7) - -#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32F0_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32F0_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32F0_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32F0_DMA1_CHAN5, 7) - -#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32F0_DMA1_CHAN6, 4) -#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32F0_DMA1_CHAN6, 4) - -#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN1, 5) -#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32F0_DMA1_CHAN7, 5) -#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN1, 5) -#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32F0_DMA1_CHAN7, 5) - -/* USARTs */ - -#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN5, 2) -#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN7, 2) -#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN4, 2) -#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN6, 2) - -#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32F0_DMA1_CHAN6, 2) -#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32F0_DMA1_CHAN7, 2) - -#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32F0_DMA1_CHAN3, 1) -#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32F0_DMA1_CHAN2, 2) - -#define DMACHAN_USART4_RX DMACHAN_SETTING(STM32F0_DMA2_CHAN5, 2) -#define DMACHAN_USART4_TX DMACHAN_SETTING(STM32F0_DMA2_CHAN3, 2) - -#define DMACHAN_USART5_RX DMACHAN_SETTING(STM32F0_DMA2_CHAN2, 2) -#define DMACHAN_USART5_TX DMACHAN_SETTING(STM32F0_DMA2_CHAN1, 2) - -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_DMA_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_exti.h b/arch/arm/src/stm32f0/chip/stm32f0_exti.h deleted file mode 100644 index a1814736687..00000000000 --- a/arch/arm/src/stm32f0/chip/stm32f0_exti.h +++ /dev/null @@ -1,131 +0,0 @@ -/************************************************************************************ - * arch/arm/src/stm32f0/chip/stm32f0_exti.h - * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Alan Carvalho de Assis - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_EXTI_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_EXTI_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include "chip.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -#define STM32F0_NEXTI 31 -#define STM32F0_EXTI_MASK 0xffffffff - -#define STM32F0_EXTI_BIT(n) (1 << (n)) - -/* Register Offsets *****************************************************************/ - -#define STM32F0_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */ -#define STM32F0_EXTI_EMR_OFFSET 0x0004 /* Event mask register */ -#define STM32F0_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */ -#define STM32F0_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */ -#define STM32F0_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */ -#define STM32F0_EXTI_PR_OFFSET 0x0014 /* Pending register */ - -/* Register Addresses ***************************************************************/ - -#define STM32F0_EXTI_IMR (STM32F0_EXTI_BASE+STM32F0_EXTI_IMR_OFFSET) -#define STM32F0_EXTI_EMR (STM32F0_EXTI_BASE+STM32F0_EXTI_EMR_OFFSET) -#define STM32F0_EXTI_RTSR (STM32F0_EXTI_BASE+STM32F0_EXTI_RTSR_OFFSET) -#define STM32F0_EXTI_FTSR (STM32F0_EXTI_BASE+STM32F0_EXTI_FTSR_OFFSET) -#define STM32F0_EXTI_SWIER (STM32F0_EXTI_BASE+STM32F0_EXTI_SWIER_OFFSET) -#define STM32F0_EXTI_PR (STM32F0_EXTI_BASE+STM32F0_EXTI_PR_OFFSET) - -/* Register Bitfield Definitions ****************************************************/ - -/* EXTI lines > 15 are associated with internal devices: */ - -#define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */ -#define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */ -#define EXTI_USB_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB wake up event */ -#define EXTI_RTC_TAMPER (1 << 19) /* EXTI line 19 is connected to the RTC Tamper and TimeStamp events */ -#define EXTI_RTC_WAKEUP (1 << 20) /* EXTI line 20 is connected to the RTC Wakeup event */ -#define EXTI_COMP1 (1 << 21) /* EXTI line 21 is connected to the COMP1 (comparator) output */ -#define EXTI_COMP2 (1 << 22) /* EXTI line 22 is connected to the COMP2 (comparator) output */ -#define EXTI_I2C1 (1 << 23) /* EXTI line 23 is connected to the I2C1 wakeup */ - /* EXTI line 24 is reserved (internally held low) */ -#define EXTI_USART1 (1 << 25) /* EXTI line 25 is connected to the USART1 wakeup */ -#define EXTI_USART2 (1 << 26) /* EXTI line 26 is connected to the USART2 wakeup */ -#define EXTI_CEC (1 << 27) /* EXTI line 27 is connected to the CEC wakeup */ -#define EXTI_USART3 (1 << 28) /* EXTI line 28 is connected to the USART3 wakeup */ - /* EXTI line 29 is reserved (internally held low) */ - /* EXTI line 30 is reserved (internally held low) */ -#define EXTI_VDDIO2 (1 << 31) /* EXTI line 31 is connected to the Vddio2 supply comparator */ - -/* Interrupt mask register */ - -#define EXTI_IMR_BIT(n) STM32F0_EXTI_BIT(n) /* 1=Interrupt request from line x is not masked */ -#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */ -#define EXTI_IMR_MASK STM32F0_EXTI_MASK - -/* Event mask register */ - -#define EXTI_EMR_BIT(n) STM32F0_EXTI_BIT(n) /* 1=Event request from line x is not mask */ -#define EXTI_EMR_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */ -#define EXTI_EMR_MASK STM32F0_EXTI_MASK - -/* Rising Trigger selection register */ - -#define EXTI_RTSR_BIT(n) STM32F0_EXTI_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */ -#define EXTI_RTSR_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */ -#define EXTI_RTSR_MASK STM32F0_EXTI_MASK - -/* Falling Trigger selection register */ - -#define EXTI_FTSR_BIT(n) STM32F0_EXTI_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */ -#define EXTI_FTSR_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */ -#define EXTI_FTSR_MASK STM32F0_EXTI_MASK - -/* Software interrupt event register */ - -#define EXTI_SWIER_BIT(n) STM32F0_EXTI_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */ -#define EXTI_SWIER_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */ -#define EXTI_SWIER_MASK STM32F0_EXTI_MASK - -/* Pending register */ - -#define EXTI_PR_BIT(n) STM32F0_EXTI_BIT(n) /* 1=Selected trigger request occurred */ -#define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ -#define EXTI_PR_MASK STM32F0_EXTI_MASK - -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_EXTI_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_syscfg.h b/arch/arm/src/stm32f0/chip/stm32f0_syscfg.h deleted file mode 100644 index 9d53a3d8930..00000000000 --- a/arch/arm/src/stm32f0/chip/stm32f0_syscfg.h +++ /dev/null @@ -1,391 +0,0 @@ -/**************************************************************************************************** - * arch/arm/src/stm32f0/chip/stm32f0_syscfg.h - * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Alan Carvalho de Assis - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_SYSCFG_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_SYSCFG_H - -/**************************************************************************************************** - * Included Files - ****************************************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************************/ - -/* Register Offsets *********************************************************************************/ - -#define STM32F0_SYSCFG_CFGR1_OFFSET 0x0000 /* SYSCFG configuration register 1 */ -#define STM32F0_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ -#define STM32F0_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32F0_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32F0_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32F0_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32F0_SYSCFG_CFGR2_OFFSET 0x0018 /* SYSCFG configuration register 2 */ -#define STM32F0_SYSCFG_ITLINE0_OFFSET 0x0080 /* SYSCFG interrupt line 0 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE1_OFFSET 0x0084 /* SYSCFG interrupt line 1 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE2_OFFSET 0x0088 /* SYSCFG interrupt line 2 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE3_OFFSET 0x008c /* SYSCFG interrupt line 3 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE4_OFFSET 0x0090 /* SYSCFG interrupt line 4 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE5_OFFSET 0x0094 /* SYSCFG interrupt line 5 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE6_OFFSET 0x0098 /* SYSCFG interrupt line 6 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE7_OFFSET 0x009c /* SYSCFG interrupt line 7 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE8_OFFSET 0x00a0 /* SYSCFG interrupt line 8 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE9_OFFSET 0x00a4 /* SYSCFG interrupt line 9 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE10_OFFSET 0x00a8 /* SYSCFG interrupt line 10 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE11_OFFSET 0x00ac /* SYSCFG interrupt line 11 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE12_OFFSET 0x00b0 /* SYSCFG interrupt line 12 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE13_OFFSET 0x00b4 /* SYSCFG interrupt line 13 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE14_OFFSET 0x00b8 /* SYSCFG interrupt line 14 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE15_OFFSET 0x00bc /* SYSCFG interrupt line 15 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE16_OFFSET 0x00c0 /* SYSCFG interrupt line 16 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE17_OFFSET 0x00c4 /* SYSCFG interrupt line 17 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE18_OFFSET 0x00c8 /* SYSCFG interrupt line 18 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE19_OFFSET 0x00cc /* SYSCFG interrupt line 19 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE20_OFFSET 0x00d0 /* SYSCFG interrupt line 20 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE21_OFFSET 0x00d4 /* SYSCFG interrupt line 21 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE22_OFFSET 0x00d8 /* SYSCFG interrupt line 22 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE23_OFFSET 0x00dc /* SYSCFG interrupt line 23 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE24_OFFSET 0x00e0 /* SYSCFG interrupt line 24 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE25_OFFSET 0x00e4 /* SYSCFG interrupt line 25 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE26_OFFSET 0x00e8 /* SYSCFG interrupt line 26 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE27_OFFSET 0x00ec /* SYSCFG interrupt line 27 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE28_OFFSET 0x00f0 /* SYSCFG interrupt line 28 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE29_OFFSET 0x00f4 /* SYSCFG interrupt line 29 status register (STM32F09x) */ -#define STM32F0_SYSCFG_ITLINE30_OFFSET 0x00f8 /* SYSCFG interrupt line 30 status register (STM32F09x) */ - -/* Register Addresses *******************************************************************************/ - -#define STM32F0_SYSCFG_CFGR1 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_CFGR1_OFFSET) - -#define STM32F0_SYSCFG_EXTICR(p) (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_EXTICR_OFFSET(p)) -#define STM32F0_SYSCFG_EXTICR1 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_EXTICR1_OFFSET) -#define STM32F0_SYSCFG_EXTICR2 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_EXTICR2_OFFSET) -#define STM32F0_SYSCFG_EXTICR3 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_EXTICR3_OFFSET) -#define STM32F0_SYSCFG_EXTICR4 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_EXTICR4_OFFSET) - -#define STM32F0_SYSCFG_CFGR2 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_CFGR2_OFFSET) - -#define STM32F0_SYSCFG_ITLINE0 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE0_OFFSET) -#define STM32F0_SYSCFG_ITLINE1 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE1_OFFSET) -#define STM32F0_SYSCFG_ITLINE2 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE2_OFFSET) -#define STM32F0_SYSCFG_ITLINE3 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE3_OFFSET) -#define STM32F0_SYSCFG_ITLINE4 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE4_OFFSET) -#define STM32F0_SYSCFG_ITLINE5 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE5_OFFSET) -#define STM32F0_SYSCFG_ITLINE6 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE6_OFFSET) -#define STM32F0_SYSCFG_ITLINE7 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE7_OFFSET) -#define STM32F0_SYSCFG_ITLINE8 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE8_OFFSET) -#define STM32F0_SYSCFG_ITLINE9 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE9_OFFSET) -#define STM32F0_SYSCFG_ITLINE10 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE10_OFFSET) -#define STM32F0_SYSCFG_ITLINE11 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE11_OFFSET) -#define STM32F0_SYSCFG_ITLINE12 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE12_OFFSET) -#define STM32F0_SYSCFG_ITLINE13 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE13_OFFSET) -#define STM32F0_SYSCFG_ITLINE14 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE14_OFFSET) -#define STM32F0_SYSCFG_ITLINE15 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE15_OFFSET) -#define STM32F0_SYSCFG_ITLINE16 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE16_OFFSET) -#define STM32F0_SYSCFG_ITLINE17 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE17_OFFSET) -#define STM32F0_SYSCFG_ITLINE18 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE18_OFFSET) -#define STM32F0_SYSCFG_ITLINE19 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE19_OFFSET) -#define STM32F0_SYSCFG_ITLINE20 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE20_OFFSET) -#define STM32F0_SYSCFG_ITLINE21 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE21_OFFSET) -#define STM32F0_SYSCFG_ITLINE22 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE22_OFFSET) -#define STM32F0_SYSCFG_ITLINE23 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE23_OFFSET) -#define STM32F0_SYSCFG_ITLINE24 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE24_OFFSET) -#define STM32F0_SYSCFG_ITLINE25 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE25_OFFSET) -#define STM32F0_SYSCFG_ITLINE26 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE26_OFFSET) -#define STM32F0_SYSCFG_ITLINE27 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE27_OFFSET) -#define STM32F0_SYSCFG_ITLINE28 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE28_OFFSET) -#define STM32F0_SYSCFG_ITLINE29 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE29_OFFSET) -#define STM32F0_SYSCFG_ITLINE30 (STM32F0_SYSCFG_BASE+STM32F0_SYSCFG_ITLINE30_OFFSET) - -/* Register Bitfield Definitions ********************************************************************/ - -/* SYSCFG memory remap register */ - -#define SYSCFG_CFGR1_MEMMODE_SHIFT (0) /* Bits 1:0 MEM_MODE: Memory mapping selection */ -#define SYSCFG_CFGR1_MEMMODE_MASK (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) -# define SYSCFG_CFGR1_MEMMODE_FLASH (0 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 00: Main Flash at 0x00000000 */ -# define SYSCFG_CFGR1_MEMMODE_SYSTEM (1 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 01: System Flash at 0x00000000 */ -# define SYSCFG_CFGR1_MEMMODE_SRAM (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 11: Embedded SRAM at 0x00000000 */ -#define SYSCFG_CFGR1_PA11_PA12_RMP (1 << 4) /* Bit 4: PA11 and PA12 remapping bit for small packages */ -#define SYSCFG_CFGR1_IRMOD_SHIFT (6) /* Bits 6-7: IR Modulation Envelope signal selection */ -#define SYSCFG_CFGR1_IRMOD_MASK (3 << SYSCFG_CFGR1_IRMOD_SHIFT) -# define SYSCFG_CFGR1_IRMOD_TIM16 (0 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 00: TIM16 selected */ -# define SYSCFG_CFGR1_IRMOD_USART1 (1 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 01: USART1 selected */ -# define SYSCFG_CFGR1_IRMOD_USART4 (2 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 10: USART1 selected */ -#define SYSCFG_CFGR1_ADC_DMARMP (1 << 8) /* Bit 8: ADC DMA remapping bit. Only STM32F03x/F04x/F05x/F07x */ -#define SYSCFG_CFGR1_USART1_TXDMARMP (1 << 9) /* Bit 9: USART1_TX_DMA request remapping bit. Only STM32F03x/F04x/F05x/F07x */ -#define SYSCFG_CFGR1_USART1_RXDMARMP (1 << 10) /* Bit 10: USART1_TX_DMA request remapping bit. Only STM32F03x/F04x/F05x/F07x */ -#define SYSCFG_CFGR1_TIM16_DMARMP (1 << 11) /* Bit 11: TIM16 DMA request remapping bit */ -#define SYSCFG_CFGR1_TIM17_DMARMP (1 << 12) /* Bit 12: TIM17 DMA request remapping bit */ -#define SYSCFG_CFGR1_TIM16_DMARMP2 (1 << 13) /* Bit 13: TIM16 alternate DMA request remapping bit */ -#define SYSCFG_CFGR1_TIM17_DMARMP2 (1 << 14) /* Bit 14: TIM17 alternate DMA request remapping bit */ -#define SYSCFG_CFGR1_I2C_PBXFMP_SHIFT (16) /* Bits 16-19: Fast Mode Plus (FM+) driving capability */ -#define SYSCFG_CFGR1_I2C_PBXFMP_MASK (15 << SYSCFG_CFGR1_I2C_PBXFMP_SHIFT) -#define SYSCFG_CFGR1_I2C1_FMP (1 << 20) /* Bit 20: I2C1 fast mode Plus driving capability */ -#define SYSCFG_CFGR1_I2C2_FMP (1 << 21) /* Bit 21: I2C2 fast mode Plus driving capability */ -#define SYSCFG_CFGR1_I2C_PAXFMP_SHIFT (22) /* Bits 22-23: Fast Mode Plus (FM+) driving capability */ -#define SYSCFG_CFGR1_I2C_PAXFMP_MASK (3 << SYSCFG_CFGR1_I2C_PAXFMP_SHIFT) -#define SYSCFG_CFGR1_SPI2_DMARMP (1 << 24) /* Bit 24: SPI2 DMA request remapping bit. */ -#define SYSCFG_CFGR1_USART2_DMARMP (1 << 25) /* Bit 25: USART2 DMA request remapping bit. */ -#define SYSCFG_CFGR1_USART3_DMARMP (1 << 26) /* Bit 26: USART3 DMA request remapping bit. */ -#define SYSCFG_CFGR1_I2C1_DMARMP (1 << 27) /* Bit 27: I2C1 DMA request remapping bit. */ -#define SYSCFG_CFGR1_TIM1_DMARMP (1 << 28) /* Bit 28: TIM1 DMA request remapping bit. */ -#define SYSCFG_CFGR1_TIM2_DMARMP (1 << 29) /* Bit 29: TIM2 DMA request remapping bit. */ -#define SYSCFG_CFGR1_TIM3_DMARMP (1 << 30) /* Bit 30: TIM3 DMA request remapping bit. */ - -/* SYSCFG external interrupt configuration register 1-4 */ - -#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */ -#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */ -#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */ -#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */ -#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */ -#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[x] pin */ - -#define SYSCFG_EXTICR_PORT_MASK (15) -#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2) -#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g))) - -#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 coinfiguration */ -#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT) -#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 coinfiguration */ -#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT) -#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 coinfiguration */ -#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT) -#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 coinfiguration */ -#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT) - -#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 coinfiguration */ -#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT) -#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 coinfiguration */ -#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT) -#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 coinfiguration */ -#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT) -#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 coinfiguration */ -#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT) - -#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 coinfiguration */ -#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT) -#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 coinfiguration */ -#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT) -#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 coinfiguration */ -#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT) -#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 coinfiguration */ -#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT) - -#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 coinfiguration */ -#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT) -#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 coinfiguration */ -#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT) -#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 coinfiguration */ -#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT) -#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 coinfiguration */ -#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT) - -/* SYSCFG configuration register 2 */ - -#define SYSCFG_CFGR2_LOCKUPLOCK (1 << 0) /* Bit 0: Cortex-M0 Hardfault output bit enable */ -#define SYSCFG_CFGR2_SRAM_PARITYLOCK (1 << 1) /* Bit 1: RAM parity lock */ -#define SYSCFG_CFGR2_PVDLOCK (1 << 2) /* Bit 2: PVD lock enable */ -#define SYSCFG_CFGR2_SRAM_PEF (1 << 8) /* Bit 8: SRAM parity error */ - -/* SYSCFG interrupt line 0 status register */ - -#define SYSCFG_ITLINE0_WWDG (1 << 0) /* Bit 0: Window Watchdog interrupt pending flag */ - -/* SYSCFG interrupt line 1 status register */ - -#define SYSCFG_ITLINE1_PVDOUT (1 << 0) /* Bit 0: PVD supply monitoring interrupt request pending (EXTI line 16) */ -#define SYSCFG_ITLINE1_VDDIO2 (1 << 0) /* Bit 1: VDDIO2 supply monitoring interrupt request pending (EXTI line 31) */ - -/* SYSCFG interrupt line 2 status register */ - -#define SYSCFG_ITLINE2_RTC_WAKEUP (1 << 0) /* Bit 0: RTC Wake Up interrupt request pending (EXTI line 20) */ -#define SYSCFG_ITLINE2_RTC_TSTAMP (1 << 1) /* Bit 1: RTC Tamper and TimeStamp interrupt request pending (EXTI line 19) */ -#define SYSCFG_ITLINE2_RTC_ALRA (1 << 2) /* Bit 2: RTC Alarm interrupt request pending (EXTI line 17) */ - -/* SYSCFG interrupt line 3 status register */ - -#define SYSCFG_ITLINE3_FLASH_ITF (1 << 0) /* Bit 0: Flash interface interrupt request pending */ - -/* SYSCFG interrupt line 4 status register */ - -#define SYSCFG_ITLINE4_RCC (1 << 0) /* Bit 0: Reset and clock control interrupt request pending */ -#define SYSCFG_ITLINE4_CRS (1 << 1) /* Bit 1: Clock recovery system interrupt request pending */ - -/* SYSCFG interrupt line 5 status register */ - -#define SYSCFG_ITLINE5_EXTI0 (1 << 0) /* Bit 0: EXTI line 0 interrupt request pending */ -#define SYSCFG_ITLINE5_EXTI1 (1 << 1) /* Bit 1: EXTI line 1 interrupt request pending */ - -/* SYSCFG interrupt line 6 status register */ - -#define SYSCFG_ITLINE6_EXTI2 (1 << 0) /* Bit 0: EXTI line 2 interrupt request pending */ -#define SYSCFG_ITLINE6_EXTI3 (1 << 1) /* Bit 1: EXTI line 3 interrupt request pending */ - -/* SYSCFG interrupt line 7 status register */ - -#define SYSCFG_ITLINE7_EXTI4 (1 << 0) /* Bit 0: EXTI line 4 interrupt request pending */ -#define SYSCFG_ITLINE7_EXTI5 (1 << 1) /* Bit 1: EXTI line 5 interrupt request pending */ -#define SYSCFG_ITLINE7_EXTI6 (1 << 2) /* Bit 2: EXTI line 6 interrupt request pending */ -#define SYSCFG_ITLINE7_EXTI7 (1 << 3) /* Bit 3: EXTI line 7 interrupt request pending */ -#define SYSCFG_ITLINE7_EXTI8 (1 << 4) /* Bit 4: EXTI line 8 interrupt request pending */ -#define SYSCFG_ITLINE7_EXTI9 (1 << 5) /* Bit 5: EXTI line 9 interrupt request pending */ -#define SYSCFG_ITLINE7_EXTI10 (1 << 6) /* Bit 6: EXTI line 10 interrupt request pending */ -#define SYSCFG_ITLINE7_EXTI11 (1 << 7) /* Bit 7: EXTI line 11 interrupt request pending */ -#define SYSCFG_ITLINE7_EXTI12 (1 << 8) /* Bit 8: EXTI line 12 interrupt request pending */ -#define SYSCFG_ITLINE7_EXTI13 (1 << 9) /* Bit 9: EXTI line 13 interrupt request pending */ -#define SYSCFG_ITLINE7_EXTI14 (1 << 10) /* Bit 10: EXTI line 14 interrupt request pending */ -#define SYSCFG_ITLINE7_EXTI15 (1 << 11) /* Bit 11: EXTI line 15 interrupt request pending */ - -/* SYSCFG interrupt line 8 status register */ - -#define SYSCFG_ITLINE8_TCS_MCE (1 << 0) /* Bit 0: Touch sensing controller max count error interrupt request pending */ -#define SYSCFG_ITLINE8_TCS_EOA (1 << 1) /* Bit 1: Touch sensing controller end of acquisition interrupt request pending */ - -/* SYSCFG interrupt line 9 status register */ - -#define SYSCFG_ITLINE9_DMA1_CH1 (1 << 0) /* Bit 0: DMA1 channel 1 interrupt request pending */ - -/* SYSCFG interrupt line 10 status register */ - -#define SYSCFG_ITLINE10_DMA1_CH2 (1 << 0) /* Bit 0: DMA1 channel 2 interrupt request pending */ -#define SYSCFG_ITLINE10_DMA1_CH3 (1 << 1) /* Bit 1: DMA1 channel 3 interrupt request pending */ -#define SYSCFG_ITLINE10_DMA2_CH1 (1 << 2) /* Bit 0: DMA2 channel 1 interrupt request pending */ -#define SYSCFG_ITLINE10_DMA2_CH2 (1 << 3) /* Bit 1: DMA2 channel 2 interrupt request pending */ - -/* SYSCFG interrupt line 11 status register */ - -#define SYSCFG_ITLINE11_DMA1_CH4 (1 << 0) /* Bit 0: DMA1 channel 4 interrupt request pending */ -#define SYSCFG_ITLINE11_DMA1_CH5 (1 << 1) /* Bit 1: DMA1 channel 5 interrupt request pending */ -#define SYSCFG_ITLINE11_DMA1_CH6 (1 << 2) /* Bit 2: DMA1 channel 6 interrupt request pending */ -#define SYSCFG_ITLINE11_DMA1_CH7 (1 << 3) /* Bit 3: DMA1 channel 7 interrupt request pending */ -#define SYSCFG_ITLINE11_DMA2_CH3 (1 << 4) /* Bit 4: DMA2 channel 3 interrupt request pending */ -#define SYSCFG_ITLINE11_DMA2_CH4 (1 << 5) /* Bit 5: DMA2 channel 4 interrupt request pending */ -#define SYSCFG_ITLINE11_DMA2_CH5 (1 << 6) /* Bit 6: DMA2 channel 5 interrupt request pending */ - -/* SYSCFG interrupt line 12 status register */ - -#define SYSCFG_ITLINE12_ADC (1 << 0) /* Bit 0: ADC interrupt request pending */ -#define SYSCFG_ITLINE12_COMP1 (1 << 1) /* Bit 1: Comparator 1 interrupt request pending */ -#define SYSCFG_ITLINE12_COMP2 (1 << 2) /* Bit 2: Comparator 2 interrupt request pending */ - -/* SYSCFG interrupt line 13 status register */ - -#define SYSCFG_ITLINE13_TIM1_CCU (1 << 0) /* Bit 0: TIM1 commutation interrupt request pending */ -#define SYSCFG_ITLINE13_TIM1_TRG (1 << 1) /* Bit 1: TIM1 triggerinterrupt request pending */ -#define SYSCFG_ITLINE13_TIM1_UPD (1 << 2) /* Bit 2: TIM1 update interrupt request pending */ -#define SYSCFG_ITLINE13_TIM1_BRK (1 << 3) /* Bit 3: TIM1 break interrupt request pending */ - -/* SYSCFG interrupt line 14 status register */ - -#define SYSCFG_ITLINE14_TIM1_CC (1 << 0) /* Bit 0: TIM1 capture compare interrupt request pending */ - -/* SYSCFG interrupt line 15 status register */ - -#define SYSCFG_ITLINE15_TIM2 (1 << 0) /* Bit 0: Timer 2 interrupt request pending */ - -/* SYSCFG interrupt line 16 status register */ - -#define SYSCFG_ITLINE16_TIM3 (1 << 0) /* Bit 0: Timer 3 interrupt request pending */ - -/* SYSCFG interrupt line 17 status register */ - -#define SYSCFG_ITLINE17_TIM6 (1 << 0) /* Bit 0: Timer 6 interrupt request pending */ -#define SYSCFG_ITLINE17_DAC (1 << 1) /* Bit 1: DAC underrun interrupt request pending */ - -/* SYSCFG interrupt line 18 status register */ - -#define SYSCFG_ITLINE18_TIM7 (1 << 0) /* Bit 0: Timer 7 interrupt request pending */ - -/* SYSCFG interrupt line 19 status register */ - -#define SYSCFG_ITLINE19_TIM14 (1 << 0) /* Bit 0: Timer 14 interrupt request pending */ - -/* SYSCFG interrupt line 20 status register */ - -#define SYSCFG_ITLINE20_TIM15 (1 << 0) /* Bit 0: Timer 15 interrupt request pending */ - -/* SYSCFG interrupt line 21 status register */ - -#define SYSCFG_ITLINE21_TIM16 (1 << 0) /* Bit 0: Timer 16 interrupt request pending */ - -/* SYSCFG interrupt line 22 status register */ - -#define SYSCFG_ITLINE22_TIM17 (1 << 0) /* Bit 0: Timer 17 interrupt request pending */ - -/* SYSCFG interrupt line 23 status register */ - -#define SYSCFG_ITLINE23_I2C1 (1 << 0) /* Bit 0: I2C1 interrupt request pending, combined with EXTI line 23 */ - -/* SYSCFG interrupt line 24 status register */ - -#define SYSCFG_ITLINE24_I2C2 (1 << 0) /* Bit 0: I2C2 interrupt request pending */ - -/* SYSCFG interrupt line 25 status register */ - -#define SYSCFG_ITLINE25_SPI1 (1 << 0) /* Bit 0: SPI1 interrupt request pending */ - -/* SYSCFG interrupt line 26 status register */ - -#define SYSCFG_ITLINE26_SPI2 (1 << 0) /* Bit 0: SPI2 interrupt request pending */ - -/* SYSCFG interrupt line 27 status register */ - -#define SYSCFG_ITLINE27_USART1 (1 << 0) /* Bit 0: USART1 interrupt request pending */ - -/* SYSCFG interrupt line 28 status register */ - -#define SYSCFG_ITLINE28_USART2 (1 << 0) /* Bit 0: USART2 interrupt request pending */ - -/* SYSCFG interrupt line 29 status register */ - -#define SYSCFG_ITLINE29_USART3 (1 << 0) /* Bit 0: USART3 interrupt request pending */ -#define SYSCFG_ITLINE29_USART4 (1 << 1) /* Bit 1: USART4 interrupt request pending */ -#define SYSCFG_ITLINE29_USART5 (1 << 2) /* Bit 2: USART5 interrupt request pending */ -#define SYSCFG_ITLINE29_USART6 (1 << 3) /* Bit 3: USART6 interrupt request pending */ -#define SYSCFG_ITLINE29_USART7 (1 << 4) /* Bit 4: USART7 interrupt request pending */ -#define SYSCFG_ITLINE29_USART8 (1 << 5) /* Bit 5: USART8 interrupt request pending */ - -/* SYSCFG interrupt line 30 status register */ - -#define SYSCFG_ITLINE30_CEC (1 << 0) /* Bit 0: CEC interrupt request pending, combined with EXTI line 27 */ -#define SYSCFG_ITLINE30_CAN (1 << 1) /* Bit 1: CAN interrupt request pending */ - -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_SYSCFG_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_wdt.h b/arch/arm/src/stm32f0/chip/stm32f0_wdt.h deleted file mode 100644 index 8c26ae717c0..00000000000 --- a/arch/arm/src/stm32f0/chip/stm32f0_wdt.h +++ /dev/null @@ -1,142 +0,0 @@ -/************************************************************************************ - * arch/arm/src/stm32f0/chip/stm32f0_wdg.h - * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Alan Carvalho de Assis - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_WDG_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_WDG_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register Offsets *****************************************************************/ - -#define STM32F0_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */ -#define STM32F0_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */ -#define STM32F0_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */ -#define STM32F0_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */ -#define STM32F0_IWDG_WINR_OFFSET 0x0010 /* Window register (32-bit) */ - -#define STM32F0_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */ -#define STM32F0_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */ -#define STM32F0_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */ - -/* Register Addresses ***************************************************************/ - -#define STM32F0_IWDG_KR (STM32F0_IWDG_BASE+STM32F0_IWDG_KR_OFFSET) -#define STM32F0_IWDG_PR (STM32F0_IWDG_BASE+STM32F0_IWDG_PR_OFFSET) -#define STM32F0_IWDG_RLR (STM32F0_IWDG_BASE+STM32F0_IWDG_RLR_OFFSET) -#define STM32F0_IWDG_SR (STM32F0_IWDG_BASE+STM32F0_IWDG_SR_OFFSET) -#define STM32F0_IWDG_WINR (STM32F0_IWDG_BASE+STM32F0_IWDG_WINR_OFFSET) - -#define STM32F0_WWDG_CR (STM32F0_WWDG_BASE+STM32F0_WWDG_CR_OFFSET) -#define STM32F0_WWDG_CFR (STM32F0_WWDG_BASE+STM32F0_WWDG_CFR_OFFSET) -#define STM32F0_WWDG_SR (STM32F0_WWDG_BASE+STM32F0_WWDG_SR_OFFSET) - -/* Register Bitfield Definitions ****************************************************/ - -/* Key register (32-bit) */ - -#define IWDG_KR_KEY_SHIFT (0) /* Bits 15-0: Key value (write only, read 0000h) */ -#define IWDG_KR_KEY_MASK (0xffff << IWDG_KR_KEY_SHIFT) - -#define IWDG_KR_KEY_ENABLE (0x5555) /* Enable register access */ -#define IWDG_KR_KEY_DISABLE (0x0000) /* Disable register access */ -#define IWDG_KR_KEY_RELOAD (0xaaaa) /* Reload the counter */ -#define IWDG_KR_KEY_START (0xcccc) /* Start the watchdog */ - -/* Prescaler register (32-bit) */ - -#define IWDG_PR_SHIFT (0) /* Bits 2-0: Prescaler divider */ -#define IWDG_PR_MASK (7 << IWDG_PR_SHIFT) -# define IWDG_PR_DIV4 (0 << IWDG_PR_SHIFT) /* 000: divider /4 */ -# define IWDG_PR_DIV8 (1 << IWDG_PR_SHIFT) /* 001: divider /8 */ -# define IWDG_PR_DIV16 (2 << IWDG_PR_SHIFT) /* 010: divider /16 */ -# define IWDG_PR_DIV32 (3 << IWDG_PR_SHIFT) /* 011: divider /32 */ -# define IWDG_PR_DIV64 (4 << IWDG_PR_SHIFT) /* 100: divider /64 */ -# define IWDG_PR_DIV128 (5 << IWDG_PR_SHIFT) /* 101: divider /128 */ -# define IWDG_PR_DIV256 (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */ - -/* Reload register (32-bit) */ - -#define IWDG_RLR_RL_SHIFT (0) /* Bits11:0 RL[11:0]: Watchdog counter reload value */ -#define IWDG_RLR_RL_MASK (0x0fff << IWDG_RLR_RL_SHIFT) - -#define IWDG_RLR_MAX (0xfff) - -/* Status register (32-bit) */ - -#define IWDG_SR_PVU (1 << 0) /* Bit 0: Watchdog prescaler value update */ -#define IWDG_SR_RVU (1 << 1) /* Bit 1: Watchdog counter reload value update */ -#define IWDG_SR_WVU (1 << 2) /* Bit 2: Watchdog counter window value update */ - -/* Window register (32-bit) */ - -#define IWDG_WINR_SHIFT (0) -#define IWDG_WINR_MASK (0x0fff << IWDG_WINR_SHIFT) - -/* Control Register (32-bit) */ - -#define WWDG_CR_T_SHIFT (0) /* Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) */ -#define WWDG_CR_T_MASK (0x7f << WWDG_CR_T_SHIFT) -# define WWDG_CR_T_MAX (0x3f << WWDG_CR_T_SHIFT) -# define WWDG_CR_T_RESET (0x40 << WWDG_CR_T_SHIFT) -#define WWDG_CR_WDGA (1 << 7) /* Bit 7: Activation bit */ - -/* Configuration register (32-bit) */ - -#define WWDG_CFR_W_SHIFT (0) /* Bits 6:0 W[6:0] 7-bit window value */ -#define WWDG_CFR_W_MASK (0x7f << WWDG_CFR_W_SHIFT) -#define WWDG_CFR_WDGTB_SHIFT (7) /* Bits 8:7 [1:0]: Timer Base */ -#define WWDG_CFR_WDGTB_MASK (3 << WWDG_CFR_WDGTB_SHIFT) -# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */ -# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */ -# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */ -# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */ -#define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */ - -/* Status register (32-bit) */ - -#define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */ - -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_WDG_H */ diff --git a/arch/arm/src/stm32f0l0/Kconfig b/arch/arm/src/stm32f0l0/Kconfig new file mode 100644 index 00000000000..e33e7f78ded --- /dev/null +++ b/arch/arm/src/stm32f0l0/Kconfig @@ -0,0 +1,1522 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "STM32F0/L0 Configuration Options" + +choice + prompt "ST STM32F0/L0 Chip Selection" + default ARCH_CHIP_STM32F051R8 + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F030C6 + bool "STM32F030C6" + select STM32F0L0_STM32F03X + select STM32F0L0_VALUELINE + +config ARCH_CHIP_STM32F030C8 + bool "STM32F030C8" + select STM32F0L0_STM32F03X + select STM32F0L0_VALUELINE + +config ARCH_CHIP_STM32F030CC + bool "STM32F030CC" + select STM32F0L0_STM32F03X + select STM32F0L0_VALUELINE + +config ARCH_CHIP_STM32F030F4 + bool "STM32F030F4" + select STM32F0L0_STM32F03X + select STM32F0L0_VALUELINE + +config ARCH_CHIP_STM32F030K6 + bool "STM32F030K6" + select STM32F0L0_STM32F03X + select STM32F0L0_VALUELINE + +config ARCH_CHIP_STM32F030R8 + bool "STM32F030R8" + select STM32F0L0_STM32F03X + select STM32F0L0_VALUELINE + +config ARCH_CHIP_STM32F030RC + bool "STM32F030RC" + select STM32F0L0_STM32F03X + select STM32F0L0_VALUELINE + +config ARCH_CHIP_STM32F031C4 + bool "STM32F031C4" + select STM32F0L0_STM32F03X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F031C6 + bool "STM32F031C6" + select STM32F0L0_STM32F03X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F031E6 + bool "STM32F031E6" + select STM32F0L0_STM32F03X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F031F4 + bool "STM32F031F4" + select STM32F0L0_STM32F03X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F031F6 + bool "STM32F031F6" + select STM32F0L0_STM32F03X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F031G4 + bool "STM32F031G4" + select STM32F0L0_STM32F03X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F031G6 + bool "STM32F031G6" + select STM32F0L0_STM32F03X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F031K4 + bool "STM32F031K4" + select STM32F0L0_STM32F03X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F031K6 + bool "STM32F031K6" + select STM32F0L0_STM32F03X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F038C6 + bool "STM32F038C6" + select STM32F0L0_STM32F03X + select STM32F0L0_LOWVOLTLINE + +config ARCH_CHIP_STM32F038E6 + bool "STM32F038E6" + select STM32F0L0_STM32F03X + select STM32F0L0_LOWVOLTLINE + +config ARCH_CHIP_STM32F038F6 + bool "STM32F038F6" + select STM32F0L0_STM32F03X + select STM32F0L0_LOWVOLTLINE + +config ARCH_CHIP_STM32F038G6 + bool "STM32F038G6" + select STM32F0L0_STM32F03X + select STM32F0L0_LOWVOLTLINE + +config ARCH_CHIP_STM32F038K6 + bool "STM32F038K6" + select STM32F0L0_STM32F03X + select STM32F0L0_LOWVOLTLINE + +config ARCH_CHIP_STM32F042C4 + bool "STM32F042C4" + select STM32F0L0_STM32F04X + select STM32F0L0_USBLINE + +config ARCH_CHIP_STM32F042C6 + bool "STM32F042C6" + select STM32F0L0_STM32F04X + select STM32F0L0_USBLINE + +config ARCH_CHIP_STM32F042F4 + bool "STM32F042F4" + select STM32F0L0_STM32F04X + select STM32F0L0_USBLINE + +config ARCH_CHIP_STM32F042F6 + bool "STM32F042F6" + select STM32F0L0_STM32F04X + select STM32F0L0_USBLINE + +config ARCH_CHIP_STM32F042G4 + bool "STM32F042G4" + select STM32F0L0_STM32F04X + select STM32F0L0_USBLINE + +config ARCH_CHIP_STM32F042G6 + bool "STM32F042G6" + select STM32F0L0_STM32F04X + select STM32F0L0_USBLINE + +config ARCH_CHIP_STM32F042K4 + bool "STM32F042K4" + select STM32F0L0_STM32F04X + select STM32F0L0_USBLINE + +config ARCH_CHIP_STM32F042K6 + bool "STM32F042K6" + select STM32F0L0_STM32F04X + select STM32F0L0_USBLINE + +config ARCH_CHIP_STM32F042T6 + bool "STM32F042T6" + select STM32F0L0_STM32F04X + select STM32F0L0_USBLINE + +config ARCH_CHIP_STM32F048C6 + bool "STM32F048C6" + select STM32F0L0_STM32F04X + select STM32F0L0_LOWVOLTLINE + +config ARCH_CHIP_STM32F048G6 + bool "STM32F048G6" + select STM32F0L0_STM32F04X + select STM32F0L0_LOWVOLTLINE + +config ARCH_CHIP_STM32F048T6 + bool "STM32F048T6" + select STM32F0L0_STM32F04X + select STM32F0L0_LOWVOLTLINE + +config ARCH_CHIP_STM32F051C4 + bool "STM32F051C4" + select STM32F0L0_STM32F05X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F051C6 + bool "STM32F051C6" + select STM32F0L0_STM32F05X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F051C8 + bool "STM32F051C8" + select STM32F0L0_STM32F05X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F051K4 + bool "STM32F051K4" + select STM32F0L0_STM32F05X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F051K6 + bool "STM32F051K6" + select STM32F0L0_STM32F05X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F051K8 + bool "STM32F051K8" + select STM32F0L0_STM32F05X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F051R4 + bool "STM32F051R4" + select STM32F0L0_STM32F05X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F051R6 + bool "STM32F051R6" + select STM32F0L0_STM32F05X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F051R8 + bool "STM32F051R8" + select STM32F0L0_STM32F05X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F051T8 + bool "STM32F051T8" + select STM32F0L0_STM32F05X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F058C8 + bool "STM32F058C8" + select STM32F0L0_STM32F05X + select STM32F0L0_LOWVOLTLINE + +config ARCH_CHIP_STM32F058R8 + bool "STM32F058R8" + select STM32F0L0_STM32F05X + select STM32F0L0_LOWVOLTLINE + +config ARCH_CHIP_STM32F058T8 + bool "STM32F058T8" + select STM32F0L0_STM32F05X + select STM32F0L0_LOWVOLTLINE + +config ARCH_CHIP_STM32F070C6 + bool "STM32F070C6" + select STM32F0L0_STM32F07X + select STM32F0L0_VALUELINE + +config ARCH_CHIP_STM32F070CB + bool "STM32F070CB" + select STM32F0L0_STM32F07X + select STM32F0L0_VALUELINE + +config ARCH_CHIP_STM32F070F6 + bool "STM32F070F6" + select STM32F0L0_STM32F07X + select STM32F0L0_VALUELINE + +config ARCH_CHIP_STM32F070RB + bool "STM32F070RB" + select STM32F0L0_STM32F07X + select STM32F0L0_VALUELINE + +config ARCH_CHIP_STM32F071C8 + bool "STM32F071C8" + select STM32F0L0_STM32F07X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F071CB + bool "STM32F071CB" + select STM32F0L0_STM32F07X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F071RB + bool "STM32F071RB" + select STM32F0L0_STM32F07X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F071V8 + bool "STM32F071V8" + select STM32F0L0_STM32F07X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F071VB + bool "STM32F071VB" + select STM32F0L0_STM32F07X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F072C8 + bool "STM32F072C8" + select STM32F0L0_STM32F07X + select STM32F0L0_USBLINE + +config ARCH_CHIP_STM32F072CB + bool "STM32F072CB" + select STM32F0L0_STM32F07X + select STM32F0L0_USBLINE + +config ARCH_CHIP_STM32F072R8 + bool "STM32F072R8" + select STM32F0L0_STM32F07X + select STM32F0L0_USBLINE + +config ARCH_CHIP_STM32F072RB + bool "STM32F072RB" + select STM32F0L0_STM32F07X + select STM32F0L0_USBLINE + +config ARCH_CHIP_STM32F072V8 + bool "STM32F072V8" + select STM32F0L0_STM32F07X + select STM32F0L0_USBLINE + +config ARCH_CHIP_STM32F072VB + bool "STM32F072VB" + select STM32F0L0_STM32F07X + select STM32F0L0_USBLINE + +config ARCH_CHIP_STM32F078CB + bool "STM32F078CB" + select STM32F0L0_STM32F07X + select STM32F0L0_LOWVOLTLINE + +config ARCH_CHIP_STM32F078RB + bool "STM32F078RB" + select STM32F0L0_STM32F07X + select STM32F0L0_LOWVOLTLINE + +config ARCH_CHIP_STM32F078VB + bool "STM32F078VB" + select STM32F0L0_STM32F07X + select STM32F0L0_LOWVOLTLINE + +config ARCH_CHIP_STM32F091CB + bool "STM32F091CB" + select STM32F0L0_STM32F09X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F091CC + bool "STM32F091CC" + select STM32F0L0_STM32F09X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F091RB + bool "STM32F091RB" + select STM32F0L0_STM32F09X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F091RC + bool "STM32F091RC" + select STM32F0L0_STM32F09X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F091VB + bool "STM32F091VB" + select STM32F0L0_STM32F09X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F091VC + bool "STM32F091VC" + select STM32F0L0_STM32F09X + select STM32F0L0_ACCESSLINE + +config ARCH_CHIP_STM32F098CC + bool "STM32F098CC" + select STM32F0L0_STM32F09X + select STM32F0L0_LOWVOLTLINE + +config ARCH_CHIP_STM32F098RC + bool "STM32F098RC" + select STM32F0L0_STM32F09X + select STM32F0L0_LOWVOLTLINE + +config ARCH_CHIP_STM32F098VC + bool "STM32F098VC" + select STM32F0L0_STM32F09X + select STM32F0L0_LOWVOLTLINE + +endchoice # ST STM32F0/L0 Chip Selection + +config ARCH_FAMILY_STM32F0XX + bool + +choice + prompt "Override Flash Size Designator" + default STM32F0L0_FLASH_CONFIG_DEFAULT + depends on ARCH_CHIP_STM32 + ---help--- + STM32F series parts numbering (sans the package type) ends with a number or letter + that designates the FLASH size. + + Designator Size in KiB + 4 16 + 6 32 + 8 64 + B 128 + C 256 + D 384 + E 512 + F 768 + G 1024 + I 2048 + + This configuration option defaults to using the configuration based on that designator + or the default smaller size if there is no last character designator is present in the + STM32 Chip Selection. + + Examples: + If the STM32F407VE is chosen, the Flash configuration would be 'E', if a variant of + the part with a 2048 KiB Flash is released in the future one could simply select + the 'I' designator here. + + If an STM32F42xxx or Series parts is chosen the default Flash configuration will be 'G' + and can be set herein to 'I' to choose the larger FLASH part. + +config STM32F0L0_FLASH_CONFIG_DEFAULT + bool "Default" + +config STM32F0L0_FLASH_CONFIG_4 + bool "4 16KiB" + +config STM32F0L0_FLASH_CONFIG_6 + bool "6 32KiB" + +config STM32F0L0_FLASH_CONFIG_8 + bool "8 64KiB" + +config STM32F0L0_FLASH_CONFIG_B + bool "B 128KiB" + +config STM32F0L0_FLASH_CONFIG_C + bool "C 256KiB" + +config STM32F0L0_FLASH_CONFIG_D + bool "D 384KiB" + +config STM32F0L0_FLASH_CONFIG_E + bool "E 512KiB" + +config STM32F0L0_FLASH_CONFIG_F + bool "F 768KiB" + +config STM32F0L0_FLASH_CONFIG_G + bool "G 1024KiB" + +config STM32F0L0_FLASH_CONFIG_I + bool "I 2048KiB" + +endchoice + +config STM32F0L0_STM32F0 + bool + default n + +config STM32F0L0_STM32L0 + bool + default n + +config STM32F0L0_STM32F03X + bool + default n + select STM32F0L0_STM32F0 + +config STM32F0L0_STM32F04X + bool + default n + select STM32F0L0_STM32F0 + +config STM32F0L0_STM32F05X + bool + default n + select STM32F0L0_STM32F0 + +config STM32F0L0_STM32F07X + bool + default n + select STM32F0L0_STM32F0 + +config STM32F0L0_STM32F09X + bool + default n + select STM32F0L0_STM32F0 + select STM32F0L0_HAVE_HSI48 + +config STM32F0L0_VALUELINE + bool + default n + select STM32F0L0_HAVE_USART3 + select STM32F0L0_HAVE_USART4 + select STM32F0L0_HAVE_USART5 + select STM32F0L0_HAVE_TIM1 + select STM32F0L0_HAVE_TIM2 + select STM32F0L0_HAVE_TIM3 + select STM32F0L0_HAVE_TIM6 + select STM32F0L0_HAVE_TIM7 + select STM32F0L0_HAVE_TIM14 + select STM32F0L0_HAVE_TIM15 + select STM32F0L0_HAVE_TIM16 + select STM32F0L0_HAVE_TIM17 + select STM32F0L0_HAVE_SPI2 if STM32F0L0_HIGHDENSITY + select STM32F0L0_HAVE_SPI3 if STM32F0L0_HIGHDENSITY + +config STM32F0L0_ACCESSLINE + bool + default n + select STM32F0L0_HAVE_USART3 + select STM32F0L0_HAVE_USART4 + select STM32F0L0_HAVE_USART5 + select STM32F0L0_HAVE_TIM1 + select STM32F0L0_HAVE_TIM2 + select STM32F0L0_HAVE_TIM3 + select STM32F0L0_HAVE_TIM6 + select STM32F0L0_HAVE_TIM7 + select STM32F0L0_HAVE_TIM14 + select STM32F0L0_HAVE_TIM15 + select STM32F0L0_HAVE_TIM16 + select STM32F0L0_HAVE_TIM17 + select STM32F0L0_HAVE_ADC2 + select STM32F0L0_HAVE_CAN1 + select STM32F0L0_HAVE_SPI2 + select STM32F0L0_HAVE_SPI3 + +config STM32F0L0_LOWVOLTLINE + bool + default n + select STM32F0L0_HAVE_USART3 + select STM32F0L0_HAVE_USART4 + select STM32F0L0_HAVE_USART5 + select STM32F0L0_HAVE_TIM1 + select STM32F0L0_HAVE_TIM2 + select STM32F0L0_HAVE_TIM3 + select STM32F0L0_HAVE_TIM6 + select STM32F0L0_HAVE_TIM7 + select STM32F0L0_HAVE_TIM14 + select STM32F0L0_HAVE_TIM15 + select STM32F0L0_HAVE_TIM16 + select STM32F0L0_HAVE_TIM17 + select STM32F0L0_HAVE_ADC2 + select STM32F0L0_HAVE_CAN1 + select STM32F0L0_HAVE_SPI2 + select STM32F0L0_HAVE_SPI3 + +config STM32F0L0_USBLINE + bool + default n + select STM32F0L0_HAVE_HSI48 + select STM32F0L0_HAVE_USART3 + select STM32F0L0_HAVE_USART4 + select STM32F0L0_HAVE_TIM1 + select STM32F0L0_HAVE_TIM2 + select STM32F0L0_HAVE_TIM3 + select STM32F0L0_HAVE_TIM6 + select STM32F0L0_HAVE_TIM7 + select STM32F0L0_HAVE_TIM14 + select STM32F0L0_HAVE_TIM15 + select STM32F0L0_HAVE_TIM16 + select STM32F0L0_HAVE_TIM17 + select STM32F0L0_HAVE_ADC2 + select STM32F0L0_HAVE_CAN1 + select STM32F0L0_HAVE_SPI2 + select STM32F0L0_HAVE_SPI3 + select STM32F0L0_HAVE_USBDEV + +config STM32F0L0_DFU + bool "DFU bootloader" + default n + depends on !STM32F0L0_VALUELINE + ---help--- + Configure and position code for use with the STMicro DFU bootloader. Do + not select this option if you will load code using JTAG/SWM. + + +choice + prompt "SysTick clock source" + default STM32F0L0_SYSTICK_CORECLK + +config STM32F0L0_SYSTICK_CORECLK + bool "Cortex-M0 core clock" + +config STM32F0L0_SYSTICK_CORECLK_DIV16 + bool "Cortex-M0 core clock divided by 16" + +endchoice + + +menu "STM32 Peripheral Support" + +# These "hidden" settings determine is a peripheral option is available for the +# selection MCU + +config STM32F0L0_HAVE_CCM + bool + default n + +config STM32F0L0_HAVE_HSI48 + bool + default n + +config STM32F0L0_HAVE_USBDEV + bool + default n + +config STM32F0L0_HAVE_FSMC + bool + default n + +config STM32F0L0_HAVE_USART3 + bool + default n + +config STM32F0L0_HAVE_USART4 + bool + default n + +config STM32F0L0_HAVE_USART5 + bool + default n + +config STM32F0L0_HAVE_USART6 + bool + default n + +config STM32F0L0_HAVE_USART7 + bool + default n + +config STM32F0L0_HAVE_USART8 + bool + default n + +config STM32F0L0_HAVE_TIM1 + bool + default n + +config STM32F0L0_HAVE_TIM2 + bool + default n + +config STM32F0L0_HAVE_TIM3 + bool + default n + +config STM32F0L0_HAVE_TIM6 + bool + default n + +config STM32F0L0_HAVE_TIM7 + bool + default n + +config STM32F0L0_HAVE_TIM14 + bool + default n + +config STM32F0L0_HAVE_TIM15 + bool + default n + +config STM32F0L0_HAVE_TIM16 + bool + default n + +config STM32F0L0_HAVE_TIM17 + bool + default n + +config STM32F0L0_HAVE_TSC + bool + default n + +config STM32F0L0_HAVE_ADC2 + bool + default n + +config STM32F0L0_HAVE_ADC3 + bool + default n + +config STM32F0L0_HAVE_ADC4 + bool + default n + +config STM32F0L0_HAVE_ADC1_DMA + bool + default n + +config STM32F0L0_HAVE_ADC2_DMA + bool + default n + +config STM32F0L0_HAVE_ADC3_DMA + bool + default n + +config STM32F0L0_HAVE_ADC4_DMA + bool + default n + +config STM32F0L0_HAVE_SDADC1 + bool + default n + +config STM32F0L0_HAVE_SDADC2 + bool + default n + +config STM32F0L0_HAVE_SDADC3 + bool + default n + +config STM32F0L0_HAVE_SDADC1_DMA + bool + default n + +config STM32F0L0_HAVE_SDADC2_DMA + bool + default n + +config STM32F0L0_HAVE_SDADC3_DMA + bool + default n + +config STM32F0L0_HAVE_CAN1 + bool + default n + +config STM32F0L0_HAVE_COMP1 + bool + default n + +config STM32F0L0_HAVE_COMP2 + bool + default n + +config STM32F0L0_HAVE_COMP3 + bool + default n + +config STM32F0L0_HAVE_COMP4 + bool + default n + +config STM32F0L0_HAVE_COMP5 + bool + default n + +config STM32F0L0_HAVE_COMP6 + bool + default n + +config STM32F0L0_HAVE_COMP7 + bool + default n + +config STM32F0L0_HAVE_DAC1 + bool + default n + +config STM32F0L0_HAVE_DAC2 + bool + default n + +config STM32F0L0_HAVE_RNG + bool + default n + +config STM32F0L0_HAVE_I2C2 + bool + default n + +config STM32F0L0_HAVE_I2C3 + bool + default n + +config STM32F0L0_HAVE_SPI2 + bool + default n + +config STM32F0L0_HAVE_SPI3 + bool + default n + +config STM32F0L0_HAVE_SPI4 + bool + default n + +config STM32F0L0_HAVE_SPI5 + bool + default n + +config STM32F0L0_HAVE_SPI6 + bool + default n + +config STM32F0L0_HAVE_SAIPLL + bool + default n + +config STM32F0L0_HAVE_I2SPLL + bool + default n + +config STM32F0L0_HAVE_OPAMP1 + bool + default n + +config STM32F0L0_HAVE_OPAMP2 + bool + default n + +config STM32F0L0_HAVE_OPAMP3 + bool + default n + +config STM32F0L0_HAVE_OPAMP4 + bool + default n + +# These are the peripheral selections proper + +config STM32F0L0_ADC1 + bool "ADC1" + default n + select STM32F0L0_ADC + +config STM32F0L0_ADC2 + bool "ADC2" + default n + select STM32F0L0_ADC + depends on STM32F0L0_HAVE_ADC2 + +config STM32F0L0_ADC3 + bool "ADC3" + default n + select STM32F0L0_ADC + depends on STM32F0L0_HAVE_ADC3 + +config STM32F0L0_ADC4 + bool "ADC4" + default n + select STM32F0L0_ADC + depends on STM32F0L0_HAVE_ADC4 + +config STM32F0L0_SDADC1 + bool "SDADC1" + default n + select STM32F0L0_SDADC + depends on STM32F0L0_HAVE_SDADC1 + +config STM32F0L0_SDADC2 + bool "SDADC2" + default n + select STM32F0L0_SDADC + depends on STM32F0L0_HAVE_SDADC2 + +config STM32F0L0_SDADC3 + bool "SDADC3" + default n + select STM32F0L0_SDADC + depends on STM32F0L0_HAVE_SDADC3 + +config STM32F0L0_COMP + bool "COMP" + default n + +config STM32F0L0_COMP1 + bool "COMP1" + default n + depends on STM32F0L0_HAVE_COMP1 + +config STM32F0L0_COMP2 + bool "COMP2" + default n + depends on STM32F0L0_HAVE_COMP2 + +config STM32F0L0_COMP3 + bool "COMP3" + default n + depends on STM32F0L0_HAVE_COMP3 + +config STM32F0L0_COMP4 + bool "COMP4" + default n + depends on STM32F0L0_HAVE_COMP4 + +config STM32F0L0_COMP5 + bool "COMP5" + default n + depends on STM32F0L0_HAVE_COMP5 + +config STM32F0L0_COMP6 + bool "COMP6" + default n + depends on STM32F0L0_HAVE_COMP6 + +config STM32F0L0_COMP7 + bool "COMP7" + default n + depends on STM32F0L0_HAVE_COMP6 + +config STM32F0L0_BKP + bool "BKP" + default n + +config STM32F0L0_BKPSRAM + bool "Enable BKP RAM Domain" + default n + +config STM32F0L0_CAN1 + bool "CAN1" + default n + select CAN + select STM32F0L0_CAN + depends on STM32F0L0_HAVE_CAN1 + +config STM32F0L0_CEC + bool "CEC" + default n + depends on STM32F0L0_VALUELINE + +config STM32F0L0_CRC + bool "CRC" + default n + +config STM32F0L0_CRYP + bool "CRYP" + default n + depends on STM32F0L0_STM32F207 || STM32F0L0_STM32F40XX + +config STM32F0L0_DMA1 + bool "DMA1" + default n + select ARCH_DMA + +config STM32F0L0_DMA2 + bool "DMA2" + default n + select ARCH_DMA + depends on !STM32F0L0_VALUELINE || (STM32F0L0_VALUELINE && STM32F0L0_HIGHDENSITY) + +config STM32F0L0_DAC1 + bool "DAC1" + default n + depends on STM32F0L0_HAVE_DAC1 + select STM32F0L0_DAC + +config STM32F0L0_DAC2 + bool "DAC2" + default n + depends on STM32F0L0_HAVE_DAC2 + select STM32F0L0_DAC + +config STM32F0L0_FSMC + bool "FSMC" + default n + depends on STM32F0L0_HAVE_FSMC + +config STM32F0L0_HASH + bool "HASH" + default n + depends on STM32F0L0_STM32F207 || STM32F0L0_STM32F40XX + +config STM32F0L0_I2C1 + bool "I2C1" + default n + select STM32F0L0_I2C + +config STM32F0L0_I2C2 + bool "I2C2" + default n + depends on STM32F0L0_HAVE_I2C2 + select STM32F0L0_I2C + +config STM32F0L0_I2C3 + bool "I2C3" + default n + depends on STM32F0L0_HAVE_I2C3 + select STM32F0L0_I2C + +config STM32F0L0_PWR + bool "PWR" + default n + +config STM32F0L0_RNG + bool "RNG" + default n + depends on STM32F0L0_HAVE_RNG + select ARCH_HAVE_RNG + +config STM32F0L0_SDIO + bool "SDIO" + default n + depends on !STM32F0L0_CONNECTIVITYLINE && !STM32F0L0_VALUELINE + select ARCH_HAVE_SDIO + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE + select ARCH_HAVE_SDIO_PREFLIGHT + +config STM32F0L0_SPI1 + bool "SPI1" + default n + select SPI + select STM32F0L0_SPI + +config STM32F0L0_SPI2 + bool "SPI2" + default n + depends on STM32F0L0_HAVE_SPI2 + select SPI + select STM32F0L0_SPI + +config STM32F0L0_SPI3 + bool "SPI3" + default n + depends on STM32F0L0_HAVE_SPI3 + select SPI + select STM32F0L0_SPI + +config STM32F0L0_SPI4 + bool "SPI4" + default n + depends on STM32F0L0_HAVE_SPI4 + select SPI + select STM32F0L0_SPI + +config STM32F0L0_SPI5 + bool "SPI5" + default n + depends on STM32F0L0_HAVE_SPI5 + select SPI + select STM32F0L0_SPI + +config STM32F0L0_SPI6 + bool "SPI6" + default n + depends on STM32F0L0_HAVE_SPI6 + select SPI + select STM32F0L0_SPI + +config STM32F0L0_SYSCFG + bool "SYSCFG" + default y + +config STM32F0L0_TIM1 + bool "TIM1" + default n + depends on STM32F0L0_HAVE_TIM1 + +config STM32F0L0_TIM2 + bool "TIM2" + default n + +config STM32F0L0_TIM3 + bool "TIM3" + default n + depends on STM32F0L0_HAVE_TIM3 + +config STM32F0L0_TIM6 + bool "TIM6" + default n + depends on STM32F0L0_HAVE_TIM6 + +config STM32F0L0_TIM7 + bool "TIM7" + default n + depends on STM32F0L0_HAVE_TIM7 + +config STM32F0L0_TIM14 + bool "TIM14" + default n + depends on STM32F0L0_HAVE_TIM14 + +config STM32F0L0_TIM15 + bool "TIM15" + default n + depends on STM32F0L0_HAVE_TIM15 + +config STM32F0L0_TIM16 + bool "TIM16" + default n + depends on STM32F0L0_HAVE_TIM16 + +config STM32F0L0_TIM17 + bool "TIM17" + default n + depends on STM32F0L0_HAVE_TIM17 + +config STM32F0L0_TSC + bool "TSC" + default n + depends on STM32F0L0_HAVE_TSC + +config STM32F0L0_USART1 + bool "USART1" + default n + select STM32F0L0_USART + +config STM32F0L0_USART2 + bool "USART2" + default n + select STM32F0L0_USART + +config STM32F0L0_USART3 + bool "USART3" + default n + depends on STM32F0L0_HAVE_USART3 + select STM32F0L0_USART + +config STM32F0L0_USART4 + bool "USART4" + default n + depends on STM32F0L0_HAVE_USART4 + select STM32F0L0_USART + +config STM32F0L0_USART5 + bool "USART5" + default n + depends on STM32F0L0_HAVE_USART5 + select STM32F0L0_USART + +config STM32F0L0_USART6 + bool "USART6" + default n + depends on STM32F0L0_HAVE_USART6 + select STM32F0L0_USART + +config STM32F0L0_USART7 + bool "USART7" + default n + depends on STM32F0L0_HAVE_USART7 + select STM32F0L0_USART + +config STM32F0L0_USART8 + bool "USART8" + default n + depends on STM32F0L0_HAVE_USART8 + select STM32F0L0_USART + +config STM32F0L0_USB + bool "USB Device" + default n + depends on STM32F0L0_HAVE_USBDEV + select USBDEV + +config STM32F0L0_IWDG + bool "IWDG" + default n + select WATCHDOG + +config STM32F0L0_WWDG + bool "WWDG" + default n + select WATCHDOG + +endmenu + +config STM32F0L0_ADC + bool + +config STM32F0L0_SDADC + bool + +config STM32F0L0_DAC + bool + +config STM32F0L0_SPI + bool + +config STM32F0L0_I2C + bool + +config STM32F0L0_CAN + bool + +config STM32F0L0_USART + bool + +config STM32F0L0_SERIALDRIVER + bool + +config STM32F0L0_1WIREDRIVER + bool + +menu "U[S]ART Configuration" + depends on STM32F0L0_USART + +comment "U[S]ART Device Configuration" + +choice + prompt "USART1 Driver Configuration" + default STM32F0L0_USART1_SERIALDRIVER + depends on STM32F0L0_USART1 + +config STM32F0L0_USART1_SERIALDRIVER + bool "Standard serial driver" + select USART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32F0L0_SERIALDRIVER + +config STM32F0L0_USART1_1WIREDRIVER + bool "1-Wire driver" + select STM32F0L0_1WIREDRIVER + +endchoice # USART1 Driver Configuration + +if STM32F0L0_USART1_SERIALDRIVER + +config USART1_RS485 + bool "RS-485 on USART1" + default n + ---help--- + Enable RS-485 interface on USART1. Your board config will have to + provide GPIO_USART1_RS485_DIR pin definition. + +config USART1_RS485_DIR_POLARITY + int "USART1 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on USART1_RS485 + ---help--- + Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # STM32F0L0_USART1_SERIALDRIVER + +choice + prompt "USART2 Driver Configuration" + default STM32F0L0_USART2_SERIALDRIVER + depends on STM32F0L0_USART2 + +config STM32F0L0_USART2_SERIALDRIVER + bool "Standard serial driver" + select USART2_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32F0L0_SERIALDRIVER + +config STM32F0L0_USART2_1WIREDRIVER + bool "1-Wire driver" + select STM32F0L0_1WIREDRIVER + +endchoice # USART2 Driver Configuration + +if STM32F0L0_USART2_SERIALDRIVER + +config USART2_RS485 + bool "RS-485 on USART2" + default n + ---help--- + Enable RS-485 interface on USART2. Your board config will have to + provide GPIO_USART2_RS485_DIR pin definition. + +config USART2_RS485_DIR_POLARITY + int "USART2 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on USART2_RS485 + ---help--- + Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # STM32F0L0_USART2_SERIALDRIVER + +choice + prompt "USART3 Driver Configuration" + default STM32F0L0_USART3_SERIALDRIVER + depends on STM32F0L0_USART3 + +config STM32F0L0_USART3_SERIALDRIVER + bool "Standard serial driver" + select USART3_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32F0L0_SERIALDRIVER + +config STM32F0L0_USART3_1WIREDRIVER + bool "1-Wire driver" + select STM32F0L0_1WIREDRIVER + +endchoice # USART3 Driver Configuration + +if STM32F0L0_USART3_SERIALDRIVER + +config USART3_RS485 + bool "RS-485 on USART3" + default n + ---help--- + Enable RS-485 interface on USART3. Your board config will have to + provide GPIO_USART3_RS485_DIR pin definition. + +config USART3_RS485_DIR_POLARITY + int "USART3 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on USART3_RS485 + ---help--- + Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # STM32F0L0_USART3_SERIALDRIVER + + +choice + prompt "USART4 Driver Configuration" + default STM32F0L0_USART4_SERIALDRIVER + depends on STM32F0L0_USART4 + +config STM32F0L0_USART4_SERIALDRIVER + bool "Standard serial driver" + select USART4_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32F0L0_SERIALDRIVER + +config STM32F0L0_USART4_1WIREDRIVER + bool "1-Wire driver" + select STM32F0L0_1WIREDRIVER + +endchoice # USART4 Driver Configuration + +if STM32F0L0_USART4_SERIALDRIVER + +config USART4_RS485 + bool "RS-485 on USART4" + default n + ---help--- + Enable RS-485 interface on USART4. Your board config will have to + provide GPIO_USART4_RS485_DIR pin definition. + +config USART4_RS485_DIR_POLARITY + int "USART4 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on USART4_RS485 + ---help--- + Polarity of DIR pin for RS-485 on USART4. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # STM32F0L0_USART4_SERIALDRIVER + +choice + prompt "USART5 Driver Configuration" + default STM32F0L0_USART5_SERIALDRIVER + depends on STM32F0L0_USART5 + +config STM32F0L0_USART5_SERIALDRIVER + bool "Standard serial driver" + select USART5_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32F0L0_SERIALDRIVER + +config STM32F0L0_USART5_1WIREDRIVER + bool "1-Wire driver" + select STM32F0L0_1WIREDRIVER + +endchoice # USART5 Driver Configuration + +if STM32F0L0_USART5_SERIALDRIVER + +config USART5_RS485 + bool "RS-485 on USART5" + default n + ---help--- + Enable RS-485 interface on USART5. Your board config will have to + provide GPIO_USART5_RS485_DIR pin definition. + +config USART5_RS485_DIR_POLARITY + int "USART5 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on USART5_RS485 + ---help--- + Polarity of DIR pin for RS-485 on USART5. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # STM32F0L0_USART5_SERIALDRIVER + + +choice + prompt "USART6 Driver Configuration" + default STM32F0L0_USART6_SERIALDRIVER + depends on STM32F0L0_USART6 + +config STM32F0L0_USART6_SERIALDRIVER + bool "Standard serial driver" + select USART6_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32F0L0_SERIALDRIVER + +config STM32F0L0_USART6_1WIREDRIVER + bool "1-Wire driver" + select STM32F0L0_1WIREDRIVER + +endchoice # USART6 Driver Configuration + +if STM32F0L0_USART6_SERIALDRIVER + +config USART6_RS485 + bool "RS-485 on USART6" + default n + ---help--- + Enable RS-485 interface on USART6. Your board config will have to + provide GPIO_USART6_RS485_DIR pin definition. + +config USART6_RS485_DIR_POLARITY + int "USART6 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on USART6_RS485 + ---help--- + Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # STM32F0L0_USART6_SERIALDRIVER + +choice + prompt "USART7 Driver Configuration" + default STM32F0L0_USART7_SERIALDRIVER + depends on STM32F0L0_USART7 + +config STM32F0L0_USART7_SERIALDRIVER + bool "Standard serial driver" + select USART7_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32F0L0_SERIALDRIVER + +config STM32F0L0_USART7_1WIREDRIVER + bool "1-Wire driver" + select STM32F0L0_1WIREDRIVER + +endchoice # USART7 Driver Configuration + +if STM32F0L0_USART7_SERIALDRIVER + +config USART7_RS485 + bool "RS-485 on USART7" + default n + ---help--- + Enable RS-485 interface on USART7. Your board config will have to + provide GPIO_USART7_RS485_DIR pin definition. + +config USART7_RS485_DIR_POLARITY + int "USART7 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on USART7_RS485 + ---help--- + Polarity of DIR pin for RS-485 on USART7. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # STM32F0L0_USART7_SERIALDRIVER + +choice + prompt "USART8 Driver Configuration" + default STM32F0L0_USART8_SERIALDRIVER + depends on STM32F0L0_USART8 + +config STM32F0L0_USART8_SERIALDRIVER + bool "Standard serial driver" + select USART8_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32F0L0_SERIALDRIVER + +config STM32F0L0_USART8_1WIREDRIVER + bool "1-Wire driver" + select STM32F0L0_1WIREDRIVER + +endchoice # USART8 Driver Configuration + +if STM32F0L0_USART8_SERIALDRIVER + +config USART8_RS485 + bool "RS-485 on USART8" + default n + ---help--- + Enable RS-485 interface on USART8. Your board config will have to + provide GPIO_USART8_RS485_DIR pin definition. + +config USART8_RS485_DIR_POLARITY + int "USART8 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on USART8_RS485 + ---help--- + Polarity of DIR pin for RS-485 on USART8. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # STM32F0L0_USART8_SERIALDRIVER + +menu "Serial Driver Configuration" + depends on STM32F0L0_SERIALDRIVER + +config STM32F0L0_SERIAL_DISABLE_REORDERING + bool "Disable reordering of ttySx devices." + default n + ---help--- + NuttX per default reorders the serial ports (/dev/ttySx) so that the + console is always on /dev/ttyS0. If more than one UART is in use this + can, however, have the side-effect that all port mappings + (hardware USART1 -> /dev/ttyS0) change if the console is moved to another + UART. This is in particular relevant if a project uses the USB console + in some configs and a serial console in other configs, but does not + want the side effect of having all serial port names change when just + the console is moved from serial to USB. + +config STM32F0L0_USART_SINGLEWIRE + bool "Single Wire Support" + default n + depends on STM32F0L0_USART + ---help--- + Enable single wire UART support. The option enables support for the + TIOCSSINGLEWIRE ioctl in the STM32F0 serial driver. + +endmenu # Serial Driver Configuration + +if PM + +config STM32F0L0_PM_SERIAL_ACTIVITY + int "PM serial activity" + default 10 + ---help--- + PM activity reported to power management logic on every serial + interrupt. + +endif + +endmenu diff --git a/arch/arm/src/stm32f0/Make.defs b/arch/arm/src/stm32f0l0/Make.defs similarity index 81% rename from arch/arm/src/stm32f0/Make.defs rename to arch/arm/src/stm32f0l0/Make.defs index 53333b7bdc1..275aec68be1 100644 --- a/arch/arm/src/stm32f0/Make.defs +++ b/arch/arm/src/stm32f0l0/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# arch/arm/src/stm32f0/Make.defs +# arch/arm/src/stm32f0l0/Make.defs # # Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. # Author: Gregory Nutt @@ -65,51 +65,51 @@ CMN_CSRCS += up_dumpnvic.c endif CHIP_ASRCS = -CHIP_CSRCS = stm32f0_clockconfig.c stm32f0_gpio.c stm32f0_irq.c -CHIP_CSRCS += stm32f0_lowputc.c stm32f0_serial.c stm32f0_start.c +CHIP_CSRCS = stm32_clockconfig.c stm32_gpio.c stm32_irq.c +CHIP_CSRCS += stm32_lowputc.c stm32_serial.c stm32_start.c # Configuration-dependent STM32F0xx files ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CHIP_CSRCS += stm32f0_idle.c +CHIP_CSRCS += stm32_idle.c endif ifneq ($(CONFIG_SCHED_TICKLESS),y) -CHIP_CSRCS += stm32f0_timerisr.c +CHIP_CSRCS += stm32_timerisr.c endif ifeq ($(CONFIG_BUILD_PROTECTED),y) -CHIP_CSRCS += stm32f0_userspace.c +CHIP_CSRCS += stm32_userspace.c endif -ifeq ($(CONFIG_STM32F0_GPIOIRQ),y) -CHIP_CSRCS += stm32f0_gpioint.c +ifeq ($(CONFIG_STM32F0L0_GPIOIRQ),y) +CHIP_CSRCS += stm32_gpioint.c endif ifeq ($(CONFIG_ARCH_IRQPRIO),y) -CHIP_CSRCS += stm32f0_irqprio.c +CHIP_CSRCS += stm32_irqprio.c endif -ifeq ($(CONFIG_STM32F0_HAVE_HSI48),y) -CHIP_CSRCS += stm32f0_hsi48.c +ifeq ($(CONFIG_STM32F0L0_HAVE_HSI48),y) +CHIP_CSRCS += stm32_hsi48.c endif -ifeq ($(CONFIG_STM32F0_USB),y) -CHIP_CSRCS += stm32f0_usbdev.c +ifeq ($(CONFIG_STM32F0L0_USB),y) +CHIP_CSRCS += stm32_usbdev.c endif -ifeq ($(CONFIG_STM32F0_I2C),y) -CHIP_CSRCS += stm32f0_i2c.c +ifeq ($(CONFIG_STM32F0L0_I2C),y) +CHIP_CSRCS += stm32_i2c.c endif -ifeq ($(CONFIG_STM32F0_SPI0),y) -CHIP_CSRCS += stm32f0_spi.c +ifeq ($(CONFIG_STM32F0L0_SPI0),y) +CHIP_CSRCS += stm32_spi.c else -ifeq ($(CONFIG_STM32F0_SPI1),y) -CHIP_CSRCS += stm32f0_spi.c +ifeq ($(CONFIG_STM32F0L0_SPI1),y) +CHIP_CSRCS += stm32_spi.c endif endif ifeq ($(CONFIG_PWM),y) -CHIP_CSRCS += stm32f0_pwm.c +CHIP_CSRCS += stm32_pwm.c endif diff --git a/arch/arm/src/stm32f0/chip.h b/arch/arm/src/stm32f0l0/chip.h similarity index 90% rename from arch/arm/src/stm32f0/chip.h rename to arch/arm/src/stm32f0l0/chip.h index 0300f9f7dab..e7375f71c2f 100644 --- a/arch/arm/src/stm32f0/chip.h +++ b/arch/arm/src/stm32f0l0/chip.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/chip.h + * arch/arm/src/stm32f0l0/chip.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_H /************************************************************************************ * Included Files @@ -46,7 +46,7 @@ /* Include the chip capabilities file */ -#include +#include #define ARMV6M_PERIPHERAL_INTERRUPTS 32 @@ -54,6 +54,6 @@ * this file for the proper setup. */ -#include "chip/stm32f0_memorymap.h" +#include "hardware/stm32_memorymap.h" -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_adc.h b/arch/arm/src/stm32f0l0/hardware/stm32_adc.h new file mode 100644 index 00000000000..75dd3ddcd4a --- /dev/null +++ b/arch/arm/src/stm32f0l0/hardware/stm32_adc.h @@ -0,0 +1,195 @@ +/******************************************************************************** + * arch/arm/src/stm32f0l0/hardware/stm32_adc.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_ADC_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_ADC_H + +/******************************************************************************** + * Included Files + ********************************************************************************/ + +#include + +#include "chip.h" + +/******************************************************************************** + * Pre-processor Definitions + ********************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +#define STM32_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */ +#define STM32_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */ +#define STM32_ADC_CR_OFFSET 0x0008 /* ADC control register */ +#define STM32_ADC_CFGR1_OFFSET 0x000c /* ADC configuration register 1 */ +#define STM32_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */ +#define STM32_ADC_SMPR_OFFSET 0x0014 /* ADC sample time register */ +#define STM32_ADC_TR_OFFSET 0x0020 /* ADC watchdog threshold register */ +#define STM32_ADC_CHSELR_OFFSET 0x0028 /* ADC channel selection register */ +#define STM32_ADC_DR_OFFSET 0x0040 /* ADC regular data register */ +#define STM32_ADC_CCR_OFFSET 0x0308 /* ADC common configuration register */ + +/* Register Addresses *******************************************************************************/ + +#define STM32_ADC_ISR (STM32_ADC_BASE + STM32_ADC_ISR_OFFSET) +#define STM32_ADC_IER (STM32_ADC_BASE + STM32_ADC_IER_OFFSET) +#define STM32_ADC_CR (STM32_ADC_BASE + STM32_ADC_CR_OFFSET) +#define STM32_ADC_CFGR1 (STM32_ADC_BASE + STM32_ADC_CFGR1_OFFSET) +#define STM32_ADC_CFGR2 (STM32_ADC_BASE + STM32_ADC_CFGR2_OFFSET) +#define STM32_ADC_SMPR (STM32_ADC_BASE + STM32_ADC_SMPR_OFFSET) +#define STM32_ADC_TR (STM32_ADC_BASE + STM32_ADC_TR_OFFSET) +#define STM32_ADC_CHSELR (STM32_ADC_BASE + STM32_ADC_CHSELR_OFFSET) +#define STM32_ADC_DR (STM32_ADC_BASE + STM32_ADC_DR_OFFSET) +#define STM32_ADC_CCR (STM32_ADC_BASE + STM32_ADC_CCR_OFFSET) + +/* Register Bitfield Definitions ************************************************/ + +/* ADC interrupt and status register (ISR) and ADC interrupt enable register (IER) */ + +#define ADC_INT_ARDY (1 << 0) /* Bit 0: ADC ready */ +#define ADC_INT_EOSMP (1 << 1) /* Bit 1: End of sampling flag */ +#define ADC_INT_EOC (1 << 2) /* Bit 2: End of conversion */ +#define ADC_INT_EOS (1 << 3) /* Bit 3: End of regular sequence flag */ +#define ADC_INT_OVR (1 << 4) /* Bit 4: Overrun */ +#define ADC_INT_AWD (1 << 7) /* Bit 7: Analog watchdog flag */ + +/* ADC control register */ + +#define ADC_CR_ADEN (1 << 0) /* Bit 0: ADC enable control */ +#define ADC_CR_ADDIS (1 << 1) /* Bit 1: ADC disable command */ +#define ADC_CR_ADSTART (1 << 2) /* Bit 2: ADC start of regular conversion */ +#define ADC_CR_ADSTP (1 << 4) /* Bit 4: ADC stop of regular conversion command */ +#define ADC_CR_ADCAL (1 << 31) /* Bit 31: ADC calibration */ + +/* ADC configuration register 1 */ + +#define ADC_CFGR1_DMAEN (1 << 0) /* Bit 0: Direct memory access enable */ +#define ADC_CFGR1_DMACFG (1 << 1) /* Bit 1: Direct memory access configuration */ +#define ADC_CFGR1_SCANDIR (1 << 2) /* Bit 2: Scan sequence direction */ +#define ADC_CFGR1_RES_SHIFT (3) /* Bits 3-4: Data resolution */ +#define ADC_CFGR1_RES_MASK (3 << ADC_CFGR1_RES_SHIFT) +# define ADC_CFGR1_RES_12BIT (0 << ADC_CFGR1_RES_SHIFT) /* 15 ADCCLK clyes */ +# define ADC_CFGR1_RES_10BIT (1 << ADC_CFGR1_RES_SHIFT) /* 13 ADCCLK clyes */ +# define ADC_CFGR1_RES_8BIT (2 << ADC_CFGR1_RES_SHIFT) /* 11 ADCCLK clyes */ +# define ADC_CFGR1_RES_6BIT (3 << ADC_CFGR1_RES_SHIFT) /* 9 ADCCLK clyes */ +#define ADC_CFGR1_ALIGN (1 << 5) /* Bit 5: Data Alignment */ +#define ADC_CFGR1_EXTSEL_SHIFT (6) /* Bits 6-8: External trigger selection */ +#define ADC_CFGR1_EXTSEL_MASK (7 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_TRG0 (0 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_TRG1 (1 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_TRG2 (2 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_TRG3 (3 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_TRG4 (4 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_TRG5 (5 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_TRG6 (6 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_TRG7 (7 << ADC_CFGR1_EXTSEL_SHIFT) +#define ADC_CFGR1_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */ +#define ADC_CFGR1_EXTEN_MASK (3 << ADC_CFGR1_EXTEN_SHIFT) +# define ADC_CFGR1_EXTEN_NONE (0 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection disabled */ +# define ADC_CFGR1_EXTEN_RISING (1 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the rising edge */ +# define ADC_CFGR1_EXTEN_FALLING (2 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the falling edge */ +# define ADC_CFGR1_EXTEN_BOTH (3 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on both edges */ +#define ADC_CFGR1_OVRMOD (1 << 12) /* Bit 12: Overrun Mode */ +#define ADC_CFGR1_CONT (1 << 13) /* Bit 13: Continuous mode for regular conversions */ +#define ADC_CFGR1_WAIT (1 << 14) /* Bit 14: Wait convertion mode */ +#define ADC_CFGR1_AUTOFF (1 << 15) /* Bit 15: Auto-off mode */ +#define ADC_CFGR1_DISCEN (1 << 16) /* Bit 16: Discontinuous mode on regular channels */ +#define ADC_CFGR1_AWDSGL (1 << 22) /* Bit 22: Enable watchdog on single/all channels */ +#define ADC_CFGR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable */ +#define ADC_CFGR1_AWDCH_SHIFT (26) /* Bits 26-30: Analog watchdog 1 channel select bits */ +#define ADC_CFGR1_AWDCH_MASK (31 << ADC_CFGR1_AWDCH_SHIFT) +# define ADC_CFGR1_AWDCH_DISABLED (0 << ADC_CFGR1_AWDCH_SHIFT) + +/* ADC configuration register 2 */ + +#define ADC_CFGR2_CKMODE_SHIFT (30) /* Bits 30-31: ADC clock mode */ +#define ADC_CFGR2_CKMODE_MASK (3 << ADC_CFGR2_CKMODE_SHIFT) +# define ADC_CFGR2_CKMODE_ADCCLK (0 << ADC_CFGR2_CKMODE_SHIFT) /* 00: ADCCLK (Asynchronous) generated at product level */ +# define ADC_CFGR2_CKMODE_PCLKd2 (1 << ADC_CFGR2_CKMODE_SHIFT) /* 01: PCLK/2 (Synchronous clock mode) */ +# define ADC_CFGR2_CKMODE_PCLKd4 (2 << ADC_CFGR2_CKMODE_SHIFT) /* 10: PCLK/4 (Synchronous clock mode) */ + +/* ADC sample time register */ + +#define ADC_SMPR_SMP_SHIFT (0) /* Bits 0-2: Sampling time selection */ +#define ADC_SMPR_SMP_MASK (7 << ADC_SMPR_SMP_SHIFT) +#define ADC_SMPR_SMP_1p5 (0 << ADC_SMPR_SMP_SHIFT) /* 000: 1.5 cycles */ +#define ADC_SMPR_SMP_7p5 (1 << ADC_SMPR_SMP_SHIFT) /* 001: 7.5 cycles */ +#define ADC_SMPR_SMP_13p5 (2 << ADC_SMPR_SMP_SHIFT) /* 010: 13.5 cycles */ +#define ADC_SMPR_SMP_28p5 (3 << ADC_SMPR_SMP_SHIFT) /* 011: 28.5 cycles */ +#define ADC_SMPR_SMP_41p5 (4 << ADC_SMPR_SMP_SHIFT) /* 100: 41.5 cycles */ +#define ADC_SMPR_SMP_55p5 (5 << ADC_SMPR_SMP_SHIFT) /* 101: 55.5 cycles */ +#define ADC_SMPR_SMP_71p5 (6 << ADC_SMPR_SMP_SHIFT) /* 110: 71.5 cycles */ +#define ADC_SMPR_SMP_239p5 (7 << ADC_SMPR_SMP_SHIFT) /* 111: 239.5 cycles */ + +/* ADC watchdog threshold register */ + +#define ADC_TR_LT_SHIFT (0) /* Bits 0-11: Analog watchdog lower threshold */ +#define ADC_TR_LT_MASK (0x0fff << ADC_TR_LT_SHIFT) +#define ADC_TR_HT_SHIFT (16) /* Bits 16-27: Analog watchdog higher threshold */ +#define ADC_TR_HT_MASK (0x0fff << ADC_TR_HT_SHIFT) + +/* ADC channel selection register */ + +#define ADC_CHSELR_CHSEL0 (1 << 0) /* Select channel 0 */ +#define ADC_CHSELR_CHSEL1 (1 << 1) /* Select channel 1 */ +#define ADC_CHSELR_CHSEL2 (1 << 2) /* Select channel 2 */ +#define ADC_CHSELR_CHSEL3 (1 << 3) /* Select channel 3 */ +#define ADC_CHSELR_CHSEL4 (1 << 4) /* Select channel 4 */ +#define ADC_CHSELR_CHSEL5 (1 << 5) /* Select channel 5 */ +#define ADC_CHSELR_CHSEL6 (1 << 6) /* Select channel 6 */ +#define ADC_CHSELR_CHSEL7 (1 << 7) /* Select channel 7 */ +#define ADC_CHSELR_CHSEL8 (1 << 8) /* Select channel 8 */ +#define ADC_CHSELR_CHSEL9 (1 << 9) /* Select channel 9 */ +#define ADC_CHSELR_CHSEL10 (1 << 10) /* Select channel 10 */ +#define ADC_CHSELR_CHSEL11 (1 << 11) /* Select channel 11 */ +#define ADC_CHSELR_CHSEL12 (1 << 12) /* Select channel 12 */ +#define ADC_CHSELR_CHSEL13 (1 << 13) /* Select channel 13 */ +#define ADC_CHSELR_CHSEL14 (1 << 14) /* Select channel 14 */ +#define ADC_CHSELR_CHSEL15 (1 << 15) /* Select channel 15 */ +#define ADC_CHSELR_CHSEL16 (1 << 16) /* Select channel 16 */ +#define ADC_CHSELR_CHSEL17 (1 << 17) /* Select channel 17 */ +#define ADC_CHSELR_CHSEL18 (1 << 18) /* Select channel 18 */ + +#define ADC_DR_RDATA_SHIFT (0) +#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) + +/* Common configuration register */ + +#define ADC_CCR_VREFEN (1 << 22) /* Bit 22: VREFINT enable */ +#define ADC_CCR_TSEN (1 << 23) /* Bit 23: Temperature sensor enable */ +#define ADC_CCR_VBATEN (1 << 24) /* Bit 22: VBAT enable */ + +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_ADC_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_can.h b/arch/arm/src/stm32f0l0/hardware/stm32_can.h similarity index 60% rename from arch/arm/src/stm32f0/chip/stm32f0_can.h rename to arch/arm/src/stm32f0l0/hardware/stm32_can.h index 05174ef1de3..a3dc2ba6e04 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_can.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32_can.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/chip/stm32f0_can.h + * arch/arm/src/stm32f0l0/hardware/stm32_can.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_CAN_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_CAN_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CAN_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CAN_H /************************************************************************************ * Included Files @@ -68,63 +68,63 @@ /* CAN control and status registers */ -#define STM32F0_CAN_MCR_OFFSET 0x0000 /* CAN master control register */ -#define STM32F0_CAN_MSR_OFFSET 0x0004 /* CAN master status register */ -#define STM32F0_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */ +#define STM32_CAN_MCR_OFFSET 0x0000 /* CAN master control register */ +#define STM32_CAN_MSR_OFFSET 0x0004 /* CAN master status register */ +#define STM32_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */ -#define STM32F0_CAN_RFR_OFFSET(m) (0x000c+((m)<<2)) -#define STM32F0_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */ -#define STM32F0_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */ +#define STM32_CAN_RFR_OFFSET(m) (0x000c + ((m) << 2)) +#define STM32_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */ +#define STM32_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */ -#define STM32F0_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */ -#define STM32F0_CAN_ESR_OFFSET 0x0018 /* CAN error status register */ -#define STM32F0_CAN_BTR_OFFSET 0x001c /* CAN bit timing register */ +#define STM32_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */ +#define STM32_CAN_ESR_OFFSET 0x0018 /* CAN error status register */ +#define STM32_CAN_BTR_OFFSET 0x001c /* CAN bit timing register */ /* CAN mailbox registers (3 TX and 2 RX) */ -#define STM32F0_CAN_TIR_OFFSET(m) (0x0180+((m)<<4)) -#define STM32F0_CAN_TI0R_OFFSET 0x0180 /* TX mailbox identifier register 0 */ -#define STM32F0_CAN_TI1R_OFFSET 0x0190 /* TX mailbox identifier register 1 */ -#define STM32F0_CAN_TI2R_OFFSET 0x01a0 /* TX mailbox identifier register 2 */ +#define STM32_CAN_TIR_OFFSET(m) (0x0180 + ((m) << 4)) +#define STM32_CAN_TI0R_OFFSET 0x0180 /* TX mailbox identifier register 0 */ +#define STM32_CAN_TI1R_OFFSET 0x0190 /* TX mailbox identifier register 1 */ +#define STM32_CAN_TI2R_OFFSET 0x01a0 /* TX mailbox identifier register 2 */ -#define STM32F0_CAN_TDTR_OFFSET(m) (0x0184+((m)<<4)) -#define STM32F0_CAN_TDT0R_OFFSET 0x0184 /* Mailbox data length control and time stamp register 0 */ -#define STM32F0_CAN_TDT1R_OFFSET 0x0194 /* Mailbox data length control and time stamp register 1 */ -#define STM32F0_CAN_TDT2R_OFFSET 0x01a4 /* Mailbox data length control and time stamp register 2 */ +#define STM32_CAN_TDTR_OFFSET(m) (0x0184 + ((m) << 4)) +#define STM32_CAN_TDT0R_OFFSET 0x0184 /* Mailbox data length control and time stamp register 0 */ +#define STM32_CAN_TDT1R_OFFSET 0x0194 /* Mailbox data length control and time stamp register 1 */ +#define STM32_CAN_TDT2R_OFFSET 0x01a4 /* Mailbox data length control and time stamp register 2 */ -#define STM32F0_CAN_TDLR_OFFSET(m) (0x0188+((m)<<4)) -#define STM32F0_CAN_TDL0R_OFFSET 0x0188 /* Mailbox data low register 0 */ -#define STM32F0_CAN_TDL1R_OFFSET 0x0198 /* Mailbox data low register 1 */ -#define STM32F0_CAN_TDL2R_OFFSET 0x01a8 /* Mailbox data low register 2 */ +#define STM32_CAN_TDLR_OFFSET(m) (0x0188 + ((m) << 4)) +#define STM32_CAN_TDL0R_OFFSET 0x0188 /* Mailbox data low register 0 */ +#define STM32_CAN_TDL1R_OFFSET 0x0198 /* Mailbox data low register 1 */ +#define STM32_CAN_TDL2R_OFFSET 0x01a8 /* Mailbox data low register 2 */ -#define STM32F0_CAN_TDHR_OFFSET(m) (0x018c+((m)<<4)) -#define STM32F0_CAN_TDH0R_OFFSET 0x018c /* Mailbox data high register 0 */ -#define STM32F0_CAN_TDH1R_OFFSET 0x019c /* Mailbox data high register 1 */ -#define STM32F0_CAN_TDH2R_OFFSET 0x01ac /* Mailbox data high register 2 */ +#define STM32_CAN_TDHR_OFFSET(m) (0x018c + ((m) << 4)) +#define STM32_CAN_TDH0R_OFFSET 0x018c /* Mailbox data high register 0 */ +#define STM32_CAN_TDH1R_OFFSET 0x019c /* Mailbox data high register 1 */ +#define STM32_CAN_TDH2R_OFFSET 0x01ac /* Mailbox data high register 2 */ -#define STM32F0_CAN_RIR_OFFSET(m) (0x01b0+((m)<<4)) -#define STM32F0_CAN_RI0R_OFFSET 0x01b0 /* Rx FIFO mailbox identifier register 0 */ -#define STM32F0_CAN_RI1R_OFFSET 0x01c0 /* Rx FIFO mailbox identifier register 1 */ +#define STM32_CAN_RIR_OFFSET(m) (0x01b0 + ((m) << 4)) +#define STM32_CAN_RI0R_OFFSET 0x01b0 /* Rx FIFO mailbox identifier register 0 */ +#define STM32_CAN_RI1R_OFFSET 0x01c0 /* Rx FIFO mailbox identifier register 1 */ -#define STM32F0_CAN_RDTR_OFFSET(m) (0x01b4+((m)<<4)) -#define STM32F0_CAN_RDT0R_OFFSET 0x01b4 /* Rx FIFO mailbox data length control and time stamp register 0 */ -#define STM32F0_CAN_RDT1R_OFFSET 0x01c4 /* Rx FIFO mailbox data length control and time stamp register 1 */ +#define STM32_CAN_RDTR_OFFSET(m) (0x01b4 + ((m) << 4)) +#define STM32_CAN_RDT0R_OFFSET 0x01b4 /* Rx FIFO mailbox data length control and time stamp register 0 */ +#define STM32_CAN_RDT1R_OFFSET 0x01c4 /* Rx FIFO mailbox data length control and time stamp register 1 */ -#define STM32F0_CAN_RDLR_OFFSET(m) (0x01b8+((m)<<4)) -#define STM32F0_CAN_RDL0R_OFFSET 0x01b8 /* Receive FIFO mailbox data low register 0 */ -#define STM32F0_CAN_RDL1R_OFFSET 0x01c8 /* Receive FIFO mailbox data low register 1 */ +#define STM32_CAN_RDLR_OFFSET(m) (0x01b8 + ((m) << 4)) +#define STM32_CAN_RDL0R_OFFSET 0x01b8 /* Receive FIFO mailbox data low register 0 */ +#define STM32_CAN_RDL1R_OFFSET 0x01c8 /* Receive FIFO mailbox data low register 1 */ -#define STM32F0_CAN_RDHR_OFFSET(m) (0x01bc+((m)<<4)) -#define STM32F0_CAN_RDH0R_OFFSET 0x01bc /* Receive FIFO mailbox data high register 0 */ -#define STM32F0_CAN_RDH1R_OFFSET 0x01cc /* Receive FIFO mailbox data high register 1 */ +#define STM32_CAN_RDHR_OFFSET(m) (0x01bc + ((m) << 4)) +#define STM32_CAN_RDH0R_OFFSET 0x01bc /* Receive FIFO mailbox data high register 0 */ +#define STM32_CAN_RDH1R_OFFSET 0x01cc /* Receive FIFO mailbox data high register 1 */ /* CAN filter registers */ -#define STM32F0_CAN_FMR_OFFSET 0x0200 /* CAN filter master register */ -#define STM32F0_CAN_FM1R_OFFSET 0x0204 /* CAN filter mode register */ -#define STM32F0_CAN_FS1R_OFFSET 0x020c /* CAN filter scale register */ -#define STM32F0_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */ -#define STM32F0_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */ +#define STM32_CAN_FMR_OFFSET 0x0200 /* CAN filter master register */ +#define STM32_CAN_FM1R_OFFSET 0x0204 /* CAN filter mode register */ +#define STM32_CAN_FS1R_OFFSET 0x020c /* CAN filter scale register */ +#define STM32_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */ +#define STM32_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */ /* There are 14 or 28 filter banks (depending) on the device. * Each filter bank is composed of two 32-bit registers, CAN_FiR: @@ -135,116 +135,116 @@ * ... */ -#define STM32F0_CAN_FIR_OFFSET(f,i) (0x240+((f)<<3)+(((i)-1)<<2)) +#define STM32_CAN_FIR_OFFSET(f,i) (0x240 + ((f) << 3)+(((i) - 1) << 2)) /* Register Addresses ***************************************************************/ -#if STM32F0_NCAN > 0 -# define STM32F0_CAN1_MCR (STM32F0_CAN1_BASE+STM32F0_CAN_MCR_OFFSET) -# define STM32F0_CAN1_MSR (STM32F0_CAN1_BASE+STM32F0_CAN_MSR_OFFSET) -# define STM32F0_CAN1_TSR (STM32F0_CAN1_BASE+STM32F0_CAN_TSR_OFFSET) -# define STM32F0_CAN1_RF0R (STM32F0_CAN1_BASE+STM32F0_CAN_RF0R_OFFSET) -# define STM32F0_CAN1_RF1R (STM32F0_CAN1_BASE+STM32F0_CAN_RF1R_OFFSET) -# define STM32F0_CAN1_IER (STM32F0_CAN1_BASE+STM32F0_CAN_IER_OFFSET) -# define STM32F0_CAN1_ESR (STM32F0_CAN1_BASE+STM32F0_CAN_ESR_OFFSET) -# define STM32F0_CAN1_BTR (STM32F0_CAN1_BASE+STM32F0_CAN_BTR_OFFSET) +#if STM32_NCAN > 0 +# define STM32_CAN1_MCR (STM32_CAN1_BASE + STM32_CAN_MCR_OFFSET) +# define STM32_CAN1_MSR (STM32_CAN1_BASE + STM32_CAN_MSR_OFFSET) +# define STM32_CAN1_TSR (STM32_CAN1_BASE + STM32_CAN_TSR_OFFSET) +# define STM32_CAN1_RF0R (STM32_CAN1_BASE + STM32_CAN_RF0R_OFFSET) +# define STM32_CAN1_RF1R (STM32_CAN1_BASE + STM32_CAN_RF1R_OFFSET) +# define STM32_CAN1_IER (STM32_CAN1_BASE + STM32_CAN_IER_OFFSET) +# define STM32_CAN1_ESR (STM32_CAN1_BASE + STM32_CAN_ESR_OFFSET) +# define STM32_CAN1_BTR (STM32_CAN1_BASE + STM32_CAN_BTR_OFFSET) -# define STM32F0_CAN1_TIR(m) (STM32F0_CAN1_BASE+STM32F0_CAN_TIR_OFFSET(m)) -# define STM32F0_CAN1_TI0R (STM32F0_CAN1_BASE+STM32F0_CAN_TI0R_OFFSET) -# define STM32F0_CAN1_TI1R (STM32F0_CAN1_BASE+STM32F0_CAN_TI1R_OFFSET) -# define STM32F0_CAN1_TI2R (STM32F0_CAN1_BASE+STM32F0_CAN_TI2R_OFFSET) +# define STM32_CAN1_TIR(m) (STM32_CAN1_BASE + STM32_CAN_TIR_OFFSET(m)) +# define STM32_CAN1_TI0R (STM32_CAN1_BASE + STM32_CAN_TI0R_OFFSET) +# define STM32_CAN1_TI1R (STM32_CAN1_BASE + STM32_CAN_TI1R_OFFSET) +# define STM32_CAN1_TI2R (STM32_CAN1_BASE + STM32_CAN_TI2R_OFFSET) -# define STM32F0_CAN1_TDTR(m) (STM32F0_CAN1_BASE+STM32F0_CAN_TDTR_OFFSET(m)) -# define STM32F0_CAN1_TDT0R (STM32F0_CAN1_BASE+STM32F0_CAN_TDT0R_OFFSET) -# define STM32F0_CAN1_TDT1R (STM32F0_CAN1_BASE+STM32F0_CAN_TDT1R_OFFSET) -# define STM32F0_CAN1_TDT2R (STM32F0_CAN1_BASE+STM32F0_CAN_TDT2R_OFFSET) +# define STM32_CAN1_TDTR(m) (STM32_CAN1_BASE + STM32_CAN_TDTR_OFFSET(m)) +# define STM32_CAN1_TDT0R (STM32_CAN1_BASE + STM32_CAN_TDT0R_OFFSET) +# define STM32_CAN1_TDT1R (STM32_CAN1_BASE + STM32_CAN_TDT1R_OFFSET) +# define STM32_CAN1_TDT2R (STM32_CAN1_BASE + STM32_CAN_TDT2R_OFFSET) -# define STM32F0_CAN1_TDLR(m) (STM32F0_CAN1_BASE+STM32F0_CAN_TDLR_OFFSET(m)) -# define STM32F0_CAN1_TDL0R (STM32F0_CAN1_BASE+STM32F0_CAN_TDL0R_OFFSET) -# define STM32F0_CAN1_TDL1R (STM32F0_CAN1_BASE+STM32F0_CAN_TDL1R_OFFSET) -# define STM32F0_CAN1_TDL2R (STM32F0_CAN1_BASE+STM32F0_CAN_TDL2R_OFFSET) +# define STM32_CAN1_TDLR(m) (STM32_CAN1_BASE + STM32_CAN_TDLR_OFFSET(m)) +# define STM32_CAN1_TDL0R (STM32_CAN1_BASE + STM32_CAN_TDL0R_OFFSET) +# define STM32_CAN1_TDL1R (STM32_CAN1_BASE + STM32_CAN_TDL1R_OFFSET) +# define STM32_CAN1_TDL2R (STM32_CAN1_BASE + STM32_CAN_TDL2R_OFFSET) -# define STM32F0_CAN1_TDHR(m) (STM32F0_CAN1_BASE+STM32F0_CAN_TDHR_OFFSET(m)) -# define STM32F0_CAN1_TDH0R (STM32F0_CAN1_BASE+STM32F0_CAN_TDH0R_OFFSET) -# define STM32F0_CAN1_TDH1R (STM32F0_CAN1_BASE+STM32F0_CAN_TDH1R_OFFSET) -# define STM32F0_CAN1_TDH2R (STM32F0_CAN1_BASE+STM32F0_CAN_TDH2R_OFFSET) +# define STM32_CAN1_TDHR(m) (STM32_CAN1_BASE + STM32_CAN_TDHR_OFFSET(m)) +# define STM32_CAN1_TDH0R (STM32_CAN1_BASE + STM32_CAN_TDH0R_OFFSET) +# define STM32_CAN1_TDH1R (STM32_CAN1_BASE + STM32_CAN_TDH1R_OFFSET) +# define STM32_CAN1_TDH2R (STM32_CAN1_BASE + STM32_CAN_TDH2R_OFFSET) -# define STM32F0_CAN1_RIR(m) (STM32F0_CAN1_BASE+STM32F0_CAN_RIR_OFFSET(m)) -# define STM32F0_CAN1_RI0R (STM32F0_CAN1_BASE+STM32F0_CAN_RI0R_OFFSET) -# define STM32F0_CAN1_RI1R (STM32F0_CAN1_BASE+STM32F0_CAN_RI1R_OFFSET) +# define STM32_CAN1_RIR(m) (STM32_CAN1_BASE + STM32_CAN_RIR_OFFSET(m)) +# define STM32_CAN1_RI0R (STM32_CAN1_BASE + STM32_CAN_RI0R_OFFSET) +# define STM32_CAN1_RI1R (STM32_CAN1_BASE + STM32_CAN_RI1R_OFFSET) -# define STM32F0_CAN1_RDTR(m) (STM32F0_CAN1_BASE+STM32F0_CAN_RDTR_OFFSET(m)) -# define STM32F0_CAN1_RDT0R (STM32F0_CAN1_BASE+STM32F0_CAN_RDT0R_OFFSET) -# define STM32F0_CAN1_RDT1R (STM32F0_CAN1_BASE+STM32F0_CAN_RDT1R_OFFSET) +# define STM32_CAN1_RDTR(m) (STM32_CAN1_BASE + STM32_CAN_RDTR_OFFSET(m)) +# define STM32_CAN1_RDT0R (STM32_CAN1_BASE + STM32_CAN_RDT0R_OFFSET) +# define STM32_CAN1_RDT1R (STM32_CAN1_BASE + STM32_CAN_RDT1R_OFFSET) -# define STM32F0_CAN1_RDLR(m) (STM32F0_CAN1_BASE+STM32F0_CAN_RDLR_OFFSET(m)) -# define STM32F0_CAN1_RDL0R (STM32F0_CAN1_BASE+STM32F0_CAN_RDL0R_OFFSET) -# define STM32F0_CAN1_RDL1R (STM32F0_CAN1_BASE+STM32F0_CAN_RDL1R_OFFSET) +# define STM32_CAN1_RDLR(m) (STM32_CAN1_BASE + STM32_CAN_RDLR_OFFSET(m)) +# define STM32_CAN1_RDL0R (STM32_CAN1_BASE + STM32_CAN_RDL0R_OFFSET) +# define STM32_CAN1_RDL1R (STM32_CAN1_BASE + STM32_CAN_RDL1R_OFFSET) -# define STM32F0_CAN1_RDHR(m) (STM32F0_CAN1_BASE+STM32F0_CAN_RDHR_OFFSET(m)) -# define STM32F0_CAN1_RDH0R (STM32F0_CAN1_BASE+STM32F0_CAN_RDH0R_OFFSET) -# define STM32F0_CAN1_RDH1R (STM32F0_CAN1_BASE+STM32F0_CAN_RDH1R_OFFSET) +# define STM32_CAN1_RDHR(m) (STM32_CAN1_BASE + STM32_CAN_RDHR_OFFSET(m)) +# define STM32_CAN1_RDH0R (STM32_CAN1_BASE + STM32_CAN_RDH0R_OFFSET) +# define STM32_CAN1_RDH1R (STM32_CAN1_BASE + STM32_CAN_RDH1R_OFFSET) -# define STM32F0_CAN1_FMR (STM32F0_CAN1_BASE+STM32F0_CAN_FMR_OFFSET) -# define STM32F0_CAN1_FM1R (STM32F0_CAN1_BASE+STM32F0_CAN_FM1R_OFFSET) -# define STM32F0_CAN1_FS1R (STM32F0_CAN1_BASE+STM32F0_CAN_FS1R_OFFSET) -# define STM32F0_CAN1_FFA1R (STM32F0_CAN1_BASE+STM32F0_CAN_FFA1R_OFFSET) -# define STM32F0_CAN1_FA1R (STM32F0_CAN1_BASE+STM32F0_CAN_FA1R_OFFSET) -# define STM32F0_CAN1_FIR(b,i) (STM32F0_CAN1_BASE+STM32F0_CAN_FIR_OFFSET(b,i)) +# define STM32_CAN1_FMR (STM32_CAN1_BASE + STM32_CAN_FMR_OFFSET) +# define STM32_CAN1_FM1R (STM32_CAN1_BASE + STM32_CAN_FM1R_OFFSET) +# define STM32_CAN1_FS1R (STM32_CAN1_BASE + STM32_CAN_FS1R_OFFSET) +# define STM32_CAN1_FFA1R (STM32_CAN1_BASE + STM32_CAN_FFA1R_OFFSET) +# define STM32_CAN1_FA1R (STM32_CAN1_BASE + STM32_CAN_FA1R_OFFSET) +# define STM32_CAN1_FIR(b,i) (STM32_CAN1_BASE + STM32_CAN_FIR_OFFSET(b,i)) #endif -#if STM32F0_NCAN > 1 -# define STM32F0_CAN2_MCR (STM32F0_CAN2_BASE+STM32F0_CAN_MCR_OFFSET) -# define STM32F0_CAN2_MSR (STM32F0_CAN2_BASE+STM32F0_CAN_MSR_OFFSET) -# define STM32F0_CAN2_TSR (STM32F0_CAN2_BASE+STM32F0_CAN_TSR_OFFSET) -# define STM32F0_CAN2_RF0R (STM32F0_CAN2_BASE+STM32F0_CAN_RF0R_OFFSET) -# define STM32F0_CAN2_RF1R (STM32F0_CAN2_BASE+STM32F0_CAN_RF1R_OFFSET) -# define STM32F0_CAN2_IER (STM32F0_CAN2_BASE+STM32F0_CAN_IER_OFFSET) -# define STM32F0_CAN2_ESR (STM32F0_CAN2_BASE+STM32F0_CAN_ESR_OFFSET) -# define STM32F0_CAN2_BTR (STM32F0_CAN2_BASE+STM32F0_CAN_BTR_OFFSET) +#if STM32_NCAN > 1 +# define STM32_CAN2_MCR (STM32_CAN2_BASE + STM32_CAN_MCR_OFFSET) +# define STM32_CAN2_MSR (STM32_CAN2_BASE + STM32_CAN_MSR_OFFSET) +# define STM32_CAN2_TSR (STM32_CAN2_BASE + STM32_CAN_TSR_OFFSET) +# define STM32_CAN2_RF0R (STM32_CAN2_BASE + STM32_CAN_RF0R_OFFSET) +# define STM32_CAN2_RF1R (STM32_CAN2_BASE + STM32_CAN_RF1R_OFFSET) +# define STM32_CAN2_IER (STM32_CAN2_BASE + STM32_CAN_IER_OFFSET) +# define STM32_CAN2_ESR (STM32_CAN2_BASE + STM32_CAN_ESR_OFFSET) +# define STM32_CAN2_BTR (STM32_CAN2_BASE + STM32_CAN_BTR_OFFSET) -# define STM32F0_CAN2_TIR(m) (STM32F0_CAN2_BASE+STM32F0_CAN_TIR_OFFSET(m)) -# define STM32F0_CAN2_TI0R (STM32F0_CAN2_BASE+STM32F0_CAN_TI0R_OFFSET) -# define STM32F0_CAN2_TI1R (STM32F0_CAN2_BASE+STM32F0_CAN_TI1R_OFFSET) -# define STM32F0_CAN2_TI2R (STM32F0_CAN2_BASE+STM32F0_CAN_TI2R_OFFSET) +# define STM32_CAN2_TIR(m) (STM32_CAN2_BASE + STM32_CAN_TIR_OFFSET(m)) +# define STM32_CAN2_TI0R (STM32_CAN2_BASE + STM32_CAN_TI0R_OFFSET) +# define STM32_CAN2_TI1R (STM32_CAN2_BASE + STM32_CAN_TI1R_OFFSET) +# define STM32_CAN2_TI2R (STM32_CAN2_BASE + STM32_CAN_TI2R_OFFSET) -# define STM32F0_CAN2_TDTR(m) (STM32F0_CAN2_BASE+STM32F0_CAN_TDTR_OFFSET(m)) -# define STM32F0_CAN2_TDT0R (STM32F0_CAN2_BASE+STM32F0_CAN_TDT0R_OFFSET) -# define STM32F0_CAN2_TDT1R (STM32F0_CAN2_BASE+STM32F0_CAN_TDT1R_OFFSET) -# define STM32F0_CAN2_TDT2R (STM32F0_CAN2_BASE+STM32F0_CAN_TDT2R_OFFSET) +# define STM32_CAN2_TDTR(m) (STM32_CAN2_BASE + STM32_CAN_TDTR_OFFSET(m)) +# define STM32_CAN2_TDT0R (STM32_CAN2_BASE + STM32_CAN_TDT0R_OFFSET) +# define STM32_CAN2_TDT1R (STM32_CAN2_BASE + STM32_CAN_TDT1R_OFFSET) +# define STM32_CAN2_TDT2R (STM32_CAN2_BASE + STM32_CAN_TDT2R_OFFSET) -# define STM32F0_CAN2_TDLR(m) (STM32F0_CAN2_BASE+STM32F0_CAN_TDLR_OFFSET(m)) -# define STM32F0_CAN2_TDL0R (STM32F0_CAN2_BASE+STM32F0_CAN_TDL0R_OFFSET) -# define STM32F0_CAN2_TDL1R (STM32F0_CAN2_BASE+STM32F0_CAN_TDL1R_OFFSET) -# define STM32F0_CAN2_TDL2R (STM32F0_CAN2_BASE+STM32F0_CAN_TDL2R_OFFSET) +# define STM32_CAN2_TDLR(m) (STM32_CAN2_BASE + STM32_CAN_TDLR_OFFSET(m)) +# define STM32_CAN2_TDL0R (STM32_CAN2_BASE + STM32_CAN_TDL0R_OFFSET) +# define STM32_CAN2_TDL1R (STM32_CAN2_BASE + STM32_CAN_TDL1R_OFFSET) +# define STM32_CAN2_TDL2R (STM32_CAN2_BASE + STM32_CAN_TDL2R_OFFSET) -# define STM32F0_CAN2_TDHR(m) (STM32F0_CAN2_BASE+STM32F0_CAN_TDHR_OFFSET(m)) -# define STM32F0_CAN2_TDH0R (STM32F0_CAN2_BASE+STM32F0_CAN_TDH0R_OFFSET) -# define STM32F0_CAN2_TDH1R (STM32F0_CAN2_BASE+STM32F0_CAN_TDH1R_OFFSET) -# define STM32F0_CAN2_TDH2R (STM32F0_CAN2_BASE+STM32F0_CAN_TDH2R_OFFSET) +# define STM32_CAN2_TDHR(m) (STM32_CAN2_BASE + STM32_CAN_TDHR_OFFSET(m)) +# define STM32_CAN2_TDH0R (STM32_CAN2_BASE + STM32_CAN_TDH0R_OFFSET) +# define STM32_CAN2_TDH1R (STM32_CAN2_BASE + STM32_CAN_TDH1R_OFFSET) +# define STM32_CAN2_TDH2R (STM32_CAN2_BASE + STM32_CAN_TDH2R_OFFSET) -# define STM32F0_CAN2_RIR(m) (STM32F0_CAN2_BASE+STM32F0_CAN_RIR_OFFSET(m)) -# define STM32F0_CAN2_RI0R (STM32F0_CAN2_BASE+STM32F0_CAN_RI0R_OFFSET) -# define STM32F0_CAN2_RI1R (STM32F0_CAN2_BASE+STM32F0_CAN_RI1R_OFFSET) +# define STM32_CAN2_RIR(m) (STM32_CAN2_BASE + STM32_CAN_RIR_OFFSET(m)) +# define STM32_CAN2_RI0R (STM32_CAN2_BASE + STM32_CAN_RI0R_OFFSET) +# define STM32_CAN2_RI1R (STM32_CAN2_BASE + STM32_CAN_RI1R_OFFSET) -# define STM32F0_CAN2_RDTR(m) (STM32F0_CAN2_BASE+STM32F0_CAN_RDTR_OFFSET(m)) -# define STM32F0_CAN2_RDT0R (STM32F0_CAN2_BASE+STM32F0_CAN_RDT0R_OFFSET) -# define STM32F0_CAN2_RDT1R (STM32F0_CAN2_BASE+STM32F0_CAN_RDT1R_OFFSET) +# define STM32_CAN2_RDTR(m) (STM32_CAN2_BASE + STM32_CAN_RDTR_OFFSET(m)) +# define STM32_CAN2_RDT0R (STM32_CAN2_BASE + STM32_CAN_RDT0R_OFFSET) +# define STM32_CAN2_RDT1R (STM32_CAN2_BASE + STM32_CAN_RDT1R_OFFSET) -# define STM32F0_CAN2_RDLR(m) (STM32F0_CAN2_BASE+STM32F0_CAN_RDLR_OFFSET(m)) -# define STM32F0_CAN2_RDL0R (STM32F0_CAN2_BASE+STM32F0_CAN_RDL0R_OFFSET) -# define STM32F0_CAN2_RDL1R (STM32F0_CAN2_BASE+STM32F0_CAN_RDL1R_OFFSET) +# define STM32_CAN2_RDLR(m) (STM32_CAN2_BASE + STM32_CAN_RDLR_OFFSET(m)) +# define STM32_CAN2_RDL0R (STM32_CAN2_BASE + STM32_CAN_RDL0R_OFFSET) +# define STM32_CAN2_RDL1R (STM32_CAN2_BASE + STM32_CAN_RDL1R_OFFSET) -# define STM32F0_CAN2_RDHR(m) (STM32F0_CAN2_BASE+STM32F0_CAN_RDHR_OFFSET(m)) -# define STM32F0_CAN2_RDH0R (STM32F0_CAN2_BASE+STM32F0_CAN_RDH0R_OFFSET) -# define STM32F0_CAN2_RDH1R (STM32F0_CAN2_BASE+STM32F0_CAN_RDH1R_OFFSET) +# define STM32_CAN2_RDHR(m) (STM32_CAN2_BASE + STM32_CAN_RDHR_OFFSET(m)) +# define STM32_CAN2_RDH0R (STM32_CAN2_BASE + STM32_CAN_RDH0R_OFFSET) +# define STM32_CAN2_RDH1R (STM32_CAN2_BASE + STM32_CAN_RDH1R_OFFSET) -# define STM32F0_CAN2_FMR (STM32F0_CAN2_BASE+STM32F0_CAN_FMR_OFFSET) -# define STM32F0_CAN2_FM1R (STM32F0_CAN2_BASE+STM32F0_CAN_FM1R_OFFSET) -# define STM32F0_CAN2_FS1R (STM32F0_CAN2_BASE+STM32F0_CAN_FS1R_OFFSET) -# define STM32F0_CAN2_FFA1R (STM32F0_CAN2_BASE+STM32F0_CAN_FFA1R_OFFSET) -# define STM32F0_CAN2_FA1R (STM32F0_CAN2_BASE+STM32F0_CAN_FA1R_OFFSET) -# define STM32F0_CAN2_FIR(b,i) (STM32F0_CAN2_BASE+STM32F0_CAN_FIR_OFFSET(b,i)) +# define STM32_CAN2_FMR (STM32_CAN2_BASE + STM32_CAN_FMR_OFFSET) +# define STM32_CAN2_FM1R (STM32_CAN2_BASE + STM32_CAN_FM1R_OFFSET) +# define STM32_CAN2_FS1R (STM32_CAN2_BASE + STM32_CAN_FS1R_OFFSET) +# define STM32_CAN2_FFA1R (STM32_CAN2_BASE + STM32_CAN_FFA1R_OFFSET) +# define STM32_CAN2_FA1R (STM32_CAN2_BASE + STM32_CAN_FA1R_OFFSET) +# define STM32_CAN2_FIR(b,i) (STM32_CAN2_BASE + STM32_CAN_FIR_OFFSET(b,i)) #endif /* Register Bitfield Definitions ****************************************************/ @@ -466,4 +466,4 @@ #define CAN_FA1R_FACT_SHIFT (0) /* Bits 13:0: Filter Active */ #define CAN_FA1R_FACT_MASK (0x3fff << CAN_FA1R_FACT_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_CAN_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CAN_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_comp.h b/arch/arm/src/stm32f0l0/hardware/stm32_comp.h similarity index 96% rename from arch/arm/src/stm32f0/chip/stm32f0_comp.h rename to arch/arm/src/stm32f0l0/hardware/stm32_comp.h index f611f98ac36..c8dca2f4e82 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_comp.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32_comp.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/chip/stm32f0_comp.h + * arch/arm/src/stm32f0l0/hardware/stm32_comp.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Mateusz Szafoni @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_COMP_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_COMP_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_COMP_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_COMP_H /************************************************************************************ * Included Files @@ -51,11 +51,11 @@ /* Register Offsets *****************************************************************/ -#define STM32F0_COMP_CSR_OFFSET 0x001c /* COMP1/COMP2 Control register */ +#define STM32_COMP_CSR_OFFSET 0x001c /* COMP1/COMP2 Control register */ /* Register Addresses ***************************************************************/ -#define STM32F0_COMP_CSR (STM32F0_COMP_BASE+STM32F0_COMP_CSR_OFFSET) +#define STM32_COMP_CSR (STM32_COMP_BASE + STM32_COMP_CSR_OFFSET) /* Register Bitfield Definitions ****************************************************/ @@ -135,4 +135,4 @@ #define COMP_CSR_COMP2OUT (1 << 14) /* Bit 14: Comparator 1 output */ #define COMP_CSR_COMP2LOCK (1 << 15) /* Bit 15: Comparator 1 lock */ -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_COMP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_COMP_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_crc.h b/arch/arm/src/stm32f0l0/hardware/stm32_crc.h similarity index 52% rename from arch/arm/src/stm32f0/chip/stm32f0_crc.h rename to arch/arm/src/stm32f0l0/hardware/stm32_crc.h index ca210266747..d368142eb9c 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_crc.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32_crc.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/chip/stm32f0_crc.h + * arch/arm/src/stm32f0l0/hardware/stm32_crc.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_CRC_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_CRC_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRC_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRC_H /************************************************************************************ * Included Files @@ -50,41 +50,41 @@ /* Register Offsets *****************************************************************/ -#define STM32F0_CRC_DR_OFFSET 0x0000 /* Data register */ -#define STM32F0_CRC_IDR_OFFSET 0x0004 /* Independent Data register */ -#define STM32F0_CRC_CR_OFFSET 0x0008 /* Control register */ -#define STM32F0_CRC_INIT_OFFSET 0x0010 /* Initial CRC value register */ -#define STM32F0_CRC_POL_OFFSET 0x0014 /* CRC polynomial register */ +#define STM32_CRC_DR_OFFSET 0x0000 /* Data register */ +#define STM32_CRC_IDR_OFFSET 0x0004 /* Independent Data register */ +#define STM32_CRC_CR_OFFSET 0x0008 /* Control register */ +#define STM32_CRC_INIT_OFFSET 0x0010 /* Initial CRC value register */ +#define STM32_CRC_POL_OFFSET 0x0014 /* CRC polynomial register */ /* Register Addresses ***************************************************************/ -#define STM32F0_CRC_DR (STM32F0_CRC_BASE+STM32F0_CRC_DR_OFFSET) -#define STM32F0_CRC_IDR (STM32F0_CRC_BASE+STM32F0_CRC_IDR_OFFSET) -#define STM32F0_CRC_CR (STM32F0_CRC_BASE+STM32F0_CRC_CR_OFFSET) -#define STM32F0_CRC_INIT (STM32F0_CRC_BASE+STM32F0_CRC_INIT_OFFSET) -#define STM32F0_CRC_POL (STM32F0_CRC_BASE+STM32F0_CRC_POL_OFFSET) +#define STM32_CRC_DR (STM32_CRC_BASE + STM32_CRC_DR_OFFSET) +#define STM32_CRC_IDR (STM32_CRC_BASE + STM32_CRC_IDR_OFFSET) +#define STM32_CRC_CR (STM32_CRC_BASE + STM32_CRC_CR_OFFSET) +#define STM32_CRC_INIT (STM32_CRC_BASE + STM32_CRC_INIT_OFFSET) +#define STM32_CRC_POL (STM32_CRC_BASE + STM32_CRC_POL_OFFSET) /* Register Bitfield Definitions ****************************************************/ /* CRC independent data register */ -#define CRC_IDR_MASK 0xff /* These bits as a temporary location for one byte, not affected by RESET bit of CR */ +#define CRC_IDR_MASK 0xff /* These bits as a temporary location for one byte, not affected by RESET bit of CR */ /* CRC control register */ -#define CRC_CR_RESET (1 << 0) /* This bit reset the CRC calculation unit and load CRC_DR with value of CRC_INIT */ -#define CRC_CR_POLYSIZE_SHIFT 3 /* Bits 3-4: Polynomial size (for STM32F07x and STM32F09x) */ -#define CRC_CR_POLYSIZE_MASK (3 << CRC_CR_POLYSIZE_SHIFT) -# define CRC_CR_POLYSIZE_32 (0 << CRC_CR_POLYSIZE_SHIFT) /* 00: 32 bit polynomial */ -# define CRC_CR_POLYSIZE_16 (1 << CRC_CR_POLYSIZE_SHIFT) /* 01: 16 bit polynomial */ -# define CRC_CR_POLYSIZE_8 (2 << CRC_CR_POLYSIZE_SHIFT) /* 10: 8 bit polynomial */ -# define CRC_CR_POLYSIZE_7 (3 << CRC_CR_POLYSIZE_SHIFT) /* 10: 8 bit polynomial */ -#define CRC_CR_REVIN_SHIFT 5 /* Bits 5-6: These bits ontrol the reversal of the bit order of the input data */ -#define CRC_CR_REVIN_MASK (3 << CRC_CR_REVIN_SHIFT) -# define CRC_CR_REVIN_NONE (0 << CRC_CR_REVIN_SHIFT) /* 00: bit order is not affected */ -# define CRC_CR_REVIN_BYTE (1 << CRC_CR_REVIN_SHIFT) /* 01: reversal done by byte */ -# define CRC_CR_REVIN_HWORD (2 << CRC_CR_REVIN_SHIFT) /* 10: reversal done by half-word */ -# define CRC_CR_REVIN_WORD (3 << CRC_CR_REVIN_SHIFT) /* 11: reversal done by word */ -#define CRC_CR_REVOUT (1 << 7) /* This bit controls the reversal of the bit order of the output data */ +#define CRC_CR_RESET (1 << 0) /* This bit reset the CRC calculation unit and load CRC_DR with value of CRC_INIT */ +#define CRC_CR_POLYSIZE_SHIFT 3 /* Bits 3-4: Polynomial size (for STM32F07x and STM32F09x) */ +#define CRC_CR_POLYSIZE_MASK (3 << CRC_CR_POLYSIZE_SHIFT) +# define CRC_CR_POLYSIZE_32 (0 << CRC_CR_POLYSIZE_SHIFT) /* 00: 32 bit polynomial */ +# define CRC_CR_POLYSIZE_16 (1 << CRC_CR_POLYSIZE_SHIFT) /* 01: 16 bit polynomial */ +# define CRC_CR_POLYSIZE_8 (2 << CRC_CR_POLYSIZE_SHIFT) /* 10: 8 bit polynomial */ +# define CRC_CR_POLYSIZE_7 (3 << CRC_CR_POLYSIZE_SHIFT) /* 10: 8 bit polynomial */ +#define CRC_CR_REVIN_SHIFT 5 /* Bits 5-6: These bits ontrol the reversal of the bit order of the input data */ +#define CRC_CR_REVIN_MASK (3 << CRC_CR_REVIN_SHIFT) +# define CRC_CR_REVIN_NONE (0 << CRC_CR_REVIN_SHIFT) /* 00: bit order is not affected */ +# define CRC_CR_REVIN_BYTE (1 << CRC_CR_REVIN_SHIFT) /* 01: reversal done by byte */ +# define CRC_CR_REVIN_HWORD (2 << CRC_CR_REVIN_SHIFT) /* 10: reversal done by half-word */ +# define CRC_CR_REVIN_WORD (3 << CRC_CR_REVIN_SHIFT) /* 11: reversal done by word */ +#define CRC_CR_REVOUT (1 << 7) /* This bit controls the reversal of the bit order of the output data */ -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_CRC_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRC_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_crs.h b/arch/arm/src/stm32f0l0/hardware/stm32_crs.h similarity index 88% rename from arch/arm/src/stm32f0/chip/stm32f0_crs.h rename to arch/arm/src/stm32f0l0/hardware/stm32_crs.h index ae2f3cd5cde..b0c79e1b80f 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_crs.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32_crs.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/chip/stm32f0_crs.h + * arch/arm/src/stm32f0l0/hardware/stm32_crs.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_CRS_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_CRS_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRS_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRS_H /************************************************************************************ * Pre-processor Definitions @@ -43,17 +43,17 @@ /* Register Offsets *****************************************************************/ -#define STM32F0_CRS_CR_OFFSET 0x0000 /* CRS control register */ -#define STM32F0_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ -#define STM32F0_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ -#define STM32F0_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ +#define STM32_CRS_CR_OFFSET 0x0000 /* CRS control register */ +#define STM32_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ +#define STM32_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ +#define STM32_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ /* Register Addresses ***************************************************************/ -#define STM32F0_CRS_CR (STM32F0_CRS_BASE+STM32F0_CRS_CR_OFFSET) -#define STM32F0_CRS_CFGR (STM32F0_CRS_BASE+STM32F0_CRS_CFGR_OFFSET) -#define STM32F0_CRS_ISR (STM32F0_CRS_BASE+STM32F0_CRS_ISR_OFFSET) -#define STM32F0_CRS_ICR (STM32F0_CRS_BASE+STM32F0_CRS_ICR_OFFSET) +#define STM32_CRS_CR (STM32_CRS_BASE + STM32_CRS_CR_OFFSET) +#define STM32_CRS_CFGR (STM32_CRS_BASE + STM32_CRS_CFGR_OFFSET) +#define STM32_CRS_ISR (STM32_CRS_BASE + STM32_CRS_ISR_OFFSET) +#define STM32_CRS_ICR (STM32_CRS_BASE + STM32_CRS_ICR_OFFSET) /* Register Bitfield Definitions ****************************************************/ @@ -112,4 +112,4 @@ #define CRS_ICR_ERRC (1 << 2) /* Bit 2: Error clear flag */ #define CRS_ICR_ESYNCC (1 << 3) /* Bit 3: Expected SYNC clear flag */ -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_CRS_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRS_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_dac.h b/arch/arm/src/stm32f0l0/hardware/stm32_dac.h similarity index 81% rename from arch/arm/src/stm32f0/chip/stm32f0_dac.h rename to arch/arm/src/stm32f0l0/hardware/stm32_dac.h index 15201108431..a61111ec0e5 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_dac.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32_dac.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/chip/stm32f0_dac.h + * arch/arm/src/stm32f0l0/hardware/stm32_dac.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_DAC_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_DAC_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DAC_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DAC_H /************************************************************************************ * Included Files @@ -50,39 +50,39 @@ /* Register Offsets *****************************************************************/ -#define STM32F0_DAC_CR_OFFSET 0x0000 /* DAC control register */ -#define STM32F0_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */ -#define STM32F0_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */ -#define STM32F0_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */ -#define STM32F0_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */ -#define STM32F0_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */ -#define STM32F0_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */ -#define STM32F0_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */ -#define STM32F0_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */ -#define STM32F0_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */ -#define STM32F0_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */ -#define STM32F0_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */ -#define STM32F0_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */ -#define STM32F0_DAC_SR_OFFSET 0x0034 /* DAC status register */ +#define STM32_DAC_CR_OFFSET 0x0000 /* DAC control register */ +#define STM32_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */ +#define STM32_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */ +#define STM32_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */ +#define STM32_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */ +#define STM32_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */ +#define STM32_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */ +#define STM32_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */ +#define STM32_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */ +#define STM32_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */ +#define STM32_DAC_SR_OFFSET 0x0034 /* DAC status register */ /* Register Addresses ***************************************************************/ /* DAC */ -# define STM32F0_DAC1_CR (STM32F0_DAC1_BASE+STM32F0_DAC_CR_OFFSET) -# define STM32F0_DAC1_SWTRIGR (STM32F0_DAC1_BASE+STM32F0_DAC_SWTRIGR_OFFSET) -# define STM32F0_DAC1_DHR12R1 (STM32F0_DAC1_BASE+STM32F0_DAC_DHR12R1_OFFSET) -# define STM32F0_DAC1_DHR12L1 (STM32F0_DAC1_BASE+STM32F0_DAC_DHR12L1_OFFSET) -# define STM32F0_DAC1_DHR8R1 (STM32F0_DAC1_BASE+STM32F0_DAC_DHR8R1_OFFSET) -# define STM32F0_DAC1_DHR12R2 (STM32F0_DAC1_BASE+STM32F0_DAC_DHR12R2_OFFSET) -# define STM32F0_DAC1_DHR12L2 (STM32F0_DAC1_BASE+STM32F0_DAC_DHR12L2_OFFSET) -# define STM32F0_DAC1_DHR8R2 (STM32F0_DAC1_BASE+STM32F0_DAC_DHR8R2_OFFSET) -# define STM32F0_DAC1_DHR12RD (STM32F0_DAC1_BASE+STM32F0_DAC_DHR12RD_OFFSET) -# define STM32F0_DAC1_DHR12LD (STM32F0_DAC1_BASE+STM32F0_DAC_DHR12LD_OFFSET) -# define STM32F0_DAC1_DHR8RD (STM32F0_DAC1_BASE+STM32F0_DAC_DHR8RD_OFFSET) -# define STM32F0_DAC1_DOR1 (STM32F0_DAC1_BASE+STM32F0_DAC_DOR1_OFFSET) -# define STM32F0_DAC1_DOR2 (STM32F0_DAC1_BASE+STM32F0_DAC_DOR2_OFFSET) -# define STM32F0_DAC1_SR (STM32F0_DAC1_BASE+STM32F0_DAC_SR_OFFSET) +#define STM32_DAC1_CR (STM32_DAC1_BASE + STM32_DAC_CR_OFFSET) +#define STM32_DAC1_SWTRIGR (STM32_DAC1_BASE + STM32_DAC_SWTRIGR_OFFSET) +#define STM32_DAC1_DHR12R1 (STM32_DAC1_BASE + STM32_DAC_DHR12R1_OFFSET) +#define STM32_DAC1_DHR12L1 (STM32_DAC1_BASE + STM32_DAC_DHR12L1_OFFSET) +#define STM32_DAC1_DHR8R1 (STM32_DAC1_BASE + STM32_DAC_DHR8R1_OFFSET) +#define STM32_DAC1_DHR12R2 (STM32_DAC1_BASE + STM32_DAC_DHR12R2_OFFSET) +#define STM32_DAC1_DHR12L2 (STM32_DAC1_BASE + STM32_DAC_DHR12L2_OFFSET) +#define STM32_DAC1_DHR8R2 (STM32_DAC1_BASE + STM32_DAC_DHR8R2_OFFSET) +#define STM32_DAC1_DHR12RD (STM32_DAC1_BASE + STM32_DAC_DHR12RD_OFFSET) +#define STM32_DAC1_DHR12LD (STM32_DAC1_BASE + STM32_DAC_DHR12LD_OFFSET) +#define STM32_DAC1_DHR8RD (STM32_DAC1_BASE + STM32_DAC_DHR8RD_OFFSET) +#define STM32_DAC1_DOR1 (STM32_DAC1_BASE + STM32_DAC_DOR1_OFFSET) +#define STM32_DAC1_DOR2 (STM32_DAC1_BASE + STM32_DAC_DOR2_OFFSET) +#define STM32_DAC1_SR (STM32_DAC1_BASE + STM32_DAC_SR_OFFSET) /* Register Bitfield Definitions ****************************************************/ @@ -215,4 +215,4 @@ #define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */ #define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */ -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_DAC_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DAC_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_dma.h b/arch/arm/src/stm32f0l0/hardware/stm32_dma.h new file mode 100644 index 00000000000..2a7cf6749c2 --- /dev/null +++ b/arch/arm/src/stm32f0l0/hardware/stm32_dma.h @@ -0,0 +1,456 @@ +/************************************************************************************ + * arch/arm/src/stm32f0l0/hardware/stm32_dma.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DMA_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DMA_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* 12 Channels Total: 7 DMA1 Channels(1-7) (and 5 DMA2 channels (1-5) if STM32F09x) */ + +#define DMA1 0 +#define DMA2 1 +#define DMA3 2 +#define DMA4 3 +#define DMA5 4 +#define DMA6 5 +#define DMA7 6 + +/* Register Offsets *****************************************************************/ + +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ + +#define STM32_DMACHAN_OFFSET(n) (0x0014*(n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 + +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ + +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET + STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET + STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET + STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET + STM32_DMACHAN_OFFSET(n)) + +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ + +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ + +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ + +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ + +#define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ + +/* Register Addresses ***************************************************************/ + +#define STM32_DMA1_ISRC (STM32_DMA1_BASE + STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE + STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE + STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE + STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE + STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE + STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE + STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE + STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE + STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE + STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE + STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE + STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE + STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE + STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE + STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE + STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE + STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE + STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE + STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE + STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE + STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE + STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE + STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE + STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE + STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE + STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE + STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE + STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE + STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE + STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE + STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE + STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE + STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE + STM32_DMA_CMAR7_OFFSET) + +#define STM32_DMA2_ISRC (STM32_DMA2_BASE + STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE + STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE + STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE + STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE + STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE + STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE + STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE + STM32_DMA_CCR5_OFFSET) +#define STM32_DMA2_CCR6 (STM32_DMA2_BASE + STM32_DMA_CCR6_OFFSET) +#define STM32_DMA2_CCR7 (STM32_DMA2_BASE + STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE + STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE + STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE + STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE + STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE + STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE + STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE + STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE + STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE + STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE + STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE + STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE + STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE + STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE + STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE + STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE + STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE + STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE + STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE + STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE + STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE + STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE + STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE + STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE + STM32_DMA_CMAR7_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +#define DMA_CHAN_SHIFT(n) ((n) << 2) +#define DMA_CHAN_MASK 0x0f +#define DMA_CHAN_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */ +#define DMA_CHAN_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */ +#define DMA_CHAN_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */ +#define DMA_CHAN_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */ + +/* DMA interrupt status register */ + +#define DMA_ISR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n) +#define DMA_ISR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_ISR_CHAN_SHIFT(n)) +#define DMA_ISR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */ +#define DMA_ISR_CHAN1_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN1_SHIFT) +#define DMA_ISR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */ +#define DMA_ISR_CHAN2_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN2_SHIFT) +#define DMA_ISR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */ +#define DMA_ISR_CHAN3_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN3_SHIFT) +#define DMA_ISR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */ +#define DMA_ISR_CHAN4_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN4_SHIFT) +#define DMA_ISR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */ +#define DMA_ISR_CHAN5_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN5_SHIFT) +#define DMA_ISR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */ +#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT) +#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */ +#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT) + +#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n)) +#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n)) +#define DMA_ISR_HTIF(n) (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n)) +#define DMA_ISR_TEIF(n) (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n)) + +/* DMA interrupt flag clear register */ + +#define DMA_IFCR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n) +#define DMA_IFCR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_IFCR_CHAN_SHIFT(n)) +#define DMA_IFCR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt flag clear */ +#define DMA_IFCR_CHAN1_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN1_SHIFT) +#define DMA_IFCR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt flag clear */ +#define DMA_IFCR_CHAN2_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN2_SHIFT) +#define DMA_IFCR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt flag clear */ +#define DMA_IFCR_CHAN3_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN3_SHIFT) +#define DMA_IFCR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt flag clear */ +#define DMA_IFCR_CHAN4_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN4_SHIFT) +#define DMA_IFCR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt flag clear */ +#define DMA_IFCR_CHAN5_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN5_SHIFT) +#define DMA_IFCR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt flag clear */ +#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT) +#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */ +#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT) +#define DMA_IFCR_ALLCHANNELS (0x0fffffff) + +#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) +#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) +#define DMA_IFCR_CHTIF(n) (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) +#define DMA_IFCR_CTEIF(n) (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) + +/* DMA channel configuration register */ + +#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */ +#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */ +#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */ +#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */ +#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */ +#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */ +#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */ +#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */ +#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 8-9: Peripheral size */ +#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT) +# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */ +# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */ +# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */ +#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 10-11: Memory size */ +#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT) +# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */ +# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */ +# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */ +#define DMA_CCR_PL_SHIFT (12) /* Bits 12-13: Channel Priority level */ +#define DMA_CCR_PL_MASK (3 << DMA_CCR_PL_SHIFT) +# define DMA_CCR_PRILO (0 << DMA_CCR_PL_SHIFT) /* 00: Low */ +# define DMA_CCR_PRIMED (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */ +# define DMA_CCR_PRIHI (2 << DMA_CCR_PL_SHIFT) /* 10: High */ +# define DMA_CCR_PRIVERYHI (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */ +#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */ + +#define DMA_CCR_ALLINTS (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE) + +/* DMA channel number of data register */ + +#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */ +#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT) + +/* DMA Channel mapping. Each DMA channel has a mapping to one of several + * possible sources/sinks of data. The requests from peripherals assigned to a + * channel are multiplexed together before entering the DMA block. This means + * that only one request on a given channel can be enabled at once. + * + * Alternative DMA channel selections are provided with a numeric suffix like _1, + * _2, etc. Drivers, however, will use the pin selection without the numeric suffix. + * Additional definitions are required in the board.h file. + */ + +/* REVISE IT: based on STM32L4 DMA Header */ + +#define STM32_DMA1_CHAN1 (0) +#define STM32_DMA1_CHAN2 (1) +#define STM32_DMA1_CHAN3 (2) +#define STM32_DMA1_CHAN4 (3) +#define STM32_DMA1_CHAN5 (4) +#define STM32_DMA1_CHAN6 (5) +#define STM32_DMA1_CHAN7 (6) + +#define STM32_DMA2_CHAN1 (7) +#define STM32_DMA2_CHAN2 (8) +#define STM32_DMA2_CHAN3 (9) +#define STM32_DMA2_CHAN4 (10) +#define STM32_DMA2_CHAN5 (11) + +#define DMACHAN_SETTING(chan, sel) ((((sel) & 0xff) << 8) | ((chan) & 0xff)) +#define DMACHAN_SETTING_CHANNEL_MASK 0x00FF +#define DMACHAN_SETTING_CHANNEL_SHIFT (0) +#define DMACHAN_SETTING_FUNCTION_MASK 0xFF00 +#define DMACHAN_SETTING_FUNCTION_SHIFT (8) + +/* ADC */ + +#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 0) + +#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 0) + +#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 0) + +/* AES */ + +#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 6) +#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 6) +#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 6) +#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 6) + +/* DAC */ + +#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_DAC1_3 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) + +#define DMACHAN_DAC2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) + +/* I2C */ + +#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 3) +#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 5) +#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 3) +#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 5) + +#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN5, 3) +#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 3) + +#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) +#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 3) + +/* QUADSPI */ + +#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 5) +#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 3) + +/* SPI */ + +#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 1) +#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 4) +#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 0) +#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 4) + +#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32_DMA1_CHAN4, 1) +#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32_DMA1_CHAN5, 1) + +#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 3) +#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 3) + +/* TIM */ + +#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 7) +#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 7) +#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 7) +#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32_DMA1_CHAN6, 7) + +#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4) +#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 4) +#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 4) + +#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5) +#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) +#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) + +#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 6) +#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 6) +#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN5, 6) +#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32_DMA1_CHAN7, 6) + +#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 5) +#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 5) +#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN2, 5) +#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32_DMA2_CHAN2, 5) + +#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) + +#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) + +#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN6, 7) +#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 7) +#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN1, 7) +#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32_DMA2_CHAN1, 7) + +#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) + +#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) +#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) + +#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5) +#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) +#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5) +#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) + +/* USARTs */ + +#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2) +#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 2) +#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2) +#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 2) + +#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32_DMA1_CHAN6, 2) +#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32_DMA1_CHAN7, 2) + +#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 1) +#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 2) + +#define DMACHAN_USART4_RX DMACHAN_SETTING(STM32_DMA2_CHAN5, 2) +#define DMACHAN_USART4_TX DMACHAN_SETTING(STM32_DMA2_CHAN3, 2) + +#define DMACHAN_USART5_RX DMACHAN_SETTING(STM32_DMA2_CHAN2, 2) +#define DMACHAN_USART5_TX DMACHAN_SETTING(STM32_DMA2_CHAN1, 2) + +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DMA_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_exti.h b/arch/arm/src/stm32f0l0/hardware/stm32_exti.h new file mode 100644 index 00000000000..7bed98bb299 --- /dev/null +++ b/arch/arm/src/stm32f0l0/hardware/stm32_exti.h @@ -0,0 +1,131 @@ +/************************************************************************************ + * arch/arm/src/stm32f0l0/hardware/stm32_exti.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_EXTI_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_EXTI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#define STM32_NEXTI 31 +#define STM32_EXTI_MASK 0xffffffff + +#define STM32_EXTI_BIT(n) (1 << (n)) + +/* Register Offsets *****************************************************************/ + +#define STM32_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */ +#define STM32_EXTI_EMR_OFFSET 0x0004 /* Event mask register */ +#define STM32_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */ +#define STM32_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */ +#define STM32_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */ +#define STM32_EXTI_PR_OFFSET 0x0014 /* Pending register */ + +/* Register Addresses ***************************************************************/ + +#define STM32_EXTI_IMR (STM32_EXTI_BASE + STM32_EXTI_IMR_OFFSET) +#define STM32_EXTI_EMR (STM32_EXTI_BASE + STM32_EXTI_EMR_OFFSET) +#define STM32_EXTI_RTSR (STM32_EXTI_BASE + STM32_EXTI_RTSR_OFFSET) +#define STM32_EXTI_FTSR (STM32_EXTI_BASE + STM32_EXTI_FTSR_OFFSET) +#define STM32_EXTI_SWIER (STM32_EXTI_BASE + STM32_EXTI_SWIER_OFFSET) +#define STM32_EXTI_PR (STM32_EXTI_BASE + STM32_EXTI_PR_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +/* EXTI lines > 15 are associated with internal devices: */ + +#define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */ +#define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */ +#define EXTI_USB_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB wake up event */ +#define EXTI_RTC_TAMPER (1 << 19) /* EXTI line 19 is connected to the RTC Tamper and TimeStamp events */ +#define EXTI_RTC_WAKEUP (1 << 20) /* EXTI line 20 is connected to the RTC Wakeup event */ +#define EXTI_COMP1 (1 << 21) /* EXTI line 21 is connected to the COMP1 (comparator) output */ +#define EXTI_COMP2 (1 << 22) /* EXTI line 22 is connected to the COMP2 (comparator) output */ +#define EXTI_I2C1 (1 << 23) /* EXTI line 23 is connected to the I2C1 wakeup */ + /* EXTI line 24 is reserved (internally held low) */ +#define EXTI_USART1 (1 << 25) /* EXTI line 25 is connected to the USART1 wakeup */ +#define EXTI_USART2 (1 << 26) /* EXTI line 26 is connected to the USART2 wakeup */ +#define EXTI_CEC (1 << 27) /* EXTI line 27 is connected to the CEC wakeup */ +#define EXTI_USART3 (1 << 28) /* EXTI line 28 is connected to the USART3 wakeup */ + /* EXTI line 29 is reserved (internally held low) */ + /* EXTI line 30 is reserved (internally held low) */ +#define EXTI_VDDIO2 (1 << 31) /* EXTI line 31 is connected to the Vddio2 supply comparator */ + +/* Interrupt mask register */ + +#define EXTI_IMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Interrupt request from line x is not masked */ +#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */ +#define EXTI_IMR_MASK STM32_EXTI_MASK + +/* Event mask register */ + +#define EXTI_EMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Event request from line x is not mask */ +#define EXTI_EMR_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */ +#define EXTI_EMR_MASK STM32_EXTI_MASK + +/* Rising Trigger selection register */ + +#define EXTI_RTSR_BIT(n) STM32_EXTI_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */ +#define EXTI_RTSR_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */ +#define EXTI_RTSR_MASK STM32_EXTI_MASK + +/* Falling Trigger selection register */ + +#define EXTI_FTSR_BIT(n) STM32_EXTI_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */ +#define EXTI_FTSR_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */ +#define EXTI_FTSR_MASK STM32_EXTI_MASK + +/* Software interrupt event register */ + +#define EXTI_SWIER_BIT(n) STM32_EXTI_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */ +#define EXTI_SWIER_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */ +#define EXTI_SWIER_MASK STM32_EXTI_MASK + +/* Pending register */ + +#define EXTI_PR_BIT(n) STM32_EXTI_BIT(n) /* 1=Selected trigger request occurred */ +#define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ +#define EXTI_PR_MASK STM32_EXTI_MASK + +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_flash.h b/arch/arm/src/stm32f0l0/hardware/stm32_flash.h similarity index 79% rename from arch/arm/src/stm32f0/chip/stm32f0_flash.h rename to arch/arm/src/stm32f0l0/hardware/stm32_flash.h index 82a94421566..58fef4e6d1c 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_flash.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32_flash.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32/chip/stm32f0_flash.h + * arch/arm/src/stm32f0l0/hardware/stm32_flash.h * * Copyright (C) 20017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_FLASH_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_FLASH_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_FLASH_H /************************************************************************************ * Included Files @@ -50,25 +50,25 @@ /* Register Offsets *****************************************************************/ -#define STM32_FLASH_ACR_OFFSET 0x0000 -#define STM32_FLASH_KEYR_OFFSET 0x0004 -#define STM32_FLASH_OPTKEYR_OFFSET 0x0008 -#define STM32_FLASH_SR_OFFSET 0x000c -#define STM32_FLASH_CR_OFFSET 0x0010 -#define STM32_FLASH_AR_OFFSET 0x0014 -#define STM32_FLASH_OBR_OFFSET 0x001c -#define STM32_FLASH_WRPR_OFFSET 0x0020 +#define STM32_FLASH_ACR_OFFSET 0x0000 +#define STM32_FLASH_KEYR_OFFSET 0x0004 +#define STM32_FLASH_OPTKEYR_OFFSET 0x0008 +#define STM32_FLASH_SR_OFFSET 0x000c +#define STM32_FLASH_CR_OFFSET 0x0010 +#define STM32_FLASH_AR_OFFSET 0x0014 +#define STM32_FLASH_OBR_OFFSET 0x001c +#define STM32_FLASH_WRPR_OFFSET 0x0020 /* Register Addresses ***************************************************************/ -#define STM32_FLASH_ACR (STM32F0_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET) -#define STM32_FLASH_KEYR (STM32F0_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) -#define STM32_FLASH_OPTKEYR (STM32F0_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) -#define STM32_FLASH_SR (STM32F0_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) -#define STM32_FLASH_CR (STM32F0_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) -#define STM32_FLASH_AR (STM32F0_FLASHIF_BASE+STM32_FLASH_AR_OFFSET) -#define STM32_FLASH_OBR (STM32F0_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET) -#define STM32_FLASH_WRPR (STM32F0_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET) +#define STM32_FLASH_ACR (STM32_FLASHIF_BASE + STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE + STM32_FLASH_KEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE + STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_SR (STM32_FLASHIF_BASE + STM32_FLASH_SR_OFFSET) +#define STM32_FLASH_CR (STM32_FLASHIF_BASE + STM32_FLASH_CR_OFFSET) +#define STM32_FLASH_AR (STM32_FLASHIF_BASE + STM32_FLASH_AR_OFFSET) +#define STM32_FLASH_OBR (STM32_FLASHIF_BASE + STM32_FLASH_OBR_OFFSET) +#define STM32_FLASH_WRPR (STM32_FLASHIF_BASE + STM32_FLASH_WRPR_OFFSET) /* Register Bitfield Definitions ****************************************************/ /* Flash Access Control Register (ACR) */ @@ -112,4 +112,4 @@ void stm32_flash_lock(void); void stm32_flash_unlock(void); -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_gpio.h b/arch/arm/src/stm32f0l0/hardware/stm32_gpio.h similarity index 62% rename from arch/arm/src/stm32f0/chip/stm32f0_gpio.h rename to arch/arm/src/stm32f0l0/hardware/stm32_gpio.h index 7f7cd395162..a1ee32b3065 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_gpio.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32_gpio.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/chip/stm32f0_gpio.h + * arch/arm/src/stm32f0l0/hardware/stm32_gpio.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_GPIO_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_GPIO_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_GPIO_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_GPIO_H /************************************************************************************ * Pre-processor Definitions @@ -43,96 +43,96 @@ /* Register Offsets *****************************************************************/ -#define STM32F0_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ -#define STM32F0_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ -#define STM32F0_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ -#define STM32F0_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ -#define STM32F0_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ -#define STM32F0_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ -#define STM32F0_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ -#define STM32F0_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ -#define STM32F0_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32F0_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32F0_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ +#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ +#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ /* Register Addresses ***************************************************************/ -#if STM32F0_NPORTS > 0 -# define STM32F0_GPIOA_MODER (STM32F0_GPIOA_BASE+STM32F0_GPIO_MODER_OFFSET) -# define STM32F0_GPIOA_OTYPER (STM32F0_GPIOA_BASE+STM32F0_GPIO_OTYPER_OFFSET) -# define STM32F0_GPIOA_OSPEED (STM32F0_GPIOA_BASE+STM32F0_GPIO_OSPEED_OFFSET) -# define STM32F0_GPIOA_PUPDR (STM32F0_GPIOA_BASE+STM32F0_GPIO_PUPDR_OFFSET) -# define STM32F0_GPIOA_IDR (STM32F0_GPIOA_BASE+STM32F0_GPIO_IDR_OFFSET) -# define STM32F0_GPIOA_ODR (STM32F0_GPIOA_BASE+STM32F0_GPIO_ODR_OFFSET) -# define STM32F0_GPIOA_BSRR (STM32F0_GPIOA_BASE+STM32F0_GPIO_BSRR_OFFSET) -# define STM32F0_GPIOA_LCKR (STM32F0_GPIOA_BASE+STM32F0_GPIO_LCKR_OFFSET) -# define STM32F0_GPIOA_AFRL (STM32F0_GPIOA_BASE+STM32F0_GPIO_AFRL_OFFSET) -# define STM32F0_GPIOA_AFRH (STM32F0_GPIOA_BASE+STM32F0_GPIO_AFRH_OFFSET) +#if STM32_NPORTS > 0 +# define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOA_IDR (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOA_ODR (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F0_NPORTS > 1 -# define STM32F0_GPIOB_MODER (STM32F0_GPIOB_BASE+STM32F0_GPIO_MODER_OFFSET) -# define STM32F0_GPIOB_OTYPER (STM32F0_GPIOB_BASE+STM32F0_GPIO_OTYPER_OFFSET) -# define STM32F0_GPIOB_OSPEED (STM32F0_GPIOB_BASE+STM32F0_GPIO_OSPEED_OFFSET) -# define STM32F0_GPIOB_PUPDR (STM32F0_GPIOB_BASE+STM32F0_GPIO_PUPDR_OFFSET) -# define STM32F0_GPIOB_IDR (STM32F0_GPIOB_BASE+STM32F0_GPIO_IDR_OFFSET) -# define STM32F0_GPIOB_ODR (STM32F0_GPIOB_BASE+STM32F0_GPIO_ODR_OFFSET) -# define STM32F0_GPIOB_BSRR (STM32F0_GPIOB_BASE+STM32F0_GPIO_BSRR_OFFSET) -# define STM32F0_GPIOB_LCKR (STM32F0_GPIOB_BASE+STM32F0_GPIO_LCKR_OFFSET) -# define STM32F0_GPIOB_AFRL (STM32F0_GPIOB_BASE+STM32F0_GPIO_AFRL_OFFSET) -# define STM32F0_GPIOB_AFRH (STM32F0_GPIOB_BASE+STM32F0_GPIO_AFRH_OFFSET) +#if STM32_NPORTS > 1 +# define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOB_IDR (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOB_ODR (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F0_NPORTS > 2 -# define STM32F0_GPIOC_MODER (STM32F0_GPIOC_BASE+STM32F0_GPIO_MODER_OFFSET) -# define STM32F0_GPIOC_OTYPER (STM32F0_GPIOC_BASE+STM32F0_GPIO_OTYPER_OFFSET) -# define STM32F0_GPIOC_OSPEED (STM32F0_GPIOC_BASE+STM32F0_GPIO_OSPEED_OFFSET) -# define STM32F0_GPIOC_PUPDR (STM32F0_GPIOC_BASE+STM32F0_GPIO_PUPDR_OFFSET) -# define STM32F0_GPIOC_IDR (STM32F0_GPIOC_BASE+STM32F0_GPIO_IDR_OFFSET) -# define STM32F0_GPIOC_ODR (STM32F0_GPIOC_BASE+STM32F0_GPIO_ODR_OFFSET) -# define STM32F0_GPIOC_BSRR (STM32F0_GPIOC_BASE+STM32F0_GPIO_BSRR_OFFSET) -# define STM32F0_GPIOC_LCKR (STM32F0_GPIOC_BASE+STM32F0_GPIO_LCKR_OFFSET) -# define STM32F0_GPIOC_AFRL (STM32F0_GPIOC_BASE+STM32F0_GPIO_AFRL_OFFSET) -# define STM32F0_GPIOC_AFRH (STM32F0_GPIOC_BASE+STM32F0_GPIO_AFRH_OFFSET) +#if STM32_NPORTS > 2 +# define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOC_IDR (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOC_ODR (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F0_NPORTS > 3 -# define STM32F0_GPIOD_MODER (STM32F0_GPIOD_BASE+STM32F0_GPIO_MODER_OFFSET) -# define STM32F0_GPIOD_OTYPER (STM32F0_GPIOD_BASE+STM32F0_GPIO_OTYPER_OFFSET) -# define STM32F0_GPIOD_OSPEED (STM32F0_GPIOD_BASE+STM32F0_GPIO_OSPEED_OFFSET) -# define STM32F0_GPIOD_PUPDR (STM32F0_GPIOD_BASE+STM32F0_GPIO_PUPDR_OFFSET) -# define STM32F0_GPIOD_IDR (STM32F0_GPIOD_BASE+STM32F0_GPIO_IDR_OFFSET) -# define STM32F0_GPIOD_ODR (STM32F0_GPIOD_BASE+STM32F0_GPIO_ODR_OFFSET) -# define STM32F0_GPIOD_BSRR (STM32F0_GPIOD_BASE+STM32F0_GPIO_BSRR_OFFSET) -# define STM32F0_GPIOD_LCKR (STM32F0_GPIOD_BASE+STM32F0_GPIO_LCKR_OFFSET) -# define STM32F0_GPIOD_AFRL (STM32F0_GPIOD_BASE+STM32F0_GPIO_AFRL_OFFSET) -# define STM32F0_GPIOD_AFRH (STM32F0_GPIOD_BASE+STM32F0_GPIO_AFRH_OFFSET) +#if STM32_NPORTS > 3 +# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOD_IDR (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOD_ODR (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F0_NPORTS > 4 -# define STM32F0_GPIOE_MODER (STM32F0_GPIOE_BASE+STM32F0_GPIO_MODER_OFFSET) -# define STM32F0_GPIOE_OTYPER (STM32F0_GPIOE_BASE+STM32F0_GPIO_OTYPER_OFFSET) -# define STM32F0_GPIOE_OSPEED (STM32F0_GPIOE_BASE+STM32F0_GPIO_OSPEED_OFFSET) -# define STM32F0_GPIOE_PUPDR (STM32F0_GPIOE_BASE+STM32F0_GPIO_PUPDR_OFFSET) -# define STM32F0_GPIOE_IDR (STM32F0_GPIOE_BASE+STM32F0_GPIO_IDR_OFFSET) -# define STM32F0_GPIOE_ODR (STM32F0_GPIOE_BASE+STM32F0_GPIO_ODR_OFFSET) -# define STM32F0_GPIOE_BSRR (STM32F0_GPIOE_BASE+STM32F0_GPIO_BSRR_OFFSET) -# define STM32F0_GPIOE_LCKR (STM32F0_GPIOE_BASE+STM32F0_GPIO_LCKR_OFFSET) -# define STM32F0_GPIOE_AFRL (STM32F0_GPIOE_BASE+STM32F0_GPIO_AFRL_OFFSET) -# define STM32F0_GPIOE_AFRH (STM32F0_GPIOE_BASE+STM32F0_GPIO_AFRH_OFFSET) +#if STM32_NPORTS > 4 +# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOE_IDR (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOE_ODR (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE + STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F0_NPORTS > 5 -# define STM32F0_GPIOF_MODER (STM32F0_GPIOF_BASE+STM32F0_GPIO_MODER_OFFSET) -# define STM32F0_GPIOF_OTYPER (STM32F0_GPIOF_BASE+STM32F0_GPIO_OTYPER_OFFSET) -# define STM32F0_GPIOF_OSPEED (STM32F0_GPIOF_BASE+STM32F0_GPIO_OSPEED_OFFSET) -# define STM32F0_GPIOF_PUPDR (STM32F0_GPIOF_BASE+STM32F0_GPIO_PUPDR_OFFSET) -# define STM32F0_GPIOF_IDR (STM32F0_GPIOF_BASE+STM32F0_GPIO_IDR_OFFSET) -# define STM32F0_GPIOF_ODR (STM32F0_GPIOF_BASE+STM32F0_GPIO_ODR_OFFSET) -# define STM32F0_GPIOF_BSRR (STM32F0_GPIOF_BASE+STM32F0_GPIO_BSRR_OFFSET) -# define STM32F0_GPIOF_LCKR (STM32F0_GPIOF_BASE+STM32F0_GPIO_LCKR_OFFSET) -# define STM32F0_GPIOF_AFRL (STM32F0_GPIOF_BASE+STM32F0_GPIO_AFRL_OFFSET) -# define STM32F0_GPIOF_AFRH (STM32F0_GPIOF_BASE+STM32F0_GPIO_AFRH_OFFSET) +#if STM32_NPORTS > 5 +# define STM32_GPIOF_MODER (STM32_GPIOF_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOF_IDR (STM32_GPIOF_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOF_ODR (STM32_GPIOF_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE + STM32_GPIO_AFRH_OFFSET) #endif /* Register Bitfield Definitions ****************************************************/ @@ -280,7 +280,7 @@ /* GPIO port bit set/reset register */ #define GPIO_BSRR_SET(n) (1 << (n)) -#define GPIO_BSRR_RESET(n) (1 << ((n)+16)) +#define GPIO_BSRR_RESET(n) (1 << ((n) + 16)) /* GPIO port configuration lock register */ @@ -330,4 +330,4 @@ #define GPIO_BRR(n) (1 << (n)) -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_GPIO_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_i2c.h b/arch/arm/src/stm32f0l0/hardware/stm32_i2c.h similarity index 80% rename from arch/arm/src/stm32f0/chip/stm32f0_i2c.h rename to arch/arm/src/stm32f0l0/hardware/stm32_i2c.h index dc677424789..3ad47e6c583 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_i2c.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32_i2c.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/chip/stm32f0_i2c.h + * arch/arm/src/stm32f0l0/hardware/stm32_i2c.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_I2C_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_I2C_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_I2C_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_I2C_H /************************************************************************************ * Pre-processor Definitions @@ -43,46 +43,46 @@ /* Register Offsets *****************************************************************/ -#define STM32F0_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ -#define STM32F0_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ -#define STM32F0_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ -#define STM32F0_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ -#define STM32F0_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ -#define STM32F0_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ -#define STM32F0_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ -#define STM32F0_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ -#define STM32F0_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ -#define STM32F0_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ -#define STM32F0_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ +#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ +#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ +#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ +#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ +#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ +#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ +#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ +#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ +#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ +#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ +#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ /* Register Addresses ***************************************************************/ -#if STM32F0_NI2C > 0 -# define STM32F0_I2C1_CR1 (STM32F0_I2C1_BASE+STM32F0_I2C_CR1_OFFSET) -# define STM32F0_I2C1_CR2 (STM32F0_I2C1_BASE+STM32F0_I2C_CR2_OFFSET) -# define STM32F0_I2C1_OAR1 (STM32F0_I2C1_BASE+STM32F0_I2C_OAR1_OFFSET) -# define STM32F0_I2C1_OAR2 (STM32F0_I2C1_BASE+STM32F0_I2C_OAR2_OFFSET) -# define STM32F0_I2C1_TIMINGR (STM32F0_I2C1_BASE+STM32F0_I2C_TIMINGR_OFFSET) -# define STM32F0_I2C1_TIMEOUTR (STM32F0_I2C1_BASE+STM32F0_I2C_TIMEOUTR_OFFSET) -# define STM32F0_I2C1_ISR (STM32F0_I2C1_BASE+STM32F0_I2C_ISR_OFFSET) -# define STM32F0_I2C1_ICR (STM32F0_I2C1_BASE+STM32F0_I2C_ICR_OFFSET) -# define STM32F0_I2C1_PECR (STM32F0_I2C1_BASE+STM32F0_I2C_PECR_OFFSET) -# define STM32F0_I2C1_RXDR (STM32F0_I2C1_BASE+STM32F0_I2C_RXDR_OFFSET) -# define STM32F0_I2C1_TXDR (STM32F0_I2C1_BASE+STM32F0_I2C_TXDR_OFFSET) +#if STM32_NI2C > 0 +# define STM32_I2C1_CR1 (STM32_I2C1_BASE + STM32_I2C_CR1_OFFSET) +# define STM32_I2C1_CR2 (STM32_I2C1_BASE + STM32_I2C_CR2_OFFSET) +# define STM32_I2C1_OAR1 (STM32_I2C1_BASE + STM32_I2C_OAR1_OFFSET) +# define STM32_I2C1_OAR2 (STM32_I2C1_BASE + STM32_I2C_OAR2_OFFSET) +# define STM32_I2C1_TIMINGR (STM32_I2C1_BASE + STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE + STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C1_ISR (STM32_I2C1_BASE + STM32_I2C_ISR_OFFSET) +# define STM32_I2C1_ICR (STM32_I2C1_BASE + STM32_I2C_ICR_OFFSET) +# define STM32_I2C1_PECR (STM32_I2C1_BASE + STM32_I2C_PECR_OFFSET) +# define STM32_I2C1_RXDR (STM32_I2C1_BASE + STM32_I2C_RXDR_OFFSET) +# define STM32_I2C1_TXDR (STM32_I2C1_BASE + STM32_I2C_TXDR_OFFSET) #endif -#if STM32F0_NI2C > 1 -# define STM32F0_I2C2_CR1 (STM32F0_I2C2_BASE+STM32F0_I2C_CR1_OFFSET) -# define STM32F0_I2C2_CR2 (STM32F0_I2C2_BASE+STM32F0_I2C_CR2_OFFSET) -# define STM32F0_I2C2_OAR1 (STM32F0_I2C2_BASE+STM32F0_I2C_OAR1_OFFSET) -# define STM32F0_I2C2_OAR2 (STM32F0_I2C2_BASE+STM32F0_I2C_OAR2_OFFSET) -# define STM32F0_I2C2_TIMINGR (STM32F0_I2C2_BASE+STM32F0_I2C_TIMINGR_OFFSET) -# define STM32F0_I2C2_TIMEOUTR (STM32F0_I2C2_BASE+STM32F0_I2C_TIMEOUTR_OFFSET) -# define STM32F0_I2C2_ISR (STM32F0_I2C2_BASE+STM32F0_I2C_ISR_OFFSET) -# define STM32F0_I2C2_ICR (STM32F0_I2C2_BASE+STM32F0_I2C_ICR_OFFSET) -# define STM32F0_I2C2_PECR (STM32F0_I2C2_BASE+STM32F0_I2C_PECR_OFFSET) -# define STM32F0_I2C2_RXDR (STM32F0_I2C2_BASE+STM32F0_I2C_RXDR_OFFSET) -# define STM32F0_I2C2_TXDR (STM32F0_I2C2_BASE+STM32F0_I2C_TXDR_OFFSET) +#if STM32_NI2C > 1 +# define STM32_I2C2_CR1 (STM32_I2C2_BASE + STM32_I2C_CR1_OFFSET) +# define STM32_I2C2_CR2 (STM32_I2C2_BASE + STM32_I2C_CR2_OFFSET) +# define STM32_I2C2_OAR1 (STM32_I2C2_BASE + STM32_I2C_OAR1_OFFSET) +# define STM32_I2C2_OAR2 (STM32_I2C2_BASE + STM32_I2C_OAR2_OFFSET) +# define STM32_I2C2_TIMINGR (STM32_I2C2_BASE + STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C2_TIMEOUTR (STM32_I2C2_BASE + STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C2_ISR (STM32_I2C2_BASE + STM32_I2C_ISR_OFFSET) +# define STM32_I2C2_ICR (STM32_I2C2_BASE + STM32_I2C_ICR_OFFSET) +# define STM32_I2C2_PECR (STM32_I2C2_BASE + STM32_I2C_PECR_OFFSET) +# define STM32_I2C2_RXDR (STM32_I2C2_BASE + STM32_I2C_RXDR_OFFSET) +# define STM32_I2C2_TXDR (STM32_I2C2_BASE + STM32_I2C_TXDR_OFFSET) #endif /* Register Bitfield Definitions ****************************************************/ @@ -235,4 +235,4 @@ #define I2C_TXDR_MASK (0xff) -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_I2C_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_I2C_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_memorymap.h b/arch/arm/src/stm32f0l0/hardware/stm32_memorymap.h similarity index 84% rename from arch/arm/src/stm32f0/chip/stm32f0_memorymap.h rename to arch/arm/src/stm32f0l0/hardware/stm32_memorymap.h index bc2436f4769..4ed9486ede9 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_memorymap.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32_memorymap.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/chip/stm32f0_memorymap.h + * arch/arm/src/stm32f0l0/hardware/stm32_memorymap.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_MEMORYMAP_H /************************************************************************************ * Included Files @@ -44,11 +44,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F0_STM32F05X) || defined(CONFIG_STM32F0_STM32F07X) \ - || defined(CONFIG_STM32F0_STM32F09X) -# include "chip/stm32f05xf07xf09x_memorymap.h" +#if defined(CONFIG_STM32F0L0_STM32F05X) || defined(CONFIG_STM32F0L0_STM32F07X) || \ + defined(CONFIG_STM32F0L0_STM32F09X) +# include "hardware/stm32f05xf07xf09x_memorymap.h" #else # error "Unsupported STM32 memory map" #endif -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_pinmap.h b/arch/arm/src/stm32f0l0/hardware/stm32_pinmap.h similarity index 81% rename from arch/arm/src/stm32f0/chip/stm32f0_pinmap.h rename to arch/arm/src/stm32f0l0/hardware/stm32_pinmap.h index 671264c893e..6fa63312a1f 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_pinmap.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32_pinmap.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/chip/stm32f0_pinmap.h + * arch/arm/src/stm32f0l0/hardware/stm32_pinmap.h * * Copyright (C) 2015 Sebastien Lorquet. All rights reserved. * Author: Sebastien Lorquet @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PINMAP_H /************************************************************************************ * Included Files @@ -43,15 +43,14 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F0_STM32F05X) -# include "chip/stm32f05x_pinmap.h" -#elif defined(CONFIG_STM32F0_STM32F07X) -# include "chip/stm32f07x_pinmap.h" -#elif defined(CONFIG_STM32F0_STM32F09X) -# include "chip/stm32f09x_pinmap.h" +#if defined(CONFIG_STM32F0L0_STM32F05X) +# include "hardware/stm32f05x_pinmap.h" +#elif defined(CONFIG_STM32F0L0_STM32F07X) +# include "hardware/stm32f07x_pinmap.h" +#elif defined(CONFIG_STM32F0L0_STM32F09X) +# include "hardware/stm32f09x_pinmap.h" #else # error "Unsupported STM32F0 pin map" #endif -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_PINMAP_H */ - +#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_pwr.h b/arch/arm/src/stm32f0l0/hardware/stm32_pwr.h similarity index 50% rename from arch/arm/src/stm32f0/chip/stm32f0_pwr.h rename to arch/arm/src/stm32f0l0/hardware/stm32_pwr.h index 609d6712a09..cd324484e3f 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_pwr.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32_pwr.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/chip/stm32f0_pwr.h + * arch/arm/src/stm32f0l0/hardware/stm32_pwr.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_PWR_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_PWR_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_PWR_H /************************************************************************************ * Included Files @@ -50,49 +50,49 @@ /* Register Offsets *****************************************************************/ -#define STM32F0_PWR_CR_OFFSET 0x0000 /* Power control register */ -#define STM32F0_PWR_CSR_OFFSET 0x0004 /* Power control/status register */ +#define STM32_PWR_CR_OFFSET 0x0000 /* Power control register */ +#define STM32_PWR_CSR_OFFSET 0x0004 /* Power control/status register */ /* Register Addresses ***************************************************************/ -#define STM32F0_PWR_CR (STM32F0_PWR_BASE+STM32F0_PWR_CR_OFFSET) -#define STM32F0_PWR_CSR (STM32F0_PWR_BASE+STM32F0_PWR_CSR_OFFSET) +#define STM32_PWR_CR (STM32_PWR_BASE + STM32_PWR_CR_OFFSET) +#define STM32_PWR_CSR (STM32_PWR_BASE + STM32_PWR_CSR_OFFSET) /* Register Bitfield Definitions ****************************************************/ /* Power control register */ -#define PWR_CR_LPDS (1 << 0) /* Bit 0: Low-Power Deepsleep/sleep; low power run */ -#define PWR_CR_PDDS (1 << 1) /* Bit 1: Power Down Deepsleep */ -#define PWR_CR_CWUF (1 << 2) /* Bit 2: Clear Wakeup Flag */ -#define PWR_CR_CSBF (1 << 3) /* Bit 3: Clear Standby Flag */ -#define PWR_CR_PVDE (1 << 4) /* Bit 4: Power Voltage Detector Enable */ -#define PWR_CR_PLS_SHIFT (5) /* Bits 7-5: PVD Level Selection */ -#define PWR_CR_PLS_MASK (7 << PWR_CR_PLS_SHIFT) -# define PWR_CR_2p2V (0 << PWR_CR_PLS_SHIFT) /* 000: 2.2V */ -# define PWR_CR_2p3V (1 << PWR_CR_PLS_SHIFT) /* 001: 2.3V */ -# define PWR_CR_2p4V (2 << PWR_CR_PLS_SHIFT) /* 010: 2.4V */ -# define PWR_CR_2p5V (3 << PWR_CR_PLS_SHIFT) /* 011: 2.5V */ -# define PWR_CR_2p6V (4 << PWR_CR_PLS_SHIFT) /* 100: 2.6V */ -# define PWR_CR_2p7V (5 << PWR_CR_PLS_SHIFT) /* 101: 2.7V */ -# define PWR_CR_2p8V (6 << PWR_CR_PLS_SHIFT) /* 110: 2.8V */ -# define PWR_CR_2p9V (7 << PWR_CR_PLS_SHIFT) /* 111: 2.9V */ -#define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */ +#define PWR_CR_LPDS (1 << 0) /* Bit 0: Low-Power Deepsleep/sleep; low power run */ +#define PWR_CR_PDDS (1 << 1) /* Bit 1: Power Down Deepsleep */ +#define PWR_CR_CWUF (1 << 2) /* Bit 2: Clear Wakeup Flag */ +#define PWR_CR_CSBF (1 << 3) /* Bit 3: Clear Standby Flag */ +#define PWR_CR_PVDE (1 << 4) /* Bit 4: Power Voltage Detector Enable */ +#define PWR_CR_PLS_SHIFT (5) /* Bits 7-5: PVD Level Selection */ +#define PWR_CR_PLS_MASK (7 << PWR_CR_PLS_SHIFT) +# define PWR_CR_2p2V (0 << PWR_CR_PLS_SHIFT) /* 000: 2.2V */ +# define PWR_CR_2p3V (1 << PWR_CR_PLS_SHIFT) /* 001: 2.3V */ +# define PWR_CR_2p4V (2 << PWR_CR_PLS_SHIFT) /* 010: 2.4V */ +# define PWR_CR_2p5V (3 << PWR_CR_PLS_SHIFT) /* 011: 2.5V */ +# define PWR_CR_2p6V (4 << PWR_CR_PLS_SHIFT) /* 100: 2.6V */ +# define PWR_CR_2p7V (5 << PWR_CR_PLS_SHIFT) /* 101: 2.7V */ +# define PWR_CR_2p8V (6 << PWR_CR_PLS_SHIFT) /* 110: 2.8V */ +# define PWR_CR_2p9V (7 << PWR_CR_PLS_SHIFT) /* 111: 2.9V */ +#define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */ /* Power control/status register */ -#define PWR_CSR_WUF (1 << 0) /* Bit 0: Wakeup Flag */ -#define PWR_CSR_SBF (1 << 1) /* Bit 1: Standby Flag */ -#define PWR_CSR_PVDO (1 << 2) /* Bit 2: PVD Output */ -#define PWR_CSR_VREFINTRDY (1 << 3) /* Bit 3: Internal voltage reference (VREFINT) ready flag */ -#define PWR_CSR_EWUP1 (1 << 8) /* Bit 8: Enable WKUP1 pin */ -#define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */ -#define PWR_CSR_EWUP3 (1 << 10) /* Bit 10: Enable WKUP3 pin */ -#define PWR_CSR_EWUP4 (1 << 11) /* Bit 11: Enable WKUP4 pin */ -#define PWR_CSR_EWUP5 (1 << 12) /* Bit 12: Enable WKUP5 pin */ -#define PWR_CSR_EWUP6 (1 << 13) /* Bit 13: Enable WKUP6 pin */ -#define PWR_CSR_EWUP7 (1 << 14) /* Bit 14: Enable WKUP7 pin */ -#define PWR_CSR_EWUP8 (1 << 15) /* Bit 15: Enable WKUP8 pin */ +#define PWR_CSR_WUF (1 << 0) /* Bit 0: Wakeup Flag */ +#define PWR_CSR_SBF (1 << 1) /* Bit 1: Standby Flag */ +#define PWR_CSR_PVDO (1 << 2) /* Bit 2: PVD Output */ +#define PWR_CSR_VREFINTRDY (1 << 3) /* Bit 3: Internal voltage reference (VREFINT) ready flag */ +#define PWR_CSR_EWUP1 (1 << 8) /* Bit 8: Enable WKUP1 pin */ +#define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */ +#define PWR_CSR_EWUP3 (1 << 10) /* Bit 10: Enable WKUP3 pin */ +#define PWR_CSR_EWUP4 (1 << 11) /* Bit 11: Enable WKUP4 pin */ +#define PWR_CSR_EWUP5 (1 << 12) /* Bit 12: Enable WKUP5 pin */ +#define PWR_CSR_EWUP6 (1 << 13) /* Bit 13: Enable WKUP6 pin */ +#define PWR_CSR_EWUP7 (1 << 14) /* Bit 14: Enable WKUP7 pin */ +#define PWR_CSR_EWUP8 (1 << 15) /* Bit 15: Enable WKUP8 pin */ -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_PWR_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_rcc.h b/arch/arm/src/stm32f0l0/hardware/stm32_rcc.h new file mode 100644 index 00000000000..3cc13769036 --- /dev/null +++ b/arch/arm/src/stm32f0l0/hardware/stm32_rcc.h @@ -0,0 +1,54 @@ +/************************************************************************************ + * arch/arm/src/stm32f0l0/hardware/stm32_rcc.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RCC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_STM32F0L0_STM32F05X) || defined(CONFIG_STM32F0L0_STM32F07X) || \ + defined(CONFIG_STM32F0L0_STM32F09X) +# include "hardware/stm32f0_rcc.h" +#else +# error "Unsupported STM32 RCC" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RCC_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_rtcc.h b/arch/arm/src/stm32f0l0/hardware/stm32_rtcc.h similarity index 82% rename from arch/arm/src/stm32f0/chip/stm32f0_rtcc.h rename to arch/arm/src/stm32f0l0/hardware/stm32_rtcc.h index a8879ac0d4b..d40da9470fb 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_rtcc.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32_rtcc.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/chip/stm32f0_rtcc.h.h + * arch/arm/src/stm32f0l0/hardware/stm32_rtcc.h.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_RTCC_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_RTCC_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RTCC_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RTCC_H /************************************************************************************ * Pre-processor Definitions @@ -43,57 +43,57 @@ /* Register Offsets *****************************************************************/ -#define STM32F0_RTC_TR_OFFSET 0x0000 /* RTC time register */ -#define STM32F0_RTC_DR_OFFSET 0x0004 /* RTC date register */ -#define STM32F0_RTC_CR_OFFSET 0x0008 /* RTC control register */ -#define STM32F0_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ -#define STM32F0_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ -#define STM32F0_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ -#define STM32F0_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ -#define STM32F0_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ -#define STM32F0_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ -#define STM32F0_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ -#define STM32F0_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ -#define STM32F0_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ -#define STM32F0_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ -#define STM32F0_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ -#define STM32F0_RTC_TAFCR_OFFSET 0x0040 /* RTC tamper and alternate function configuration register */ -#define STM32F0_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ +#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */ +#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */ +#define STM32_RTC_CR_OFFSET 0x0008 /* RTC control register */ +#define STM32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ +#define STM32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ +#define STM32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ +#define STM32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ +#define STM32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ +#define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ +#define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ +#define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ +#define STM32_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ +#define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ +#define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ +#define STM32_RTC_TAFCR_OFFSET 0x0040 /* RTC tamper and alternate function configuration register */ +#define STM32_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ -#define STM32F0_RTC_BKR_OFFSET(n) (0x0050+((n)<<2)) -#define STM32F0_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */ -#define STM32F0_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */ -#define STM32F0_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */ -#define STM32F0_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */ -#define STM32F0_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */ +#define STM32_RTC_BKR_OFFSET(n) (0x0050 + ((n) << 2)) +#define STM32_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */ +#define STM32_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */ +#define STM32_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */ +#define STM32_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */ +#define STM32_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */ /* Register Addresses ***************************************************************/ -#define STM32F0_RTC_TR (STM32F0_RTC_BASE+STM32F0_RTC_TR_OFFSET) -#define STM32F0_RTC_DR (STM32F0_RTC_BASE+STM32F0_RTC_DR_OFFSET) -#define STM32F0_RTC_CR (STM32F0_RTC_BASE+STM32F0_RTC_CR_OFFSET) -#define STM32F0_RTC_ISR (STM32F0_RTC_BASE+STM32F0_RTC_ISR_OFFSET) -#define STM32F0_RTC_PRER (STM32F0_RTC_BASE+STM32F0_RTC_PRER_OFFSET) -#define STM32F0_RTC_WUTR (STM32F0_RTC_BASE+STM32F0_RTC_WUTR_OFFSET) -#define STM32F0_RTC_ALRMAR (STM32F0_RTC_BASE+STM32F0_RTC_ALRMAR_OFFSET) -#define STM32F0_RTC_WPR (STM32F0_RTC_BASE+STM32F0_RTC_WPR_OFFSET) -#define STM32F0_RTC_SSR (STM32F0_RTC_BASE+STM32F0_RTC_SSR_OFFSET) -#define STM32F0_RTC_SHIFTR (STM32F0_RTC_BASE+STM32F0_RTC_SHIFTR_OFFSET) -#define STM32F0_RTC_TSTR (STM32F0_RTC_BASE+STM32F0_RTC_TSTR_OFFSET) -#define STM32F0_RTC_TSDR (STM32F0_RTC_BASE+STM32F0_RTC_TSDR_OFFSET) -#define STM32F0_RTC_TSSSR (STM32F0_RTC_BASE+STM32F0_RTC_TSSSR_OFFSET) -#define STM32F0_RTC_CALR (STM32F0_RTC_BASE+STM32F0_RTC_CALR_OFFSET) -#define STM32F0_RTC_TAFCR (STM32F0_RTC_BASE+STM32F0_RTC_TAFCR_OFFSET) -#define STM32F0_RTC_ALRMASSR (STM32F0_RTC_BASE+STM32F0_RTC_ALRMASSR_OFFSET) +#define STM32_RTC_TR (STM32_RTC_BASE + STM32_RTC_TR_OFFSET) +#define STM32_RTC_DR (STM32_RTC_BASE + STM32_RTC_DR_OFFSET) +#define STM32_RTC_CR (STM32_RTC_BASE + STM32_RTC_CR_OFFSET) +#define STM32_RTC_ISR (STM32_RTC_BASE + STM32_RTC_ISR_OFFSET) +#define STM32_RTC_PRER (STM32_RTC_BASE + STM32_RTC_PRER_OFFSET) +#define STM32_RTC_WUTR (STM32_RTC_BASE + STM32_RTC_WUTR_OFFSET) +#define STM32_RTC_ALRMAR (STM32_RTC_BASE + STM32_RTC_ALRMAR_OFFSET) +#define STM32_RTC_WPR (STM32_RTC_BASE + STM32_RTC_WPR_OFFSET) +#define STM32_RTC_SSR (STM32_RTC_BASE + STM32_RTC_SSR_OFFSET) +#define STM32_RTC_SHIFTR (STM32_RTC_BASE + STM32_RTC_SHIFTR_OFFSET) +#define STM32_RTC_TSTR (STM32_RTC_BASE + STM32_RTC_TSTR_OFFSET) +#define STM32_RTC_TSDR (STM32_RTC_BASE + STM32_RTC_TSDR_OFFSET) +#define STM32_RTC_TSSSR (STM32_RTC_BASE + STM32_RTC_TSSSR_OFFSET) +#define STM32_RTC_CALR (STM32_RTC_BASE + STM32_RTC_CALR_OFFSET) +#define STM32_RTC_TAFCR (STM32_RTC_BASE + STM32_RTC_TAFCR_OFFSET) +#define STM32_RTC_ALRMASSR (STM32_RTC_BASE + STM32_RTC_ALRMASSR_OFFSET) -#define STM32F0_RTC_BKR(n) (STM32F0_RTC_BASE+STM32F0_RTC_BKR_OFFSET(n)) -#define STM32F0_RTC_BK0R (STM32F0_RTC_BASE+STM32F0_RTC_BK0R_OFFSET) -#define STM32F0_RTC_BK1R (STM32F0_RTC_BASE+STM32F0_RTC_BK1R_OFFSET) -#define STM32F0_RTC_BK2R (STM32F0_RTC_BASE+STM32F0_RTC_BK2R_OFFSET) -#define STM32F0_RTC_BK3R (STM32F0_RTC_BASE+STM32F0_RTC_BK3R_OFFSET) -#define STM32F0_RTC_BK4R (STM32F0_RTC_BASE+STM32F0_RTC_BK4R_OFFSET) +#define STM32_RTC_BKR(n) (STM32_RTC_BASE + STM32_RTC_BKR_OFFSET(n)) +#define STM32_RTC_BK0R (STM32_RTC_BASE + STM32_RTC_BK0R_OFFSET) +#define STM32_RTC_BK1R (STM32_RTC_BASE + STM32_RTC_BK1R_OFFSET) +#define STM32_RTC_BK2R (STM32_RTC_BASE + STM32_RTC_BK2R_OFFSET) +#define STM32_RTC_BK3R (STM32_RTC_BASE + STM32_RTC_BK3R_OFFSET) +#define STM32_RTC_BK4R (STM32_RTC_BASE + STM32_RTC_BK4R_OFFSET) -#define STM32F0_RTC_BKCOUNT 5 +#define STM32_RTC_BKCOUNT 5 /* Register Bitfield Definitions ****************************************************/ @@ -321,4 +321,4 @@ #define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */ #define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_RTCC_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RTCC_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_spi.h b/arch/arm/src/stm32f0l0/hardware/stm32_spi.h similarity index 66% rename from arch/arm/src/stm32f0/chip/stm32f0_spi.h rename to arch/arm/src/stm32f0l0/hardware/stm32_spi.h index 87ab0ed2581..4f78fc1dcb1 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_spi.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32_spi.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/chip/stm32f0_spi.h + * arch/arm/src/stm32f0l0/hardware/stm32_spi.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_SPI_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_SPI_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SPI_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SPI_H /************************************************************************************ * Included Files @@ -49,90 +49,90 @@ /* Maximum allowed speed as per data sheet for all SPIs (both pclk1 and pclk2)*/ -#define STM32F0_SPI_CLK_MAX 50000000UL +#define STM32_SPI_CLK_MAX 50000000UL /* Register Offsets *****************************************************************/ -#define STM32F0_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32F0_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32F0_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32F0_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32F0_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32F0_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32F0_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ -#define STM32F0_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */ -#define STM32F0_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */ +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */ +#define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */ /* Register Addresses ***************************************************************/ -#if STM32F0_NSPI > 0 -# define STM32F0_SPI1_CR1 (STM32F0_SPI1_BASE+STM32F0_SPI_CR1_OFFSET) -# define STM32F0_SPI1_CR2 (STM32F0_SPI1_BASE+STM32F0_SPI_CR2_OFFSET) -# define STM32F0_SPI1_SR (STM32F0_SPI1_BASE+STM32F0_SPI_SR_OFFSET) -# define STM32F0_SPI1_DR (STM32F0_SPI1_BASE+STM32F0_SPI_DR_OFFSET) -# define STM32F0_SPI1_CRCPR (STM32F0_SPI1_BASE+STM32F0_SPI_CRCPR_OFFSET) -# define STM32F0_SPI1_RXCRCR (STM32F0_SPI1_BASE+STM32F0_SPI_RXCRCR_OFFSET) -# define STM32F0_SPI1_TXCRCR (STM32F0_SPI1_BASE+STM32F0_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 0 +# define STM32_SPI1_CR1 (STM32_SPI1_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI1_CR2 (STM32_SPI1_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI1_SR (STM32_SPI1_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI1_DR (STM32_SPI1_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI1_CRCPR (STM32_SPI1_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32F0_NSPI > 1 -# define STM32F0_SPI2_CR1 (STM32F0_SPI2_BASE+STM32F0_SPI_CR1_OFFSET) -# define STM32F0_SPI2_CR2 (STM32F0_SPI2_BASE+STM32F0_SPI_CR2_OFFSET) -# define STM32F0_SPI2_SR (STM32F0_SPI2_BASE+STM32F0_SPI_SR_OFFSET) -# define STM32F0_SPI2_DR (STM32F0_SPI2_BASE+STM32F0_SPI_DR_OFFSET) -# define STM32F0_SPI2_CRCPR (STM32F0_SPI2_BASE+STM32F0_SPI_CRCPR_OFFSET) -# define STM32F0_SPI2_RXCRCR (STM32F0_SPI2_BASE+STM32F0_SPI_RXCRCR_OFFSET) -# define STM32F0_SPI2_TXCRCR (STM32F0_SPI2_BASE+STM32F0_SPI_TXCRCR_OFFSET) -# define STM32F0_SPI2_I2SCFGR (STM32F0_SPI2_BASE+STM32F0_SPI_I2SCFGR_OFFSET) -# define STM32F0_SPI2_I2SPR (STM32F0_SPI2_BASE+STM32F0_SPI_I2SPR_OFFSET) +#if STM32_NSPI > 1 +# define STM32_SPI2_CR1 (STM32_SPI2_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI2_CR2 (STM32_SPI2_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI2_SR (STM32_SPI2_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI2_DR (STM32_SPI2_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI2_CRCPR (STM32_SPI2_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE + STM32_SPI_TXCRCR_OFFSET) +# define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE + STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI2_I2SPR (STM32_SPI2_BASE + STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F0_NSPI > 2 -# define STM32F0_SPI3_CR1 (STM32F0_SPI3_BASE+STM32F0_SPI_CR1_OFFSET) -# define STM32F0_SPI3_CR2 (STM32F0_SPI3_BASE+STM32F0_SPI_CR2_OFFSET) -# define STM32F0_SPI3_SR (STM32F0_SPI3_BASE+STM32F0_SPI_SR_OFFSET) -# define STM32F0_SPI3_DR (STM32F0_SPI3_BASE+STM32F0_SPI_DR_OFFSET) -# define STM32F0_SPI3_CRCPR (STM32F0_SPI3_BASE+STM32F0_SPI_CRCPR_OFFSET) -# define STM32F0_SPI3_RXCRCR (STM32F0_SPI3_BASE+STM32F0_SPI_RXCRCR_OFFSET) -# define STM32F0_SPI3_TXCRCR (STM32F0_SPI3_BASE+STM32F0_SPI_TXCRCR_OFFSET) -# define STM32F0_SPI3_I2SCFGR (STM32F0_SPI3_BASE+STM32F0_SPI_I2SCFGR_OFFSET) -# define STM32F0_SPI3_I2SPR (STM32F0_SPI3_BASE+STM32F0_SPI_I2SPR_OFFSET) +#if STM32_NSPI > 2 +# define STM32_SPI3_CR1 (STM32_SPI3_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI3_CR2 (STM32_SPI3_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI3_SR (STM32_SPI3_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI3_DR (STM32_SPI3_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI3_CRCPR (STM32_SPI3_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE + STM32_SPI_TXCRCR_OFFSET) +# define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE + STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI3_I2SPR (STM32_SPI3_BASE + STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F0_NSPI > 3 -# define STM32F0_SPI4_CR1 (STM32F0_SPI4_BASE+STM32F0_SPI_CR1_OFFSET) -# define STM32F0_SPI4_CR2 (STM32F0_SPI4_BASE+STM32F0_SPI_CR2_OFFSET) -# define STM32F0_SPI4_SR (STM32F0_SPI4_BASE+STM32F0_SPI_SR_OFFSET) -# define STM32F0_SPI4_DR (STM32F0_SPI4_BASE+STM32F0_SPI_DR_OFFSET) -# define STM32F0_SPI4_CRCPR (STM32F0_SPI4_BASE+STM32F0_SPI_CRCPR_OFFSET) -# define STM32F0_SPI4_RXCRCR (STM32F0_SPI4_BASE+STM32F0_SPI_RXCRCR_OFFSET) -# define STM32F0_SPI4_TXCRCR (STM32F0_SPI4_BASE+STM32F0_SPI_TXCRCR_OFFSET) -# define STM32F0_SPI4_I2SCFGR (STM32F0_SPI4_BASE+STM32F0_SPI_I2SCFGR_OFFSET) -# define STM32F0_SPI4_I2SPR (STM32F0_SPI4_BASE+STM32F0_SPI_I2SPR_OFFSET) +#if STM32_NSPI > 3 +# define STM32_SPI4_CR1 (STM32_SPI4_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI4_CR2 (STM32_SPI4_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI4_SR (STM32_SPI4_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI4_DR (STM32_SPI4_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI4_CRCPR (STM32_SPI4_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI4_RXCRCR (STM32_SPI4_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI4_TXCRCR (STM32_SPI4_BASE + STM32_SPI_TXCRCR_OFFSET) +# define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE + STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI4_I2SPR (STM32_SPI4_BASE + STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F0_NSPI > 4 -# define STM32F0_SPI5_CR1 (STM32F0_SPI5_BASE+STM32F0_SPI_CR1_OFFSET) -# define STM32F0_SPI5_CR2 (STM32F0_SPI5_BASE+STM32F0_SPI_CR2_OFFSET) -# define STM32F0_SPI5_SR (STM32F0_SPI5_BASE+STM32F0_SPI_SR_OFFSET) -# define STM32F0_SPI5_DR (STM32F0_SPI5_BASE+STM32F0_SPI_DR_OFFSET) -# define STM32F0_SPI5_CRCPR (STM32F0_SPI5_BASE+STM32F0_SPI_CRCPR_OFFSET) -# define STM32F0_SPI5_RXCRCR (STM32F0_SPI5_BASE+STM32F0_SPI_RXCRCR_OFFSET) -# define STM32F0_SPI5_TXCRCR (STM32F0_SPI5_BASE+STM32F0_SPI_TXCRCR_OFFSET) -# define STM32F0_SPI5_I2SCFGR (STM32F0_SPI5_BASE+STM32F0_SPI_I2SCFGR_OFFSET) -# define STM32F0_SPI5_I2SPR (STM32F0_SPI5_BASE+STM32F0_SPI_I2SPR_OFFSET) +#if STM32_NSPI > 4 +# define STM32_SPI5_CR1 (STM32_SPI5_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI5_CR2 (STM32_SPI5_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI5_SR (STM32_SPI5_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI5_DR (STM32_SPI5_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI5_CRCPR (STM32_SPI5_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI5_RXCRCR (STM32_SPI5_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI5_TXCRCR (STM32_SPI5_BASE + STM32_SPI_TXCRCR_OFFSET) +# define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE + STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI5_I2SPR (STM32_SPI5_BASE + STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F0_NSPI > 5 -# define STM32F0_SPI6_CR1 (STM32F0_SPI6_BASE+STM32F0_SPI_CR1_OFFSET) -# define STM32F0_SPI6_CR2 (STM32F0_SPI6_BASE+STM32F0_SPI_CR2_OFFSET) -# define STM32F0_SPI6_SR (STM32F0_SPI6_BASE+STM32F0_SPI_SR_OFFSET) -# define STM32F0_SPI6_DR (STM32F0_SPI6_BASE+STM32F0_SPI_DR_OFFSET) -# define STM32F0_SPI6_CRCPR (STM32F0_SPI6_BASE+STM32F0_SPI_CRCPR_OFFSET) -# define STM32F0_SPI6_RXCRCR (STM32F0_SPI6_BASE+STM32F0_SPI_RXCRCR_OFFSET) -# define STM32F0_SPI6_TXCRCR (STM32F0_SPI6_BASE+STM32F0_SPI_TXCRCR_OFFSET) -# define STM32F0_SPI6_I2SCFGR (STM32F0_SPI6_BASE+STM32F0_SPI_I2SCFGR_OFFSET) -# define STM32F0_SPI6_I2SPR (STM32F0_SPI6_BASE+STM32F0_SPI_I2SPR_OFFSET) +#if STM32_NSPI > 5 +# define STM32_SPI6_CR1 (STM32_SPI6_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI6_CR2 (STM32_SPI6_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI6_SR (STM32_SPI6_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI6_DR (STM32_SPI6_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI6_CRCPR (STM32_SPI6_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI6_RXCRCR (STM32_SPI6_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI6_TXCRCR (STM32_SPI6_BASE + STM32_SPI_TXCRCR_OFFSET) +# define STM32_SPI6_I2SCFGR (STM32_SPI6_BASE + STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI6_I2SPR (STM32_SPI6_BASE + STM32_SPI_I2SPR_OFFSET) #endif /* Register Bitfield Definitions ****************************************************/ @@ -249,4 +249,4 @@ #define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */ #define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */ -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_SPI_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SPI_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_syscfg.h b/arch/arm/src/stm32f0l0/hardware/stm32_syscfg.h new file mode 100644 index 00000000000..79ccf889988 --- /dev/null +++ b/arch/arm/src/stm32f0l0/hardware/stm32_syscfg.h @@ -0,0 +1,391 @@ +/**************************************************************************************************** + * arch/arm/src/stm32f0l0/hardware/stm32_syscfg.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SYSCFG_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SYSCFG_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +#define STM32_SYSCFG_CFGR1_OFFSET 0x0000 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x0018 /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_ITLINE0_OFFSET 0x0080 /* SYSCFG interrupt line 0 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE1_OFFSET 0x0084 /* SYSCFG interrupt line 1 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE2_OFFSET 0x0088 /* SYSCFG interrupt line 2 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE3_OFFSET 0x008c /* SYSCFG interrupt line 3 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE4_OFFSET 0x0090 /* SYSCFG interrupt line 4 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE5_OFFSET 0x0094 /* SYSCFG interrupt line 5 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE6_OFFSET 0x0098 /* SYSCFG interrupt line 6 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE7_OFFSET 0x009c /* SYSCFG interrupt line 7 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE8_OFFSET 0x00a0 /* SYSCFG interrupt line 8 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE9_OFFSET 0x00a4 /* SYSCFG interrupt line 9 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE10_OFFSET 0x00a8 /* SYSCFG interrupt line 10 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE11_OFFSET 0x00ac /* SYSCFG interrupt line 11 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE12_OFFSET 0x00b0 /* SYSCFG interrupt line 12 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE13_OFFSET 0x00b4 /* SYSCFG interrupt line 13 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE14_OFFSET 0x00b8 /* SYSCFG interrupt line 14 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE15_OFFSET 0x00bc /* SYSCFG interrupt line 15 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE16_OFFSET 0x00c0 /* SYSCFG interrupt line 16 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE17_OFFSET 0x00c4 /* SYSCFG interrupt line 17 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE18_OFFSET 0x00c8 /* SYSCFG interrupt line 18 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE19_OFFSET 0x00cc /* SYSCFG interrupt line 19 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE20_OFFSET 0x00d0 /* SYSCFG interrupt line 20 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE21_OFFSET 0x00d4 /* SYSCFG interrupt line 21 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE22_OFFSET 0x00d8 /* SYSCFG interrupt line 22 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE23_OFFSET 0x00dc /* SYSCFG interrupt line 23 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE24_OFFSET 0x00e0 /* SYSCFG interrupt line 24 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE25_OFFSET 0x00e4 /* SYSCFG interrupt line 25 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE26_OFFSET 0x00e8 /* SYSCFG interrupt line 26 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE27_OFFSET 0x00ec /* SYSCFG interrupt line 27 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE28_OFFSET 0x00f0 /* SYSCFG interrupt line 28 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE29_OFFSET 0x00f4 /* SYSCFG interrupt line 29 status register (STM32F09x) */ +#define STM32_SYSCFG_ITLINE30_OFFSET 0x00f8 /* SYSCFG interrupt line 30 status register (STM32F09x) */ + +/* Register Addresses *******************************************************************************/ + +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET) + +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR4_OFFSET) + +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR2_OFFSET) + +#define STM32_SYSCFG_ITLINE0 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE0_OFFSET) +#define STM32_SYSCFG_ITLINE1 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE1_OFFSET) +#define STM32_SYSCFG_ITLINE2 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE2_OFFSET) +#define STM32_SYSCFG_ITLINE3 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE3_OFFSET) +#define STM32_SYSCFG_ITLINE4 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE4_OFFSET) +#define STM32_SYSCFG_ITLINE5 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE5_OFFSET) +#define STM32_SYSCFG_ITLINE6 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE6_OFFSET) +#define STM32_SYSCFG_ITLINE7 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE7_OFFSET) +#define STM32_SYSCFG_ITLINE8 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE8_OFFSET) +#define STM32_SYSCFG_ITLINE9 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE9_OFFSET) +#define STM32_SYSCFG_ITLINE10 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE10_OFFSET) +#define STM32_SYSCFG_ITLINE11 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE11_OFFSET) +#define STM32_SYSCFG_ITLINE12 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE12_OFFSET) +#define STM32_SYSCFG_ITLINE13 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE13_OFFSET) +#define STM32_SYSCFG_ITLINE14 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE14_OFFSET) +#define STM32_SYSCFG_ITLINE15 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE15_OFFSET) +#define STM32_SYSCFG_ITLINE16 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE16_OFFSET) +#define STM32_SYSCFG_ITLINE17 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE17_OFFSET) +#define STM32_SYSCFG_ITLINE18 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE18_OFFSET) +#define STM32_SYSCFG_ITLINE19 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE19_OFFSET) +#define STM32_SYSCFG_ITLINE20 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE20_OFFSET) +#define STM32_SYSCFG_ITLINE21 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE21_OFFSET) +#define STM32_SYSCFG_ITLINE22 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE22_OFFSET) +#define STM32_SYSCFG_ITLINE23 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE23_OFFSET) +#define STM32_SYSCFG_ITLINE24 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE24_OFFSET) +#define STM32_SYSCFG_ITLINE25 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE25_OFFSET) +#define STM32_SYSCFG_ITLINE26 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE26_OFFSET) +#define STM32_SYSCFG_ITLINE27 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE27_OFFSET) +#define STM32_SYSCFG_ITLINE28 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE28_OFFSET) +#define STM32_SYSCFG_ITLINE29 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE29_OFFSET) +#define STM32_SYSCFG_ITLINE30 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE30_OFFSET) + +/* Register Bitfield Definitions ********************************************************************/ + +/* SYSCFG memory remap register */ + +#define SYSCFG_CFGR1_MEMMODE_SHIFT (0) /* Bits 1:0 MEM_MODE: Memory mapping selection */ +#define SYSCFG_CFGR1_MEMMODE_MASK (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) +# define SYSCFG_CFGR1_MEMMODE_FLASH (0 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 00: Main Flash at 0x00000000 */ +# define SYSCFG_CFGR1_MEMMODE_SYSTEM (1 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 01: System Flash at 0x00000000 */ +# define SYSCFG_CFGR1_MEMMODE_SRAM (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 11: Embedded SRAM at 0x00000000 */ +#define SYSCFG_CFGR1_PA11_PA12_RMP (1 << 4) /* Bit 4: PA11 and PA12 remapping bit for small packages */ +#define SYSCFG_CFGR1_IRMOD_SHIFT (6) /* Bits 6-7: IR Modulation Envelope signal selection */ +#define SYSCFG_CFGR1_IRMOD_MASK (3 << SYSCFG_CFGR1_IRMOD_SHIFT) +# define SYSCFG_CFGR1_IRMOD_TIM16 (0 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 00: TIM16 selected */ +# define SYSCFG_CFGR1_IRMOD_USART1 (1 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 01: USART1 selected */ +# define SYSCFG_CFGR1_IRMOD_USART4 (2 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 10: USART1 selected */ +#define SYSCFG_CFGR1_ADC_DMARMP (1 << 8) /* Bit 8: ADC DMA remapping bit. Only STM32F03x/F04x/F05x/F07x */ +#define SYSCFG_CFGR1_USART1_TXDMARMP (1 << 9) /* Bit 9: USART1_TX_DMA request remapping bit. Only STM32F03x/F04x/F05x/F07x */ +#define SYSCFG_CFGR1_USART1_RXDMARMP (1 << 10) /* Bit 10: USART1_TX_DMA request remapping bit. Only STM32F03x/F04x/F05x/F07x */ +#define SYSCFG_CFGR1_TIM16_DMARMP (1 << 11) /* Bit 11: TIM16 DMA request remapping bit */ +#define SYSCFG_CFGR1_TIM17_DMARMP (1 << 12) /* Bit 12: TIM17 DMA request remapping bit */ +#define SYSCFG_CFGR1_TIM16_DMARMP2 (1 << 13) /* Bit 13: TIM16 alternate DMA request remapping bit */ +#define SYSCFG_CFGR1_TIM17_DMARMP2 (1 << 14) /* Bit 14: TIM17 alternate DMA request remapping bit */ +#define SYSCFG_CFGR1_I2C_PBXFMP_SHIFT (16) /* Bits 16-19: Fast Mode Plus (FM+) driving capability */ +#define SYSCFG_CFGR1_I2C_PBXFMP_MASK (15 << SYSCFG_CFGR1_I2C_PBXFMP_SHIFT) +#define SYSCFG_CFGR1_I2C1_FMP (1 << 20) /* Bit 20: I2C1 fast mode Plus driving capability */ +#define SYSCFG_CFGR1_I2C2_FMP (1 << 21) /* Bit 21: I2C2 fast mode Plus driving capability */ +#define SYSCFG_CFGR1_I2C_PAXFMP_SHIFT (22) /* Bits 22-23: Fast Mode Plus (FM+) driving capability */ +#define SYSCFG_CFGR1_I2C_PAXFMP_MASK (3 << SYSCFG_CFGR1_I2C_PAXFMP_SHIFT) +#define SYSCFG_CFGR1_SPI2_DMARMP (1 << 24) /* Bit 24: SPI2 DMA request remapping bit. */ +#define SYSCFG_CFGR1_USART2_DMARMP (1 << 25) /* Bit 25: USART2 DMA request remapping bit. */ +#define SYSCFG_CFGR1_USART3_DMARMP (1 << 26) /* Bit 26: USART3 DMA request remapping bit. */ +#define SYSCFG_CFGR1_I2C1_DMARMP (1 << 27) /* Bit 27: I2C1 DMA request remapping bit. */ +#define SYSCFG_CFGR1_TIM1_DMARMP (1 << 28) /* Bit 28: TIM1 DMA request remapping bit. */ +#define SYSCFG_CFGR1_TIM2_DMARMP (1 << 29) /* Bit 29: TIM2 DMA request remapping bit. */ +#define SYSCFG_CFGR1_TIM3_DMARMP (1 << 30) /* Bit 30: TIM3 DMA request remapping bit. */ + +/* SYSCFG external interrupt configuration register 1-4 */ + +#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */ +#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */ +#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */ +#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */ +#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */ +#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[x] pin */ + +#define SYSCFG_EXTICR_PORT_MASK (15) +#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2) +#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g))) + +#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT) +#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT) +#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT) +#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT) + +#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT) +#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT) +#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT) +#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT) + +#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT) +#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT) +#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT) +#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT) + +#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT) +#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT) +#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT) +#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT) + +/* SYSCFG configuration register 2 */ + +#define SYSCFG_CFGR2_LOCKUPLOCK (1 << 0) /* Bit 0: Cortex-M0 Hardfault output bit enable */ +#define SYSCFG_CFGR2_SRAM_PARITYLOCK (1 << 1) /* Bit 1: RAM parity lock */ +#define SYSCFG_CFGR2_PVDLOCK (1 << 2) /* Bit 2: PVD lock enable */ +#define SYSCFG_CFGR2_SRAM_PEF (1 << 8) /* Bit 8: SRAM parity error */ + +/* SYSCFG interrupt line 0 status register */ + +#define SYSCFG_ITLINE0_WWDG (1 << 0) /* Bit 0: Window Watchdog interrupt pending flag */ + +/* SYSCFG interrupt line 1 status register */ + +#define SYSCFG_ITLINE1_PVDOUT (1 << 0) /* Bit 0: PVD supply monitoring interrupt request pending (EXTI line 16) */ +#define SYSCFG_ITLINE1_VDDIO2 (1 << 0) /* Bit 1: VDDIO2 supply monitoring interrupt request pending (EXTI line 31) */ + +/* SYSCFG interrupt line 2 status register */ + +#define SYSCFG_ITLINE2_RTC_WAKEUP (1 << 0) /* Bit 0: RTC Wake Up interrupt request pending (EXTI line 20) */ +#define SYSCFG_ITLINE2_RTC_TSTAMP (1 << 1) /* Bit 1: RTC Tamper and TimeStamp interrupt request pending (EXTI line 19) */ +#define SYSCFG_ITLINE2_RTC_ALRA (1 << 2) /* Bit 2: RTC Alarm interrupt request pending (EXTI line 17) */ + +/* SYSCFG interrupt line 3 status register */ + +#define SYSCFG_ITLINE3_FLASH_ITF (1 << 0) /* Bit 0: Flash interface interrupt request pending */ + +/* SYSCFG interrupt line 4 status register */ + +#define SYSCFG_ITLINE4_RCC (1 << 0) /* Bit 0: Reset and clock control interrupt request pending */ +#define SYSCFG_ITLINE4_CRS (1 << 1) /* Bit 1: Clock recovery system interrupt request pending */ + +/* SYSCFG interrupt line 5 status register */ + +#define SYSCFG_ITLINE5_EXTI0 (1 << 0) /* Bit 0: EXTI line 0 interrupt request pending */ +#define SYSCFG_ITLINE5_EXTI1 (1 << 1) /* Bit 1: EXTI line 1 interrupt request pending */ + +/* SYSCFG interrupt line 6 status register */ + +#define SYSCFG_ITLINE6_EXTI2 (1 << 0) /* Bit 0: EXTI line 2 interrupt request pending */ +#define SYSCFG_ITLINE6_EXTI3 (1 << 1) /* Bit 1: EXTI line 3 interrupt request pending */ + +/* SYSCFG interrupt line 7 status register */ + +#define SYSCFG_ITLINE7_EXTI4 (1 << 0) /* Bit 0: EXTI line 4 interrupt request pending */ +#define SYSCFG_ITLINE7_EXTI5 (1 << 1) /* Bit 1: EXTI line 5 interrupt request pending */ +#define SYSCFG_ITLINE7_EXTI6 (1 << 2) /* Bit 2: EXTI line 6 interrupt request pending */ +#define SYSCFG_ITLINE7_EXTI7 (1 << 3) /* Bit 3: EXTI line 7 interrupt request pending */ +#define SYSCFG_ITLINE7_EXTI8 (1 << 4) /* Bit 4: EXTI line 8 interrupt request pending */ +#define SYSCFG_ITLINE7_EXTI9 (1 << 5) /* Bit 5: EXTI line 9 interrupt request pending */ +#define SYSCFG_ITLINE7_EXTI10 (1 << 6) /* Bit 6: EXTI line 10 interrupt request pending */ +#define SYSCFG_ITLINE7_EXTI11 (1 << 7) /* Bit 7: EXTI line 11 interrupt request pending */ +#define SYSCFG_ITLINE7_EXTI12 (1 << 8) /* Bit 8: EXTI line 12 interrupt request pending */ +#define SYSCFG_ITLINE7_EXTI13 (1 << 9) /* Bit 9: EXTI line 13 interrupt request pending */ +#define SYSCFG_ITLINE7_EXTI14 (1 << 10) /* Bit 10: EXTI line 14 interrupt request pending */ +#define SYSCFG_ITLINE7_EXTI15 (1 << 11) /* Bit 11: EXTI line 15 interrupt request pending */ + +/* SYSCFG interrupt line 8 status register */ + +#define SYSCFG_ITLINE8_TCS_MCE (1 << 0) /* Bit 0: Touch sensing controller max count error interrupt request pending */ +#define SYSCFG_ITLINE8_TCS_EOA (1 << 1) /* Bit 1: Touch sensing controller end of acquisition interrupt request pending */ + +/* SYSCFG interrupt line 9 status register */ + +#define SYSCFG_ITLINE9_DMA1_CH1 (1 << 0) /* Bit 0: DMA1 channel 1 interrupt request pending */ + +/* SYSCFG interrupt line 10 status register */ + +#define SYSCFG_ITLINE10_DMA1_CH2 (1 << 0) /* Bit 0: DMA1 channel 2 interrupt request pending */ +#define SYSCFG_ITLINE10_DMA1_CH3 (1 << 1) /* Bit 1: DMA1 channel 3 interrupt request pending */ +#define SYSCFG_ITLINE10_DMA2_CH1 (1 << 2) /* Bit 0: DMA2 channel 1 interrupt request pending */ +#define SYSCFG_ITLINE10_DMA2_CH2 (1 << 3) /* Bit 1: DMA2 channel 2 interrupt request pending */ + +/* SYSCFG interrupt line 11 status register */ + +#define SYSCFG_ITLINE11_DMA1_CH4 (1 << 0) /* Bit 0: DMA1 channel 4 interrupt request pending */ +#define SYSCFG_ITLINE11_DMA1_CH5 (1 << 1) /* Bit 1: DMA1 channel 5 interrupt request pending */ +#define SYSCFG_ITLINE11_DMA1_CH6 (1 << 2) /* Bit 2: DMA1 channel 6 interrupt request pending */ +#define SYSCFG_ITLINE11_DMA1_CH7 (1 << 3) /* Bit 3: DMA1 channel 7 interrupt request pending */ +#define SYSCFG_ITLINE11_DMA2_CH3 (1 << 4) /* Bit 4: DMA2 channel 3 interrupt request pending */ +#define SYSCFG_ITLINE11_DMA2_CH4 (1 << 5) /* Bit 5: DMA2 channel 4 interrupt request pending */ +#define SYSCFG_ITLINE11_DMA2_CH5 (1 << 6) /* Bit 6: DMA2 channel 5 interrupt request pending */ + +/* SYSCFG interrupt line 12 status register */ + +#define SYSCFG_ITLINE12_ADC (1 << 0) /* Bit 0: ADC interrupt request pending */ +#define SYSCFG_ITLINE12_COMP1 (1 << 1) /* Bit 1: Comparator 1 interrupt request pending */ +#define SYSCFG_ITLINE12_COMP2 (1 << 2) /* Bit 2: Comparator 2 interrupt request pending */ + +/* SYSCFG interrupt line 13 status register */ + +#define SYSCFG_ITLINE13_TIM1_CCU (1 << 0) /* Bit 0: TIM1 commutation interrupt request pending */ +#define SYSCFG_ITLINE13_TIM1_TRG (1 << 1) /* Bit 1: TIM1 triggerinterrupt request pending */ +#define SYSCFG_ITLINE13_TIM1_UPD (1 << 2) /* Bit 2: TIM1 update interrupt request pending */ +#define SYSCFG_ITLINE13_TIM1_BRK (1 << 3) /* Bit 3: TIM1 break interrupt request pending */ + +/* SYSCFG interrupt line 14 status register */ + +#define SYSCFG_ITLINE14_TIM1_CC (1 << 0) /* Bit 0: TIM1 capture compare interrupt request pending */ + +/* SYSCFG interrupt line 15 status register */ + +#define SYSCFG_ITLINE15_TIM2 (1 << 0) /* Bit 0: Timer 2 interrupt request pending */ + +/* SYSCFG interrupt line 16 status register */ + +#define SYSCFG_ITLINE16_TIM3 (1 << 0) /* Bit 0: Timer 3 interrupt request pending */ + +/* SYSCFG interrupt line 17 status register */ + +#define SYSCFG_ITLINE17_TIM6 (1 << 0) /* Bit 0: Timer 6 interrupt request pending */ +#define SYSCFG_ITLINE17_DAC (1 << 1) /* Bit 1: DAC underrun interrupt request pending */ + +/* SYSCFG interrupt line 18 status register */ + +#define SYSCFG_ITLINE18_TIM7 (1 << 0) /* Bit 0: Timer 7 interrupt request pending */ + +/* SYSCFG interrupt line 19 status register */ + +#define SYSCFG_ITLINE19_TIM14 (1 << 0) /* Bit 0: Timer 14 interrupt request pending */ + +/* SYSCFG interrupt line 20 status register */ + +#define SYSCFG_ITLINE20_TIM15 (1 << 0) /* Bit 0: Timer 15 interrupt request pending */ + +/* SYSCFG interrupt line 21 status register */ + +#define SYSCFG_ITLINE21_TIM16 (1 << 0) /* Bit 0: Timer 16 interrupt request pending */ + +/* SYSCFG interrupt line 22 status register */ + +#define SYSCFG_ITLINE22_TIM17 (1 << 0) /* Bit 0: Timer 17 interrupt request pending */ + +/* SYSCFG interrupt line 23 status register */ + +#define SYSCFG_ITLINE23_I2C1 (1 << 0) /* Bit 0: I2C1 interrupt request pending, combined with EXTI line 23 */ + +/* SYSCFG interrupt line 24 status register */ + +#define SYSCFG_ITLINE24_I2C2 (1 << 0) /* Bit 0: I2C2 interrupt request pending */ + +/* SYSCFG interrupt line 25 status register */ + +#define SYSCFG_ITLINE25_SPI1 (1 << 0) /* Bit 0: SPI1 interrupt request pending */ + +/* SYSCFG interrupt line 26 status register */ + +#define SYSCFG_ITLINE26_SPI2 (1 << 0) /* Bit 0: SPI2 interrupt request pending */ + +/* SYSCFG interrupt line 27 status register */ + +#define SYSCFG_ITLINE27_USART1 (1 << 0) /* Bit 0: USART1 interrupt request pending */ + +/* SYSCFG interrupt line 28 status register */ + +#define SYSCFG_ITLINE28_USART2 (1 << 0) /* Bit 0: USART2 interrupt request pending */ + +/* SYSCFG interrupt line 29 status register */ + +#define SYSCFG_ITLINE29_USART3 (1 << 0) /* Bit 0: USART3 interrupt request pending */ +#define SYSCFG_ITLINE29_USART4 (1 << 1) /* Bit 1: USART4 interrupt request pending */ +#define SYSCFG_ITLINE29_USART5 (1 << 2) /* Bit 2: USART5 interrupt request pending */ +#define SYSCFG_ITLINE29_USART6 (1 << 3) /* Bit 3: USART6 interrupt request pending */ +#define SYSCFG_ITLINE29_USART7 (1 << 4) /* Bit 4: USART7 interrupt request pending */ +#define SYSCFG_ITLINE29_USART8 (1 << 5) /* Bit 5: USART8 interrupt request pending */ + +/* SYSCFG interrupt line 30 status register */ + +#define SYSCFG_ITLINE30_CEC (1 << 0) /* Bit 0: CEC interrupt request pending, combined with EXTI line 27 */ +#define SYSCFG_ITLINE30_CAN (1 << 1) /* Bit 1: CAN interrupt request pending */ + +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SYSCFG_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_tim.h b/arch/arm/src/stm32f0l0/hardware/stm32_tim.h similarity index 92% rename from arch/arm/src/stm32f0/chip/stm32f0_tim.h rename to arch/arm/src/stm32f0l0/hardware/stm32_tim.h index 12add9370fa..793e5fb68da 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_tim.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32_tim.h @@ -1,5 +1,5 @@ /**************************************************************************************************** - * arch/arm/src/stm32f0/chip/stm32f0_tim.h + * arch/arm/src/stm32f0l0/hardware/stm32_tim.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ****************************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_TIM_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_TIM_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_TIM_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_TIM_H /**************************************************************************************************** * Pre-processor Definitions @@ -49,4 +49,4 @@ /* Register Bitfield Definitions ********************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_TIM_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_TIM_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_uart.h b/arch/arm/src/stm32f0l0/hardware/stm32_uart.h similarity index 71% rename from arch/arm/src/stm32f0/chip/stm32f0_uart.h rename to arch/arm/src/stm32f0l0/hardware/stm32_uart.h index 62af4d5ca19..f762b631d5a 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_uart.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32_uart.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/chip/stm32f0_uart.h + * arch/arm/src/stm32f0l0/hardware/stm32_uart.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_UART_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_UART_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_UART_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_UART_H /************************************************************************************ * Included Files @@ -51,88 +51,88 @@ /* Register Offsets *****************************************************************/ -#define STM32F0_USART_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32F0_USART_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32F0_USART_CR3_OFFSET 0x0008 /* Control register 3 */ -#define STM32F0_USART_BRR_OFFSET 0x000c /* Baud Rate register */ -#define STM32F0_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ -#define STM32F0_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ -#define STM32F0_USART_RQR_OFFSET 0x0018 /* Request register */ -#define STM32F0_USART_ISR_OFFSET 0x001c /* Interrupot and status register */ -#define STM32F0_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ -#define STM32F0_USART_RDR_OFFSET 0x0024 /* Receive Data register */ -#define STM32F0_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ +#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ +#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */ +#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ +#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ +#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ +#define STM32_USART_ISR_OFFSET 0x001c /* Interrupot and status register */ +#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ +#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */ +#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ /* Register Addresses ***************************************************************/ -#if STM32F0_NUSART > 0 -# define STM32F0_USART1_CR1 (STM32F0_USART1_BASE+STM32F0_USART_CR1_OFFSET) -# define STM32F0_USART1_CR2 (STM32F0_USART1_BASE+STM32F0_USART_CR2_OFFSET) -# define STM32F0_USART1_CR3 (STM32F0_USART1_BASE+STM32F0_USART_CR3_OFFSET) -# define STM32F0_USART1_BRR (STM32F0_USART1_BASE+STM32F0_USART_BRR_OFFSET) -# define STM32F0_USART1_GTPR (STM32F0_USART1_BASE+STM32F0_USART_GTPR_OFFSET) -# define STM32F0_USART1_RTOR (STM32F0_USART1_BASE+STM32F0_USART_RTOR_OFFSET) -# define STM32F0_USART1_RQR (STM32F0_USART1_BASE+STM32F0_USART_RQR_OFFSET) -# define STM32F0_USART1_ISR (STM32F0_USART1_BASE+STM32F0_USART_ISR_OFFSET) -# define STM32F0_USART1_ICR (STM32F0_USART1_BASE+STM32F0_USART_ICR_OFFSET) -# define STM32F0_USART1_RDR (STM32F0_USART1_BASE+STM32F0_USART_RDR_OFFSET) -# define STM32F0_USART1_TDR (STM32F0_USART1_BASE+STM32F0_USART_TDR_OFFSET) +#if STM32_NUSART > 0 +# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET) #endif -#if STM32F0_NUSART > 1 -# define STM32F0_USART2_CR1 (STM32F0_USART2_BASE+STM32F0_USART_CR1_OFFSET) -# define STM32F0_USART2_CR2 (STM32F0_USART2_BASE+STM32F0_USART_CR2_OFFSET) -# define STM32F0_USART2_CR3 (STM32F0_USART2_BASE+STM32F0_USART_CR3_OFFSET) -# define STM32F0_USART2_BRR (STM32F0_USART2_BASE+STM32F0_USART_BRR_OFFSET) -# define STM32F0_USART2_GTPR (STM32F0_USART2_BASE+STM32F0_USART_GTPR_OFFSET) -# define STM32F0_USART2_RTOR (STM32F0_USART2_BASE+STM32F0_USART_RTOR_OFFSET) -# define STM32F0_USART2_RQR (STM32F0_USART2_BASE+STM32F0_USART_RQR_OFFSET) -# define STM32F0_USART2_ISR (STM32F0_USART2_BASE+STM32F0_USART_ISR_OFFSET) -# define STM32F0_USART2_ICR (STM32F0_USART2_BASE+STM32F0_USART_ICR_OFFSET) -# define STM32F0_USART2_RDR (STM32F0_USART2_BASE+STM32F0_USART_RDR_OFFSET) -# define STM32F0_USART2_TDR (STM32F0_USART2_BASE+STM32F0_USART_TDR_OFFSET) +#if STM32_NUSART > 1 +# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET) #endif -#if STM32F0_NUSART > 2 -# define STM32F0_USART3_CR1 (STM32F0_USART3_BASE+STM32F0_USART_CR1_OFFSET) -# define STM32F0_USART3_CR2 (STM32F0_USART3_BASE+STM32F0_USART_CR2_OFFSET) -# define STM32F0_USART3_CR3 (STM32F0_USART3_BASE+STM32F0_USART_CR3_OFFSET) -# define STM32F0_USART3_BRR (STM32F0_USART3_BASE+STM32F0_USART_BRR_OFFSET) -# define STM32F0_USART3_GTPR (STM32F0_USART3_BASE+STM32F0_USART_GTPR_OFFSET) -# define STM32F0_USART3_RTOR (STM32F0_USART3_BASE+STM32F0_USART_RTOR_OFFSET) -# define STM32F0_USART3_RQR (STM32F0_USART3_BASE+STM32F0_USART_RQR_OFFSET) -# define STM32F0_USART3_ISR (STM32F0_USART3_BASE+STM32F0_USART_ISR_OFFSET) -# define STM32F0_USART3_ICR (STM32F0_USART3_BASE+STM32F0_USART_ICR_OFFSET) -# define STM32F0_USART3_RDR (STM32F0_USART3_BASE+STM32F0_USART_RDR_OFFSET) -# define STM32F0_USART3_TDR (STM32F0_USART3_BASE+STM32F0_USART_TDR_OFFSET) +#if STM32_NUSART > 2 +# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET) #endif -#if STM32F0_NUSART > 3 -# define STM32F0_USART4_CR1 (STM32F0_USART4_BASE+STM32F0_USART_CR1_OFFSET) -# define STM32F0_USART4_CR2 (STM32F0_USART4_BASE+STM32F0_USART_CR2_OFFSET) -# define STM32F0_USART4_CR3 (STM32F0_USART4_BASE+STM32F0_USART_CR3_OFFSET) -# define STM32F0_USART4_BRR (STM32F0_USART4_BASE+STM32F0_USART_BRR_OFFSET) -# define STM32F0_USART4_GTPR (STM32F0_USART4_BASE+STM32F0_USART_GTPR_OFFSET) -# define STM32F0_USART4_RTOR (STM32F0_USART4_BASE+STM32F0_USART_RTOR_OFFSET) -# define STM32F0_USART4_RQR (STM32F0_USART4_BASE+STM32F0_USART_RQR_OFFSET) -# define STM32F0_USART4_ISR (STM32F0_USART4_BASE+STM32F0_USART_ISR_OFFSET) -# define STM32F0_USART4_ICR (STM32F0_USART4_BASE+STM32F0_USART_ICR_OFFSET) -# define STM32F0_USART4_RDR (STM32F0_USART4_BASE+STM32F0_USART_RDR_OFFSET) -# define STM32F0_USART4_TDR (STM32F0_USART4_BASE+STM32F0_USART_TDR_OFFSET) +#if STM32_NUSART > 3 +# define STM32_USART4_CR1 (STM32_USART4_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART4_CR2 (STM32_USART4_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART4_CR3 (STM32_USART4_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART4_BRR (STM32_USART4_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART4_GTPR (STM32_USART4_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART4_RTOR (STM32_USART4_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART4_RQR (STM32_USART4_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART4_ISR (STM32_USART4_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART4_ICR (STM32_USART4_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART4_RDR (STM32_USART4_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART4_TDR (STM32_USART4_BASE + STM32_USART_TDR_OFFSET) #endif -#if STM32F0_NUSART > 4 -# define STM32F0_USART5_CR1 (STM32F0_USART5_BASE+STM32F0_USART_CR1_OFFSET) -# define STM32F0_USART5_CR2 (STM32F0_USART5_BASE+STM32F0_USART_CR2_OFFSET) -# define STM32F0_USART5_CR3 (STM32F0_USART5_BASE+STM32F0_USART_CR3_OFFSET) -# define STM32F0_USART5_BRR (STM32F0_USART5_BASE+STM32F0_USART_BRR_OFFSET) -# define STM32F0_USART5_GTPR (STM32F0_USART5_BASE+STM32F0_USART_GTPR_OFFSET) -# define STM32F0_USART5_RTOR (STM32F0_USART5_BASE+STM32F0_USART_RTOR_OFFSET) -# define STM32F0_USART5_RQR (STM32F0_USART5_BASE+STM32F0_USART_RQR_OFFSET) -# define STM32F0_USART5_ISR (STM32F0_USART5_BASE+STM32F0_USART_ISR_OFFSET) -# define STM32F0_USART5_ICR (STM32F0_USART5_BASE+STM32F0_USART_ICR_OFFSET) -# define STM32F0_USART5_RDR (STM32F0_USART5_BASE+STM32F0_USART_RDR_OFFSET) -# define STM32F0_USART5_TDR (STM32F0_USART5_BASE+STM32F0_USART_TDR_OFFSET) +#if STM32_NUSART > 4 +# define STM32_USART5_CR1 (STM32_USART5_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART5_CR2 (STM32_USART5_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART5_CR3 (STM32_USART5_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART5_BRR (STM32_USART5_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART5_GTPR (STM32_USART5_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART5_RTOR (STM32_USART5_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART5_RQR (STM32_USART5_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART5_ISR (STM32_USART5_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART5_ICR (STM32_USART5_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART5_RDR (STM32_USART5_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART5_TDR (STM32_USART5_BASE + STM32_USART_TDR_OFFSET) #endif /* Register Bitfield Definitions ****************************************************/ @@ -313,4 +313,4 @@ #define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */ #define USART_TDR_MASK (0xff << USART_TDR_SHIFT) -#endif /* __ARCH_ARM_STC_STM32F0_CHIP_STM32F0_UART_H */ +#endif /* __ARCH_ARM_STC_STM32F0L0_CHIP_STM32_UART_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_usbdev.h b/arch/arm/src/stm32f0l0/hardware/stm32_usbdev.h similarity index 73% rename from arch/arm/src/stm32f0/chip/stm32f0_usbdev.h rename to arch/arm/src/stm32f0l0/hardware/stm32_usbdev.h index 19ea51787f8..a93160654e7 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_usbdev.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32_usbdev.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/chip/stm32f0_usbdev.h + * arch/arm/src/stm32f0l0/hardware/stm32_usbdev.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_USBDEV_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_USBDEV_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_USBDEV_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_USBDEV_H /************************************************************************************ * Included Files @@ -43,7 +43,7 @@ #include #include -#ifdef CONFIG_STM32F0_HAVE_USBDEV +#ifdef CONFIG_STM32F0L0_HAVE_USBDEV /************************************************************************************ * Pre-processor Definitions @@ -53,70 +53,70 @@ /* Endpoint Registers */ -#define STM32F0_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */ -#define STM32F0_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */ -#define STM32F0_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */ -#define STM32F0_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */ -#define STM32F0_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */ -#define STM32F0_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */ -#define STM32F0_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */ -#define STM32F0_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */ -#define STM32F0_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */ +#define STM32_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */ +#define STM32_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */ +#define STM32_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */ +#define STM32_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */ +#define STM32_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */ +#define STM32_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */ +#define STM32_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */ +#define STM32_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */ +#define STM32_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */ /* Common Registers */ -#define STM32F0_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */ -#define STM32F0_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */ -#define STM32F0_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */ -#define STM32F0_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */ -#define STM32F0_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */ -#define STM32F0_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register (16-bits) */ -#define STM32F0_USB_BCDR_OFFSET 0x0058 /* Battery charging detector (16-bits) */ +#define STM32_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */ +#define STM32_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */ +#define STM32_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */ +#define STM32_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */ +#define STM32_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */ +#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register (16-bits) */ +#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector (16-bits) */ /* Buffer Descriptor Table (Relatative to BTABLE address) */ -#define STM32F0_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */ -#define STM32F0_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */ -#define STM32F0_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */ -#define STM32F0_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */ +#define STM32_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */ +#define STM32_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */ +#define STM32_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */ +#define STM32_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */ -#define STM32F0_USB_BTABLE_RADDR(ep,o) ((((uint32_t)getreg16(STM32F0_USB_BTABLE) + ((ep) << 3)) + (o)) << 1) -#define STM32F0_USB_ADDR_TX_OFFSET(ep) STM32F0_USB_BTABLE_RADDR(ep,STM32F0_USB_ADDR_TX_WOFFSET) -#define STM32F0_USB_COUNT_TX_OFFSET(ep) STM32F0_USB_BTABLE_RADDR(ep,STM32F0_USB_COUNT_TX_WOFFSET) -#define STM32F0_USB_ADDR_RX_OFFSET(ep) STM32F0_USB_BTABLE_RADDR(ep,STM32F0_USB_ADDR_RX_WOFFSET) -#define STM32F0_USB_COUNT_RX_OFFSET(ep) STM32F0_USB_BTABLE_RADDR(ep,STM32F0_USB_COUNT_RX_WOFFSET) +#define STM32_USB_BTABLE_RADDR(ep,o) ((((uint32_t)getreg16(STM32_USB_BTABLE) + ((ep) << 3)) + (o)) << 1) +#define STM32_USB_ADDR_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_TX_WOFFSET) +#define STM32_USB_COUNT_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_TX_WOFFSET) +#define STM32_USB_ADDR_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_RX_WOFFSET) +#define STM32_USB_COUNT_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_RX_WOFFSET) /* Register Addresses ***************************************************************/ /* Endpoint Registers */ -#define STM32F0_USB_EPR(n) (STM32F0_USB_BASE+STM32F0_USB_EPR_OFFSET(n)) -#define STM32F0_USB_EP0R (STM32F0_USB_BASE+STM32F0_USB_EP0R_OFFSET) -#define STM32F0_USB_EP1R (STM32F0_USB_BASE+STM32F0_USB_EP1R_OFFSET) -#define STM32F0_USB_EP2R (STM32F0_USB_BASE+STM32F0_USB_EP2R_OFFSET) -#define STM32F0_USB_EP3R (STM32F0_USB_BASE+STM32F0_USB_EP3R_OFFSET) -#define STM32F0_USB_EP4R (STM32F0_USB_BASE+STM32F0_USB_EP4R_OFFSET) -#define STM32F0_USB_EP5R (STM32F0_USB_BASE+STM32F0_USB_EP5R_OFFSET) -#define STM32F0_USB_EP6R (STM32F0_USB_BASE+STM32F0_USB_EP6R_OFFSET) -#define STM32F0_USB_EP7R (STM32F0_USB_BASE+STM32F0_USB_EP7R_OFFSET) +#define STM32_USB_EPR(n) (STM32_USB_BASE + STM32_USB_EPR_OFFSET(n)) +#define STM32_USB_EP0R (STM32_USB_BASE + STM32_USB_EP0R_OFFSET) +#define STM32_USB_EP1R (STM32_USB_BASE + STM32_USB_EP1R_OFFSET) +#define STM32_USB_EP2R (STM32_USB_BASE + STM32_USB_EP2R_OFFSET) +#define STM32_USB_EP3R (STM32_USB_BASE + STM32_USB_EP3R_OFFSET) +#define STM32_USB_EP4R (STM32_USB_BASE + STM32_USB_EP4R_OFFSET) +#define STM32_USB_EP5R (STM32_USB_BASE + STM32_USB_EP5R_OFFSET) +#define STM32_USB_EP6R (STM32_USB_BASE + STM32_USB_EP6R_OFFSET) +#define STM32_USB_EP7R (STM32_USB_BASE + STM32_USB_EP7R_OFFSET) /* Common Registers */ -#define STM32F0_USB_CNTR (STM32F0_USB_BASE+STM32F0_USB_CNTR_OFFSET) -#define STM32F0_USB_ISTR (STM32F0_USB_BASE+STM32F0_USB_ISTR_OFFSET) -#define STM32F0_USB_FNR (STM32F0_USB_BASE+STM32F0_USB_FNR_OFFSET) -#define STM32F0_USB_DADDR (STM32F0_USB_BASE+STM32F0_USB_DADDR_OFFSET) -#define STM32F0_USB_BTABLE (STM32F0_USB_BASE+STM32F0_USB_BTABLE_OFFSET) -#define STM32F0_USB_LPMCSR (STM32F0_USB_BASE+STM32F0_USB_LPMCSR_OFFSET) -#define STM32F0_USB_BCDR (STM32F0_USB_BASE+STM32F0_USB_BCDR_OFFSET) +#define STM32_USB_CNTR (STM32_USB_BASE + STM32_USB_CNTR_OFFSET) +#define STM32_USB_ISTR (STM32_USB_BASE + STM32_USB_ISTR_OFFSET) +#define STM32_USB_FNR (STM32_USB_BASE + STM32_USB_FNR_OFFSET) +#define STM32_USB_DADDR (STM32_USB_BASE + STM32_USB_DADDR_OFFSET) +#define STM32_USB_BTABLE (STM32_USB_BASE + STM32_USB_BTABLE_OFFSET) +#define STM32_USB_LPMCSR (STM32_USB_BASE + STM32_USB_LPMCSR_OFFSET) +#define STM32_USB_BCDR (STM32_USB_BASE + STM32_USB_BCDR_OFFSET) -/* Buffer Descriptor Table (Relatative to BTABLE address) */ +/* Buffer Descriptor Table (Relative to BTABLE address) */ -#define STM32F0_USB_BTABLE_ADDR(ep,o) (STM32F0_USBRAM_BASE+STM32F0_USB_BTABLE_RADDR(ep,o)) -#define STM32F0_USB_ADDR_TX(ep) STM32F0_USB_BTABLE_ADDR(ep,STM32F0_USB_ADDR_TX_WOFFSET) -#define STM32F0_USB_COUNT_TX(ep) STM32F0_USB_BTABLE_ADDR(ep,STM32F0_USB_COUNT_TX_WOFFSET) -#define STM32F0_USB_ADDR_RX(ep) STM32F0_USB_BTABLE_ADDR(ep,STM32F0_USB_ADDR_RX_WOFFSET) -#define STM32F0_USB_COUNT_RX(ep) STM32F0_USB_BTABLE_ADDR(ep,STM32F0_USB_COUNT_RX_WOFFSET) +#define STM32_USB_BTABLE_ADDR(ep,o) (STM32_USBRAM_BASE + STM32_USB_BTABLE_RADDR(ep,o)) +#define STM32_USB_ADDR_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_TX_WOFFSET) +#define STM32_USB_COUNT_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_TX_WOFFSET) +#define STM32_USB_ADDR_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_RX_WOFFSET) +#define STM32_USB_COUNT_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_RX_WOFFSET) /* Register Bitfield Definitions ****************************************************/ @@ -260,5 +260,5 @@ #define USB_COUNT_RX_SHIFT (0) /* Bits 9-0: Reception Byte Count */ #define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT) -#endif /* CONFIG_STM32F0_HAVE_USBDEV */ -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_USBDEV_H */ +#endif /* CONFIG_STM32F0L0_HAVE_USBDEV */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_USBDEV_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_wdt.h b/arch/arm/src/stm32f0l0/hardware/stm32_wdt.h new file mode 100644 index 00000000000..e545b818af6 --- /dev/null +++ b/arch/arm/src/stm32f0l0/hardware/stm32_wdt.h @@ -0,0 +1,142 @@ +/************************************************************************************ + * arch/arm/src/stm32f0l0/hardware/stm32_wdt.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_WDG_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_WDG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */ +#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */ +#define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */ +#define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */ +#define STM32_IWDG_WINR_OFFSET 0x0010 /* Window register (32-bit) */ + +#define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */ +#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */ +#define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */ + +/* Register Addresses ***************************************************************/ + +#define STM32_IWDG_KR (STM32_IWDG_BASE + STM32_IWDG_KR_OFFSET) +#define STM32_IWDG_PR (STM32_IWDG_BASE + STM32_IWDG_PR_OFFSET) +#define STM32_IWDG_RLR (STM32_IWDG_BASE + STM32_IWDG_RLR_OFFSET) +#define STM32_IWDG_SR (STM32_IWDG_BASE + STM32_IWDG_SR_OFFSET) +#define STM32_IWDG_WINR (STM32_IWDG_BASE + STM32_IWDG_WINR_OFFSET) + +#define STM32_WWDG_CR (STM32_WWDG_BASE + STM32_WWDG_CR_OFFSET) +#define STM32_WWDG_CFR (STM32_WWDG_BASE + STM32_WWDG_CFR_OFFSET) +#define STM32_WWDG_SR (STM32_WWDG_BASE + STM32_WWDG_SR_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +/* Key register (32-bit) */ + +#define IWDG_KR_KEY_SHIFT (0) /* Bits 15-0: Key value (write only, read 0000h) */ +#define IWDG_KR_KEY_MASK (0xffff << IWDG_KR_KEY_SHIFT) + +#define IWDG_KR_KEY_ENABLE (0x5555) /* Enable register access */ +#define IWDG_KR_KEY_DISABLE (0x0000) /* Disable register access */ +#define IWDG_KR_KEY_RELOAD (0xaaaa) /* Reload the counter */ +#define IWDG_KR_KEY_START (0xcccc) /* Start the watchdog */ + +/* Prescaler register (32-bit) */ + +#define IWDG_PR_SHIFT (0) /* Bits 2-0: Prescaler divider */ +#define IWDG_PR_MASK (7 << IWDG_PR_SHIFT) +# define IWDG_PR_DIV4 (0 << IWDG_PR_SHIFT) /* 000: divider /4 */ +# define IWDG_PR_DIV8 (1 << IWDG_PR_SHIFT) /* 001: divider /8 */ +# define IWDG_PR_DIV16 (2 << IWDG_PR_SHIFT) /* 010: divider /16 */ +# define IWDG_PR_DIV32 (3 << IWDG_PR_SHIFT) /* 011: divider /32 */ +# define IWDG_PR_DIV64 (4 << IWDG_PR_SHIFT) /* 100: divider /64 */ +# define IWDG_PR_DIV128 (5 << IWDG_PR_SHIFT) /* 101: divider /128 */ +# define IWDG_PR_DIV256 (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */ + +/* Reload register (32-bit) */ + +#define IWDG_RLR_RL_SHIFT (0) /* Bits11:0 RL[11:0]: Watchdog counter reload value */ +#define IWDG_RLR_RL_MASK (0x0fff << IWDG_RLR_RL_SHIFT) + +#define IWDG_RLR_MAX (0xfff) + +/* Status register (32-bit) */ + +#define IWDG_SR_PVU (1 << 0) /* Bit 0: Watchdog prescaler value update */ +#define IWDG_SR_RVU (1 << 1) /* Bit 1: Watchdog counter reload value update */ +#define IWDG_SR_WVU (1 << 2) /* Bit 2: Watchdog counter window value update */ + +/* Window register (32-bit) */ + +#define IWDG_WINR_SHIFT (0) +#define IWDG_WINR_MASK (0x0fff << IWDG_WINR_SHIFT) + +/* Control Register (32-bit) */ + +#define WWDG_CR_T_SHIFT (0) /* Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) */ +#define WWDG_CR_T_MASK (0x7f << WWDG_CR_T_SHIFT) +# define WWDG_CR_T_MAX (0x3f << WWDG_CR_T_SHIFT) +# define WWDG_CR_T_RESET (0x40 << WWDG_CR_T_SHIFT) +#define WWDG_CR_WDGA (1 << 7) /* Bit 7: Activation bit */ + +/* Configuration register (32-bit) */ + +#define WWDG_CFR_W_SHIFT (0) /* Bits 6:0 W[6:0] 7-bit window value */ +#define WWDG_CFR_W_MASK (0x7f << WWDG_CFR_W_SHIFT) +#define WWDG_CFR_WDGTB_SHIFT (7) /* Bits 8:7 [1:0]: Timer Base */ +#define WWDG_CFR_WDGTB_MASK (3 << WWDG_CFR_WDGTB_SHIFT) +# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */ +# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */ +# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */ +# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */ +#define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */ + +/* Status register (32-bit) */ + +#define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */ + +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_WDG_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f05x_pinmap.h b/arch/arm/src/stm32f0l0/hardware/stm32f05x_pinmap.h similarity index 96% rename from arch/arm/src/stm32f0/chip/stm32f05x_pinmap.h rename to arch/arm/src/stm32f0l0/hardware/stm32f05x_pinmap.h index 2e63d59ead0..718eb32d2db 100644 --- a/arch/arm/src/stm32f0/chip/stm32f05x_pinmap.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32f05x_pinmap.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/chip/stm32f05x_pinmap.h + * arch/arm/src/stm32f0l0/hardware/stm32f05x_pinmap.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F05X_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F05X_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F05X_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F05X_PINMAP_H /************************************************************************************ * Included Files @@ -43,7 +43,7 @@ #include -#include "stm32f0_gpio.h" +#include "stm32_gpio.h" /************************************************************************************ * Pre-processor Definitions @@ -133,4 +133,4 @@ #define GPIO_I2C2_SCL (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN10) #define GPIO_I2C2_SDA (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN11) -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F05X_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F05X_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f05xf07xf09x_memorymap.h b/arch/arm/src/stm32f0l0/hardware/stm32f05xf07xf09x_memorymap.h new file mode 100644 index 00000000000..bf2a6b13be9 --- /dev/null +++ b/arch/arm/src/stm32f0l0/hardware/stm32f05xf07xf09x_memorymap.h @@ -0,0 +1,157 @@ +/************************************************************************************ + * arch/arm/src/stm32f0l0/hardware/stm32f05xf07xf09x_memorymap.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_ST32F05XF07XF09X_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_ST32F05XF07XF09X_MEMORYMAP_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* ST32F05XF07X Address Blocks ******************************************************/ + +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ + /* 0x60000000-0xdfffffff: Reserved */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ + +#define STM32_REGION_MASK 0xf0000000 +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) + +/* Code Base Addresses **************************************************************/ + +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ + /* 0x00100000-0x07ffffff: Reserved */ +#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ + /* 0x08100000-0x0fffffff: Reserved */ +#define STM32_CCMRAM_BASE 0x10000000 /* 0x10000000-0x1000ffff: 64Kb CCM data RAM */ + /* 0x10010000-0x1ffeffff: Reserved */ +#define STM32_SYSMEM_BASE 0x1fffd800 /* 0x1fff0000-0x1fff7a0f: System memory */ + /* 0x1fff7a10-0x1fff7fff: Reserved */ +#define STM32_OPTION_BASE 0x1ffff800 /* 0x1fffc000-0x1fffc007: Option bytes */ + /* 0x1fffc008-0x1fffffff: Reserved */ + +/* System Memory Addresses **********************************************************/ + +#define STM32_SYSMEM_UID 0x1ffff7ac /* The 96-bit unique device identifier */ +#define STM32_SYSMEM_FSIZE 0x1ffff7cc /* This bitfield indicates the size of + * the device Flash memory expressed in + * Kbytes. Example: 0x040 corresponds + * to 64 Kbytes + */ + +/* Peripheral Base Addresses ********************************************************/ + +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40009fff: APB1 */ + /* 0x4000a000-0x4000ffff: Reserved */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40006bff: APB2 */ + /* 0x40016c00-0x4001ffff: Reserved */ +#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */ + /* 0x40024400-0x4007ffff: Reserved */ +#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x480017ff: AHB2 */ + /* 0x48001800-0x4fffFfff: Reserved */ +#define STM32_AHB3_BASE 0x50000000 /* 0x50000000-0x500007ff: AHB3 */ + +/* APB1 Base Addresses **************************************************************/ + +#define STM32_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff TIM2 */ +#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff TIM3 */ +#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */ +#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */ +#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff TIM14 */ +#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */ +#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */ +#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */ +#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff SPI2, or */ +#define STM32_I2S2_BASE 0x40003800 /* 0x40003800-0x40003bff I2S2 */ +#define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff USART2 */ +#define STM32_USART3_BASE 0x40004800 /* 0x40004800-0x40004bff USART3 */ +#define STM32_USART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff USART4 */ +#define STM32_USART5_BASE 0x40005000 /* 0x40005000-0x400053ff USART5 */ +#define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff I2C1 */ +#define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff I2C2 */ +#define STM32_USB_BASE 0x40005c00 /* 0x40005c00-0x40005fff USB device FS */ +#define STM32_USBRAM_BASE 0x40006000 /* 0x40006000-0x400063ff USB SRAM 512B */ +#define STM32_CAN_BASE 0x40006400 /* 0x40006400-0x400067ff bxCAN */ +#define STM32_CRS_BASE 0x40006c00 /* 0x40006c00-0x40006fff CRS */ +#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */ +#define STM32_DAC_BASE 0x40007400 /* 0x40007400-0x400077ff DAC */ +#define STM32_CEC_BASE 0x40007800 /* 0x40007800-0x40007bff HDMI CEC */ + +/* APB2 Base Addresses **************************************************************/ + +#define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103ff SYSCFG + COMP + OPAMP */ +#define STM32_EXTI_BASE 0x40010400 /* 0x40010400-0x400107ff EXTI */ +#define STM32_USART6_BASE 0x40011400 /* 0x40011400-0x400117ff USART6 */ +#define STM32_USART7_BASE 0x40011800 /* 0x40011800-0x40011bff USART7 */ +#define STM32_USART8_BASE 0x40011c00 /* 0x40011c00-0x40011fff USART8 */ +#define STM32_ADC_BASE 0x40012400 /* 0x40012400-0x400127ff ADC */ +#define STM32_TIM1_BASE 0x40012c00 /* 0x40012c00-0x40012fff TIM1 */ +#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */ +#define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */ +#define STM32_TIM15_BASE 0x40014000 /* 0x40014000-0x400143ff TIM15 */ +#define STM32_TIM16_BASE 0x40014400 /* 0x40014400-0x400147ff TIM16 */ +#define STM32_TIM17_BASE 0x40014800 /* 0x40014800-0x40014bff TIM17 */ +#define STM32_DBGMCU_BASE 0x40015800 /* 0x40015800-0x40015bff DBGMCU */ + +/* AHB1 Base Addresses **************************************************************/ + +#define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */ +#define STM32_DMA2_BASE 0x40020400 /* 0x40020400-0x400207ff: DMA2 */ +#define STM32_RCC_BASE 0x40021000 /* 0x40021000-0x400213ff: Reset and Clock control RCC */ +#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000-0x400223ff: Flash memory interface */ +#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */ +#define STM32_TSC_BASE 0x40024000 /* 0x40024000-0x400243ff: TSC */ + +/* AHB2 Base Addresses **************************************************************/ + +#define STM32_GPIOA_BASE 0x48000000 /* 0x48000000-0x480003ff: GPIO Port A */ +#define STM32_GPIOB_BASE 0x48000400 /* 0x48000400-0x480007ff: GPIO Port B */ +#define STM32_GPIOC_BASE 0x48000800 /* 0x48000800-0x48000bff: GPIO Port C */ +#define STM32_GPIOD_BASE 0X48000C00 /* 0x48000c00-0x48000fff: GPIO Port D */ +#define STM32_GPIOE_BASE 0x48001000 /* 0x48001000-0x480013ff: GPIO Port E */ +#define STM32_GPIOF_BASE 0x48001400 /* 0x48001400-0x480017ff: GPIO Port F */ + +/* Cortex-M4 Base Addresses *********************************************************/ +/* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in this + * address range + */ + +#define STM32_SCS_BASE 0xe000e000 +#define STM32_DEBUGMCU_BASE 0xe0042000 + +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_ST32F05XF07XF09X_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f07x_pinmap.h b/arch/arm/src/stm32f0l0/hardware/stm32f07x_pinmap.h similarity index 98% rename from arch/arm/src/stm32f0/chip/stm32f07x_pinmap.h rename to arch/arm/src/stm32f0l0/hardware/stm32f07x_pinmap.h index 4ac07ab59cb..dc2a5a7645b 100644 --- a/arch/arm/src/stm32f0/chip/stm32f07x_pinmap.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32f07x_pinmap.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/chip/stm32f07x_pinmap.h + * arch/arm/src/stm32f0l0/hardware/stm32f07x_pinmap.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F07X_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F07X_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F07X_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F07X_PINMAP_H /************************************************************************************ * Included Files @@ -43,7 +43,7 @@ #include -#include "stm32f0_gpio.h" +#include "stm32_gpio.h" /************************************************************************************ * Pre-processor Definitions @@ -397,4 +397,4 @@ #define GPIO_USB_NOE (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN13) -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F07X_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F07X_PINMAP_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f09x_pinmap.h b/arch/arm/src/stm32f0l0/hardware/stm32f09x_pinmap.h similarity index 99% rename from arch/arm/src/stm32f0/chip/stm32f09x_pinmap.h rename to arch/arm/src/stm32f0l0/hardware/stm32f09x_pinmap.h index b144846d953..7d1c4291176 100644 --- a/arch/arm/src/stm32f0/chip/stm32f09x_pinmap.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32f09x_pinmap.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/chip/stm32f09x_pinmap.h + * arch/arm/src/stm32f0l0/hardware/stm32f09x_pinmap.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F09X_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F09X_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F09X_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F09X_PINMAP_H /************************************************************************************ * Included Files @@ -43,7 +43,7 @@ #include -#include "stm32f0_gpio.h" +#include "stm32_gpio.h" /************************************************************************************ * Pre-processor Definitions @@ -427,4 +427,4 @@ #define GPIO_USART8_RX_3 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN13) #define GPIO_USART8_CK_RST (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN14) -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F09X_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F09X_PINMAP_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_rcc.h b/arch/arm/src/stm32f0l0/hardware/stm32f0_rcc.h similarity index 92% rename from arch/arm/src/stm32f0/chip/stm32f0_rcc.h rename to arch/arm/src/stm32f0l0/hardware/stm32f0_rcc.h index dadd1cf4cac..125677606ef 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_rcc.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32f0_rcc.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/chip/stm32f0_rcc.h + * arch/arm/src/stm32f0l0/hardware/stm32f0_rcc.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_RCC_H -#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_RCC_H +#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_RCC_H /************************************************************************************ * Pre-processor Definitions @@ -43,37 +43,37 @@ /* Register Offsets *****************************************************************/ -#define STM32F0_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32F0_RCC_CFGR_OFFSET 0x0004 /* Clock configuration register */ -#define STM32F0_RCC_CIR_OFFSET 0x0008 /* Clock interrupt register */ -#define STM32F0_RCC_APB2RSTR_OFFSET 0x000c /* APB2 Peripheral reset register */ -#define STM32F0_RCC_APB1RSTR_OFFSET 0x0010 /* APB1 Peripheral reset register */ -#define STM32F0_RCC_AHBENR_OFFSET 0x0014 /* AHB Peripheral Clock enable register */ -#define STM32F0_RCC_APB2ENR_OFFSET 0x0018 /* APB2 Peripheral Clock enable register */ -#define STM32F0_RCC_APB1ENR_OFFSET 0x001c /* APB1 Peripheral Clock enable register */ -#define STM32F0_RCC_BDCR_OFFSET 0x0020 /* Backup domain control register */ -#define STM32F0_RCC_CSR_OFFSET 0x0024 /* Control/status register */ -#define STM32F0_RCC_AHBRSTR_OFFSET 0x0028 /* AHB Reset register */ -#define STM32F0_RCC_CFGR2_OFFSET 0x002c /* Clock configuration register 2 */ -#define STM32F0_RCC_CFGR3_OFFSET 0x0030 /* Clock configuration register 3 */ -#define STM32F0_RCC_CR2_OFFSET 0x0034 /* Clock control register 2 */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_CFGR_OFFSET 0x0004 /* Clock configuration register */ +#define STM32_RCC_CIR_OFFSET 0x0008 /* Clock interrupt register */ +#define STM32_RCC_APB2RSTR_OFFSET 0x000c /* APB2 Peripheral reset register */ +#define STM32_RCC_APB1RSTR_OFFSET 0x0010 /* APB1 Peripheral reset register */ +#define STM32_RCC_AHBENR_OFFSET 0x0014 /* AHB Peripheral Clock enable register */ +#define STM32_RCC_APB2ENR_OFFSET 0x0018 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR_OFFSET 0x001c /* APB1 Peripheral Clock enable register */ +#define STM32_RCC_BDCR_OFFSET 0x0020 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0024 /* Control/status register */ +#define STM32_RCC_AHBRSTR_OFFSET 0x0028 /* AHB Reset register */ +#define STM32_RCC_CFGR2_OFFSET 0x002c /* Clock configuration register 2 */ +#define STM32_RCC_CFGR3_OFFSET 0x0030 /* Clock configuration register 3 */ +#define STM32_RCC_CR2_OFFSET 0x0034 /* Clock control register 2 */ /* Register Addresses ***************************************************************/ -#define STM32F0_RCC_CR (STM32F0_RCC_BASE+STM32F0_RCC_CR_OFFSET) -#define STM32F0_RCC_CFGR (STM32F0_RCC_BASE+STM32F0_RCC_CFGR_OFFSET) -#define STM32F0_RCC_CIR (STM32F0_RCC_BASE+STM32F0_RCC_CIR_OFFSET) -#define STM32F0_RCC_APB2RSTR (STM32F0_RCC_BASE+STM32F0_RCC_APB2RSTR_OFFSET) -#define STM32F0_RCC_APB1RSTR (STM32F0_RCC_BASE+STM32F0_RCC_APB1RSTR_OFFSET) -#define STM32F0_RCC_AHBENR (STM32F0_RCC_BASE+STM32F0_RCC_AHBENR_OFFSET) -#define STM32F0_RCC_APB2ENR (STM32F0_RCC_BASE+STM32F0_RCC_APB2ENR_OFFSET) -#define STM32F0_RCC_APB1ENR (STM32F0_RCC_BASE+STM32F0_RCC_APB1ENR_OFFSET) -#define STM32F0_RCC_BDCR (STM32F0_RCC_BASE+STM32F0_RCC_BDCR_OFFSET) -#define STM32F0_RCC_CSR (STM32F0_RCC_BASE+STM32F0_RCC_CSR_OFFSET) -#define STM32F0_RCC_AHBRSTR (STM32F0_RCC_BASE+STM32F0_RCC_AHBRSTR_OFFSET) -#define STM32F0_RCC_CFGR2 (STM32F0_RCC_BASE+STM32F0_RCC_CFGR2_OFFSET) -#define STM32F0_RCC_CFGR3 (STM32F0_RCC_BASE+STM32F0_RCC_CFGR3_OFFSET) -#define STM32F0_RCC_CR2 (STM32F0_RCC_BASE+STM32F0_RCC_CR2_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_CIR (STM32_RCC_BASE+STM32_RCC_CIR_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_APB1RSTR (STM32_RCC_BASE+STM32_RCC_APB1RSTR_OFFSET) +#define STM32_RCC_AHBENR (STM32_RCC_BASE+STM32_RCC_AHBENR_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) +#define STM32_RCC_AHBRSTR (STM32_RCC_BASE+STM32_RCC_AHBRSTR_OFFSET) +#define STM32_RCC_CFGR2 (STM32_RCC_BASE+STM32_RCC_CFGR2_OFFSET) +#define STM32_RCC_CFGR3 (STM32_RCC_BASE+STM32_RCC_CFGR3_OFFSET) +#define STM32_RCC_CR2 (STM32_RCC_BASE+STM32_RCC_CR2_OFFSET) /* Register Bitfield Definitions ****************************************************/ @@ -391,4 +391,4 @@ #define RCC_CR2_HSI48CAL_SHIFT (24) /* Bits 24-31: HSI48 factory clock calibration */ #define RCC_CR2_HSI48CAL_MASK (0xff << RCC_CR2_HSI48CAL_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_RCC_H */ diff --git a/arch/arm/src/stm32f0/stm32f0_clockconfig.c b/arch/arm/src/stm32f0l0/stm32_clockconfig.c similarity index 77% rename from arch/arm/src/stm32f0/stm32f0_clockconfig.c rename to arch/arm/src/stm32f0l0/stm32_clockconfig.c index 06b2c86c0ce..0356d4ee2e6 100644 --- a/arch/arm/src/stm32f0/stm32f0_clockconfig.c +++ b/arch/arm/src/stm32f0l0/stm32_clockconfig.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0/stm32f0_clockconfig.c + * arch/arm/src/stm32f0l0/stm32_clockconfig.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -48,18 +48,18 @@ #include "up_arch.h" #include "up_internal.h" -#include "stm32f0_rcc.h" -#include "stm32f0_clockconfig.h" -#include "chip/stm32f0_syscfg.h" -#include "chip/stm32f0_flash.h" -#include "chip/stm32f0_gpio.h" +#include "stm32_rcc.h" +#include "stm32_clockconfig.h" +#include "hardware/stm32_syscfg.h" +#include "hardware/stm32_flash.h" +#include "hardware/stm32_gpio.h" /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32f0_clockconfig + * Name: stm32_clockconfig * * Description: * Called to initialize the STM32F0xx. This does whatever setup is needed @@ -68,29 +68,29 @@ * ****************************************************************************/ -void stm32f0_clockconfig(void) +void stm32_clockconfig(void) { uint32_t regval; /* Verify if PLL is already setup. If so configure to use HSI mode */ - if ((getreg32(STM32F0_RCC_CFGR) & RCC_CFGR_SWS_MASK) == RCC_CFGR_SWS_PLL) + if ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) == RCC_CFGR_SWS_PLL) { /* Select HSI mode */ - regval = getreg32(STM32F0_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; - putreg32(regval, STM32F0_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); - while ((getreg32(STM32F0_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_HSI); + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_HSI); } /* Disable the PLL */ - regval = getreg32(STM32F0_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_PLLON; - putreg32(regval, STM32F0_RCC_CR); - while ((getreg32(STM32F0_RCC_CR) & RCC_CR_PLLRDY) != 0); + putreg32(regval, STM32_RCC_CR); + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) != 0); /* Enable FLASH prefetch buffer and set flash latency */ @@ -101,16 +101,16 @@ void stm32f0_clockconfig(void) /* Set HCLK = SYSCLK */ - regval = getreg32(STM32F0_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; regval |= RCC_CFGR_HPRE_SYSCLK; - putreg32(regval, STM32F0_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Set PCLK = HCLK */ regval &= ~RCC_CFGR_PPRE1_MASK; regval |= RCC_CFGR_PPRE1_HCLK; - putreg32(regval, STM32F0_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Configure the PLL to generate the system clock * @@ -120,28 +120,28 @@ void stm32f0_clockconfig(void) */ regval &= ~(RCC_CFGR_PLLSRC_MASK | RCC_CFGR_PLLXTPRE_MASK | RCC_CFGR_PLLMUL_MASK); - regval |= (RCC_CFGR_PLLSRC_HSId2 | RCC_CFGR_PLLXTPRE_DIV1 | STM32F0_CFGR_PLLMUL); - putreg32(regval, STM32F0_RCC_CFGR); + regval |= (RCC_CFGR_PLLSRC_HSId2 | RCC_CFGR_PLLXTPRE_DIV1 | STM32_CFGR_PLLMUL); + putreg32(regval, STM32_RCC_CFGR); /* Enable the PLL */ - regval = getreg32(STM32F0_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32F0_RCC_CR); - while ((getreg32(STM32F0_RCC_CR) & RCC_CR_PLLRDY) == 0); + putreg32(regval, STM32_RCC_CR); + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0); /* Configure to use the PLL */ - regval = getreg32(STM32F0_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32F0_RCC_CFGR); - while ((getreg32(STM32F0_RCC_CFGR) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL); + putreg32(regval, STM32_RCC_CFGR); + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL); /* Enable basic peripheral support */ /* Enable all GPIO modules */ - regval = getreg32(STM32F0_RCC_AHBENR); + regval = getreg32(STM32_RCC_AHBENR); regval |= RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPBEN | RCC_AHBENR_IOPCEN |\ RCC_AHBENR_IOPDEN | RCC_AHBENR_IOPEEN | RCC_AHBENR_IOPFEN; - putreg32(regval, STM32F0_RCC_AHBENR); + putreg32(regval, STM32_RCC_AHBENR); } diff --git a/arch/arm/src/stm32f0/stm32f0_clockconfig.h b/arch/arm/src/stm32f0l0/stm32_clockconfig.h similarity index 91% rename from arch/arm/src/stm32f0/stm32f0_clockconfig.h rename to arch/arm/src/stm32f0l0/stm32_clockconfig.h index 06f104b524b..af1c4ac9758 100644 --- a/arch/arm/src/stm32f0/stm32f0_clockconfig.h +++ b/arch/arm/src/stm32f0l0/stm32_clockconfig.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/stm32f0_clockconfig.h + * arch/arm/src/stm32f0l0/stm32_clockconfig.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_CLOCKCONFIG_H -#define __ARCH_ARM_SRC_STM32F0_STM32F0_CLOCKCONFIG_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_CLOCKCONFIG_H +#define __ARCH_ARM_SRC_STM32F0L0_STM32_CLOCKCONFIG_H /************************************************************************************ * Included Files @@ -58,7 +58,7 @@ extern "C" ************************************************************************************/ /************************************************************************************ - * Name: stm32f0_clockconfig + * Name: stm32_clockconfig * * Description: * Called to initialize the STM32F0XX. This does whatever setup is needed to put @@ -67,11 +67,11 @@ extern "C" * ************************************************************************************/ -void stm32f0_clockconfig(void); +void stm32_clockconfig(void); #ifdef __cplusplus } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_CLOCKCONFIG_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_CLOCKCONFIG_H */ diff --git a/arch/arm/src/stm32f0/stm32f0_gpio.c b/arch/arm/src/stm32f0l0/stm32_gpio.c similarity index 85% rename from arch/arm/src/stm32f0/stm32f0_gpio.c rename to arch/arm/src/stm32f0l0/stm32_gpio.c index d6ee49b6e92..14801b3225a 100644 --- a/arch/arm/src/stm32f0/stm32f0_gpio.c +++ b/arch/arm/src/stm32f0l0/stm32_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0/stm32f0_gpio.c + * arch/arm/src/stm32f0l0/stm32_gpio.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -47,39 +47,39 @@ #include #include -#include +#include #include "up_arch.h" #include "chip.h" -#include "stm32f0_gpio.h" +#include "stm32_gpio.h" -#include "chip/stm32f0_syscfg.h" +#include "hardware/stm32_syscfg.h" /**************************************************************************** * Public Data ****************************************************************************/ /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32F0_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { -#if STM32F0_NPORTS > 0 - STM32F0_GPIOA_BASE, +#if STM32_NPORTS > 0 + STM32_GPIOA_BASE, #endif -#if STM32F0_NPORTS > 1 - STM32F0_GPIOB_BASE, +#if STM32_NPORTS > 1 + STM32_GPIOB_BASE, #endif -#if STM32F0_NPORTS > 2 - STM32F0_GPIOC_BASE, +#if STM32_NPORTS > 2 + STM32_GPIOC_BASE, #endif -#if STM32F0_NPORTS > 3 - STM32F0_GPIOD_BASE, +#if STM32_NPORTS > 3 + STM32_GPIOD_BASE, #endif -#if STM32F0_NPORTS > 4 - STM32F0_GPIOE_BASE, +#if STM32_NPORTS > 4 + STM32_GPIOE_BASE, #endif -#if STM32F0_NPORTS > 5 - STM32F0_GPIOF_BASE, +#if STM32_NPORTS > 5 + STM32_GPIOF_BASE, #endif }; @@ -88,13 +88,13 @@ const uint32_t g_gpiobase[STM32F0_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32f0_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32f0_start(). + * Typically called from stm32_start(). * * Assumptions: * This function is called early in the initialization sequence so that @@ -102,17 +102,17 @@ const uint32_t g_gpiobase[STM32F0_NPORTS] = * ****************************************************************************/ -void stm32f0_gpioinit(void) +void stm32_gpioinit(void) { } /**************************************************************************** - * Name: stm32f0_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32f0_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -123,7 +123,7 @@ void stm32f0_gpioinit(void) * To-Do: Auto Power Enable ****************************************************************************/ -int stm32f0_configgpio(uint32_t cfgset) +int stm32_configgpio(uint32_t cfgset) { uintptr_t base; uint32_t regval; @@ -138,7 +138,7 @@ int stm32f0_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32F0_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -163,7 +163,7 @@ int stm32f0_configgpio(uint32_t cfgset) break; case GPIO_OUTPUT: /* General purpose output mode */ - stm32f0_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); /* Set the initial output value */ + stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); /* Set the initial output value */ pinmode = GPIO_MODER_OUTPUT; break; @@ -184,10 +184,10 @@ int stm32f0_configgpio(uint32_t cfgset) /* Now apply the configuration to the mode register */ - regval = getreg32(base + STM32F0_GPIO_MODER_OFFSET); + regval = getreg32(base + STM32_GPIO_MODER_OFFSET); regval &= ~GPIO_MODER_MASK(pin); regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); - putreg32(regval, base + STM32F0_GPIO_MODER_OFFSET); + putreg32(regval, base + STM32_GPIO_MODER_OFFSET); /* Set up the pull-up/pull-down configuration (all but analog pins) */ @@ -210,10 +210,10 @@ int stm32f0_configgpio(uint32_t cfgset) } } - regval = getreg32(base + STM32F0_GPIO_PUPDR_OFFSET); + regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); regval &= ~GPIO_PUPDR_MASK(pin); regval |= (setting << GPIO_PUPDR_SHIFT(pin)); - putreg32(regval, base + STM32F0_GPIO_PUPDR_OFFSET); + putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); /* Set the alternate function (Only alternate function pins) */ @@ -228,12 +228,12 @@ int stm32f0_configgpio(uint32_t cfgset) if (pin < 8) { - regoffset = STM32F0_GPIO_AFRL_OFFSET; + regoffset = STM32_GPIO_AFRL_OFFSET; pos = pin; } else { - regoffset = STM32F0_GPIO_AFRH_OFFSET; + regoffset = STM32_GPIO_AFRH_OFFSET; pos = pin - 8; } @@ -267,14 +267,14 @@ int stm32f0_configgpio(uint32_t cfgset) setting = 0; } - regval = getreg32(base + STM32F0_GPIO_OSPEED_OFFSET); + regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); regval &= ~GPIO_OSPEED_MASK(pin); regval |= (setting << GPIO_OSPEED_SHIFT(pin)); - putreg32(regval, base + STM32F0_GPIO_OSPEED_OFFSET); + putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); /* Set push-pull/open-drain (Only outputs and alternate function pins) */ - regval = getreg32(base + STM32F0_GPIO_OTYPER_OFFSET); + regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); setting = GPIO_OTYPER_OD(pin); if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && @@ -287,7 +287,7 @@ int stm32f0_configgpio(uint32_t cfgset) regval &= ~setting; } - putreg32(regval, base + STM32F0_GPIO_OTYPER_OFFSET); + putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); /* Otherwise, it is an input pin. Should it configured as an EXTI interrupt? */ @@ -309,7 +309,7 @@ int stm32f0_configgpio(uint32_t cfgset) /* Set the bits in the SYSCFG EXTICR register */ - regaddr = STM32F0_SYSCFG_EXTICR(pin); + regaddr = STM32_SYSCFG_EXTICR(pin); regval = getreg32(regaddr); shift = SYSCFG_EXTICR_EXTI_SHIFT(pin); regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift); @@ -324,7 +324,7 @@ int stm32f0_configgpio(uint32_t cfgset) } /**************************************************************************** - * Name: stm32f0_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set it @@ -343,7 +343,7 @@ int stm32f0_configgpio(uint32_t cfgset) * To-Do: Auto Power Disable ****************************************************************************/ -int stm32f0_unconfiggpio(uint32_t cfgset) +int stm32_unconfiggpio(uint32_t cfgset) { /* Reuse port and pin number and set it to default HiZ INPUT */ @@ -352,18 +352,18 @@ int stm32f0_unconfiggpio(uint32_t cfgset) /* To-Do: Mark its unuse for automatic power saving options */ - return stm32f0_configgpio(cfgset); + return stm32_configgpio(cfgset); } /**************************************************************************** - * Name: stm32f0_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32f0_gpiowrite(uint32_t pinset, bool value) +void stm32_gpiowrite(uint32_t pinset, bool value) { uint32_t base; uint32_t bit; @@ -371,7 +371,7 @@ void stm32f0_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32F0_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -392,27 +392,27 @@ void stm32f0_gpiowrite(uint32_t pinset, bool value) bit = GPIO_BSRR_RESET(pin); } - putreg32(bit, base + STM32F0_GPIO_BSRR_OFFSET); + putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); } } /**************************************************************************** - * Name: stm32f0_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32f0_gpioread(uint32_t pinset) +bool stm32_gpioread(uint32_t pinset) { uint32_t base; unsigned int port; unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32F0_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -421,7 +421,7 @@ bool stm32f0_gpioread(uint32_t pinset) /* Get the pin number and return the input state of that pin */ pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(base + STM32F0_GPIO_IDR_OFFSET) & (1 << pin)) != 0); + return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); } return 0; diff --git a/arch/arm/src/stm32f0/stm32f0_gpio.h b/arch/arm/src/stm32f0l0/stm32_gpio.h similarity index 92% rename from arch/arm/src/stm32f0/stm32f0_gpio.h rename to arch/arm/src/stm32f0l0/stm32_gpio.h index 14c95cce3f6..67cbfb8e47e 100644 --- a/arch/arm/src/stm32f0/stm32f0_gpio.h +++ b/arch/arm/src/stm32f0l0/stm32_gpio.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/stm32f0_gpio.h + * arch/arm/src/stm32f0l0/stm32_gpio.h * * Copyright (C) 2009, 2011-2012, 2015 Gregory Nutt. All rights reserved. * Copyright (C) 2015-2016 Sebastien Lorquet. All rights reserved. @@ -36,8 +36,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_GPIO_H -#define __ARCH_ARM_SRC_STM32F0_STM32F0_GPIO_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_GPIO_H +#define __ARCH_ARM_SRC_STM32F0L0_STM32_GPIO_H /************************************************************************************ * Included Files @@ -51,16 +51,16 @@ #endif #include -#include +#include #include "chip.h" -#include "chip/stm32f0_pinmap.h" +#include "hardware/stm32_pinmap.h" /************************************************************************************ * Pre-Processor Declarations ************************************************************************************/ -/* Bit-encoded input to stm32f0_configgpio() */ +/* Bit-encoded input to stm32_configgpio() */ /* Each port bit of the general-purpose I/O (GPIO) ports can be individually configured * by software in several modes: @@ -241,19 +241,19 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32F0_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /************************************************************************************ * Public Function Prototypes ************************************************************************************/ /************************************************************************************ - * Name: stm32f0_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32f0_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -262,10 +262,10 @@ EXTERN const uint32_t g_gpiobase[STM32F0_NPORTS]; * ************************************************************************************/ -int stm32f0_configgpio(uint32_t cfgset); +int stm32_configgpio(uint32_t cfgset); /************************************************************************************ - * Name: stm32f0_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set it @@ -283,30 +283,30 @@ int stm32f0_configgpio(uint32_t cfgset); * ************************************************************************************/ -int stm32f0_unconfiggpio(uint32_t cfgset); +int stm32_unconfiggpio(uint32_t cfgset); /************************************************************************************ - * Name: stm32f0_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ************************************************************************************/ -void stm32f0_gpiowrite(uint32_t pinset, bool value); +void stm32_gpiowrite(uint32_t pinset, bool value); /************************************************************************************ - * Name: stm32f0_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ************************************************************************************/ -bool stm32f0_gpioread(uint32_t pinset); +bool stm32_gpioread(uint32_t pinset); /************************************************************************************ - * Name: stm32f0_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -325,11 +325,11 @@ bool stm32f0_gpioread(uint32_t pinset); * ************************************************************************************/ -int stm32f0_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func, void *arg); +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, + bool event, xcpt_t func, void *arg); /************************************************************************************ - * Function: stm32f0_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address @@ -337,23 +337,23 @@ int stm32f0_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ************************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -int stm32f0_dumpgpio(uint32_t pinset, const char *msg); +int stm32_dumpgpio(uint32_t pinset, const char *msg); #else -# define stm32f0_dumpgpio(p,m) +# define stm32_dumpgpio(p,m) #endif /************************************************************************************ - * Function: stm32f0_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32f0_start(). + * Typically called from stm32_start(). * ************************************************************************************/ -void stm32f0_gpioinit(void); +void stm32_gpioinit(void); #undef EXTERN #if defined(__cplusplus) @@ -361,4 +361,4 @@ void stm32f0_gpioinit(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_GPIO_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32f0/stm32f0_hsi48.c b/arch/arm/src/stm32f0l0/stm32_hsi48.c similarity index 86% rename from arch/arm/src/stm32f0/stm32f0_hsi48.c rename to arch/arm/src/stm32f0l0/stm32_hsi48.c index 74230b25aa1..9dfd1a3e848 100644 --- a/arch/arm/src/stm32f0/stm32f0_hsi48.c +++ b/arch/arm/src/stm32f0l0/stm32_hsi48.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0/stm32f0_hsi48.c + * arch/arm/src/stm32f0l0/stm32_hsi48.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -41,17 +41,17 @@ #include "up_arch.h" #include "chip.h" -#include "chip/stm32f0_rcc.h" -#include "chip/stm32f0_crs.h" +#include "hardware/stm32_rcc.h" +#include "hardware/stm32_crs.h" -#include "stm32f0_hsi48.h" +#include "stm32_hsi48.h" /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32f0_enable_hsi48 + * Name: stm32_enable_hsi48 * * Description: * On STM32F04x, STM32F07x and STM32F09x devices only, the HSI48 clock @@ -77,7 +77,7 @@ * ****************************************************************************/ -void stm32f0_enable_hsi48(enum syncsrc_e syncsrc) +void stm32_enable_hsi48(enum syncsrc_e syncsrc) { uint32_t regval; @@ -93,22 +93,22 @@ void stm32f0_enable_hsi48(enum syncsrc_e syncsrc) * enabled. */ - regval = getreg32(STM32F0_RCC_CR2); + regval = getreg32(STM32_RCC_CR2); regval |= RCC_CR2_HSI48ON; - putreg32(regval, STM32F0_RCC_CR2); + putreg32(regval, STM32_RCC_CR2); if (syncsrc == SYNCSRC_USB) { /* Select the HSI48 as the USB clock source */ - regval = getreg32(STM32F0_RCC_CFGR3); + regval = getreg32(STM32_RCC_CFGR3); regval &= ~RCC_CFGR3_USBSW; - putreg32(regval, STM32F0_RCC_CFGR3); + putreg32(regval, STM32_RCC_CFGR3); } /* Wait for the HSI48 clock to stabilize */ - while ((getreg32(STM32F0_RCC_CR2) & RCC_CR2_HSI48RDY) == 0); + while ((getreg32(STM32_RCC_CR2) & RCC_CR2_HSI48RDY) == 0); /* The CRS synchronization (SYNC) source, selectable through the CRS_CFGR @@ -116,7 +116,7 @@ void stm32f0_enable_hsi48(enum syncsrc_e syncsrc) * clock or the USB SOF signal. */ - regval = getreg32(STM32F0_CRS_CFGR); + regval = getreg32(STM32_CRS_CFGR); regval &= ~CRS_CFGR_SYNCSRC_MASK; switch (syncsrc) @@ -135,20 +135,20 @@ void stm32f0_enable_hsi48(enum syncsrc_e syncsrc) break; } - putreg32(regval, STM32F0_CRS_CFGR); + putreg32(regval, STM32_CRS_CFGR); /* Set the AUTOTRIMEN bit the CRS_CR register to enables the automatic * hardware adjustment of TRIM bits according to the measured frequency * error between the selected SYNC event. */ - regval = getreg32(STM32F0_CRS_CR); + regval = getreg32(STM32_CRS_CR); regval |= CRS_CR_AUTOTRIMEN; - putreg32(regval, STM32F0_CRS_CR); + putreg32(regval, STM32_CRS_CR); } /**************************************************************************** - * Name: stm32f0_disable_hsi48 + * Name: stm32_disable_hsi48 * * Description: * Disable the HSI48 clock. @@ -161,23 +161,23 @@ void stm32f0_enable_hsi48(enum syncsrc_e syncsrc) * ****************************************************************************/ -void stm32f0_disable_hsi48(void) +void stm32_disable_hsi48(void) { uint32_t regval; /* Disable the HSI48 clock */ - regval = getreg32(STM32F0_RCC_CR2); + regval = getreg32(STM32_RCC_CR2); regval &= ~RCC_CR2_HSI48ON; - putreg32(regval, STM32F0_RCC_CR2); + putreg32(regval, STM32_RCC_CR2); /* Set other registers to the default settings. */ - regval = getreg32(STM32F0_CRS_CFGR); + regval = getreg32(STM32_CRS_CFGR); regval &= ~CRS_CFGR_SYNCSRC_MASK; - putreg32(regval, STM32F0_CRS_CFGR); + putreg32(regval, STM32_CRS_CFGR); - regval = getreg32(STM32F0_CRS_CR); + regval = getreg32(STM32_CRS_CR); regval &= ~CRS_CR_AUTOTRIMEN; - putreg32(regval, STM32F0_CRS_CR); + putreg32(regval, STM32_CRS_CR); } diff --git a/arch/arm/src/stm32f0/stm32f0_hsi48.h b/arch/arm/src/stm32f0l0/stm32_hsi48.h similarity index 91% rename from arch/arm/src/stm32f0/stm32f0_hsi48.h rename to arch/arm/src/stm32f0l0/stm32_hsi48.h index 6c9eb38b107..a8772b6197a 100644 --- a/arch/arm/src/stm32f0/stm32f0_hsi48.h +++ b/arch/arm/src/stm32f0l0/stm32_hsi48.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/stm32f0_rcc.h + * arch/arm/src/stm32f0l0/stm32_rcc.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_HSI48_H -#define __ARCH_ARM_SRC_STM32F0_STM32F0_HSI48_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_HSI48_H +#define __ARCH_ARM_SRC_STM32F0L0_STM32_HSI48_H /************************************************************************************ * Included Files @@ -43,7 +43,7 @@ #include -#ifdef CONFIG_STM32F0_HAVE_HSI48 +#ifdef CONFIG_STM32F0L0_HAVE_HSI48 /************************************************************************************ * Public Types @@ -61,7 +61,7 @@ enum syncsrc_e ************************************************************************************/ /**************************************************************************** - * Name: stm32f0_enable_hsi48 + * Name: stm32_enable_hsi48 * * Description: * On STM32F04x, STM32F07x and STM32F09x devices only, the HSI48 clock @@ -87,10 +87,10 @@ enum syncsrc_e * ****************************************************************************/ -void stm32f0_enable_hsi48(enum syncsrc_e syncsrc); +void stm32_enable_hsi48(enum syncsrc_e syncsrc); /**************************************************************************** - * Name: stm32f0_disable_hsi48 + * Name: stm32_disable_hsi48 * * Description: * Disable the HSI48 clock. @@ -103,7 +103,7 @@ void stm32f0_enable_hsi48(enum syncsrc_e syncsrc); * ****************************************************************************/ -void stm32f0_disable_hsi48(void); +void stm32_disable_hsi48(void); -#endif /* CONFIG_STM32F0_HAVE_HSI48 */ -#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_HSI48_H */ +#endif /* CONFIG_STM32F0L0_HAVE_HSI48 */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_HSI48_H */ diff --git a/arch/arm/src/stm32f0/stm32f0_i2c.c b/arch/arm/src/stm32f0l0/stm32_i2c.c similarity index 72% rename from arch/arm/src/stm32f0/stm32f0_i2c.c rename to arch/arm/src/stm32f0l0/stm32_i2c.c index a8d0500aaea..d3f4a705c0b 100644 --- a/arch/arm/src/stm32f0/stm32f0_i2c.c +++ b/arch/arm/src/stm32f0l0/stm32_i2c.c @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32l4/stm32f0_i2c.c + * arch/arm/src/stm32f0l0/stm32_i2c.c * STM32L4 I2C driver - based on STM32F3 I2C Hardware Layer - Device Driver * * Copyright (C) 2011 Uros Platise. All rights reserved. @@ -91,13 +91,13 @@ #include "up_arch.h" -#include "stm32f0_gpio.h" -#include "stm32f0_rcc.h" -#include "stm32f0_i2c.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" +#include "stm32_i2c.h" /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32F0_I2C1) || defined(CONFIG_STM32F0_I2C2) || defined(CONFIG_STM32F0_I2C3) +#if defined(CONFIG_STM32F0L0_I2C1) || defined(CONFIG_STM32F0L0_I2C2) || defined(CONFIG_STM32F0L0_I2C3) /************************************************************************************ * Pre-processor Definitions @@ -110,24 +110,24 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32F0_I2CTIMEOSEC) && !defined(CONFIG_STM32F0_I2CTIMEOMS) -# define CONFIG_STM32F0_I2CTIMEOSEC 0 -# define CONFIG_STM32F0_I2CTIMEOMS 500 /* Default is 500 milliseconds */ -#elif !defined(CONFIG_STM32F0_I2CTIMEOSEC) -# define CONFIG_STM32F0_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32F0_I2CTIMEOMS) -# define CONFIG_STM32F0_I2CTIMEOMS 0 /* User provided seconds */ +#if !defined(CONFIG_STM32F0L0_I2CTIMEOSEC) && !defined(CONFIG_STM32F0L0_I2CTIMEOMS) +# define CONFIG_STM32F0L0_I2CTIMEOSEC 0 +# define CONFIG_STM32F0L0_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#elif !defined(CONFIG_STM32F0L0_I2CTIMEOSEC) +# define CONFIG_STM32F0L0_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32F0L0_I2CTIMEOMS) +# define CONFIG_STM32F0L0_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32F0_I2CTIMEOTICKS -# define CONFIG_STM32F0_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32F0_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32F0_I2CTIMEOMS)) +#ifndef CONFIG_STM32F0L0_I2CTIMEOTICKS +# define CONFIG_STM32F0L0_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32F0L0_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32F0L0_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32F0_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32F0_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32F0_I2CTIMEOTICKS) +#ifndef CONFIG_STM32F0L0_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32F0L0_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32F0L0_I2CTIMEOTICKS) #endif #define I2C_OUTPUT \ @@ -156,10 +156,10 @@ */ #ifndef CONFIG_I2C_TRACE -# define stm32f0_i2c_tracereset(p) -# define stm32f0_i2c_tracenew(p,s) -# define stm32f0_i2c_traceevent(p,e,a) -# define stm32f0_i2c_tracedump(p) +# define stm32_i2c_tracereset(p) +# define stm32_i2c_tracenew(p,s) +# define stm32_i2c_traceevent(p,e,a) +# define stm32_i2c_tracedump(p) #endif #ifndef CONFIG_I2C_NTRACE @@ -171,7 +171,7 @@ ************************************************************************************/ /* Interrupt state */ -enum stm32f0_intstate_e +enum stm32_intstate_e { INTSTATE_IDLE = 0, /* No I2C activity */ INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ @@ -180,7 +180,7 @@ enum stm32f0_intstate_e /* Trace events */ -enum stm32f0_trace_e +enum stm32_trace_e { I2CEVENT_NONE = 0, /* No events have occurred with this status */ I2CEVENT_SENDADDR, /* Start/Master bit set and address sent, param = msgc */ @@ -197,18 +197,18 @@ enum stm32f0_trace_e /* Trace data */ -struct stm32f0_trace_s +struct stm32_trace_s { uint32_t status; /* I2C 32-bit SR2|SR1 status */ uint32_t count; /* Interrupt count when status change */ - enum stm32f0_intstate_e event; /* Last event that occurred with this status */ + enum stm32_intstate_e event; /* Last event that occurred with this status */ uint32_t parm; /* Parameter associated with the event */ clock_t time; /* First of event or first status */ }; /* I2C Device hardware configuration */ -struct stm32f0_i2c_config_s +struct stm32_i2c_config_s { uint32_t base; /* I2C base address */ uint32_t clk_bit; /* Clock enable bit */ @@ -222,16 +222,16 @@ struct stm32f0_i2c_config_s /* I2C Device Private Data */ -struct stm32f0_i2c_priv_s +struct stm32_i2c_priv_s { const struct i2c_ops_s *ops; /* Standard I2C operations */ - const struct stm32f0_i2c_config_s *config; /* Port configuration */ + const struct stm32_i2c_config_s *config; /* Port configuration */ int refs; /* Reference count */ sem_t sem_excl; /* Mutual exclusion semaphore */ #ifndef CONFIG_I2C_POLLED sem_t sem_isr; /* Interrupt wait semaphore */ #endif - volatile uint8_t intstate; /* Interrupt handshake (see enum stm32f0_intstate_e) */ + volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */ uint8_t msgc; /* Message count */ struct i2c_msg_s *msgv; /* Message list */ @@ -249,7 +249,7 @@ struct stm32f0_i2c_priv_s /* The actual trace data */ - struct stm32f0_trace_s trace[CONFIG_I2C_NTRACE]; + struct stm32_trace_s trace[CONFIG_I2C_NTRACE]; #endif uint32_t status; /* End of transfer SR2|SR1 status */ @@ -259,46 +259,46 @@ struct stm32f0_i2c_priv_s * Private Function Prototypes ************************************************************************************/ -static inline uint32_t stm32f0_i2c_getreg32(FAR struct stm32f0_i2c_priv_s *priv, - uint8_t offset); -static inline void stm32f0_i2c_putreg32(FAR struct stm32f0_i2c_priv_s *priv, - uint8_t offset, uint32_t value); -static inline void stm32f0_i2c_modifyreg32(FAR struct stm32f0_i2c_priv_s *priv, +static inline uint32_t stm32_i2c_getreg32(FAR struct stm32_i2c_priv_s *priv, + uint8_t offset); +static inline void stm32_i2c_putreg32(FAR struct stm32_i2c_priv_s *priv, + uint8_t offset, uint32_t value); +static inline void stm32_i2c_modifyreg32(FAR struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -static inline void stm32f0_i2c_sem_wait(FAR struct stm32f0_i2c_priv_s *priv); -#ifdef CONFIG_STM32F0_I2C_DYNTIMEO -static useconds_t stm32f0_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32F0_I2C_DYNTIMEO */ -static inline int stm32f0_i2c_sem_waitdone(FAR struct stm32f0_i2c_priv_s *priv); -static inline void stm32f0_i2c_sem_waitstop(FAR struct stm32f0_i2c_priv_s *priv); -static inline void stm32f0_i2c_sem_post(FAR struct stm32f0_i2c_priv_s *priv); -static inline void stm32f0_i2c_sem_init(FAR struct stm32f0_i2c_priv_s *priv); -static inline void stm32f0_i2c_sem_destroy(FAR struct stm32f0_i2c_priv_s *priv); +static inline void stm32_i2c_sem_wait(FAR struct stm32_i2c_priv_s *priv); +#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO +static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs); +#endif /* CONFIG_STM32F0L0_I2C_DYNTIMEO */ +static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sem_post(FAR struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sem_destroy(FAR struct stm32_i2c_priv_s *priv); #ifdef CONFIG_I2C_TRACE -static void stm32f0_i2c_tracereset(FAR struct stm32f0_i2c_priv_s *priv); -static void stm32f0_i2c_tracenew(FAR struct stm32f0_i2c_priv_s *priv, - uint32_t status); -static void stm32f0_i2c_traceevent(FAR struct stm32f0_i2c_priv_s *priv, - enum stm32f0_trace_e event, uint32_t parm); -static void stm32f0_i2c_tracedump(FAR struct stm32f0_i2c_priv_s *priv); +static void stm32_i2c_tracereset(FAR struct stm32_i2c_priv_s *priv); +static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, + uint32_t status); +static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm); +static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv); #endif /* CONFIG_I2C_TRACE */ -static void stm32f0_i2c_setclock(FAR struct stm32f0_i2c_priv_s *priv, - uint32_t frequency); -static inline void stm32f0_i2c_sendstart(FAR struct stm32f0_i2c_priv_s *priv); -static inline void stm32f0_i2c_clrstart(FAR struct stm32f0_i2c_priv_s *priv); -static inline void stm32f0_i2c_sendstop(FAR struct stm32f0_i2c_priv_s *priv); -static inline uint32_t stm32f0_i2c_getstatus(FAR struct stm32f0_i2c_priv_s *priv); -static int stm32f0_i2c_isr_process(struct stm32f0_i2c_priv_s * priv); +static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, + uint32_t frequency); +static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_clrstart(FAR struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv); +static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv); +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s * priv); #ifndef CONFIG_I2C_POLLED -static int stm32f0_i2c_isr(int irq, void *context, FAR void *arg); +static int stm32_i2c_isr(int irq, void *context, FAR void *arg); #endif -static int stm32f0_i2c_init(FAR struct stm32f0_i2c_priv_s *priv); -static int stm32f0_i2c_deinit(FAR struct stm32f0_i2c_priv_s *priv); -static int stm32f0_i2c_transfer(FAR struct i2c_master_s *dev, - FAR struct i2c_msg_s *msgs, int count); +static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv); +static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv); +static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, + FAR struct i2c_msg_s *msgs, int count); #ifdef CONFIG_I2C_RESET -static int stm32f0_i2c_reset(FAR struct i2c_master_s *dev); +static int stm32_i2c_reset(FAR struct i2c_master_s *dev); #endif /************************************************************************************ @@ -307,31 +307,31 @@ static int stm32f0_i2c_reset(FAR struct i2c_master_s *dev); /* Device Structures, Instantiation */ -static const struct i2c_ops_s stm32f0_i2c_ops = +static const struct i2c_ops_s stm32_i2c_ops = { - .transfer = stm32f0_i2c_transfer + .transfer = stm32_i2c_transfer #ifdef CONFIG_I2C_RESET - , .reset = stm32f0_i2c_reset + , .reset = stm32_i2c_reset #endif }; -#ifdef CONFIG_STM32F0_I2C1 -static const struct stm32f0_i2c_config_s stm32f0_i2c1_config = +#ifdef CONFIG_STM32F0L0_I2C1 +static const struct stm32_i2c_config_s stm32_i2c1_config = { - .base = STM32F0_I2C1_BASE, + .base = STM32_I2C1_BASE, .clk_bit = RCC_APB1ENR_I2C1EN, .reset_bit = RCC_APB1RSTR_I2C1RST, .scl_pin = GPIO_I2C1_SCL, .sda_pin = GPIO_I2C1_SDA, #ifndef CONFIG_I2C_POLLED - .irq = STM32F0_IRQ_I2C1 + .irq = STM32_IRQ_I2C1 #endif }; -static struct stm32f0_i2c_priv_s stm32f0_i2c1_priv = +static struct stm32_i2c_priv_s stm32_i2c1_priv = { - .ops = &stm32f0_i2c_ops, - .config = &stm32f0_i2c1_config, + .ops = &stm32_i2c_ops, + .config = &stm32_i2c1_config, .refs = 0, .intstate = INTSTATE_IDLE, .msgc = 0, @@ -343,23 +343,23 @@ static struct stm32f0_i2c_priv_s stm32f0_i2c1_priv = }; #endif -#ifdef CONFIG_STM32F0_I2C2 -static const struct stm32f0_i2c_config_s stm32f0_i2c2_config = +#ifdef CONFIG_STM32F0L0_I2C2 +static const struct stm32_i2c_config_s stm32_i2c2_config = { - .base = STM32F0_I2C2_BASE, + .base = STM32_I2C2_BASE, .clk_bit = RCC_APB1ENR1_I2C2EN, .reset_bit = RCC_APB1RSTR1_I2C2RST, .scl_pin = GPIO_I2C2_SCL, .sda_pin = GPIO_I2C2_SDA, #ifndef CONFIG_I2C_POLLED - .irq = STM32F0_IRQ_I2C2 + .irq = STM32_IRQ_I2C2 #endif }; -static struct stm32f0_i2c_priv_s stm32f0_i2c2_priv = +static struct stm32_i2c_priv_s stm32_i2c2_priv = { - .ops = &stm32f0_i2c_ops, - .config = &stm32f0_i2c2_config, + .ops = &stm32_i2c_ops, + .config = &stm32_i2c2_config, .refs = 0, .intstate = INTSTATE_IDLE, .msgc = 0, @@ -371,23 +371,23 @@ static struct stm32f0_i2c_priv_s stm32f0_i2c2_priv = }; #endif -#ifdef CONFIG_STM32F0_I2C3 -static const struct stm32f0_i2c_config_s stm32f0_i2c3_config = +#ifdef CONFIG_STM32F0L0_I2C3 +static const struct stm32_i2c_config_s stm32_i2c3_config = { - .base = STM32F0_I2C3_BASE, + .base = STM32_I2C3_BASE, .clk_bit = RCC_APB1ENR1_I2C3EN, .reset_bit = RCC_APB1RSTR1_I2C3RST, .scl_pin = GPIO_I2C3_SCL, .sda_pin = GPIO_I2C3_SDA, #ifndef CONFIG_I2C_POLLED - .irq = STM32F0_IRQ_I2C3 + .irq = STM32_IRQ_I2C3 #endif }; -static struct stm32f0_i2c_priv_s stm32f0_i2c3_priv = +static struct stm32_i2c_priv_s stm32_i2c3_priv = { - .ops = &stm32f0_i2c_ops, - .config = &stm32f0_i2c3_config, + .ops = &stm32_i2c_ops, + .config = &stm32_i2c3_config, .refs = 0, .intstate = INTSTATE_IDLE, .msgc = 0, @@ -404,42 +404,42 @@ static struct stm32f0_i2c_priv_s stm32f0_i2c3_priv = ************************************************************************************/ /************************************************************************************ - * Name: stm32f0_i2c_getreg32 + * Name: stm32_i2c_getreg32 * * Description: * Get a 32-bit register value by offset * ************************************************************************************/ -static inline uint32_t stm32f0_i2c_getreg32(FAR struct stm32f0_i2c_priv_s *priv, - uint8_t offset) +static inline uint32_t stm32_i2c_getreg32(FAR struct stm32_i2c_priv_s *priv, + uint8_t offset) { return getreg32(priv->config->base + offset); } /************************************************************************************ - * Name: stm32f0_i2c_putreg32 + * Name: stm32_i2c_putreg32 * * Description: * Put a 32-bit register value by offset * ************************************************************************************/ -static inline void stm32f0_i2c_putreg32(FAR struct stm32f0_i2c_priv_s *priv, - uint8_t offset, uint32_t value) +static inline void stm32_i2c_putreg32(FAR struct stm32_i2c_priv_s *priv, + uint8_t offset, uint32_t value) { putreg32(value, priv->config->base + offset); } /************************************************************************************ - * Name: stm32f0_i2c_modifyreg32 + * Name: stm32_i2c_modifyreg32 * * Description: * Modify a 32-bit register value by offset * ************************************************************************************/ -static inline void stm32f0_i2c_modifyreg32(FAR struct stm32f0_i2c_priv_s *priv, +static inline void stm32_i2c_modifyreg32(FAR struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits) { @@ -447,14 +447,14 @@ static inline void stm32f0_i2c_modifyreg32(FAR struct stm32f0_i2c_priv_s *priv, } /************************************************************************************ - * Name: stm32f0_i2c_sem_wait + * Name: stm32_i2c_sem_wait * * Description: * Take the exclusive access, waiting as necessary * ************************************************************************************/ -static inline void stm32f0_i2c_sem_wait(FAR struct stm32f0_i2c_priv_s *priv) +static inline void stm32_i2c_sem_wait(FAR struct stm32_i2c_priv_s *priv) { int ret; @@ -474,15 +474,15 @@ static inline void stm32f0_i2c_sem_wait(FAR struct stm32f0_i2c_priv_s *priv) } /************************************************************************************ - * Name: stm32f0_i2c_tousecs + * Name: stm32_i2c_tousecs * * Description: * Return a micro-second delay based on the number of bytes left to be processed. * ************************************************************************************/ -#ifdef CONFIG_STM32F0_I2C_DYNTIMEO -static useconds_t stm32f0_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs) +#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO +static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs) { size_t bytecount = 0; int i; @@ -498,12 +498,12 @@ static useconds_t stm32f0_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs) * factor. */ - return (useconds_t)(CONFIG_STM32F0_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return (useconds_t)(CONFIG_STM32F0L0_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif /************************************************************************************ - * Name: stm32f0_i2c_enableinterrupts + * Name: stm32_i2c_enableinterrupts * * Description: * Enable I2C interrupts @@ -511,14 +511,14 @@ static useconds_t stm32f0_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs) ************************************************************************************/ #ifndef CONFIG_I2C_POLLED -static inline void stm32f0_i2c_enableinterrupts(struct stm32f0_i2c_priv_s *priv) +static inline void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv) { - stm32f0_i2c_modifyreg32(priv, STM32F0_I2C_CR1_OFFSET, 0, I2C_CR1_TXRX); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_TXRX); } #endif /************************************************************************************ - * Name: stm32f0_i2c_disableinterrupts + * Name: stm32_i2c_disableinterrupts * * Description: * Enable I2C interrupts @@ -526,14 +526,14 @@ static inline void stm32f0_i2c_enableinterrupts(struct stm32f0_i2c_priv_s *priv) ************************************************************************************/ #ifndef CONFIG_I2C_POLLED -static inline void stm32f0_i2c_disableinterrupts(struct stm32f0_i2c_priv_s *priv) +static inline void stm32_i2c_disableinterrupts(struct stm32_i2c_priv_s *priv) { - stm32f0_i2c_modifyreg32(priv, STM32F0_I2C_CR1_OFFSET, I2C_CR1_TXRX, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_TXRX, 0); } #endif /************************************************************************************ - * Name: stm32f0_i2c_sem_waitdone + * Name: stm32_i2c_sem_waitdone * * Description: * Wait for a transfer to complete @@ -541,7 +541,7 @@ static inline void stm32f0_i2c_disableinterrupts(struct stm32f0_i2c_priv_s *priv ************************************************************************************/ #ifndef CONFIG_I2C_POLLED -static inline int stm32f0_i2c_sem_waitdone(FAR struct stm32f0_i2c_priv_s *priv) +static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv) { struct timespec abstime; irqstate_t flags; @@ -551,7 +551,7 @@ static inline int stm32f0_i2c_sem_waitdone(FAR struct stm32f0_i2c_priv_s *priv) /* Enable I2C interrupts */ - stm32f0_i2c_modifyreg32(priv, STM32F0_I2C_CR1_OFFSET, 0, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX)); /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -568,22 +568,22 @@ static inline int stm32f0_i2c_sem_waitdone(FAR struct stm32f0_i2c_priv_s *priv) /* Calculate a time in the future */ -#if CONFIG_STM32F0_I2CTIMEOSEC > 0 - abstime.tv_sec += CONFIG_STM32F0_I2CTIMEOSEC; +#if CONFIG_STM32F0L0_I2CTIMEOSEC > 0 + abstime.tv_sec += CONFIG_STM32F0L0_I2CTIMEOSEC; #endif /* Add a value proportional to the number of bytes in the transfer */ -#ifdef CONFIG_STM32F0_I2C_DYNTIMEO - abstime.tv_nsec += 1000 * stm32f0_i2c_tousecs(priv->msgc, priv->msgv); +#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO + abstime.tv_nsec += 1000 * stm32_i2c_tousecs(priv->msgc, priv->msgv); if (abstime.tv_nsec >= 1000 * 1000 * 1000) { abstime.tv_sec++; abstime.tv_nsec -= 1000 * 1000 * 1000; } -#elif CONFIG_STM32F0_I2CTIMEOMS > 0 - abstime.tv_nsec += CONFIG_STM32F0_I2CTIMEOMS * 1000 * 1000; +#elif CONFIG_STM32F0L0_I2CTIMEOMS > 0 + abstime.tv_nsec += CONFIG_STM32F0L0_I2CTIMEOMS * 1000 * 1000; if (abstime.tv_nsec >= 1000 * 1000 * 1000) { abstime.tv_sec++; @@ -614,13 +614,13 @@ static inline int stm32f0_i2c_sem_waitdone(FAR struct stm32f0_i2c_priv_s *priv) /* Disable I2C interrupts */ - stm32f0_i2c_modifyreg32(priv, STM32F0_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); leave_critical_section(flags); return ret; } #else -static inline int stm32f0_i2c_sem_waitdone(FAR struct stm32f0_i2c_priv_s *priv) +static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv) { clock_t timeout; clock_t start; @@ -629,10 +629,10 @@ static inline int stm32f0_i2c_sem_waitdone(FAR struct stm32f0_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32F0_I2C_DYNTIMEO - timeout = USEC2TICK(stm32f0_i2c_tousecs(priv->msgc, priv->msgv)); +#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO + timeout = USEC2TICK(stm32_i2c_tousecs(priv->msgc, priv->msgv)); #else - timeout = CONFIG_STM32F0_I2CTIMEOTICKS; + timeout = CONFIG_STM32F0L0_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -653,7 +653,7 @@ static inline int stm32f0_i2c_sem_waitdone(FAR struct stm32f0_i2c_priv_s *priv) * reports that it is done. */ - stm32f0_i2c_isr_process(priv); + stm32_i2c_isr_process(priv); } /* Loop until the transfer is complete. */ @@ -672,95 +672,95 @@ static inline int stm32f0_i2c_sem_waitdone(FAR struct stm32f0_i2c_priv_s *priv) #endif /************************************************************************************ - * Name: stm32f0_i2c_set_7bit_address + * Name: stm32_i2c_set_7bit_address * * Description: * ************************************************************************************/ static inline void -stm32f0_i2c_set_7bit_address(FAR struct stm32f0_i2c_priv_s *priv) +stm32_i2c_set_7bit_address(FAR struct stm32_i2c_priv_s *priv) { - stm32f0_i2c_modifyreg32(priv, STM32F0_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, ((priv->msgv->addr & 0x7F) << I2C_CR2_SADD7_SHIFT)); } /************************************************************************************ - * Name: stm32f0_i2c_set_bytes_to_transfer + * Name: stm32_i2c_set_bytes_to_transfer * * Description: * ************************************************************************************/ static inline void -stm32f0_i2c_set_bytes_to_transfer(FAR struct stm32f0_i2c_priv_s *priv, - uint8_t n_bytes) +stm32_i2c_set_bytes_to_transfer(FAR struct stm32_i2c_priv_s *priv, + uint8_t n_bytes) { - stm32f0_i2c_modifyreg32(priv, STM32F0_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, (n_bytes << I2C_CR2_NBYTES_SHIFT)); } /************************************************************************************ - * Name: stm32f0_i2c_set_write_transfer_dir + * Name: stm32_i2c_set_write_transfer_dir * * Description: * ************************************************************************************/ static inline void -stm32f0_i2c_set_write_transfer_dir(FAR struct stm32f0_i2c_priv_s *priv) +stm32_i2c_set_write_transfer_dir(FAR struct stm32_i2c_priv_s *priv) { - stm32f0_i2c_modifyreg32(priv, STM32F0_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); } /************************************************************************************ - * Name: stm32f0_i2c_set_read_transfer_dir + * Name: stm32_i2c_set_read_transfer_dir * * Description: * ************************************************************************************/ static inline void -stm32f0_i2c_set_read_transfer_dir(FAR struct stm32f0_i2c_priv_s *priv) +stm32_i2c_set_read_transfer_dir(FAR struct stm32_i2c_priv_s *priv) { - stm32f0_i2c_modifyreg32(priv, STM32F0_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN); } /************************************************************************************ - * Name: stm32f0_i2c_enable_autoend + * Name: stm32_i2c_enable_autoend * * Description: * ************************************************************************************/ static inline void -stm32f0_i2c_enable_autoend(FAR struct stm32f0_i2c_priv_s *priv) +stm32_i2c_enable_autoend(FAR struct stm32_i2c_priv_s *priv) { - stm32f0_i2c_modifyreg32(priv, STM32F0_I2C_CR2_OFFSET, 0, I2C_CR2_AUTOEND); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_AUTOEND); } /************************************************************************************ - * Name: stm32f0_i2c_disable_autoend + * Name: stm32_i2c_disable_autoend * * Description: * ************************************************************************************/ static inline void -stm32f0_i2c_disable_autoend(FAR struct stm32f0_i2c_priv_s *priv) +stm32_i2c_disable_autoend(FAR struct stm32_i2c_priv_s *priv) { - stm32f0_i2c_modifyreg32(priv, STM32F0_I2C_CR2_OFFSET, I2C_CR2_AUTOEND, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_AUTOEND, 0); } /************************************************************************************ - * Name: stm32f0_i2c_sem_waitstop + * Name: stm32_i2c_sem_waitstop * * Description: * Wait for a STOP to complete * ************************************************************************************/ -static inline void stm32f0_i2c_sem_waitstop(FAR struct stm32f0_i2c_priv_s *priv) +static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv) { clock_t start; clock_t elapsed; @@ -770,10 +770,10 @@ static inline void stm32f0_i2c_sem_waitstop(FAR struct stm32f0_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32F0_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32F0_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32F0L0_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32F0_I2CTIMEOTICKS; + timeout = CONFIG_STM32F0L0_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress; but stop might also @@ -791,7 +791,7 @@ static inline void stm32f0_i2c_sem_waitstop(FAR struct stm32f0_i2c_priv_s *priv) /* Check for STOP condition */ - cr = stm32f0_i2c_getreg32(priv, STM32F0_I2C_CR2_OFFSET); + cr = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); if ((cr & I2C_CR2_STOP) == 0) { return; @@ -799,7 +799,7 @@ static inline void stm32f0_i2c_sem_waitstop(FAR struct stm32f0_i2c_priv_s *priv) /* Check for timeout error */ - sr = stm32f0_i2c_getreg32(priv, STM32F0_I2C_ISR_OFFSET); + sr = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); if ((sr & I2C_INT_TIMEOUT) != 0) { return; @@ -818,27 +818,27 @@ static inline void stm32f0_i2c_sem_waitstop(FAR struct stm32f0_i2c_priv_s *priv) } /************************************************************************************ - * Name: stm32f0_i2c_sem_post + * Name: stm32_i2c_sem_post * * Description: * Release the mutual exclusion semaphore * ************************************************************************************/ -static inline void stm32f0_i2c_sem_post(FAR struct stm32f0_i2c_priv_s *priv) +static inline void stm32_i2c_sem_post(FAR struct stm32_i2c_priv_s *priv) { nxsem_post(&priv->sem_excl); } /************************************************************************************ - * Name: stm32f0_i2c_sem_init + * Name: stm32_i2c_sem_init * * Description: * Initialize semaphores * ************************************************************************************/ -static inline void stm32f0_i2c_sem_init(FAR struct stm32f0_i2c_priv_s *priv) +static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv) { nxsem_init(&priv->sem_excl, 0, 1); @@ -853,14 +853,14 @@ static inline void stm32f0_i2c_sem_init(FAR struct stm32f0_i2c_priv_s *priv) } /************************************************************************************ - * Name: stm32f0_i2c_sem_destroy + * Name: stm32_i2c_sem_destroy * * Description: * Destroy semaphores. * ************************************************************************************/ -static inline void stm32f0_i2c_sem_destroy(FAR struct stm32f0_i2c_priv_s *priv) +static inline void stm32_i2c_sem_destroy(FAR struct stm32_i2c_priv_s *priv) { nxsem_destroy(&priv->sem_excl); #ifndef CONFIG_I2C_POLLED @@ -869,7 +869,7 @@ static inline void stm32f0_i2c_sem_destroy(FAR struct stm32f0_i2c_priv_s *priv) } /************************************************************************************ - * Name: stm32f0_i2c_trace* + * Name: stm32_i2c_trace* * * Description: * I2C trace instrumentation @@ -877,9 +877,9 @@ static inline void stm32f0_i2c_sem_destroy(FAR struct stm32f0_i2c_priv_s *priv) ************************************************************************************/ #ifdef CONFIG_I2C_TRACE -static void stm32f0_i2c_traceclear(FAR struct stm32f0_i2c_priv_s *priv) +static void stm32_i2c_traceclear(FAR struct stm32_i2c_priv_s *priv) { - struct stm32f0_trace_s *trace = &priv->trace[priv->tndx]; + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; trace->status = 0; /* I2C 32-bit SR2|SR1 status */ trace->count = 0; /* Interrupt count when status change */ @@ -888,19 +888,19 @@ static void stm32f0_i2c_traceclear(FAR struct stm32f0_i2c_priv_s *priv) trace->time = 0; /* Time of first status or event */ } -static void stm32f0_i2c_tracereset(FAR struct stm32f0_i2c_priv_s *priv) +static void stm32_i2c_tracereset(FAR struct stm32_i2c_priv_s *priv) { /* Reset the trace info for a new data collection */ priv->tndx = 0; priv->start_time = clock_systimer(); - stm32f0_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); } -static void stm32f0_i2c_tracenew(FAR struct stm32f0_i2c_priv_s *priv, +static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint32_t status) { - struct stm32f0_trace_s *trace = &priv->trace[priv->tndx]; + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; /* Is the current entry uninitialized? Has the status changed? */ @@ -924,7 +924,7 @@ static void stm32f0_i2c_tracenew(FAR struct stm32f0_i2c_priv_s *priv, /* Initialize the new trace entry */ - stm32f0_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); trace->status = status; trace->count = 1; trace->time = clock_systimer(); @@ -937,10 +937,10 @@ static void stm32f0_i2c_tracenew(FAR struct stm32f0_i2c_priv_s *priv, } } -static void stm32f0_i2c_traceevent(FAR struct stm32f0_i2c_priv_s *priv, - enum stm32f0_trace_e event, uint32_t parm) +static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm) { - struct stm32f0_trace_s *trace; + struct stm32_trace_s *trace; if (event != I2CEVENT_NONE) { @@ -960,13 +960,13 @@ static void stm32f0_i2c_traceevent(FAR struct stm32f0_i2c_priv_s *priv, } priv->tndx++; - stm32f0_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); } } -static void stm32f0_i2c_tracedump(FAR struct stm32f0_i2c_priv_s *priv) +static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv) { - struct stm32f0_trace_s *trace; + struct stm32_trace_s *trace; int i; syslog(LOG_DEBUG, "Elapsed time: %ld\n", @@ -984,14 +984,14 @@ static void stm32f0_i2c_tracedump(FAR struct stm32f0_i2c_priv_s *priv) #endif /* CONFIG_I2C_TRACE */ /************************************************************************************ - * Name: stm32f0_i2c_setclock + * Name: stm32_i2c_setclock * * Description: * Set the I2C clock * ************************************************************************************/ -static void stm32f0_i2c_setclock(FAR struct stm32f0_i2c_priv_s *priv, uint32_t frequency) +static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequency) { uint32_t pe; uint8_t presc; @@ -1028,16 +1028,16 @@ static void stm32f0_i2c_setclock(FAR struct stm32f0_i2c_priv_s *priv, uint32_t f { /* Disable the selected I2C peripheral to configure TRISE */ - pe = (stm32f0_i2c_getreg32(priv, STM32F0_I2C_CR1_OFFSET) & I2C_CR1_PE); + pe = (stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET) & I2C_CR1_PE); if (pe) { - stm32f0_i2c_modifyreg32(priv, STM32F0_I2C_CR1_OFFSET, I2C_CR1_PE, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); } /* Update timing and control registers */ /* TODO: speed/timing calcs, taking into consideration - * STM32F0_PCLK1_FREQUENCY, or SYSCLK, or HSI16 + * STM32_PCLK1_FREQUENCY, or SYSCLK, or HSI16 * clock source, RCC_CCIPR, I2CxSEL, 0 = PCKL, 1 = SCLK, 2 = HSI16, 3 = reserved #warning "check set filters before timing, see RM0351 35.4.4 p 1112" * analog filter; suppress spikes up to 50 ns in fast-mode and fast-mode plus @@ -1094,13 +1094,13 @@ static void stm32f0_i2c_setclock(FAR struct stm32f0_i2c_priv_s *priv, uint32_t f (scl_h_period << I2C_TIMINGR_SCLH_SHIFT) | (scl_l_period << I2C_TIMINGR_SCLL_SHIFT); - stm32f0_i2c_putreg32(priv, STM32F0_I2C_TIMINGR_OFFSET, timingr); + stm32_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); /* Re-enable the peripheral (or not) */ if (pe) { - stm32f0_i2c_modifyreg32(priv, STM32F0_I2C_CR1_OFFSET, 0, I2C_CR1_PE); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); } /* Save the new I2C frequency */ @@ -1110,14 +1110,14 @@ static void stm32f0_i2c_setclock(FAR struct stm32f0_i2c_priv_s *priv, uint32_t f } /************************************************************************************ - * Name: stm32f0_i2c_sendstart + * Name: stm32_i2c_sendstart * * Description: * Send the START conditions/force Master mode * ************************************************************************************/ -static inline void stm32f0_i2c_sendstart(FAR struct stm32f0_i2c_priv_s *priv) +static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv) { /* Get run-time data */ @@ -1128,41 +1128,41 @@ static inline void stm32f0_i2c_sendstart(FAR struct stm32f0_i2c_priv_s *priv) /* Disable ACK on receive by default and generate START */ - stm32f0_i2c_set_bytes_to_transfer(priv, priv->dcnt); - stm32f0_i2c_set_7bit_address(priv); + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); + stm32_i2c_set_7bit_address(priv); if (priv->flags & I2C_M_READ) { - stm32f0_i2c_set_read_transfer_dir(priv); + stm32_i2c_set_read_transfer_dir(priv); } else { - stm32f0_i2c_set_write_transfer_dir(priv); + stm32_i2c_set_write_transfer_dir(priv); } if (priv->msgc == 1) { - /* stm32f0_i2c_enable_autoend(priv); */ + /* stm32_i2c_enable_autoend(priv); */ } else { - /* stm32f0_i2c_disable_autoend(priv); */ + /* stm32_i2c_disable_autoend(priv); */ } /* TODO check NACK */ /* TODO handle NACKR? */ - stm32f0_i2c_modifyreg32(priv, STM32F0_I2C_CR2_OFFSET, 0, I2C_CR2_START); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); } /************************************************************************************ - * Name: stm32f0_i2c_clrstart + * Name: stm32_i2c_clrstart * * Description: * Clear the STOP, START or PEC condition on certain error recovery steps. * ************************************************************************************/ -static inline void stm32f0_i2c_clrstart(FAR struct stm32f0_i2c_priv_s *priv) +static inline void stm32_i2c_clrstart(FAR struct stm32_i2c_priv_s *priv) { /* "Note: When the STOP, START or PEC bit is set, the software must * not perform any write access to I2C_CR1 before this bit is @@ -1183,40 +1183,40 @@ static inline void stm32f0_i2c_clrstart(FAR struct stm32f0_i2c_priv_s *priv) /* TODO check PEC (32 bit separate reg) */ - stm32f0_i2c_modifyreg32(priv, STM32F0_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_START | I2C_CR2_STOP, 0); } /************************************************************************************ - * Name: stm32f0_i2c_sendstop + * Name: stm32_i2c_sendstop * * Description: * Send the STOP conditions * ************************************************************************************/ -static inline void stm32f0_i2c_sendstop(FAR struct stm32f0_i2c_priv_s *priv) +static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv) { /* TODO check NACK */ - stm32f0_i2c_modifyreg32(priv, STM32F0_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); } /************************************************************************************ - * Name: stm32f0_i2c_getstatus + * Name: stm32_i2c_getstatus * * Description: * Get 32-bit status (SR1 and SR2 combined) * ************************************************************************************/ -static inline uint32_t stm32f0_i2c_getstatus(FAR struct stm32f0_i2c_priv_s *priv) +static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv) { - return getreg32(priv->config->base + STM32F0_I2C_ISR_OFFSET); + return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET); } /************************************************************************************ - * Name: stm32f0_i2c_isr_startmessage + * Name: stm32_i2c_isr_startmessage * * Description: * Common logic when a message is started. Just adds the even to the trace buffer @@ -1224,9 +1224,9 @@ static inline uint32_t stm32f0_i2c_getstatus(FAR struct stm32f0_i2c_priv_s *priv * ************************************************************************************/ -static inline void stm32f0_i2c_isr_startmessage(struct stm32f0_i2c_priv_s *priv) +static inline void stm32_i2c_isr_startmessage(struct stm32_i2c_priv_s *priv) { - stm32f0_i2c_traceevent(priv, I2CEVENT_SENDADDR, priv->msgc); + stm32_i2c_traceevent(priv, I2CEVENT_SENDADDR, priv->msgc); /* Increment to next pointer and decrement message count */ @@ -1235,34 +1235,34 @@ static inline void stm32f0_i2c_isr_startmessage(struct stm32f0_i2c_priv_s *priv) } /************************************************************************************ - * Name: stm32f0_i2c_clearinterrupts + * Name: stm32_i2c_clearinterrupts * * Description: * Clear all interrupts * ************************************************************************************/ -static inline void stm32f0_i2c_clearinterrupts(struct stm32f0_i2c_priv_s *priv) +static inline void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv) { #warning "check this clears interrupts?" - stm32f0_i2c_modifyreg32(priv, STM32F0_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); + stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); } /************************************************************************************ - * Name: stm32f0_i2c_isr_process + * Name: stm32_i2c_isr_process * * Description: * Common Interrupt Service Routine * ************************************************************************************/ -static int stm32f0_i2c_isr_process(struct stm32f0_i2c_priv_s *priv) +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) { - uint32_t status = stm32f0_i2c_getstatus(priv); + uint32_t status = stm32_i2c_getstatus(priv); /* Check for new trace setup */ - stm32f0_i2c_tracenew(priv, status); + stm32_i2c_tracenew(priv, status); #warning "TODO: check clear interrupts after all actions" @@ -1272,7 +1272,7 @@ static int stm32f0_i2c_isr_process(struct stm32f0_i2c_priv_s *priv) } else if (priv->astart) { - stm32f0_i2c_isr_startmessage(priv); + stm32_i2c_isr_startmessage(priv); priv->astart = false; } @@ -1285,8 +1285,8 @@ static int stm32f0_i2c_isr_process(struct stm32f0_i2c_priv_s *priv) { /* Send a byte */ - stm32f0_i2c_traceevent(priv, I2CEVENT_SENDBYTE, priv->dcnt); - stm32f0_i2c_putreg32(priv, STM32F0_I2C_TXDR_OFFSET, *priv->ptr++); + stm32_i2c_traceevent(priv, I2CEVENT_SENDBYTE, priv->dcnt); + stm32_i2c_putreg32(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr++); priv->dcnt--; } } @@ -1297,8 +1297,8 @@ static int stm32f0_i2c_isr_process(struct stm32f0_i2c_priv_s *priv) #warning "TODO: ADDRCF clear address interrupt flag" #ifndef CONFIG_I2C_POLLED - stm32f0_i2c_traceevent(priv, I2CEVENT_ITBUFEN, 0); - stm32f0_i2c_enableinterrupts(priv); + stm32_i2c_traceevent(priv, I2CEVENT_ITBUFEN, 0); + stm32_i2c_enableinterrupts(priv); #endif } @@ -1310,7 +1310,7 @@ static int stm32f0_i2c_isr_process(struct stm32f0_i2c_priv_s *priv) if (priv->dcnt > 0) { - stm32f0_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); /* No interrupts or context switches may occur in the following * sequence. Otherwise, additional bytes may be sent by the @@ -1322,7 +1322,7 @@ static int stm32f0_i2c_isr_process(struct stm32f0_i2c_priv_s *priv) #endif /* Receive a byte */ - *priv->ptr++ = (uint8_t) stm32f0_i2c_getreg32(priv, STM32F0_I2C_RXDR_OFFSET); + *priv->ptr++ = (uint8_t) stm32_i2c_getreg32(priv, STM32_I2C_RXDR_OFFSET); /* Disable acknowledge when last byte is to be received */ @@ -1345,13 +1345,13 @@ static int stm32f0_i2c_isr_process(struct stm32f0_i2c_priv_s *priv) #ifndef CONFIG_I2C_POLLED if (priv->dcnt > 0) { - stm32f0_i2c_traceevent(priv, I2CEVENT_REITBUFEN, 0); - stm32f0_i2c_enableinterrupts(priv); + stm32_i2c_traceevent(priv, I2CEVENT_REITBUFEN, 0); + stm32_i2c_enableinterrupts(priv); } else if ((priv->dcnt == 0) && (priv->msgc == 0)) { - stm32f0_i2c_traceevent(priv, I2CEVENT_DISITBUFEN, 0); - stm32f0_i2c_disableinterrupts(priv); + stm32_i2c_traceevent(priv, I2CEVENT_DISITBUFEN, 0); + stm32_i2c_disableinterrupts(priv); } #endif @@ -1373,7 +1373,7 @@ static int stm32f0_i2c_isr_process(struct stm32f0_i2c_priv_s *priv) { if (priv->msgv->flags & I2C_M_NOSTART) { - stm32f0_i2c_traceevent(priv, I2CEVENT_BTFNOSTART, priv->msgc); + stm32_i2c_traceevent(priv, I2CEVENT_BTFNOSTART, priv->msgc); priv->ptr = priv->msgv->buffer; priv->dcnt = priv->msgv->length; priv->flags = priv->msgv->flags; @@ -1383,20 +1383,20 @@ static int stm32f0_i2c_isr_process(struct stm32f0_i2c_priv_s *priv) /* Restart this ISR! */ #ifndef CONFIG_I2C_POLLED - stm32f0_i2c_enableinterrupts(priv); + stm32_i2c_enableinterrupts(priv); #endif } else { - stm32f0_i2c_traceevent(priv, I2CEVENT_BTFRESTART, priv->msgc); - stm32f0_i2c_sendstart(priv); + stm32_i2c_traceevent(priv, I2CEVENT_BTFRESTART, priv->msgc); + stm32_i2c_sendstart(priv); } } else if (priv->msgv) { - stm32f0_i2c_traceevent(priv, I2CEVENT_BTFSTOP, 0); + stm32_i2c_traceevent(priv, I2CEVENT_BTFSTOP, 0); - stm32f0_i2c_sendstop(priv); + stm32_i2c_sendstop(priv); /* Is there a thread waiting for this event (there should be) */ @@ -1427,11 +1427,11 @@ static int stm32f0_i2c_isr_process(struct stm32f0_i2c_priv_s *priv) if ((status & I2C_ISR_ERRORMASK) != 0) { - stm32f0_i2c_traceevent(priv, I2CEVENT_ERROR, 0); + stm32_i2c_traceevent(priv, I2CEVENT_ERROR, 0); /* Clear interrupt flags */ - stm32f0_i2c_clearinterrupts(priv); + stm32_i2c_clearinterrupts(priv); /* Is there a thread waiting for this event (there should be) */ @@ -1455,7 +1455,7 @@ static int stm32f0_i2c_isr_process(struct stm32f0_i2c_priv_s *priv) } /************************************************************************************ - * Name: stm32f0_i2c_isr_process + * Name: stm32_i2c_isr_process * * Description: * Common I2C interrupt service routine @@ -1463,12 +1463,12 @@ static int stm32f0_i2c_isr_process(struct stm32f0_i2c_priv_s *priv) ************************************************************************************/ #ifndef CONFIG_I2C_POLLED -static int stm32f0_i2c_isr(int irq, void *context, FAR void *arg) +static int stm32_i2c_isr(int irq, void *context, FAR void *arg) { - struct stm32f0_i2c_priv_s *priv = (struct stm32f0_i2c_priv_s *)arg; + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg; DEBUGASSERT(priv != NULL); - return stm32f0_i2c_isr_process(priv); + return stm32_i2c_isr_process(priv); } #endif @@ -1477,43 +1477,43 @@ static int stm32f0_i2c_isr(int irq, void *context, FAR void *arg) ************************************************************************************/ /************************************************************************************ - * Name: stm32f0_i2c_init + * Name: stm32_i2c_init * * Description: * Setup the I2C hardware, ready for operation with defaults * ************************************************************************************/ -static int stm32f0_i2c_init(FAR struct stm32f0_i2c_priv_s *priv) +static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv) { int ret; /* Power-up and configure GPIOs */ /* Enable power and reset the peripheral */ - modifyreg32(STM32F0_RCC_APB1ENR, 0, priv->config->clk_bit); - modifyreg32(STM32F0_RCC_APB1RSTR, 0, priv->config->reset_bit); - modifyreg32(STM32F0_RCC_APB1RSTR, priv->config->reset_bit, 0); + modifyreg32(STM32_RCC_APB1ENR, 0, priv->config->clk_bit); + modifyreg32(STM32_RCC_APB1RSTR, 0, priv->config->reset_bit); + modifyreg32(STM32_RCC_APB1RSTR, priv->config->reset_bit, 0); /* Configure pins */ - ret = stm32f0_configgpio(priv->config->scl_pin); + ret = stm32_configgpio(priv->config->scl_pin); if (ret < 0) { return ret; } - ret = stm32f0_configgpio(priv->config->sda_pin); + ret = stm32_configgpio(priv->config->sda_pin); if (ret < 0) { - stm32f0_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->scl_pin); return ret; } #ifndef CONFIG_I2C_POLLED /* Attach and enable the I2C interrupt */ - irq_attach(priv->config->irq, stm32f0_i2c_isr, priv); + irq_attach(priv->config->irq, stm32_i2c_isr, priv); up_enable_irq(priv->config->irq); #endif @@ -1528,32 +1528,32 @@ static int stm32f0_i2c_init(FAR struct stm32f0_i2c_priv_s *priv) /* TODO: i2c clock source RCC_CCIPR */ /* RCC_CCIPR I2CxSEL (default is PCLK clock) */ - stm32f0_i2c_setclock(priv, 100000); + stm32_i2c_setclock(priv, 100000); /* Enable I2C */ - stm32f0_i2c_modifyreg32(priv, STM32F0_I2C_CR1_OFFSET, 0, I2C_CR1_PE); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); return OK; } /************************************************************************************ - * Name: stm32f0_i2c_deinit + * Name: stm32_i2c_deinit * * Description: * Shutdown the I2C hardware * ************************************************************************************/ -static int stm32f0_i2c_deinit(FAR struct stm32f0_i2c_priv_s *priv) +static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv) { /* Disable I2C */ - stm32f0_i2c_putreg32(priv, STM32F0_I2C_CR1_OFFSET, 0); + stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); /* Unconfigure GPIO pins */ - stm32f0_unconfiggpio(priv->config->scl_pin); - stm32f0_unconfiggpio(priv->config->sda_pin); + stm32_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->sda_pin); /* Disable and detach interrupts */ @@ -1564,7 +1564,7 @@ static int stm32f0_i2c_deinit(FAR struct stm32f0_i2c_priv_s *priv) /* Disable clocking */ - modifyreg32(STM32F0_RCC_APB1ENR, priv->config->clk_bit, 0); + modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0); return OK; } @@ -1573,17 +1573,17 @@ static int stm32f0_i2c_deinit(FAR struct stm32f0_i2c_priv_s *priv) ************************************************************************************/ /************************************************************************************ - * Name: stm32f0_i2c_transfer + * Name: stm32_i2c_transfer * * Description: * Generic I2C transfer function * ************************************************************************************/ -static int stm32f0_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs, +static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs, int count) { - FAR struct stm32f0_i2c_priv_s *priv = (struct stm32f0_i2c_priv_s *)dev; + FAR struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; uint32_t status = 0; int ret = OK; @@ -1591,15 +1591,15 @@ static int stm32f0_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg /* Ensure that address or flags don't change meanwhile */ - stm32f0_i2c_sem_wait(priv); + stm32_i2c_sem_wait(priv); /* Wait for any STOP in progress. */ - stm32f0_i2c_sem_waitstop(priv); + stm32_i2c_sem_waitstop(priv); /* Clear any pending error interrupts */ - stm32f0_i2c_clearinterrupts(priv); + stm32_i2c_clearinterrupts(priv); /* "Note: When the STOP, START or PEC bit is set, the software must * not perform any write access to I2C_CR1 before this bit is @@ -1608,7 +1608,7 @@ static int stm32f0_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg * not cleared by hardware, then we will have to do that from hardware. */ - stm32f0_i2c_clrstart(priv); + stm32_i2c_clrstart(priv); /* Old transfers are done */ @@ -1617,7 +1617,7 @@ static int stm32f0_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg /* Reset I2C trace logic */ - stm32f0_i2c_tracereset(priv); + stm32_i2c_tracereset(priv); /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !) * REVISIT: Note that the frequency is set only on the first message. @@ -1625,31 +1625,31 @@ static int stm32f0_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg * each message segment. */ - stm32f0_i2c_setclock(priv, msgs->frequency); + stm32_i2c_setclock(priv, msgs->frequency); /* Trigger start condition, then the process moves into the ISR. I2C - * interrupts will be enabled within stm32f0_i2c_waitdone(). + * interrupts will be enabled within stm32_i2c_waitdone(). */ priv->status = 0; #ifndef CONFIG_I2C_POLLED - stm32f0_i2c_enableinterrupts(priv); + stm32_i2c_enableinterrupts(priv); #endif - stm32f0_i2c_sendstart(priv); + stm32_i2c_sendstart(priv); /* Wait for an ISR, if there was a timeout, fetch latest status to get * the BUSY flag. */ - if (stm32f0_i2c_sem_waitdone(priv) < 0) + if (stm32_i2c_sem_waitdone(priv) < 0) { - status = stm32f0_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); ret = -ETIMEDOUT; i2cerr("ERROR: Timed out: CR1: %08x status: %08x\n", - stm32f0_i2c_getreg32(priv, STM32F0_I2C_CR1_OFFSET), status); + stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET), status); /* "Note: When the STOP, START or PEC bit is set, the software must * not perform any write access to I2C_CR1 before this bit is @@ -1657,7 +1657,7 @@ static int stm32f0_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg * second STOP, START or PEC request." */ - stm32f0_i2c_clrstart(priv); + stm32_i2c_clrstart(priv); /* Clear busy flag in case of timeout */ @@ -1675,7 +1675,7 @@ static int stm32f0_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg /* Refresh status */ do { - status = stm32f0_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); } while (STATUS_BUSY(status)); #endif @@ -1736,7 +1736,7 @@ static int stm32f0_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg /* This is not an error, but should not happen. The BUSY signal can hang, * however, if there are unhealthy devices on the bus that need to be reset. - * NOTE: We will only see this buy indication if stm32f0_i2c_sem_waitdone() + * NOTE: We will only see this buy indication if stm32_i2c_sem_waitdone() * fails above; Otherwise it is cleared. */ @@ -1749,13 +1749,13 @@ static int stm32f0_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg /* Dump the trace result */ - stm32f0_i2c_tracedump(priv); - stm32f0_i2c_sem_post(priv); + stm32_i2c_tracedump(priv); + stm32_i2c_sem_post(priv); return ret; } /************************************************************************************ - * Name: stm32f0_i2c_reset + * Name: stm32_i2c_reset * * Description: * Perform an I2C bus reset in an attempt to break loose stuck I2C devices. @@ -1769,9 +1769,9 @@ static int stm32f0_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg ************************************************************************************/ #ifdef CONFIG_I2C_RESET -static int stm32f0_i2c_reset(FAR struct i2c_master_s * dev) +static int stm32_i2c_reset(FAR struct i2c_master_s * dev) { - FAR struct stm32f0_i2c_priv_s *priv = (struct stm32f0_i2c_priv_s *)dev; + FAR struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; unsigned int clock_count; unsigned int stretch_count; uint32_t scl_gpio; @@ -1787,7 +1787,7 @@ static int stm32f0_i2c_reset(FAR struct i2c_master_s * dev) /* Lock out other clients */ - stm32f0_i2c_sem_wait(priv); + stm32_i2c_sem_wait(priv); /* Save the current frequency */ @@ -1795,7 +1795,7 @@ static int stm32f0_i2c_reset(FAR struct i2c_master_s * dev) /* De-init the port */ - stm32f0_i2c_deinit(priv); + stm32_i2c_deinit(priv); /* Use GPIO configuration to un-wedge the bus */ @@ -1804,12 +1804,12 @@ static int stm32f0_i2c_reset(FAR struct i2c_master_s * dev) /* Let SDA go high */ - stm32f0_gpiowrite(sda_gpio, 1); + stm32_gpiowrite(sda_gpio, 1); /* Clock the bus until any slaves currently driving it let it go. */ clock_count = 0; - while (!stm32f0_gpioread(sda_gpio)) + while (!stm32_gpioread(sda_gpio)) { /* Give up if we have tried too hard */ @@ -1824,7 +1824,7 @@ static int stm32f0_i2c_reset(FAR struct i2c_master_s * dev) */ stretch_count = 0; - while (!stm32f0_gpioread(scl_gpio)) + while (!stm32_gpioread(scl_gpio)) { /* Give up if we have tried too hard */ @@ -1838,12 +1838,12 @@ static int stm32f0_i2c_reset(FAR struct i2c_master_s * dev) /* Drive SCL low */ - stm32f0_gpiowrite(scl_gpio, 0); + stm32_gpiowrite(scl_gpio, 0); up_udelay(10); /* Drive SCL high again */ - stm32f0_gpiowrite(scl_gpio, 1); + stm32_gpiowrite(scl_gpio, 1); up_udelay(10); } @@ -1851,37 +1851,37 @@ static int stm32f0_i2c_reset(FAR struct i2c_master_s * dev) * state machines. */ - stm32f0_gpiowrite(sda_gpio, 0); + stm32_gpiowrite(sda_gpio, 0); up_udelay(10); - stm32f0_gpiowrite(scl_gpio, 0); + stm32_gpiowrite(scl_gpio, 0); up_udelay(10); - stm32f0_gpiowrite(scl_gpio, 1); + stm32_gpiowrite(scl_gpio, 1); up_udelay(10); - stm32f0_gpiowrite(sda_gpio, 1); + stm32_gpiowrite(sda_gpio, 1); up_udelay(10); /* Revert the GPIO configuration. */ - stm32f0_unconfiggpio(sda_gpio); - stm32f0_unconfiggpio(scl_gpio); + stm32_unconfiggpio(sda_gpio); + stm32_unconfiggpio(scl_gpio); /* Re-init the port */ - ret = stm32f0_i2c_init(priv); + ret = stm32_i2c_init(priv); if (ret < 0) { - i2cerr("ERROR: stm32f0_i2c_init failed: %d\n", ret); + i2cerr("ERROR: stm32_i2c_init failed: %d\n", ret); } /* Restore the frequency */ - stm32f0_i2c_setclock(priv, frequency); + stm32_i2c_setclock(priv, frequency); out: /* Release the port for re-use by other clients */ - stm32f0_i2c_sem_post(priv); + stm32_i2c_sem_post(priv); return ret; } #endif /* CONFIG_I2C_RESET */ @@ -1891,25 +1891,25 @@ out: ************************************************************************************/ /************************************************************************************ - * Name: stm32f0_i2cbus_initialize + * Name: stm32_i2cbus_initialize * * Description: * Initialize one I2C bus * ************************************************************************************/ -FAR struct i2c_master_s *stm32f0_i2cbus_initialize(int port) +FAR struct i2c_master_s *stm32_i2cbus_initialize(int port) { - struct stm32f0_i2c_priv_s *priv = NULL; + struct stm32_i2c_priv_s *priv = NULL; irqstate_t flags; int ret; -#if STM32F0_PCLK1_FREQUENCY < 4000000 -# warning STM32F0_I2C_INIT: Peripheral clock must be at least 4 MHz to support 400 kHz operation. +#if STM32_PCLK1_FREQUENCY < 4000000 +# warning STM32_I2C_INIT: Peripheral clock must be at least 4 MHz to support 400 kHz operation. #endif -#if STM32F0_PCLK1_FREQUENCY < 2000000 -# warning STM32F0_I2C_INIT: Peripheral clock must be at least 2 MHz to support 100 kHz operation. +#if STM32_PCLK1_FREQUENCY < 2000000 +# warning STM32_I2C_INIT: Peripheral clock must be at least 2 MHz to support 100 kHz operation. return NULL; #endif @@ -1917,19 +1917,19 @@ FAR struct i2c_master_s *stm32f0_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32F0_I2C1 +#ifdef CONFIG_STM32F0L0_I2C1 case 1: - priv = (struct stm32f0_i2c_priv_s *)&stm32f0_i2c1_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32F0_I2C2 +#ifdef CONFIG_STM32F0L0_I2C2 case 2: - priv = (struct stm32f0_i2c_priv_s *)&stm32f0_i2c2_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif -#ifdef CONFIG_STM32F0_I2C3 +#ifdef CONFIG_STM32F0L0_I2C3 case 3: - priv = (struct stm32f0_i2c_priv_s *)&stm32f0_i2c3_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif default: @@ -1944,11 +1944,11 @@ FAR struct i2c_master_s *stm32f0_i2cbus_initialize(int port) if ((volatile int)priv->refs++ == 0) { - stm32f0_i2c_sem_init(priv); - ret = stm32f0_i2c_init(priv); + stm32_i2c_sem_init(priv); + ret = stm32_i2c_init(priv); if (ret < 0) { - i2cerr("ERROR: stm32f0_i2c_init failed: %d\n", ret); + i2cerr("ERROR: stm32_i2c_init failed: %d\n", ret); } } @@ -1957,16 +1957,16 @@ FAR struct i2c_master_s *stm32f0_i2cbus_initialize(int port) } /************************************************************************************ - * Name: stm32f0_i2cbus_uninitialize + * Name: stm32_i2cbus_uninitialize * * Description: * Uninitialize an I2C bus * ************************************************************************************/ -int stm32f0_i2cbus_uninitialize(FAR struct i2c_master_s * dev) +int stm32_i2cbus_uninitialize(FAR struct i2c_master_s * dev) { - FAR struct stm32f0_i2c_priv_s *priv = (struct stm32f0_i2c_priv_s *)dev; + FAR struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; irqstate_t flags; DEBUGASSERT(dev); @@ -1990,12 +1990,12 @@ int stm32f0_i2cbus_uninitialize(FAR struct i2c_master_s * dev) /* Disable power and other HW resource (GPIO's) */ - stm32f0_i2c_deinit(priv); + stm32_i2c_deinit(priv); /* Release unused resources */ - stm32f0_i2c_sem_destroy(priv); + stm32_i2c_sem_destroy(priv); return OK; } -#endif /* CONFIG_STM32F0_I2C1 || CONFIG_STM32F0_I2C2 || CONFIG_STM32F0_I2C3 */ +#endif /* CONFIG_STM32F0L0_I2C1 || CONFIG_STM32F0L0_I2C2 || CONFIG_STM32F0L0_I2C3 */ diff --git a/arch/arm/src/stm32f0/stm32f0_i2c.h b/arch/arm/src/stm32f0l0/stm32_i2c.h similarity index 83% rename from arch/arm/src/stm32f0/stm32f0_i2c.h rename to arch/arm/src/stm32f0l0/stm32_i2c.h index dd127b788ac..9a9d881dce8 100644 --- a/arch/arm/src/stm32f0/stm32f0_i2c.h +++ b/arch/arm/src/stm32f0l0/stm32_i2c.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0/stm32f0_i2c.h + * arch/arm/src/stm32f0l0/stm32_i2c.h * * Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_I2C_H -#define __ARCH_ARM_SRC_STM32F0_STM32F0_I2C_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_I2C_H +#define __ARCH_ARM_SRC_STM32F0L0_STM32_I2C_H /**************************************************************************** * Included Files @@ -44,7 +44,7 @@ #include #include "chip.h" -#include "chip/stm32f0_i2c.h" +#include "hardware/stm32_i2c.h" /**************************************************************************** * Pre-processor Definitions @@ -54,10 +54,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32F0_I2C_DYNTIMEO -# if CONFIG_STM32F0_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32F0_I2C_DYNTIMEO because of CONFIG_STM32F0_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32F0_I2C_DYNTIMEO +#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO +# if CONFIG_STM32F0L0_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32F0L0_I2C_DYNTIMEO because of CONFIG_STM32F0L0_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32F0L0_I2C_DYNTIMEO # endif #endif @@ -66,7 +66,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32f0_i2cbus_initialize + * Name: stm32_i2cbus_initialize * * Description: * Initialize the selected I2C port. And return a unique instance of struct @@ -82,16 +82,16 @@ * ****************************************************************************/ -FAR struct i2c_master_s *stm32f0_i2cbus_initialize(int port); +FAR struct i2c_master_s *stm32_i2cbus_initialize(int port); /**************************************************************************** - * Name: stm32f0_i2cbus_uninitialize + * Name: stm32_i2cbus_uninitialize * * Description: * De-initialize the selected I2C port, and power down the device. * * Input Parameters: - * Device structure as returned by the stm32f0_i2cbus_initialize() + * Device structure as returned by the stm32_i2cbus_initialize() * * Returned Value: * OK on success, ERROR when internal reference count mismatch or dev @@ -99,6 +99,6 @@ FAR struct i2c_master_s *stm32f0_i2cbus_initialize(int port); * ****************************************************************************/ -int stm32f0_i2cbus_uninitialize(FAR struct i2c_master_s *dev); +int stm32_i2cbus_uninitialize(FAR struct i2c_master_s *dev); -#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_I2C_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_I2C_H */ diff --git a/arch/arm/src/stm32f0/stm32f0_idle.c b/arch/arm/src/stm32f0l0/stm32_idle.c similarity index 98% rename from arch/arm/src/stm32f0/stm32f0_idle.c rename to arch/arm/src/stm32f0l0/stm32_idle.c index b785c07a46c..3e1fa00d172 100644 --- a/arch/arm/src/stm32f0/stm32f0_idle.c +++ b/arch/arm/src/stm32f0l0/stm32_idle.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0/stm32f0_idle.c + * arch/arm/src/stm32f0l0/stm32_idle.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -97,7 +97,7 @@ void up_idle(void) * disabled in order to save power." */ -#ifdef CONFIG_STM32F0_GPDMA +#ifdef CONFIG_STM32F0L0_GPDMA if (g_dma_inprogress == 0) #endif { diff --git a/arch/arm/src/stm32f0/stm32f0_irq.c b/arch/arm/src/stm32f0l0/stm32_irq.c similarity index 85% rename from arch/arm/src/stm32f0/stm32f0_irq.c rename to arch/arm/src/stm32f0l0/stm32_irq.c index 96462f3b037..3161352812e 100644 --- a/arch/arm/src/stm32f0/stm32f0_irq.c +++ b/arch/arm/src/stm32f0l0/stm32_irq.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0/stm32f0_irq.c + * arch/arm/src/stm32f0l0/stm32_irq.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -51,7 +51,7 @@ #include "up_arch.h" #include "up_internal.h" -//#include "stm32f0_irq.h" +//#include "stm32_irq.h" /**************************************************************************** * Pre-processor Definitions @@ -80,7 +80,7 @@ volatile uint32_t *g_current_regs[1]; ****************************************************************************/ /**************************************************************************** - * Name: stm32f0_dumpnvic + * Name: stm32_dumpnvic * * Description: * Dump some interesting NVIC registers @@ -88,7 +88,7 @@ volatile uint32_t *g_current_regs[1]; ****************************************************************************/ #if defined(CONFIG_DEBUG_IRQ_INFO) -static void stm32f0_dumpnvic(const char *msg, int irq) +static void stm32_dumpnvic(const char *msg, int irq) { irqstate_t flags; @@ -120,12 +120,12 @@ static void stm32f0_dumpnvic(const char *msg, int irq) } #else -# define stm32f0_dumpnvic(msg, irq) +# define stm32_dumpnvic(msg, irq) #endif /**************************************************************************** - * Name: stm32f0_nmi, stm32f0_busfault, stm32f0_usagefault, stm32f0_pendsv, - * stm32f0_dbgmonitor, stm32f0_pendsv, stm32f0_reserved + * Name: stm32_nmi, stm32_busfault, stm32_usagefault, stm32_pendsv, + * stm32_dbgmonitor, stm32_pendsv, stm32_reserved * * Description: * Handlers for various execptions. None are handled and all are fatal @@ -135,7 +135,7 @@ static void stm32f0_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int stm32f0_nmi(int irq, FAR void *context, FAR void *arg) +static int stm32_nmi(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -143,7 +143,7 @@ static int stm32f0_nmi(int irq, FAR void *context, FAR void *arg) return 0; } -static int stm32f0_pendsv(int irq, FAR void *context, FAR void *arg) +static int stm32_pendsv(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -151,7 +151,7 @@ static int stm32f0_pendsv(int irq, FAR void *context, FAR void *arg) return 0; } -static int stm32f0_reserved(int irq, FAR void *context, FAR void *arg) +static int stm32_reserved(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -161,14 +161,14 @@ static int stm32f0_reserved(int irq, FAR void *context, FAR void *arg) #endif /**************************************************************************** - * Name: stm32f0_clrpend + * Name: stm32_clrpend * * Description: * Clear a pending interrupt at the NVIC. * ****************************************************************************/ -static inline void stm32f0_clrpend(int irq) +static inline void stm32_clrpend(int irq) { /* This will be called on each interrupt exit whether the interrupt can be * enambled or not. So this assertion is necessarily lame. @@ -178,13 +178,13 @@ static inline void stm32f0_clrpend(int irq) /* Check for an external interrupt */ - if (irq >= STM32F0_IRQ_EXTINT && irq < (STM32F0_IRQ_EXTINT + 32)) + if (irq >= STM32_IRQ_EXTINT && irq < (STM32_IRQ_EXTINT + 32)) { /* Set the appropriate bit in the ISER register to enable the * interrupt */ - putreg32((1 << (irq - STM32F0_IRQ_EXTINT)), ARMV6M_NVIC_ICPR); + putreg32((1 << (irq - STM32_IRQ_EXTINT)), ARMV6M_NVIC_ICPR); } } @@ -228,25 +228,25 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(STM32F0_IRQ_SVCALL, up_svcall, NULL); - irq_attach(STM32F0_IRQ_HARDFAULT, up_hardfault, NULL); + irq_attach(STM32_IRQ_SVCALL, up_svcall, NULL); + irq_attach(STM32_IRQ_HARDFAULT, up_hardfault, NULL); /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32F0_IRQ_NMI, stm32f0_nmi, NULL); - irq_attach(STM32F0_IRQ_PENDSV, stm32f0_pendsv, NULL); - irq_attach(STM32F0_IRQ_RESERVED, stm32f0_reserved, NULL); + irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL); #endif - stm32f0_dumpnvic("initial", NR_IRQS); + stm32_dumpnvic("initial", NR_IRQS); /* Initialize logic to support a second level of interrupt decoding for * configured pin interrupts. */ -#ifdef CONFIG_STM32F0_GPIOIRQ - stm32f0_gpioirqinitialize(); +#ifdef CONFIG_STM32F0L0_GPIOIRQ + stm32_gpioirqinitialize(); #endif #ifndef CONFIG_SUPPRESS_INTERRUPTS @@ -271,23 +271,23 @@ void up_disable_irq(int irq) /* Check for an external interrupt */ - if (irq >= STM32F0_IRQ_EXTINT && irq < (STM32F0_IRQ_EXTINT + 32)) + if (irq >= STM32_IRQ_EXTINT && irq < (STM32_IRQ_EXTINT + 32)) { /* Set the appropriate bit in the ICER register to disable the * interrupt */ - putreg32((1 << (irq - STM32F0_IRQ_EXTINT)), ARMV6M_NVIC_ICER); + putreg32((1 << (irq - STM32_IRQ_EXTINT)), ARMV6M_NVIC_ICER); } /* Handle processor exceptions. Only SysTick can be disabled */ - else if (irq == STM32F0_IRQ_SYSTICK) + else if (irq == STM32_IRQ_SYSTICK) { modifyreg32(ARMV6M_SYSTICK_CSR, SYSTICK_CSR_ENABLE, 0); } - stm32f0_dumpnvic("disable", irq); + stm32_dumpnvic("disable", irq); } /**************************************************************************** @@ -308,23 +308,23 @@ void up_enable_irq(int irq) /* Check for external interrupt */ - if (irq >= STM32F0_IRQ_EXTINT && irq < (STM32F0_IRQ_EXTINT + 32)) + if (irq >= STM32_IRQ_EXTINT && irq < (STM32_IRQ_EXTINT + 32)) { /* Set the appropriate bit in the ISER register to enable the * interrupt */ - putreg32((1 << (irq - STM32F0_IRQ_EXTINT)), ARMV6M_NVIC_ISER); + putreg32((1 << (irq - STM32_IRQ_EXTINT)), ARMV6M_NVIC_ISER); } /* Handle processor exceptions. Only SysTick can be disabled */ - else if (irq == STM32F0_IRQ_SYSTICK) + else if (irq == STM32_IRQ_SYSTICK) { modifyreg32(ARMV6M_SYSTICK_CSR, 0, SYSTICK_CSR_ENABLE); } - stm32f0_dumpnvic("enable", irq); + stm32_dumpnvic("enable", irq); } /**************************************************************************** @@ -337,5 +337,5 @@ void up_enable_irq(int irq) void up_ack_irq(int irq) { - stm32f0_clrpend(irq); + stm32_clrpend(irq); } diff --git a/arch/arm/src/stm32f0/stm32f0_lowputc.c b/arch/arm/src/stm32f0l0/stm32_lowputc.c similarity index 57% rename from arch/arm/src/stm32f0/stm32f0_lowputc.c rename to arch/arm/src/stm32f0l0/stm32_lowputc.c index 12e20197bc9..c4fa20726ce 100644 --- a/arch/arm/src/stm32f0/stm32f0_lowputc.c +++ b/arch/arm/src/stm32f0l0/stm32_lowputc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0/stm32f0_lowputc.c + * arch/arm/src/stm32f0l0/stm32_lowputc.c * * Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -49,9 +49,9 @@ #include "chip.h" -#include "stm32f0_rcc.h" -#include "stm32f0_gpio.h" -#include "stm32f0_uart.h" +#include "stm32_rcc.h" +#include "stm32_gpio.h" +#include "stm32_uart.h" /**************************************************************************** * Pre-processor Definitions @@ -61,88 +61,88 @@ #ifdef HAVE_CONSOLE # if defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32F0_CONSOLE_BASE STM32F0_USART1_BASE -# define STM32F0_APBCLOCK STM32F0_PCLK2_FREQUENCY -# define STM32F0_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32F0_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32F0_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32F0_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP # ifdef CONFIG_USART1_RS485 -# define STM32F0_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR # if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32F0_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32F0_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define STM32F0_CONSOLE_BASE STM32F0_USART2_BASE -# define STM32F0_APBCLOCK STM32F0_PCLK1_FREQUENCY -# define STM32F0_CONSOLE_BAUD CONFIG_USART2_BAUD -# define STM32F0_CONSOLE_BITS CONFIG_USART2_BITS -# define STM32F0_CONSOLE_PARITY CONFIG_USART2_PARITY -# define STM32F0_CONSOLE_2STOP CONFIG_USART2_2STOP +# define STM32_CONSOLE_BASE STM32_USART2_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP # ifdef CONFIG_USART2_RS485 -# define STM32F0_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR # if (CONFIG_USART2_RS485_DIR_POLARITY == 0) -# define STM32F0_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32F0_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART3_SERIAL_CONSOLE) -# define STM32F0_CONSOLE_BASE STM32F0_USART3_BASE -# define STM32F0_APBCLOCK STM32F0_PCLK1_FREQUENCY -# define STM32F0_CONSOLE_BAUD CONFIG_USART3_BAUD -# define STM32F0_CONSOLE_BITS CONFIG_USART3_BITS -# define STM32F0_CONSOLE_PARITY CONFIG_USART3_PARITY -# define STM32F0_CONSOLE_2STOP CONFIG_USART3_2STOP +# define STM32_CONSOLE_BASE STM32_USART3_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART3_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP # ifdef CONFIG_USART3_RS485 -# define STM32F0_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR # if (CONFIG_USART3_RS485_DIR_POLARITY == 0) -# define STM32F0_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32F0_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART4_SERIAL_CONSOLE) -# define STM32F0_CONSOLE_BASE STM32F0_USART4_BASE -# define STM32F0_APBCLOCK STM32F0_PCLK1_FREQUENCY -# define STM32F0_CONSOLE_BAUD CONFIG_USART4_BAUD -# define STM32F0_CONSOLE_BITS CONFIG_USART4_BITS -# define STM32F0_CONSOLE_PARITY CONFIG_USART4_PARITY -# define STM32F0_CONSOLE_2STOP CONFIG_USART4_2STOP +# define STM32_CONSOLE_BASE STM32_USART4_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_BAUD CONFIG_USART4_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART4_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART4_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART4_2STOP # ifdef CONFIG_USART4_RS485 -# define STM32F0_CONSOLE_RS485_DIR GPIO_USART4_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART4_RS485_DIR # if (CONFIG_USART4_RS485_DIR_POLARITY == 0) -# define STM32F0_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32F0_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART5_SERIAL_CONSOLE) -# define STM32F0_CONSOLE_BASE STM32F0_USART5_BASE -# define STM32F0_APBCLOCK STM32F0_PCLK1_FREQUENCY -# define STM32F0_CONSOLE_BAUD CONFIG_USART5_BAUD -# define STM32F0_CONSOLE_BITS CONFIG_USART5_BITS -# define STM32F0_CONSOLE_PARITY CONFIG_USART5_PARITY -# define STM32F0_CONSOLE_2STOP CONFIG_USART5_2STOP +# define STM32_CONSOLE_BASE STM32_USART5_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_BAUD CONFIG_USART5_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART5_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART5_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART5_2STOP # ifdef CONFIG_USART5_RS485 -# define STM32F0_CONSOLE_RS485_DIR GPIO_USART5_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART5_RS485_DIR # if (CONFIG_USART5_RS485_DIR_POLARITY == 0) -# define STM32F0_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32F0_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # endif /* CR1 settings */ -# if STM32F0_CONSOLE_BITS == 9 +# if STM32_CONSOLE_BITS == 9 # define USART_CR1_M0_VALUE USART_CR1_M0 # define USART_CR1_M1_VALUE 0 -# elif STM32F0_CONSOLE_BITS == 7 +# elif STM32_CONSOLE_BITS == 7 # define USART_CR1_M0_VALUE 0 # define USART_CR1_M1_VALUE USART_CR1_M1 # else /* 8 bits */ @@ -150,9 +150,9 @@ # define USART_CR1_M1_VALUE 0 # endif -# if STM32F0_CONSOLE_PARITY == 1 /* odd parity */ +# if STM32_CONSOLE_PARITY == 1 /* odd parity */ # define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32F0_CONSOLE_PARITY == 2 /* even parity */ +# elif STM32_CONSOLE_PARITY == 2 /* even parity */ # define USART_CR1_PARITY_VALUE USART_CR1_PCE # else /* no parity */ # define USART_CR1_PARITY_VALUE 0 @@ -168,7 +168,7 @@ /* CR2 settings */ -# if STM32F0_CONSOLE_2STOP != 0 +# if STM32_CONSOLE_2STOP != 0 # define USART_CR2_STOP2_VALUE USART_CR2_STOP2 # else # define USART_CR2_STOP2_VALUE 0 @@ -210,19 +210,19 @@ * UARTDIV = 2 * fCK / baud */ -# define STM32F0_USARTDIV8 \ - (((STM32F0_APBCLOCK << 1) + (STM32F0_CONSOLE_BAUD >> 1)) / STM32F0_CONSOLE_BAUD) -# define STM32F0_USARTDIV16 \ - ((STM32F0_APBCLOCK + (STM32F0_CONSOLE_BAUD >> 1)) / STM32F0_CONSOLE_BAUD) +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) /* Use oversamply by 8 only if the divisor is small. But what is small? */ -# if STM32F0_USARTDIV8 > 100 -# define STM32F0_BRR_VALUE STM32F0_USARTDIV16 +# if STM32_USARTDIV8 > 100 +# define STM32_BRR_VALUE STM32_USARTDIV16 # else # define USE_OVER8 1 -# define STM32F0_BRR_VALUE \ - ((STM32F0_USARTDIV8 & 0xfff0) | ((STM32F0_USARTDIV8 & 0x000f) >> 1)) +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) # endif #endif /* HAVE_CONSOLE */ @@ -244,25 +244,25 @@ void up_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX data register is empty */ - while ((getreg32(STM32F0_CONSOLE_BASE + STM32F0_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); -#ifdef STM32F0_CONSOLE_RS485_DIR - stm32f0_gpiowrite(STM32F0_CONSOLE_RS485_DIR, STM32F0_CONSOLE_RS485_DIR_POLARITY); + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); +#ifdef STM32_CONSOLE_RS485_DIR + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Then send the character */ - putreg32((uint32_t)ch, STM32F0_CONSOLE_BASE + STM32F0_USART_TDR_OFFSET); + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); -#ifdef STM32F0_CONSOLE_RS485_DIR - while ((getreg32(STM32F0_CONSOLE_BASE + STM32F0_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32f0_gpiowrite(STM32F0_CONSOLE_RS485_DIR, !STM32F0_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY); #endif #endif /* HAVE_CONSOLE */ } /**************************************************************************** - * Name: stm32f0_lowsetup + * Name: stm32_lowsetup * * Description: * This performs basic initialization of the USART used for the serial @@ -271,7 +271,7 @@ void up_lowputc(char ch) * ****************************************************************************/ -void stm32f0_lowsetup(void) +void stm32_lowsetup(void) { #if defined(HAVE_USART) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) @@ -280,83 +280,83 @@ void stm32f0_lowsetup(void) /* Setup clocking and GPIO pins for all configured USARTs */ -#ifdef CONFIG_STM32F0_USART1 +#ifdef CONFIG_STM32F0L0_USART1 /* Enable USART APB2 clock */ - modifyreg32(STM32F0_RCC_APB2ENR, 0, RCC_APB2ENR_USART1EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_USART1EN); /* Configure RX/TX pins */ - stm32f0_configgpio(GPIO_USART1_TX); - stm32f0_configgpio(GPIO_USART1_RX); + stm32_configgpio(GPIO_USART1_TX); + stm32_configgpio(GPIO_USART1_RX); #ifdef CONFIG_USART1_RS485 - stm32f0_configgpio(GPIO_USART1_RS485_DIR); - stm32f0_gpiowrite(GPIO_USART1_RS485_DIR, !CONFIG_USART1_RS485_DIR_POLARITY); + stm32_configgpio(GPIO_USART1_RS485_DIR); + stm32_gpiowrite(GPIO_USART1_RS485_DIR, !CONFIG_USART1_RS485_DIR_POLARITY); #endif #endif -#ifdef CONFIG_STM32F0_USART2 +#ifdef CONFIG_STM32F0L0_USART2 /* Enable USART APB1 clock */ - modifyreg32(STM32F0_RCC_APB1ENR, 0, RCC_APB1ENR_USART2EN); + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART2EN); /* Configure RX/TX pins */ - stm32f0_configgpio(GPIO_USART2_TX); - stm32f0_configgpio(GPIO_USART2_RX); + stm32_configgpio(GPIO_USART2_TX); + stm32_configgpio(GPIO_USART2_RX); #ifdef CONFIG_USART2_RS485 - stm32f0_configgpio(GPIO_USART2_RS485_DIR); - stm32f0_gpiowrite(GPIO_USART2_RS485_DIR, !CONFIG_USART2_RS485_DIR_POLARITY); + stm32_configgpio(GPIO_USART2_RS485_DIR); + stm32_gpiowrite(GPIO_USART2_RS485_DIR, !CONFIG_USART2_RS485_DIR_POLARITY); #endif #endif -#ifdef CONFIG_STM32F0_USART3 +#ifdef CONFIG_STM32F0L0_USART3 /* Enable USART APB1 clock */ - modifyreg32(STM32F0_RCC_APB1ENR, 0, RCC_APB1ENR_USART3EN); + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART3EN); /* Configure RX/TX pins */ - stm32f0_configgpio(GPIO_USART3_TX); - stm32f0_configgpio(GPIO_USART3_RX); + stm32_configgpio(GPIO_USART3_TX); + stm32_configgpio(GPIO_USART3_RX); #ifdef CONFIG_USART3_RS485 - stm32f0_configgpio(GPIO_USART3_RS485_DIR); - stm32f0_gpiowrite(GPIO_USART3_RS485_DIR, !CONFIG_USART3_RS485_DIR_POLARITY); + stm32_configgpio(GPIO_USART3_RS485_DIR); + stm32_gpiowrite(GPIO_USART3_RS485_DIR, !CONFIG_USART3_RS485_DIR_POLARITY); #endif #endif -#ifdef CONFIG_STM32F0_USART4 +#ifdef CONFIG_STM32F0L0_USART4 /* Enable USART APB1 clock */ - modifyreg32(STM32F0_RCC_APB1ENR, 0, RCC_APB1ENR_USART4EN); + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART4EN); /* Configure RX/TX pins */ - stm32f0_configgpio(GPIO_USART4_TX); - stm32f0_configgpio(GPIO_USART4_RX); + stm32_configgpio(GPIO_USART4_TX); + stm32_configgpio(GPIO_USART4_RX); #ifdef CONFIG_USART4_RS485 - stm32f0_configgpio(GPIO_USART4_RS485_DIR); - stm32f0_gpiowrite(GPIO_USART4_RS485_DIR, !CONFIG_USART4_RS485_DIR_POLARITY); + stm32_configgpio(GPIO_USART4_RS485_DIR); + stm32_gpiowrite(GPIO_USART4_RS485_DIR, !CONFIG_USART4_RS485_DIR_POLARITY); #endif #endif -#ifdef CONFIG_STM32F0_USART5 +#ifdef CONFIG_STM32F0L0_USART5 /* Enable USART APB1 clock */ - modifyreg32(STM32F0_RCC_APB1ENR, 0, RCC_APB1ENR_USART5EN); + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART5EN); /* Configure RX/TX pins */ - stm32f0_configgpio(GPIO_USART5_TX); - stm32f0_configgpio(GPIO_USART5_RX); + stm32_configgpio(GPIO_USART5_TX); + stm32_configgpio(GPIO_USART5_RX); #ifdef CONFIG_USART5_RS485 - stm32f0_configgpio(GPIO_USART5_RS485_DIR); - stm32f0_gpiowrite(GPIO_USART5_RS485_DIR, !CONFIG_USART5_RS485_DIR_POLARITY); + stm32_configgpio(GPIO_USART5_RS485_DIR); + stm32_gpiowrite(GPIO_USART5_RS485_DIR, !CONFIG_USART5_RS485_DIR_POLARITY); #endif #endif @@ -365,41 +365,41 @@ void stm32f0_lowsetup(void) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) /* Configure CR2 */ - cr = getreg32(STM32F0_CONSOLE_BASE + STM32F0_USART_CR2_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); cr &= ~USART_CR2_CLRBITS; cr |= USART_CR2_SETBITS; - putreg32(cr, STM32F0_CONSOLE_BASE + STM32F0_USART_CR2_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); /* Configure CR1 */ - cr = getreg32(STM32F0_CONSOLE_BASE + STM32F0_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); cr &= ~USART_CR1_CLRBITS; cr |= USART_CR1_SETBITS; - putreg32(cr, STM32F0_CONSOLE_BASE + STM32F0_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); /* Configure CR3 */ - cr = getreg32(STM32F0_CONSOLE_BASE + STM32F0_USART_CR3_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_CLRBITS; cr |= USART_CR3_SETBITS; - putreg32(cr, STM32F0_CONSOLE_BASE + STM32F0_USART_CR3_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); /* Configure the USART Baud Rate */ - putreg32(STM32F0_BRR_VALUE, STM32F0_CONSOLE_BASE + STM32F0_USART_BRR_OFFSET); + putreg32(STM32_BRR_VALUE, STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); /* Select oversampling by 8 */ - cr = getreg32(STM32F0_CONSOLE_BASE + STM32F0_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #ifdef USE_OVER8 cr |= USART_CR1_OVER8; - putreg32(cr, STM32F0_CONSOLE_BASE + STM32F0_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* Enable Rx, Tx, and the USART */ cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32F0_CONSOLE_BASE + STM32F0_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ #endif /* HAVE_USART */ diff --git a/arch/arm/src/stm32f0/stm32f0_lowputc.h b/arch/arm/src/stm32f0l0/stm32_lowputc.h similarity index 91% rename from arch/arm/src/stm32f0/stm32f0_lowputc.h rename to arch/arm/src/stm32f0l0/stm32_lowputc.h index 9584d9faa5a..ee6a1723eca 100644 --- a/arch/arm/src/stm32f0/stm32f0_lowputc.h +++ b/arch/arm/src/stm32f0l0/stm32_lowputc.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/stm32f0_lowputc.h + * arch/arm/src/stm32f0l0/stm32_lowputc.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_LOWPUTC_H -#define __ARCH_ARM_SRC_STM32F0_STM32F0_LOWPUTC_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_LOWPUTC_H +#define __ARCH_ARM_SRC_STM32F0L0_STM32_LOWPUTC_H /************************************************************************************ * Included Files @@ -61,7 +61,7 @@ extern "C" #endif /************************************************************************************ - * Name: stm32f0_lowsetup + * Name: stm32_lowsetup * * Description: * Called at the very beginning of _start. Performs low level initialization @@ -69,7 +69,7 @@ extern "C" * ************************************************************************************/ -void stm32f0_lowsetup(void); +void stm32_lowsetup(void); #undef EXTERN #if defined(__cplusplus) @@ -77,4 +77,4 @@ void stm32f0_lowsetup(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_LOWPUTC_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_LOWPUTC_H */ diff --git a/arch/arm/src/stm32f0/stm32f0_rcc.h b/arch/arm/src/stm32f0l0/stm32_rcc.h similarity index 90% rename from arch/arm/src/stm32f0/stm32f0_rcc.h rename to arch/arm/src/stm32f0l0/stm32_rcc.h index e23484ae438..ba111b1f43d 100644 --- a/arch/arm/src/stm32f0/stm32f0_rcc.h +++ b/arch/arm/src/stm32f0l0/stm32_rcc.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/stm32f0_rcc.h + * arch/arm/src/stm32f0l0/stm32_rcc.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_RCC_H -#define __ARCH_ARM_SRC_STM32F0_STM32F0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32F0L0_STM32_RCC_H /************************************************************************************ * Included Files @@ -46,6 +46,6 @@ #include "up_arch.h" #include "chip.h" -#include "chip/stm32f0_rcc.h" +#include "hardware/stm32_rcc.h" -#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_RCC_H */ diff --git a/arch/arm/src/stm32f0/stm32f0_serial.c b/arch/arm/src/stm32f0l0/stm32_serial.c similarity index 77% rename from arch/arm/src/stm32f0/stm32f0_serial.c rename to arch/arm/src/stm32f0l0/stm32_serial.c index 824d8a73611..1ef9c94d9e9 100644 --- a/arch/arm/src/stm32f0/stm32f0_serial.c +++ b/arch/arm/src/stm32f0l0/stm32_serial.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0/stm32f0_serial.c + * arch/arm/src/stm32f0l0/stm32_serial.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -63,10 +63,10 @@ #include "up_arch.h" #include "up_internal.h" #include "chip.h" -#include "stm32f0_gpio.h" -#include "stm32f0_uart.h" -#include "stm32f0_rcc.h" -#include "chip/stm32f0_pinmap.h" +#include "stm32_gpio.h" +#include "stm32_uart.h" +#include "stm32_rcc.h" +#include "hardware/stm32_pinmap.h" /* board.h should be included last. It may depend on defintions from * previous header files and it may, in certain cases, override definitions @@ -98,14 +98,14 @@ */ # if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) -# ifndef CONFIG_STM32F0_DMA1 -# error STM32F0 USART2/3 receive DMA requires CONFIG_STM32F0_DMA1 +# ifndef CONFIG_STM32F0L0_DMA1 +# error STM32F0 USART2/3 receive DMA requires CONFIG_STM32F0L0_DMA1 # endif # endif # if defined(CONFIG_USART4_RXDMA) || defined(CONFIG_USART5_RXDMA) -# ifndef CONFIG_STM32F0_DMA2 -# error STM32F0 USART4/5 receive DMA requires CONFIG_STM32F0_DMA2 +# ifndef CONFIG_STM32F0L0_DMA2 +# error STM32F0 USART4/5 receive DMA requires CONFIG_STM32F0L0_DMA2 # endif # endif @@ -174,8 +174,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32F0_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32F0_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY 10 #endif #if defined(CONFIG_PM) # define PM_IDLE_DOMAIN 0 /* Revisit */ @@ -189,10 +189,10 @@ * register. It must not collide with USART_CR1_USED_INTS or USART_CR3_EIE * 2) USART_CR3_EIE is also carried in the up_dev_s ie member. * - * See stm32f0serial_restoreusartint where the masking is done. + * See stm32serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32F0_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32F0L0_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -204,7 +204,7 @@ * Private Types ****************************************************************************/ -struct stm32f0_serial_s +struct stm32_serial_s { struct uart_dev_s dev; /* Generic USART device */ uint16_t ie; /* Saved interrupt mask bits value */ @@ -274,46 +274,46 @@ struct stm32f0_serial_s ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -static void stm32f0serial_setformat(FAR struct uart_dev_s *dev); +static void stm32serial_setformat(FAR struct uart_dev_s *dev); #endif -static int stm32f0serial_setup(FAR struct uart_dev_s *dev); -static void stm32f0serial_shutdown(FAR struct uart_dev_s *dev); -static int stm32f0serial_attach(FAR struct uart_dev_s *dev); -static void stm32f0serial_detach(FAR struct uart_dev_s *dev); +static int stm32serial_setup(FAR struct uart_dev_s *dev); +static void stm32serial_shutdown(FAR struct uart_dev_s *dev); +static int stm32serial_attach(FAR struct uart_dev_s *dev); +static void stm32serial_detach(FAR struct uart_dev_s *dev); static int up_interrupt(int irq, FAR void *context, FAR void *arg); -static int stm32f0serial_ioctl(FAR struct file *filep, int cmd, - unsigned long arg); +static int stm32serial_ioctl(FAR struct file *filep, int cmd, + unsigned long arg); #ifndef SERIAL_HAVE_ONLY_DMA -static int stm32f0serial_receive(FAR struct uart_dev_s *dev, - FAR unsigned int *status); -static void stm32f0serial_rxint(FAR struct uart_dev_s *dev, bool enable); -static bool stm32f0serial_rxavailable(FAR struct uart_dev_s *dev); +static int stm32serial_receive(FAR struct uart_dev_s *dev, + FAR unsigned int *status); +static void stm32serial_rxint(FAR struct uart_dev_s *dev, bool enable); +static bool stm32serial_rxavailable(FAR struct uart_dev_s *dev); #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32f0serial_rxflowcontrol(FAR struct uart_dev_s *dev, - unsigned int nbuffered, bool upper); +static bool stm32serial_rxflowcontrol(FAR struct uart_dev_s *dev, + unsigned int nbuffered, bool upper); #endif -static void stm32f0serial_send(FAR struct uart_dev_s *dev, int ch); -static void stm32f0serial_txint(FAR struct uart_dev_s *dev, bool enable); -static bool stm32f0serial_txready(FAR struct uart_dev_s *dev); +static void stm32serial_send(FAR struct uart_dev_s *dev, int ch); +static void stm32serial_txint(FAR struct uart_dev_s *dev, bool enable); +static bool stm32serial_txready(FAR struct uart_dev_s *dev); #ifdef SERIAL_HAVE_DMA -static int stm32f0serial_dmasetup(FAR struct uart_dev_s *dev); -static void stm32f0serial_dmashutdown(FAR struct uart_dev_s *dev); -static int stm32f0serial_dmareceive(FAR struct uart_dev_s *dev, - FAR unsigned int *status); -static void stm32f0serial_dmarxint(FAR struct uart_dev_s *dev, bool enable); -static bool stm32f0serial_dmarxavailable(struct uart_dev_s *dev); +static int stm32serial_dmasetup(FAR struct uart_dev_s *dev); +static void stm32serial_dmashutdown(FAR struct uart_dev_s *dev); +static int stm32serial_dmareceive(FAR struct uart_dev_s *dev, + FAR unsigned int *status); +static void stm32serial_dmarxint(FAR struct uart_dev_s *dev, bool enable); +static bool stm32serial_dmarxavailable(struct uart_dev_s *dev); -static void stm32f0serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, - FAR void *arg); +static void stm32serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, + FAR void *arg); #endif #ifdef CONFIG_PM -static void stm32f0serial_pmnotify(FAR struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int stm32f0serial_pmprepare(FAR struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); +static void stm32serial_pmnotify(FAR struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int stm32serial_pmprepare(FAR struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); #endif /**************************************************************************** @@ -323,48 +323,48 @@ static int stm32f0serial_pmprepare(FAR struct pm_callback_s *cb, int domain, #ifndef SERIAL_HAVE_ONLY_DMA static const struct uart_ops_s g_uart_ops = { - .setup = stm32f0serial_setup, - .shutdown = stm32f0serial_shutdown, - .attach = stm32f0serial_attach, - .detach = stm32f0serial_detach, - .ioctl = stm32f0serial_ioctl, - .receive = stm32f0serial_receive, - .rxint = stm32f0serial_rxint, - .rxavailable = stm32f0serial_rxavailable, + .setup = stm32serial_setup, + .shutdown = stm32serial_shutdown, + .attach = stm32serial_attach, + .detach = stm32serial_detach, + .ioctl = stm32serial_ioctl, + .receive = stm32serial_receive, + .rxint = stm32serial_rxint, + .rxavailable = stm32serial_rxavailable, #ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = stm32f0serial_rxflowcontrol, + .rxflowcontrol = stm32serial_rxflowcontrol, #endif - .send = stm32f0serial_send, - .txint = stm32f0serial_txint, - .txready = stm32f0serial_txready, - .txempty = stm32f0serial_txready, + .send = stm32serial_send, + .txint = stm32serial_txint, + .txready = stm32serial_txready, + .txempty = stm32serial_txready, }; #endif #ifdef SERIAL_HAVE_DMA static const struct uart_ops_s g_uart_dma_ops = { - .setup = stm32f0serial_dmasetup, - .shutdown = stm32f0serial_dmashutdown, - .attach = stm32f0serial_attach, - .detach = stm32f0serial_detach, - .ioctl = stm32f0serial_ioctl, - .receive = stm32f0serial_dmareceive, - .rxint = stm32f0serial_dmarxint, - .rxavailable = stm32f0serial_dmarxavailable, + .setup = stm32serial_dmasetup, + .shutdown = stm32serial_dmashutdown, + .attach = stm32serial_attach, + .detach = stm32serial_detach, + .ioctl = stm32serial_ioctl, + .receive = stm32serial_dmareceive, + .rxint = stm32serial_dmarxint, + .rxavailable = stm32serial_dmarxavailable, #ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = stm32f0serial_rxflowcontrol, + .rxflowcontrol = stm32serial_rxflowcontrol, #endif - .send = stm32f0serial_send, - .txint = stm32f0serial_txint, - .txready = stm32f0serial_txready, - .txempty = stm32f0serial_txready, + .send = stm32serial_send, + .txint = stm32serial_txint, + .txready = stm32serial_txready, + .txempty = stm32serial_txready, }; #endif /* I/O buffers */ -#ifdef CONFIG_STM32F0_USART1 +#ifdef CONFIG_STM32F0L0_USART1 static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -372,7 +372,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32F0_USART2 +#ifdef CONFIG_STM32F0L0_USART2 static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; # ifdef CONFIG_USART2_RXDMA @@ -380,7 +380,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32F0_USART3 +#ifdef CONFIG_STM32F0L0_USART3 static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; # ifdef CONFIG_USART3_RXDMA @@ -388,7 +388,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32F0_USART4 +#ifdef CONFIG_STM32F0L0_USART4 static char g_usart4rxbuffer[CONFIG_USART4_RXBUFSIZE]; static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE]; # ifdef CONFIG_USART4_RXDMA @@ -396,7 +396,7 @@ static char g_usart4rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32F0_USART5 +#ifdef CONFIG_STM32F0L0_USART5 static char g_usart5rxbuffer[CONFIG_USART5_RXBUFSIZE]; static char g_usart5txbuffer[CONFIG_USART5_TXBUFSIZE]; # ifdef CONFIG_USART5_RXDMA @@ -406,8 +406,8 @@ static char g_usart5rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32F0_USART1 -static struct stm32f0_serial_s g_usart1priv = +#ifdef CONFIG_STM32F0L0_USART1 +static struct stm32_serial_s g_usart1priv = { .dev = { @@ -432,13 +432,13 @@ static struct stm32f0_serial_s g_usart1priv = .priv = &g_usart1priv, }, - .irq = STM32F0_IRQ_USART1, + .irq = STM32_IRQ_USART1, .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, .baud = CONFIG_USART1_BAUD, - .apbclock = STM32F0_PCLK2_FREQUENCY, - .usartbase = STM32F0_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) @@ -467,8 +467,8 @@ static struct stm32f0_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32F0_USART2 -static struct stm32f0_serial_s g_usart2priv = +#ifdef CONFIG_STM32F0L0_USART2 +static struct stm32_serial_s g_usart2priv = { .dev = { @@ -493,13 +493,13 @@ static struct stm32f0_serial_s g_usart2priv = .priv = &g_usart2priv, }, - .irq = STM32F0_IRQ_USART2, + .irq = STM32_IRQ_USART2, .parity = CONFIG_USART2_PARITY, .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, .baud = CONFIG_USART2_BAUD, - .apbclock = STM32F0_PCLK1_FREQUENCY, - .usartbase = STM32F0_USART2_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) @@ -528,8 +528,8 @@ static struct stm32f0_serial_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32F0_USART3 -static struct stm32f0_serial_s g_usart3priv = +#ifdef CONFIG_STM32F0L0_USART3 +static struct stm32_serial_s g_usart3priv = { .dev = { @@ -554,13 +554,13 @@ static struct stm32f0_serial_s g_usart3priv = .priv = &g_usart3priv, }, - .irq = STM32F0_IRQ_USART345678, + .irq = STM32_IRQ_USART345678, .parity = CONFIG_USART3_PARITY, .bits = CONFIG_USART3_BITS, .stopbits2 = CONFIG_USART3_2STOP, .baud = CONFIG_USART3_BAUD, - .apbclock = STM32F0_PCLK1_FREQUENCY, - .usartbase = STM32F0_USART3_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART3_BASE, .tx_gpio = GPIO_USART3_TX, .rx_gpio = GPIO_USART3_RX, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) @@ -589,8 +589,8 @@ static struct stm32f0_serial_s g_usart3priv = /* This describes the state of the STM32 USART4 port. */ -#ifdef CONFIG_STM32F0_USART4 -static struct stm32f0_serial_s g_usart4priv = +#ifdef CONFIG_STM32F0L0_USART4 +static struct stm32_serial_s g_usart4priv = { .dev = { @@ -615,7 +615,7 @@ static struct stm32f0_serial_s g_usart4priv = .priv = &g_usart4priv, }, - .irq = STM32F0_IRQ_USART345678, + .irq = STM32_IRQ_USART345678, .parity = CONFIG_USART4_PARITY, .bits = CONFIG_USART4_BITS, .stopbits2 = CONFIG_USART4_2STOP, @@ -626,8 +626,8 @@ static struct stm32f0_serial_s g_usart4priv = .oflow = false, #endif .baud = CONFIG_USART4_BAUD, - .apbclock = STM32F0_PCLK1_FREQUENCY, - .usartbase = STM32F0_USART4_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART4_BASE, .tx_gpio = GPIO_USART4_TX, .rx_gpio = GPIO_USART4_RX, #ifdef CONFIG_SERIAL_OFLOWCONTROL @@ -654,8 +654,8 @@ static struct stm32f0_serial_s g_usart4priv = /* This describes the state of the STM32 USART5 port. */ -#ifdef CONFIG_STM32F0_USART5 -static struct stm32f0_serial_s g_usart5priv = +#ifdef CONFIG_STM32F0L0_USART5 +static struct stm32_serial_s g_usart5priv = { .dev = { @@ -680,7 +680,7 @@ static struct stm32f0_serial_s g_usart5priv = .priv = &g_usart5priv, }, - .irq = STM32F0_IRQ_USART345678, + .irq = STM32_IRQ_USART345678, .parity = CONFIG_USART5_PARITY, .bits = CONFIG_USART5_BITS, .stopbits2 = CONFIG_USART5_2STOP, @@ -691,8 +691,8 @@ static struct stm32f0_serial_s g_usart5priv = .oflow = false, #endif .baud = CONFIG_USART5_BAUD, - .apbclock = STM32F0_PCLK1_FREQUENCY, - .usartbase = STM32F0_USART5_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART5_BASE, .tx_gpio = GPIO_USART5_TX, .rx_gpio = GPIO_USART5_RX, #ifdef CONFIG_SERIAL_OFLOWCONTROL @@ -719,21 +719,21 @@ static struct stm32f0_serial_s g_usart5priv = /* This table lets us iterate over the configured USARTs */ -FAR static struct stm32f0_serial_s * const g_uart_devs[STM32F0_NUSART] = +FAR static struct stm32_serial_s * const g_uart_devs[STM32_NUSART] = { -#ifdef CONFIG_STM32F0_USART1 +#ifdef CONFIG_STM32F0L0_USART1 [0] = &g_usart1priv, #endif -#ifdef CONFIG_STM32F0_USART2 +#ifdef CONFIG_STM32F0L0_USART2 [1] = &g_usart2priv, #endif -#ifdef CONFIG_STM32F0_USART3 +#ifdef CONFIG_STM32F0L0_USART3 [2] = &g_usart3priv, #endif -#ifdef CONFIG_STM32F0_USART4 +#ifdef CONFIG_STM32F0L0_USART4 [3] = &g_usart4priv, #endif -#ifdef CONFIG_STM32F0_USART5 +#ifdef CONFIG_STM32F0L0_USART5 [4] = &g_usart5priv, #endif }; @@ -741,8 +741,8 @@ FAR static struct stm32f0_serial_s * const g_uart_devs[STM32F0_NUSART] = #ifdef CONFIG_PM static struct pm_callback_s g_serialcb = { - .notify = stm32f0serial_pmnotify, - .prepare = stm32f0serial_pmprepare, + .notify = stm32serial_pmnotify, + .prepare = stm32serial_pmprepare, }; #endif @@ -751,31 +751,31 @@ static struct pm_callback_s g_serialcb = ****************************************************************************/ /**************************************************************************** - * Name: stm32f0serial_getreg + * Name: stm32serial_getreg ****************************************************************************/ -static inline uint32_t stm32f0serial_getreg(FAR struct stm32f0_serial_s *priv, - int offset) +static inline uint32_t stm32serial_getreg(FAR struct stm32_serial_s *priv, + int offset) { return getreg32(priv->usartbase + offset); } /**************************************************************************** - * Name: stm32f0serial_putreg + * Name: stm32serial_putreg ****************************************************************************/ -static inline void stm32f0serial_putreg(FAR struct stm32f0_serial_s *priv, - int offset, uint32_t value) +static inline void stm32serial_putreg(FAR struct stm32_serial_s *priv, + int offset, uint32_t value) { putreg32(value, priv->usartbase + offset); } /**************************************************************************** - * Name: stm32f0serial_setusartint + * Name: stm32serial_setusartint ****************************************************************************/ -static void stm32f0serial_setusartint(FAR struct stm32f0_serial_s *priv, - uint16_t ie) +static void stm32serial_setusartint(FAR struct stm32_serial_s *priv, + uint16_t ie) { uint32_t cr; @@ -785,39 +785,39 @@ static void stm32f0serial_setusartint(FAR struct stm32f0_serial_s *priv, /* And restore the interrupt state (see the interrupt enable/usage table above) */ - cr = stm32f0serial_getreg(priv, STM32F0_USART_CR1_OFFSET); + cr = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); cr &= ~(USART_CR1_USED_INTS); cr |= (ie & (USART_CR1_USED_INTS)); - stm32f0serial_putreg(priv, STM32F0_USART_CR1_OFFSET, cr); + stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); - cr = stm32f0serial_getreg(priv, STM32F0_USART_CR3_OFFSET); + cr = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_EIE; cr |= (ie & USART_CR3_EIE); - stm32f0serial_putreg(priv, STM32F0_USART_CR3_OFFSET, cr); + stm32serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); } /**************************************************************************** - * Name: stm32f0serial_restoreusartint + * Name: stm32serial_restoreusartint ****************************************************************************/ -static void stm32f0serial_restoreusartint(FAR struct stm32f0_serial_s *priv, - uint16_t ie) +static void stm32serial_restoreusartint(FAR struct stm32_serial_s *priv, + uint16_t ie) { irqstate_t flags; flags = enter_critical_section(); - stm32f0serial_setusartint(priv, ie); + stm32serial_setusartint(priv, ie); leave_critical_section(flags); } /**************************************************************************** - * Name: stm32f0serial_disableusartint + * Name: stm32serial_disableusartint ****************************************************************************/ -static void stm32f0serial_disableusartint(FAR struct stm32f0_serial_s *priv, - FAR uint16_t *ie) +static void stm32serial_disableusartint(FAR struct stm32_serial_s *priv, + FAR uint16_t *ie) { irqstate_t flags; @@ -846,8 +846,8 @@ static void stm32f0serial_disableusartint(FAR struct stm32f0_serial_s *priv, * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) */ - cr1 = stm32f0serial_getreg(priv, STM32F0_USART_CR1_OFFSET); - cr3 = stm32f0serial_getreg(priv, STM32F0_USART_CR3_OFFSET); + cr1 = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr3 = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); /* Return the current interrupt mask value for the used interrupts. Notice * that this depends on the fact that none of the used interrupt enable bits @@ -859,13 +859,13 @@ static void stm32f0serial_disableusartint(FAR struct stm32f0_serial_s *priv, /* Disable all interrupts */ - stm32f0serial_setusartint(priv, 0); + stm32serial_setusartint(priv, 0); leave_critical_section(flags); } /**************************************************************************** - * Name: stm32f0serial_dmanextrx + * Name: stm32serial_dmanextrx * * Description: * Returns the index into the RX FIFO where the DMA will place the next @@ -874,18 +874,18 @@ static void stm32f0serial_disableusartint(FAR struct stm32f0_serial_s *priv, ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -static int stm32f0serial_dmanextrx(FAR struct stm32f0_serial_s *priv) +static int stm32serial_dmanextrx(FAR struct stm32_serial_s *priv) { size_t dmaresidual; - dmaresidual = stm32f0_dmaresidual(priv->rxdma); + dmaresidual = stm32_dmaresidual(priv->rxdma); return (RXDMA_BUFFER_SIZE - (int)dmaresidual); } #endif /**************************************************************************** - * Name: stm32f0serial_setformat + * Name: stm32serial_setformat * * Description: * Set the serial line format and speed. @@ -893,9 +893,9 @@ static int stm32f0serial_dmanextrx(FAR struct stm32f0_serial_s *priv) ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -static void stm32f0serial_setformat(FAR struct uart_dev_s *dev) +static void stm32serial_setformat(FAR struct uart_dev_s *dev) { - FAR struct stm32f0_serial_s *priv = (FAR struct stm32f0_serial_s *)dev->priv; + FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)dev->priv; uint32_t regval; /* This first implementation is for U[S]ARTs that support oversampling @@ -924,7 +924,7 @@ static void stm32f0serial_setformat(FAR struct uart_dev_s *dev) /* Use oversamply by 8 only if the divisor is small. But what is small? */ - cr1 = stm32f0serial_getreg(priv, STM32F0_USART_CR1_OFFSET); + cr1 = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); if (usartdiv8 > 100) { /* Use usartdiv16 */ @@ -948,12 +948,12 @@ static void stm32f0serial_setformat(FAR struct uart_dev_s *dev) cr1 |= USART_CR1_OVER8; } - stm32f0serial_putreg(priv, STM32F0_USART_CR1_OFFSET, cr1); - stm32f0serial_putreg(priv, STM32F0_USART_BRR_OFFSET, brr); + stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); /* Configure parity mode */ - regval = stm32f0serial_getreg(priv, STM32F0_USART_CR1_OFFSET); + regval = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); if (priv->parity == 1) /* Odd parity */ @@ -990,11 +990,11 @@ static void stm32f0serial_setformat(FAR struct uart_dev_s *dev) * 1 start, 8 data (no parity), n stop. */ - stm32f0serial_putreg(priv, STM32F0_USART_CR1_OFFSET, regval); + stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure STOP bits */ - regval = stm32f0serial_getreg(priv, STM32F0_USART_CR2_OFFSET); + regval = stm32serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK); if (priv->stopbits2) @@ -1002,14 +1002,14 @@ static void stm32f0serial_setformat(FAR struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32f0serial_putreg(priv, STM32F0_USART_CR2_OFFSET, regval); + stm32serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure hardware flow control */ - regval = stm32f0serial_getreg(priv, STM32F0_USART_CR3_OFFSET); + regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32F0_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32F0L0_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1023,12 +1023,12 @@ static void stm32f0serial_setformat(FAR struct uart_dev_s *dev) } #endif - stm32f0serial_putreg(priv, STM32F0_USART_CR3_OFFSET, regval); + stm32serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); } #endif /* CONFIG_SUPPRESS_UART_CONFIG */ /**************************************************************************** - * Name: stm32f0serial_setapbclock + * Name: stm32serial_setapbclock * * Description: * Enable or disable APB clock for the USART peripheral @@ -1039,9 +1039,9 @@ static void stm32f0serial_setformat(FAR struct uart_dev_s *dev) * ****************************************************************************/ -static void stm32f0serial_setapbclock(FAR struct uart_dev_s *dev, bool on) +static void stm32serial_setapbclock(FAR struct uart_dev_s *dev, bool on) { - FAR struct stm32f0_serial_s *priv = (FAR struct stm32f0_serial_s *)dev->priv; + FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)dev->priv; uint32_t rcc_en; uint32_t regaddr; @@ -1051,34 +1051,34 @@ static void stm32f0serial_setapbclock(FAR struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32F0_USART1 - case STM32F0_USART1_BASE: +#ifdef CONFIG_STM32F0L0_USART1 + case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32F0_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32F0_USART2 - case STM32F0_USART2_BASE: +#ifdef CONFIG_STM32F0L0_USART2 + case STM32_USART2_BASE: rcc_en = RCC_APB1ENR_USART2EN; - regaddr = STM32F0_RCC_APB1ENR; + regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F0_USART3 - case STM32F0_USART3_BASE: +#ifdef CONFIG_STM32F0L0_USART3 + case STM32_USART3_BASE: rcc_en = RCC_APB1ENR_USART3EN; - regaddr = STM32F0_RCC_APB1ENR; + regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F0_USART4 - case STM32F0_USART4_BASE: +#ifdef CONFIG_STM32F0L0_USART4 + case STM32_USART4_BASE: rcc_en = RCC_APB1ENR_USART4EN; - regaddr = STM32F0_RCC_APB1ENR; + regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F0_USART5 - case STM32F0_USART5_BASE: +#ifdef CONFIG_STM32F0L0_USART5 + case STM32_USART5_BASE: rcc_en = RCC_APB1ENR_USART5EN; - regaddr = STM32F0_RCC_APB1ENR; + regaddr = STM32_RCC_APB1ENR; break; #endif } @@ -1096,7 +1096,7 @@ static void stm32f0serial_setapbclock(FAR struct uart_dev_s *dev, bool on) } /**************************************************************************** - * Name: stm32f0serial_setup + * Name: stm32serial_setup * * Description: * Configure the USART baud, bits, parity, etc. This method is called the @@ -1104,30 +1104,30 @@ static void stm32f0serial_setapbclock(FAR struct uart_dev_s *dev, bool on) * ****************************************************************************/ -static int stm32f0serial_setup(FAR struct uart_dev_s *dev) +static int stm32serial_setup(FAR struct uart_dev_s *dev) { - FAR struct stm32f0_serial_s *priv = (FAR struct stm32f0_serial_s *)dev->priv; + FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)dev->priv; #ifndef CONFIG_SUPPRESS_UART_CONFIG uint32_t regval; /* Note: The logic here depends on the fact that that the USART module - * was enabled in stm32f0_lowsetup(). + * was enabled in stm32_lowsetup(). */ /* Enable USART APB1/2 clock */ - stm32f0serial_setapbclock(dev, true); + stm32serial_setapbclock(dev, true); /* Configure pins for USART use */ - stm32f0_configgpio(priv->tx_gpio); - stm32f0_configgpio(priv->rx_gpio); + stm32_configgpio(priv->tx_gpio); + stm32_configgpio(priv->rx_gpio); #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32f0_configgpio(priv->cts_gpio); + stm32_configgpio(priv->cts_gpio); } #endif @@ -1136,27 +1136,27 @@ static int stm32f0serial_setup(FAR struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32F0_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32F0L0_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; #endif - stm32f0_configgpio(config); + stm32_configgpio(config); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32f0_configgpio(priv->rs485_dir_gpio); - stm32f0_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_configgpio(priv->rs485_dir_gpio); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); } #endif /* Configure CR2 */ /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - regval = stm32f0serial_getreg(priv, STM32F0_USART_CR2_OFFSET); + regval = stm32serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); @@ -1167,34 +1167,34 @@ static int stm32f0serial_setup(FAR struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32f0serial_putreg(priv, STM32F0_USART_CR2_OFFSET, regval); + stm32serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 */ /* Clear TE, REm and all interrupt enable bits */ - regval = stm32f0serial_getreg(priv, STM32F0_USART_CR1_OFFSET); + regval = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - stm32f0serial_putreg(priv, STM32F0_USART_CR1_OFFSET, regval); + stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 */ /* Clear CTSE, RTSE, and all interrupt enable bits */ - regval = stm32f0serial_getreg(priv, STM32F0_USART_CR3_OFFSET); + regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); - stm32f0serial_putreg(priv, STM32F0_USART_CR3_OFFSET, regval); + stm32serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); /* Configure the USART line format and speed. */ - stm32f0serial_setformat(dev); + stm32serial_setformat(dev); /* Enable Rx, Tx, and the USART */ - regval = stm32f0serial_getreg(priv, STM32F0_USART_CR1_OFFSET); + regval = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32f0serial_putreg(priv, STM32F0_USART_CR1_OFFSET, regval); + stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1205,7 +1205,7 @@ static int stm32f0serial_setup(FAR struct uart_dev_s *dev) } /**************************************************************************** - * Name: stm32f0serial_dmasetup + * Name: stm32serial_dmasetup * * Description: * Configure the USART baud, bits, parity, etc. This method is called the @@ -1214,9 +1214,9 @@ static int stm32f0serial_setup(FAR struct uart_dev_s *dev) ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -static int stm32f0serial_dmasetup(FAR struct uart_dev_s *dev) +static int stm32serial_dmasetup(FAR struct uart_dev_s *dev) { - FAR struct stm32f0_serial_s *priv = (FAR struct stm32f0_serial_s *)dev->priv; + FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)dev->priv; int result; uint32_t regval; @@ -1224,7 +1224,7 @@ static int stm32f0serial_dmasetup(FAR struct uart_dev_s *dev) if (!dev->isconsole) { - result = stm32f0serial_setup(dev); + result = stm32serial_setup(dev); if (result != OK) { return result; @@ -1233,15 +1233,15 @@ static int stm32f0serial_dmasetup(FAR struct uart_dev_s *dev) /* Acquire the DMA channel. This should always succeed. */ - priv->rxdma = stm32f0_dmachannel(priv->rxdma_channel); + priv->rxdma = stm32_dmachannel(priv->rxdma_channel); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32f0_dmasetup(priv->rxdma, - priv->usartbase + STM32F0_USART_RDR_OFFSET, + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -1251,8 +1251,8 @@ static int stm32f0serial_dmasetup(FAR struct uart_dev_s *dev) { /* Configure for circular DMA reception into the RX FIFO */ - stm32f0_dmasetup(priv->rxdma, - priv->usartbase + STM32F0_USART_RDR_OFFSET, + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -1266,9 +1266,9 @@ static int stm32f0serial_dmasetup(FAR struct uart_dev_s *dev) /* Enable receive DMA for the USART */ - regval = stm32f0serial_getreg(priv, STM32F0_USART_CR3_OFFSET); + regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); regval |= USART_CR3_DMAR; - stm32f0serial_putreg(priv, STM32F0_USART_CR3_OFFSET, regval); + stm32serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) @@ -1278,7 +1278,7 @@ static int stm32f0serial_dmasetup(FAR struct uart_dev_s *dev) * in and DMA transfer is stopped. */ - stm32f0_dmastart(priv->rxdma, stm32f0serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32serial_dmarxcallback, (void *)priv, false); } else @@ -1289,7 +1289,7 @@ static int stm32f0serial_dmasetup(FAR struct uart_dev_s *dev) * worth of time to claim bytes before they are overwritten. */ - stm32f0_dmastart(priv->rxdma, stm32f0serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32serial_dmarxcallback, (void *)priv, true); } @@ -1298,7 +1298,7 @@ static int stm32f0serial_dmasetup(FAR struct uart_dev_s *dev) #endif /**************************************************************************** - * Name: stm32f0serial_shutdown + * Name: stm32serial_shutdown * * Description: * Disable the USART. This method is called when the serial @@ -1306,24 +1306,24 @@ static int stm32f0serial_dmasetup(FAR struct uart_dev_s *dev) * ****************************************************************************/ -static void stm32f0serial_shutdown(FAR struct uart_dev_s *dev) +static void stm32serial_shutdown(FAR struct uart_dev_s *dev) { - FAR struct stm32f0_serial_s *priv = (FAR struct stm32f0_serial_s *)dev->priv; + FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)dev->priv; uint32_t regval; /* Disable all interrupts */ - stm32f0serial_disableusartint(priv, NULL); + stm32serial_disableusartint(priv, NULL); /* Disable USART APB1/2 clock */ - stm32f0serial_setapbclock(dev, false); + stm32serial_setapbclock(dev, false); /* Disable Rx, Tx, and the USART */ - regval = stm32f0serial_getreg(priv, STM32F0_USART_CR1_OFFSET); + regval = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32f0serial_putreg(priv, STM32F0_USART_CR1_OFFSET, regval); + stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Release pins. "If the serial-attached device is powered down, the TX * pin causes back-powering, potentially confusing the device to the point @@ -1333,33 +1333,33 @@ static void stm32f0serial_shutdown(FAR struct uart_dev_s *dev) * then this may need to be a configuration option. */ - stm32f0_unconfiggpio(priv->tx_gpio); - stm32f0_unconfiggpio(priv->rx_gpio); + stm32_unconfiggpio(priv->tx_gpio); + stm32_unconfiggpio(priv->rx_gpio); #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32f0_unconfiggpio(priv->cts_gpio); + stm32_unconfiggpio(priv->cts_gpio); } #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->rts_gpio != 0) { - stm32f0_unconfiggpio(priv->rts_gpio); + stm32_unconfiggpio(priv->rts_gpio); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32f0_unconfiggpio(priv->rs485_dir_gpio); + stm32_unconfiggpio(priv->rs485_dir_gpio); } #endif } /**************************************************************************** - * Name: stm32f0serial_dmashutdown + * Name: stm32serial_dmashutdown * * Description: * Disable the USART. This method is called when the serial @@ -1368,27 +1368,27 @@ static void stm32f0serial_shutdown(FAR struct uart_dev_s *dev) ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -static void stm32f0serial_dmashutdown(FAR struct uart_dev_s *dev) +static void stm32serial_dmashutdown(FAR struct uart_dev_s *dev) { - FAR struct stm32f0_serial_s *priv = (FAR struct stm32f0_serial_s *)dev->priv; + FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)dev->priv; /* Perform the normal USART shutdown */ - stm32f0serial_shutdown(dev); + stm32serial_shutdown(dev); /* Stop the DMA channel */ - stm32f0_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); /* Release the DMA channel */ - stm32f0_dmafree(priv->rxdma); + stm32_dmafree(priv->rxdma); priv->rxdma = NULL; } #endif /**************************************************************************** - * Name: stm32f0serial_attach + * Name: stm32serial_attach * * Description: * Configure the USART to operation in interrupt driven mode. This method is @@ -1402,9 +1402,9 @@ static void stm32f0serial_dmashutdown(FAR struct uart_dev_s *dev) * ****************************************************************************/ -static int stm32f0serial_attach(FAR struct uart_dev_s *dev) +static int stm32serial_attach(FAR struct uart_dev_s *dev) { - FAR struct stm32f0_serial_s *priv = (FAR struct stm32f0_serial_s *)dev->priv; + FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -1423,7 +1423,7 @@ static int stm32f0serial_attach(FAR struct uart_dev_s *dev) } /**************************************************************************** - * Name: stm32f0serial_detach + * Name: stm32serial_detach * * Description: * Detach USART interrupts. This method is called when the serial port is @@ -1432,9 +1432,9 @@ static int stm32f0serial_attach(FAR struct uart_dev_s *dev) * ****************************************************************************/ -static void stm32f0serial_detach(FAR struct uart_dev_s *dev) +static void stm32serial_detach(FAR struct uart_dev_s *dev) { - FAR struct stm32f0_serial_s *priv = (FAR struct stm32f0_serial_s *)dev->priv; + FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -1453,7 +1453,7 @@ static void stm32f0serial_detach(FAR struct uart_dev_s *dev) static int up_interrupt(int irq, FAR void *context, FAR void *arg) { - FAR struct stm32f0_serial_s *priv = (FAR struct stm32f0_serial_s *)arg; + FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)arg; int passes; bool handled; @@ -1461,8 +1461,8 @@ static int up_interrupt(int irq, FAR void *context, FAR void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32F0_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F0_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1476,7 +1476,7 @@ static int up_interrupt(int irq, FAR void *context, FAR void *arg) /* Get the masked USART status word. */ - priv->sr = stm32f0serial_getreg(priv, STM32F0_USART_ISR_OFFSET); + priv->sr = stm32serial_getreg(priv, STM32_USART_ISR_OFFSET); /* USART interrupts: * @@ -1510,8 +1510,8 @@ static int up_interrupt(int irq, FAR void *context, FAR void *arg) if ((priv->sr & USART_ISR_TC) != 0 && (priv->ie & USART_CR1_TCIE) != 0 && (priv->ie & USART_CR1_TXEIE) == 0) { - stm32f0_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); - stm32f0serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); } #endif @@ -1537,7 +1537,7 @@ static int up_interrupt(int irq, FAR void *context, FAR void *arg) * interrupt clear register (ICR). */ - stm32f0serial_putreg(priv, STM32F0_USART_ICR_OFFSET, + stm32serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -1556,14 +1556,14 @@ static int up_interrupt(int irq, FAR void *context, FAR void *arg) } /**************************************************************************** - * Name: stm32f0serial_ioctl + * Name: stm32serial_ioctl * * Description: * All ioctl calls will be routed through this method * ****************************************************************************/ -static int stm32f0serial_ioctl(FAR struct file *filep, int cmd, +static int stm32serial_ioctl(FAR struct file *filep, int cmd, unsigned long arg) { #if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) @@ -1571,7 +1571,7 @@ static int stm32f0serial_ioctl(FAR struct file *filep, int cmd, FAR struct uart_dev_s *dev = inode->i_private; #endif #if defined(CONFIG_SERIAL_TERMIOS) - FAR struct stm32f0_serial_s *priv = (FAR struct stm32f0_serial_s *)dev->priv; + FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)dev->priv; #endif int ret = OK; @@ -1580,20 +1580,20 @@ static int stm32f0serial_ioctl(FAR struct file *filep, int cmd, #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - FAR struct stm32f0_serial_s *user = (FAR struct stm32f0_serial_s *)arg; + FAR struct stm32_serial_s *user = (FAR struct stm32_serial_s *)arg; if (!user) { ret = -EINVAL; } else { - memcpy(user, dev, sizeof(struct stm32f0_serial_s)); + memcpy(user, dev, sizeof(struct stm32_serial_s)); } } break; #endif -#ifdef CONFIG_STM32F0_USART_SINGLEWIRE +#ifdef CONFIG_STM32F0L0_USART_SINGLEWIRE #warning please review the potential use of ALTERNATE_FUNCTION_OPENDRAIN case TIOCSSINGLEWIRE: { @@ -1601,20 +1601,20 @@ static int stm32f0serial_ioctl(FAR struct file *filep, int cmd, * half-duplex mode. */ - uint32_t cr = stm32f0serial_getreg(priv, STM32F0_USART_CR3_OFFSET); + uint32_t cr = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); if (arg == SER_SINGLEWIRE_ENABLED) { - stm32f0_configgpio(priv->tx_gpio | GPIO_OPENDRAIN); + stm32_configgpio(priv->tx_gpio | GPIO_OPENDRAIN); cr |= USART_CR3_HDSEL; } else { - stm32f0_configgpio(priv->tx_gpio | GPIO_PUSHPULL); + stm32_configgpio(priv->tx_gpio | GPIO_PUSHPULL); cr &= ~USART_CR3_HDSEL; } - stm32f0serial_putreg(priv, STM32F0_USART_CR3_OFFSET, cr); + stm32serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); } break; #endif @@ -1709,13 +1709,13 @@ static int stm32f0serial_ioctl(FAR struct file *filep, int cmd, * TCSADRAIN / TCSAFLUSH */ - stm32f0serial_setformat(dev); + stm32serial_setformat(dev); } break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32F0_USART_BREAKS -# ifdef CONFIG_STM32F0_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32F0L0_USART_BREAKS +# ifdef CONFIG_STM32F0L0_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -1727,12 +1727,12 @@ static int stm32f0serial_ioctl(FAR struct file *filep, int cmd, priv->ie |= USART_CR1_IE_BREAK_INPROGRESS; - stm32f0serial_txint(dev, false); + stm32serial_txint(dev, false); /* Configure TX as a GPIO output pin and Send a break signal*/ tx_break = GPIO_OUTPUT | (~(GPIO_MODE_MASK|GPIO_OUTPUT_SET) & priv->tx_gpio); - stm32f0_configgpio(tx_break); + stm32_configgpio(tx_break); leave_critical_section(flags); } @@ -1746,13 +1746,13 @@ static int stm32f0serial_ioctl(FAR struct file *filep, int cmd, /* Configure TX back to U(S)ART */ - stm32f0_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; /* Enable further tx activity */ - stm32f0serial_txint(dev, true); + stm32serial_txint(dev, true); leave_critical_section(flags); } @@ -1764,8 +1764,8 @@ static int stm32f0serial_ioctl(FAR struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32f0serial_getreg(priv, STM32F0_USART_CR1_OFFSET); - stm32f0serial_putreg(priv, STM32F0_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); + cr1 = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); leave_critical_section(flags); } break; @@ -1776,8 +1776,8 @@ static int stm32f0serial_ioctl(FAR struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32f0serial_getreg(priv, STM32F0_USART_CR1_OFFSET); - stm32f0serial_putreg(priv, STM32F0_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); + cr1 = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } break; @@ -1793,7 +1793,7 @@ static int stm32f0serial_ioctl(FAR struct file *filep, int cmd, } /**************************************************************************** - * Name: stm32f0serial_receive + * Name: stm32serial_receive * * Description: * Called (usually) from the interrupt level to receive one @@ -1803,15 +1803,15 @@ static int stm32f0serial_ioctl(FAR struct file *filep, int cmd, ****************************************************************************/ #ifndef SERIAL_HAVE_ONLY_DMA -static int stm32f0serial_receive(FAR struct uart_dev_s *dev, - FAR unsigned int *status) +static int stm32serial_receive(FAR struct uart_dev_s *dev, + FAR unsigned int *status) { - FAR struct stm32f0_serial_s *priv = (FAR struct stm32f0_serial_s *)dev->priv; + FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)dev->priv; uint32_t rdr; /* Get the Rx byte */ - rdr = stm32f0serial_getreg(priv, STM32F0_USART_RDR_OFFSET); + rdr = stm32serial_getreg(priv, STM32_USART_RDR_OFFSET); /* Get the Rx byte plux error information. Return those in status */ @@ -1825,7 +1825,7 @@ static int stm32f0serial_receive(FAR struct uart_dev_s *dev, #endif /**************************************************************************** - * Name: stm32f0serial_rxint + * Name: stm32serial_rxint * * Description: * Call to enable or disable RX interrupts @@ -1833,9 +1833,9 @@ static int stm32f0serial_receive(FAR struct uart_dev_s *dev, ****************************************************************************/ #ifndef SERIAL_HAVE_ONLY_DMA -static void stm32f0serial_rxint(FAR struct uart_dev_s *dev, bool enable) +static void stm32serial_rxint(FAR struct uart_dev_s *dev, bool enable) { - FAR struct stm32f0_serial_s *priv = (FAR struct stm32f0_serial_s *)dev->priv; + FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)dev->priv; irqstate_t flags; uint16_t ie; @@ -1877,13 +1877,13 @@ static void stm32f0serial_rxint(FAR struct uart_dev_s *dev, bool enable) /* Then set the new interrupt state */ - stm32f0serial_restoreusartint(priv, ie); + stm32serial_restoreusartint(priv, ie); leave_critical_section(flags); } #endif /**************************************************************************** - * Name: stm32f0serial_rxavailable + * Name: stm32serial_rxavailable * * Description: * Return true if the receive register is not empty @@ -1891,15 +1891,15 @@ static void stm32f0serial_rxint(FAR struct uart_dev_s *dev, bool enable) ****************************************************************************/ #ifndef SERIAL_HAVE_ONLY_DMA -static bool stm32f0serial_rxavailable(FAR struct uart_dev_s *dev) +static bool stm32serial_rxavailable(FAR struct uart_dev_s *dev) { - FAR struct stm32f0_serial_s *priv = (FAR struct stm32f0_serial_s *)dev->priv; - return ((stm32f0serial_getreg(priv, STM32F0_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); + FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)dev->priv; + return ((stm32serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); } #endif /**************************************************************************** - * Name: stm32f0serial_rxflowcontrol + * Name: stm32serial_rxflowcontrol * * Description: * Called when Rx buffer is full (or exceeds configured watermark levels @@ -1922,18 +1922,18 @@ static bool stm32f0serial_rxavailable(FAR struct uart_dev_s *dev) ****************************************************************************/ #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32f0serial_rxflowcontrol(FAR struct uart_dev_s *dev, - unsigned int nbuffered, bool upper) +static bool stm32serial_rxflowcontrol(FAR struct uart_dev_s *dev, + unsigned int nbuffered, bool upper) { - FAR struct stm32f0_serial_s *priv = (FAR struct stm32f0_serial_s *)dev->priv; + FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32F0_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32F0L0_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ - stm32f0_gpiowrite(priv->rts_gpio, upper); + stm32_gpiowrite(priv->rts_gpio, upper); return upper; } @@ -1979,7 +1979,7 @@ static bool stm32f0serial_rxflowcontrol(FAR struct uart_dev_s *dev, #endif /**************************************************************************** - * Name: stm32f0serial_dmareceive + * Name: stm32serial_dmareceive * * Description: * Called (usually) from the interrupt level to receive one @@ -1989,13 +1989,13 @@ static bool stm32f0serial_rxflowcontrol(FAR struct uart_dev_s *dev, ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -static int stm32f0serial_dmareceive(FAR struct uart_dev_s *dev, - FAR unsigned int *status) +static int stm32serial_dmareceive(FAR struct uart_dev_s *dev, + FAR unsigned int *status) { - FAR struct stm32f0_serial_s *priv = (FAR struct stm32f0_serial_s *)dev->priv; + FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)dev->priv; int c = 0; - if (stm32f0serial_dmanextrx(priv) != priv->rxdmanext) + if (stm32serial_dmanextrx(priv) != priv->rxdmanext) { c = priv->rxfifo[priv->rxdmanext]; @@ -2022,7 +2022,7 @@ static int stm32f0serial_dmareceive(FAR struct uart_dev_s *dev, #endif /**************************************************************************** - * Name: stm32f0serial_dmareenable + * Name: stm32serial_dmareenable * * Description: * Call to re-enable RX DMA. @@ -2030,12 +2030,12 @@ static int stm32f0serial_dmareceive(FAR struct uart_dev_s *dev, ****************************************************************************/ #if defined(SERIAL_HAVE_DMA) && defined(CONFIG_SERIAL_IFLOWCONTROL) -static void stm32f0serial_dmareenable(FAR struct stm32f0_serial_s *priv) +static void stm32serial_dmareenable(FAR struct stm32_serial_s *priv) { /* Configure for non-circular DMA reception into the RX fifo */ - stm32f0_dmasetup(priv->rxdma, - priv->usartbase + STM32F0_USART_RDR_OFFSET, + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -2051,13 +2051,13 @@ static void stm32f0serial_dmareenable(FAR struct stm32f0_serial_s *priv) * DMA transfer is stopped. */ - stm32f0_dmastart(priv->rxdma, stm32f0serial_dmarxcallback, (FAR void *)priv, - false); + stm32_dmastart(priv->rxdma, stm32serial_dmarxcallback, (FAR void *)priv, + false); } #endif /**************************************************************************** - * Name: stm32f0serial_dmarxint + * Name: stm32serial_dmarxint * * Description: * Call to enable or disable RX interrupts @@ -2065,9 +2065,9 @@ static void stm32f0serial_dmareenable(FAR struct stm32f0_serial_s *priv) ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -static void stm32f0serial_dmarxint(FAR struct uart_dev_s *dev, bool enable) +static void stm32serial_dmarxint(FAR struct uart_dev_s *dev, bool enable) { - FAR struct stm32f0_serial_s *priv = (FAR struct stm32f0_serial_s *)dev->priv; + FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)dev->priv; /* En/disable DMA reception. * @@ -2084,14 +2084,14 @@ static void stm32f0serial_dmarxint(FAR struct uart_dev_s *dev, bool enable) { /* Re-enable RX DMA. */ - stm32f0serial_dmareenable(priv); + stm32serial_dmareenable(priv); } #endif } #endif /**************************************************************************** - * Name: stm32f0serial_dmarxavailable + * Name: stm32serial_dmarxavailable * * Description: * Return true if the receive register is not empty @@ -2099,51 +2099,51 @@ static void stm32f0serial_dmarxint(FAR struct uart_dev_s *dev, bool enable) ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -static bool stm32f0serial_dmarxavailable(FAR struct uart_dev_s *dev) +static bool stm32serial_dmarxavailable(FAR struct uart_dev_s *dev) { - FAR struct stm32f0_serial_s *priv = (FAR struct stm32f0_serial_s *)dev->priv; + FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)dev->priv; /* Compare our receive pointer to the current DMA pointer, if they * do not match, then there are bytes to be received. */ - return (stm32f0serial_dmanextrx(priv) != priv->rxdmanext); + return (stm32serial_dmanextrx(priv) != priv->rxdmanext); } #endif /**************************************************************************** - * Name: stm32f0serial_send + * Name: stm32serial_send * * Description: * This method will send one byte on the USART * ****************************************************************************/ -static void stm32f0serial_send(FAR struct uart_dev_s *dev, int ch) +static void stm32serial_send(FAR struct uart_dev_s *dev, int ch) { - FAR struct stm32f0_serial_s *priv = (FAR struct stm32f0_serial_s *)dev->priv; + FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)dev->priv; #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32f0_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); } #endif - stm32f0serial_putreg(priv, STM32F0_USART_TDR_OFFSET, (uint32_t)ch); + stm32serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); } /**************************************************************************** - * Name: stm32f0serial_txint + * Name: stm32serial_txint * * Description: * Call to enable or disable TX interrupts * ****************************************************************************/ -static void stm32f0serial_txint(FAR struct uart_dev_s *dev, bool enable) +static void stm32serial_txint(FAR struct uart_dev_s *dev, bool enable) { - FAR struct stm32f0_serial_s *priv = (FAR struct stm32f0_serial_s *)dev->priv; + FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)dev->priv; irqstate_t flags; /* USART transmit interrupts: @@ -2174,14 +2174,14 @@ static void stm32f0serial_txint(FAR struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32F0_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32F0L0_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { return; } # endif - stm32f0serial_restoreusartint(priv, ie); + stm32serial_restoreusartint(priv, ie); /* Fake a TX interrupt here by just calling uart_xmitchars() with * interrupts disabled (note this may recurse). @@ -2194,28 +2194,28 @@ static void stm32f0serial_txint(FAR struct uart_dev_s *dev, bool enable) { /* Disable the TX interrupt */ - stm32f0serial_restoreusartint(priv, priv->ie & ~USART_CR1_TXEIE); + stm32serial_restoreusartint(priv, priv->ie & ~USART_CR1_TXEIE); } leave_critical_section(flags); } /**************************************************************************** - * Name: stm32f0serial_txready + * Name: stm32serial_txready * * Description: * Return true if the transmit data register is empty * ****************************************************************************/ -static bool stm32f0serial_txready(FAR struct uart_dev_s *dev) +static bool stm32serial_txready(FAR struct uart_dev_s *dev) { - FAR struct stm32f0_serial_s *priv = (FAR struct stm32f0_serial_s *)dev->priv; - return ((stm32f0serial_getreg(priv, STM32F0_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); + FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)dev->priv; + return ((stm32serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } /**************************************************************************** - * Name: stm32f0serial_dmarxcallback + * Name: stm32serial_dmarxcallback * * Description: * This function checks the current DMA state and calls the generic @@ -2224,12 +2224,12 @@ static bool stm32f0serial_txready(FAR struct uart_dev_s *dev) ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -static void stm32f0serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, +static void stm32serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, FAR void *arg) { - FAR struct stm32f0_serial_s *priv = (FAR struct stm32f0_serial_s *)arg; + FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)arg; - if (priv->rxenable && stm32f0serial_dmarxavailable(&priv->dev)) + if (priv->rxenable && stm32serial_dmarxavailable(&priv->dev)) { uart_recvchars(&priv->dev); @@ -2239,7 +2239,7 @@ static void stm32f0serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, { /* Re-enable RX DMA. */ - stm32f0serial_dmareenable(priv); + stm32serial_dmareenable(priv); } #endif } @@ -2247,7 +2247,7 @@ static void stm32f0serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, #endif /**************************************************************************** - * Name: stm32f0serial_pmnotify + * Name: stm32serial_pmnotify * * Description: * Notify the driver of new power state. This callback is called after @@ -2269,7 +2269,7 @@ static void stm32f0serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, ****************************************************************************/ #ifdef CONFIG_PM -static void stm32f0serial_pmnotify(FAR struct pm_callback_s *cb, int domain, +static void stm32serial_pmnotify(FAR struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { switch (pmstate) @@ -2310,7 +2310,7 @@ static void stm32f0serial_pmnotify(FAR struct pm_callback_s *cb, int domain, #endif /**************************************************************************** - * Name: stm32f0serial_pmprepare + * Name: stm32serial_pmprepare * * Description: * Request the driver to prepare for a new power state. This is a warning @@ -2343,8 +2343,8 @@ static void stm32f0serial_pmnotify(FAR struct pm_callback_s *cb, int domain, ****************************************************************************/ #ifdef CONFIG_PM -static int stm32f0serial_pmprepare(FAR struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) +static int stm32serial_pmprepare(FAR struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) { /* Logic to prepare for a reduced power state goes here. */ @@ -2366,7 +2366,7 @@ static int stm32f0serial_pmprepare(FAR struct pm_callback_s *cb, int domain, * Description: * Performs the low level USART initialization early in debug so that the * serial console will be available during bootup. This must be called - * before stm32f0serial_getregit. + * before stm32serial_getregit. * ****************************************************************************/ @@ -2378,25 +2378,25 @@ void up_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32F0_NUSART; i++) + for (i = 0; i < STM32_NUSART; i++) { if (g_uart_devs[i]) { - stm32f0serial_disableusartint(g_uart_devs[i], NULL); + stm32serial_disableusartint(g_uart_devs[i], NULL); } } /* Configure whichever one is the console */ #if CONSOLE_USART > 0 - stm32f0serial_setup(&g_uart_devs[CONSOLE_USART - 1]->dev); + stm32serial_setup(&g_uart_devs[CONSOLE_USART - 1]->dev); #endif #endif /* HAVE USART */ } #endif /**************************************************************************** - * Name: stm32f0serial_getregit + * Name: stm32serial_getregit * * Description: * Register serial console and serial ports. This assumes @@ -2427,7 +2427,7 @@ void up_serialinit(void) #if CONSOLE_USART > 0 (void)uart_register("/dev/console", &g_uart_devs[CONSOLE_USART - 1]->dev); -#ifndef CONFIG_STM32F0_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32F0L0_SERIAL_DISABLE_REORDERING /* If not disabled, register the console USART to ttyS0 and exclude * it from initializing it further down */ @@ -2439,7 +2439,7 @@ void up_serialinit(void) #ifdef SERIAL_HAVE_CONSOLE_DMA /* If we need to re-initialise the console to enable DMA do that here. */ - stm32f0serial_dmasetup(&g_uart_devs[CONSOLE_USART - 1]->dev); + stm32serial_dmasetup(&g_uart_devs[CONSOLE_USART - 1]->dev); #endif #endif /* CONSOLE_USART > 0 */ @@ -2447,7 +2447,7 @@ void up_serialinit(void) strcpy(devname, "/dev/ttySx"); - for (i = 0; i < STM32F0_NUSART; i++) + for (i = 0; i < STM32_NUSART; i++) { /* Don't create a device for non-configured ports. */ @@ -2456,7 +2456,7 @@ void up_serialinit(void) continue; } -#ifndef CONFIG_STM32F0_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32F0L0_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) @@ -2474,7 +2474,7 @@ void up_serialinit(void) } /**************************************************************************** - * Name: stm32f0serial_dmapoll + * Name: stm32serial_dmapoll * * Description: * Checks receive DMA buffers for received bytes that have not accumulated @@ -2485,7 +2485,7 @@ void up_serialinit(void) ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -void stm32f0serial_dmapoll(void) +void stm32serial_dmapoll(void) { irqstate_t flags; @@ -2494,35 +2494,35 @@ void stm32f0serial_dmapoll(void) #ifdef CONFIG_USART1_RXDMA if (g_usart1priv.rxdma != NULL) { - stm32f0serial_dmarxcallback(g_usart1priv.rxdma, 0, &g_usart1priv); + stm32serial_dmarxcallback(g_usart1priv.rxdma, 0, &g_usart1priv); } #endif #ifdef CONFIG_USART2_RXDMA if (g_usart2priv.rxdma != NULL) { - stm32f0serial_dmarxcallback(g_usart2priv.rxdma, 0, &g_usart2priv); + stm32serial_dmarxcallback(g_usart2priv.rxdma, 0, &g_usart2priv); } #endif #ifdef CONFIG_USART3_RXDMA if (g_usart3priv.rxdma != NULL) { - stm32f0serial_dmarxcallback(g_usart3priv.rxdma, 0, &g_usart3priv); + stm32serial_dmarxcallback(g_usart3priv.rxdma, 0, &g_usart3priv); } #endif #ifdef CONFIG_USART4_RXDMA if (g_usart4priv.rxdma != NULL) { - stm32f0serial_dmarxcallback(g_usart4priv.rxdma, 0, &g_usart4priv); + stm32serial_dmarxcallback(g_usart4priv.rxdma, 0, &g_usart4priv); } #endif #ifdef CONFIG_USART5_RXDMA if (g_usart5priv.rxdma != NULL) { - stm32f0serial_dmarxcallback(g_usart5priv.rxdma, 0, &g_usart5priv); + stm32serial_dmarxcallback(g_usart5priv.rxdma, 0, &g_usart5priv); } #endif @@ -2541,10 +2541,10 @@ void stm32f0serial_dmapoll(void) int up_putc(int ch) { #if CONSOLE_USART > 0 - struct stm32f0_serial_s *priv = g_uart_devs[CONSOLE_USART - 1]; + struct stm32_serial_s *priv = g_uart_devs[CONSOLE_USART - 1]; uint16_t ie; - stm32f0serial_disableusartint(priv, &ie); + stm32serial_disableusartint(priv, &ie); /* Check for LF */ @@ -2556,7 +2556,7 @@ int up_putc(int ch) } up_lowputc(ch); - stm32f0serial_restoreusartint(priv, ie); + stm32serial_restoreusartint(priv, ie); #endif return ch; } diff --git a/arch/arm/src/stm32f0/stm32f0_serial.h b/arch/arm/src/stm32f0l0/stm32_serial.h similarity index 92% rename from arch/arm/src/stm32f0/stm32f0_serial.h rename to arch/arm/src/stm32f0l0/stm32_serial.h index c3922c62011..b51ef343fee 100644 --- a/arch/arm/src/stm32f0/stm32f0_serial.h +++ b/arch/arm/src/stm32f0l0/stm32_serial.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/stm32f0_serial.h + * arch/arm/src/stm32f0l0/stm32_serial.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_SERIAL_H -#define __ARCH_ARM_SRC_STM32F0_STM32F0_SERIAL_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_SERIAL_H +#define __ARCH_ARM_SRC_STM32F0L0_STM32_SERIAL_H /************************************************************************************ * Included Files @@ -47,4 +47,4 @@ * Pre-processor Definitions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_SERIAL_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_SERIAL_H */ diff --git a/arch/arm/src/stm32f0/stm32f0_start.c b/arch/arm/src/stm32f0l0/stm32_start.c similarity index 95% rename from arch/arm/src/stm32f0/stm32f0_start.c rename to arch/arm/src/stm32f0l0/stm32_start.c index f175430c287..88cf1a09c75 100644 --- a/arch/arm/src/stm32f0/stm32f0_start.c +++ b/arch/arm/src/stm32f0l0/stm32_start.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0/stm32f0_start.c + * arch/arm/src/stm32f0l0/stm32_start.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -50,9 +50,9 @@ #include "up_arch.h" #include "up_internal.h" -#include "stm32f0_clockconfig.h" -#include "stm32f0_lowputc.h" -#include "stm32f0_start.h" +#include "stm32_clockconfig.h" +#include "stm32_lowputc.h" +#include "stm32_start.h" /**************************************************************************** * Pre-processor Definitions @@ -104,8 +104,8 @@ void __start(void) /* Configure the uart so that we can get debug output as soon as possible */ - stm32f0_clockconfig(); - stm32f0_lowsetup(); + stm32_clockconfig(); + stm32_lowsetup(); showprogress('A'); /* Clear .bss. We'll do this inline (vs. calling memset) just to be @@ -146,13 +146,13 @@ void __start(void) */ #ifdef CONFIG_BUILD_PROTECTED - stm32f0_userspace(); + stm32_userspace(); showprogress('E'); #endif /* Initialize onboard resources */ - stm32f0_boardinitialize(); + stm32_boardinitialize(); showprogress('F'); /* Then start NuttX */ diff --git a/arch/arm/src/stm32f0/stm32f0_start.h b/arch/arm/src/stm32f0l0/stm32_start.h similarity index 89% rename from arch/arm/src/stm32f0/stm32f0_start.h rename to arch/arm/src/stm32f0l0/stm32_start.h index dc1779a5d15..73087cbe3f7 100644 --- a/arch/arm/src/stm32f0/stm32f0_start.h +++ b/arch/arm/src/stm32f0l0/stm32_start.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/stm32f0_start.h + * arch/arm/src/stm32f0l0/stm32_start.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_START_H -#define __ARCH_ARM_SRC_STM32F0_STM32F0_START_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_START_H +#define __ARCH_ARM_SRC_STM32F0L0_STM32_START_H /************************************************************************************ * Included Files @@ -57,20 +57,20 @@ extern "C" ************************************************************************************/ /************************************************************************************ - * Name: stm32f0_boardinitialize + * Name: stm32_boardinitialize * * Description: * All STM32 architectures must provide the following entry point. This entry - * point is called early in the intitialization -- after all memory has been + * point is called early in the initialization -- after all memory has been * configured and mapped but before any devices have been initialized. * ************************************************************************************/ -void stm32f0_boardinitialize(void); +void stm32_boardinitialize(void); #ifdef __cplusplus } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_START_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_START_H */ diff --git a/arch/arm/src/stm32f0/stm32f0_timerisr.c b/arch/arm/src/stm32f0l0/stm32_timerisr.c similarity index 90% rename from arch/arm/src/stm32f0/stm32f0_timerisr.c rename to arch/arm/src/stm32f0l0/stm32_timerisr.c index d6cb2315396..2f1a0e42fee 100644 --- a/arch/arm/src/stm32f0/stm32f0_timerisr.c +++ b/arch/arm/src/stm32f0l0/stm32_timerisr.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0/stm32f0_timerisr.c + * arch/arm/src/stm32f0l0/stm32_timerisr.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -62,10 +62,10 @@ * (when CLKSOURCE = 0). ..." */ -#if defined(CONFIG_STM32F0_SYSTICK_CORECLK) -# define SYSTICK_CLOCK STM32F0_SYSCLK_FREQUENCY /* Core clock */ -#elif defined(CONFIG_STM32F0_SYSTICK_CORECLK_DIV16) -# define SYSTICK_CLOCK (STM32F0_SYSCLK_FREQUENCY / 16) /* Core clock divided by 16 */ +#if defined(CONFIG_STM32F0L0_SYSTICK_CORECLK) +# define SYSTICK_CLOCK STM32_SYSCLK_FREQUENCY /* Core clock */ +#elif defined(CONFIG_STM32F0L0_SYSTICK_CORECLK_DIV16) +# define SYSTICK_CLOCK (STM32_SYSCLK_FREQUENCY / 16) /* Core clock divided by 16 */ #endif /* The desired timer interrupt frequency is provided by the definition @@ -99,7 +99,7 @@ ****************************************************************************/ /**************************************************************************** - * Function: stm32f0_timerisr + * Function: stm32_timerisr * * Description: * The timer ISR will perform a variety of services for various portions @@ -107,7 +107,7 @@ * ****************************************************************************/ -static int stm32f0_timerisr(int irq, uint32_t *regs, FAR void *arg) +static int stm32_timerisr(int irq, uint32_t *regs, FAR void *arg) { /* Process timer interrupt */ @@ -145,14 +145,14 @@ void arm_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(STM32F0_IRQ_SYSTICK, (xcpt_t)stm32f0_timerisr, NULL); + (void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); /* Enable SysTick interrupts. "The CLKSOURCE bit in SysTick Control and * Status register selects either the core clock (when CLKSOURCE = 1) or * a divide-by-16 of the core clock (when CLKSOURCE = 0). ..." */ -#ifdef CONFIG_STM32F0_SYSTICK_CORECLK +#ifdef CONFIG_STM32F0L0_SYSTICK_CORECLK putreg32((SYSTICK_CSR_CLKSOURCE | SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE), ARMV6M_SYSTICK_CSR); #else @@ -161,5 +161,5 @@ void arm_timer_initialize(void) /* And enable the timer interrupt */ - up_enable_irq(STM32F0_IRQ_SYSTICK); + up_enable_irq(STM32_IRQ_SYSTICK); } diff --git a/arch/arm/src/stm32f0/stm32f0_uart.h b/arch/arm/src/stm32f0l0/stm32_uart.h similarity index 60% rename from arch/arm/src/stm32f0/stm32f0_uart.h rename to arch/arm/src/stm32f0l0/stm32_uart.h index d5bd3f6ef78..823b2cdc468 100644 --- a/arch/arm/src/stm32f0/stm32f0_uart.h +++ b/arch/arm/src/stm32f0l0/stm32_uart.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32/stm32f0_uart.h + * arch/arm/src/stm32f0l0/stm32_uart.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32F0_STM32F0_UART_H -#define __ARCH_ARM_STC_STM32F0_STM32F0_UART_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_UART_H +#define __ARCH_ARM_SRC_STM32F0L0_STM32_UART_H /************************************************************************************ * Included Files @@ -45,7 +45,7 @@ #include "chip.h" -#include "chip/stm32f0_uart.h" +#include "hardware/stm32_uart.h" /************************************************************************************ * Pre-processor Definitions @@ -54,29 +54,29 @@ * device. */ -#if STM32F0_NUSART < 8 || !defined(CONFIG_STM32F0_HAVE_USART8) -# undef CONFIG_STM32F0_USART8 +#if STM32_NUSART < 8 || !defined(CONFIG_STM32F0L0_HAVE_USART8) +# undef CONFIG_STM32F0L0_USART8 #endif -#if STM32F0_NUSART < 7 || !defined(CONFIG_STM32F0_HAVE_USART7) -# undef CONFIG_STM32F0_USART7 +#if STM32_NUSART < 7 || !defined(CONFIG_STM32F0L0_HAVE_USART7) +# undef CONFIG_STM32F0L0_USART7 #endif -#if STM32F0_NUSART < 6 || !defined(CONFIG_STM32F0_HAVE_USART6) -# undef CONFIG_STM32F0_USART6 +#if STM32_NUSART < 6 || !defined(CONFIG_STM32F0L0_HAVE_USART6) +# undef CONFIG_STM32F0L0_USART6 #endif -#if STM32F0_NUSART < 5 || !defined(CONFIG_STM32F0_HAVE_USART5) -# undef CONFIG_STM32F0_USART5 +#if STM32_NUSART < 5 || !defined(CONFIG_STM32F0L0_HAVE_USART5) +# undef CONFIG_STM32F0L0_USART5 #endif -#if STM32F0_NUSART < 4 || !defined(CONFIG_STM32F0_HAVE_USART4) -# undef CONFIG_STM32F0_USART4 +#if STM32_NUSART < 4 || !defined(CONFIG_STM32F0L0_HAVE_USART4) +# undef CONFIG_STM32F0L0_USART4 #endif -#if STM32F0_NUSART < 3 || !defined(CONFIG_STM32F0_HAVE_USART3) -# undef CONFIG_STM32F0_USART3 +#if STM32_NUSART < 3 || !defined(CONFIG_STM32F0L0_HAVE_USART3) +# undef CONFIG_STM32F0L0_USART3 #endif -#if STM32F0_NUSART < 2 -# undef CONFIG_STM32F0_USART2 +#if STM32_NUSART < 2 +# undef CONFIG_STM32F0L0_USART2 #endif -#if STM32F0_NUSART < 1 -# undef CONFIG_STM32F0_USART1 +#if STM32_NUSART < 1 +# undef CONFIG_STM32F0L0_USART1 #endif /* USART 3-8 are multiplexed to the same interrupt. Current interrupt @@ -85,128 +85,128 @@ * issue in the future. */ -#if defined(CONFIG_STM32F0_USART3) -# undef CONFIG_STM32F0_USART4 -# undef CONFIG_STM32F0_USART5 -# undef CONFIG_STM32F0_USART6 -# undef CONFIG_STM32F0_USART7 -# undef CONFIG_STM32F0_USART8 -#elif defined(CONFIG_STM32F0_USART4) -# undef CONFIG_STM32F0_USART5 -# undef CONFIG_STM32F0_USART6 -# undef CONFIG_STM32F0_USART7 -# undef CONFIG_STM32F0_USART8 -#elif defined(CONFIG_STM32F0_USART5) -# undef CONFIG_STM32F0_USART6 -# undef CONFIG_STM32F0_USART7 -# undef CONFIG_STM32F0_USART8 -#elif defined(CONFIG_STM32F0_USART6) -# undef CONFIG_STM32F0_USART7 -# undef CONFIG_STM32F0_USART8 -#elif defined(CONFIG_STM32F0_USART7) -# undef CONFIG_STM32F0_USART8 +#if defined(CONFIG_STM32F0L0_USART3) +# undef CONFIG_STM32F0L0_USART4 +# undef CONFIG_STM32F0L0_USART5 +# undef CONFIG_STM32F0L0_USART6 +# undef CONFIG_STM32F0L0_USART7 +# undef CONFIG_STM32F0L0_USART8 +#elif defined(CONFIG_STM32F0L0_USART4) +# undef CONFIG_STM32F0L0_USART5 +# undef CONFIG_STM32F0L0_USART6 +# undef CONFIG_STM32F0L0_USART7 +# undef CONFIG_STM32F0L0_USART8 +#elif defined(CONFIG_STM32F0L0_USART5) +# undef CONFIG_STM32F0L0_USART6 +# undef CONFIG_STM32F0L0_USART7 +# undef CONFIG_STM32F0L0_USART8 +#elif defined(CONFIG_STM32F0L0_USART6) +# undef CONFIG_STM32F0L0_USART7 +# undef CONFIG_STM32F0L0_USART8 +#elif defined(CONFIG_STM32F0L0_USART7) +# undef CONFIG_STM32F0L0_USART8 #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32F0_USART1) || defined(CONFIG_STM32F0_USART2) || \ - defined(CONFIG_STM32F0_USART3) || defined(CONFIG_STM32F0_USART4) || \ - defined(CONFIG_STM32F0_USART5) || defined(CONFIG_STM32F0_USART6) || \ - defined(CONFIG_STM32F0_USART7) || defined(CONFIG_STM32F0_USART8) +#if defined(CONFIG_STM32F0L0_USART1) || defined(CONFIG_STM32F0L0_USART2) || \ + defined(CONFIG_STM32F0L0_USART3) || defined(CONFIG_STM32F0L0_USART4) || \ + defined(CONFIG_STM32F0L0_USART5) || defined(CONFIG_STM32F0L0_USART6) || \ + defined(CONFIG_STM32F0L0_USART7) || defined(CONFIG_STM32F0L0_USART8) # define HAVE_USART 1 #endif /* Sanity checks */ -#if !defined(CONFIG_STM32F0_USART1) -# undef CONFIG_STM32F0_USART1_SERIALDRIVER -# undef CONFIG_STM32F0_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32F0L0_USART1) +# undef CONFIG_STM32F0L0_USART1_SERIALDRIVER +# undef CONFIG_STM32F0L0_USART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0_USART2) -# undef CONFIG_STM32F0_USART2_SERIALDRIVER -# undef CONFIG_STM32F0_USART2_1WIREDRIVER +#if !defined(CONFIG_STM32F0L0_USART2) +# undef CONFIG_STM32F0L0_USART2_SERIALDRIVER +# undef CONFIG_STM32F0L0_USART2_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0_USART3) -# undef CONFIG_STM32F0_USART3_SERIALDRIVER -# undef CONFIG_STM32F0_USART3_1WIREDRIVER +#if !defined(CONFIG_STM32F0L0_USART3) +# undef CONFIG_STM32F0L0_USART3_SERIALDRIVER +# undef CONFIG_STM32F0L0_USART3_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0_USART4) -# undef CONFIG_STM32F0_USART4_SERIALDRIVER -# undef CONFIG_STM32F0_USART4_1WIREDRIVER +#if !defined(CONFIG_STM32F0L0_USART4) +# undef CONFIG_STM32F0L0_USART4_SERIALDRIVER +# undef CONFIG_STM32F0L0_USART4_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0_USART5) -# undef CONFIG_STM32F0_USART5_SERIALDRIVER -# undef CONFIG_STM32F0_USART5_1WIREDRIVER +#if !defined(CONFIG_STM32F0L0_USART5) +# undef CONFIG_STM32F0L0_USART5_SERIALDRIVER +# undef CONFIG_STM32F0L0_USART5_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0_USART6) -# undef CONFIG_STM32F0_USART6_SERIALDRIVER -# undef CONFIG_STM32F0_USART6_1WIREDRIVER +#if !defined(CONFIG_STM32F0L0_USART6) +# undef CONFIG_STM32F0L0_USART6_SERIALDRIVER +# undef CONFIG_STM32F0L0_USART6_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0_USART7) -# undef CONFIG_STM32F0_USART7_SERIALDRIVER -# undef CONFIG_STM32F0_USART7_1WIREDRIVER +#if !defined(CONFIG_STM32F0L0_USART7) +# undef CONFIG_STM32F0L0_USART7_SERIALDRIVER +# undef CONFIG_STM32F0L0_USART7_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0_USART8) -# undef CONFIG_STM32F0_USART8_SERIALDRIVER -# undef CONFIG_STM32F0_USART8_1WIREDRIVER +#if !defined(CONFIG_STM32F0L0_USART8) +# undef CONFIG_STM32F0L0_USART8_SERIALDRIVER +# undef CONFIG_STM32F0L0_USART8_1WIREDRIVER #endif /* Check 1-Wire and U(S)ART conflicts */ -#if defined(CONFIG_STM32F0_USART1_1WIREDRIVER) && defined(CONFIG_STM32F0_USART1_SERIALDRIVER) -# error Both CONFIG_STM32F0_USART1_1WIREDRIVER and CONFIG_STM32F0_USART1_SERIALDRIVER defined -# undef CONFIG_STM32F0_USART1_1WIREDRIVER +#if defined(CONFIG_STM32F0L0_USART1_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART1_SERIALDRIVER) +# error Both CONFIG_STM32F0L0_USART1_1WIREDRIVER and CONFIG_STM32F0L0_USART1_SERIALDRIVER defined +# undef CONFIG_STM32F0L0_USART1_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0_USART2_1WIREDRIVER) && defined(CONFIG_STM32F0_USART2_SERIALDRIVER) -# error Both CONFIG_STM32F0_USART2_1WIREDRIVER and CONFIG_STM32F0_USART2_SERIALDRIVER defined -# undef CONFIG_STM32F0_USART2_1WIREDRIVER +#if defined(CONFIG_STM32F0L0_USART2_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART2_SERIALDRIVER) +# error Both CONFIG_STM32F0L0_USART2_1WIREDRIVER and CONFIG_STM32F0L0_USART2_SERIALDRIVER defined +# undef CONFIG_STM32F0L0_USART2_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0_USART3_1WIREDRIVER) && defined(CONFIG_STM32F0_USART3_SERIALDRIVER) -# error Both CONFIG_STM32F0_USART3_1WIREDRIVER and CONFIG_STM32F0_USART3_SERIALDRIVER defined -# undef CONFIG_STM32F0_USART3_1WIREDRIVER +#if defined(CONFIG_STM32F0L0_USART3_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART3_SERIALDRIVER) +# error Both CONFIG_STM32F0L0_USART3_1WIREDRIVER and CONFIG_STM32F0L0_USART3_SERIALDRIVER defined +# undef CONFIG_STM32F0L0_USART3_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0_USART4_1WIREDRIVER) && defined(CONFIG_STM32F0_USART4_SERIALDRIVER) -# error Both CONFIG_STM32F0_USART4_1WIREDRIVER and CONFIG_STM32F0_USART4_SERIALDRIVER defined -# undef CONFIG_STM32F0_USART4_1WIREDRIVER +#if defined(CONFIG_STM32F0L0_USART4_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART4_SERIALDRIVER) +# error Both CONFIG_STM32F0L0_USART4_1WIREDRIVER and CONFIG_STM32F0L0_USART4_SERIALDRIVER defined +# undef CONFIG_STM32F0L0_USART4_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0_USART5_1WIREDRIVER) && defined(CONFIG_STM32F0_USART5_SERIALDRIVER) -# error Both CONFIG_STM32F0_USART5_1WIREDRIVER and CONFIG_STM32F0_USART5_SERIALDRIVER defined -# undef CONFIG_STM32F0_USART5_1WIREDRIVER +#if defined(CONFIG_STM32F0L0_USART5_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART5_SERIALDRIVER) +# error Both CONFIG_STM32F0L0_USART5_1WIREDRIVER and CONFIG_STM32F0L0_USART5_SERIALDRIVER defined +# undef CONFIG_STM32F0L0_USART5_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0_USART6_1WIREDRIVER) && defined(CONFIG_STM32F0_USART6_SERIALDRIVER) -# error Both CONFIG_STM32F0_USART6_1WIREDRIVER and CONFIG_STM32F0_USART6_SERIALDRIVER defined -# undef CONFIG_STM32F0_USART6_1WIREDRIVER +#if defined(CONFIG_STM32F0L0_USART6_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART6_SERIALDRIVER) +# error Both CONFIG_STM32F0L0_USART6_1WIREDRIVER and CONFIG_STM32F0L0_USART6_SERIALDRIVER defined +# undef CONFIG_STM32F0L0_USART6_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0_USART7_1WIREDRIVER) && defined(CONFIG_STM32F0_USART7_SERIALDRIVER) -# error Both CONFIG_STM32F0_USART7_1WIREDRIVER and CONFIG_STM32F0_USART7_SERIALDRIVER defined -# undef CONFIG_STM32F0_USART7_1WIREDRIVER +#if defined(CONFIG_STM32F0L0_USART7_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART7_SERIALDRIVER) +# error Both CONFIG_STM32F0L0_USART7_1WIREDRIVER and CONFIG_STM32F0L0_USART7_SERIALDRIVER defined +# undef CONFIG_STM32F0L0_USART7_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0_USART8_1WIREDRIVER) && defined(CONFIG_STM32F0_USART8_SERIALDRIVER) -# error Both CONFIG_STM32F0_USART8_1WIREDRIVER and CONFIG_STM32F0_USART8_SERIALDRIVER defined -# undef CONFIG_STM32F0_USART8_1WIREDRIVER +#if defined(CONFIG_STM32F0L0_USART8_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART8_SERIALDRIVER) +# error Both CONFIG_STM32F0L0_USART8_1WIREDRIVER and CONFIG_STM32F0L0_USART8_SERIALDRIVER defined +# undef CONFIG_STM32F0L0_USART8_1WIREDRIVER #endif /* Is the serial driver enabled? */ -#if defined(CONFIG_STM32F0_USART1_SERIALDRIVER) || defined(CONFIG_STM32F0_USART2_SERIALDRIVER) || \ - defined(CONFIG_STM32F0_USART3_SERIALDRIVER) || defined(CONFIG_STM32F0_USART4_SERIALDRIVER) || \ - defined(CONFIG_STM32F0_USART5_SERIALDRIVER) || defined(CONFIG_STM32F0_USART6_SERIALDRIVER) || \ - defined(CONFIG_STM32F0_USART7_SERIALDRIVER) || defined(CONFIG_STM32F0_USART8_SERIALDRIVER) +#if defined(CONFIG_STM32F0L0_USART1_SERIALDRIVER) || defined(CONFIG_STM32F0L0_USART2_SERIALDRIVER) || \ + defined(CONFIG_STM32F0L0_USART3_SERIALDRIVER) || defined(CONFIG_STM32F0L0_USART4_SERIALDRIVER) || \ + defined(CONFIG_STM32F0L0_USART5_SERIALDRIVER) || defined(CONFIG_STM32F0L0_USART6_SERIALDRIVER) || \ + defined(CONFIG_STM32F0L0_USART7_SERIALDRIVER) || defined(CONFIG_STM32F0L0_USART8_SERIALDRIVER) # define HAVE_SERIALDRIVER 1 #endif /* Is the 1-Wire driver? */ -#if defined(CONFIG_STM32F0_USART1_1WIREDRIVER) || defined(CONFIG_STM32F0_USART2_1WIREDRIVER) || \ - defined(CONFIG_STM32F0_USART3_1WIREDRIVER) || defined(CONFIG_STM32F0_USART4_1WIREDRIVER) || \ - defined(CONFIG_STM32F0_USART5_1WIREDRIVER) || defined(CONFIG_STM32F0_USART6_1WIREDRIVER) || \ - defined(CONFIG_STM32F0_USART7_1WIREDRIVER) || defined(CONFIG_STM32F0_USART8_1WIREDRIVER) +#if defined(CONFIG_STM32F0L0_USART1_1WIREDRIVER) || defined(CONFIG_STM32F0L0_USART2_1WIREDRIVER) || \ + defined(CONFIG_STM32F0L0_USART3_1WIREDRIVER) || defined(CONFIG_STM32F0L0_USART4_1WIREDRIVER) || \ + defined(CONFIG_STM32F0L0_USART5_1WIREDRIVER) || defined(CONFIG_STM32F0L0_USART6_1WIREDRIVER) || \ + defined(CONFIG_STM32F0L0_USART7_1WIREDRIVER) || defined(CONFIG_STM32F0L0_USART8_1WIREDRIVER) # define HAVE_1WIREDRIVER 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F0_USART1_SERIALDRIVER) +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART1_SERIALDRIVER) # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_USART4_SERIAL_CONSOLE @@ -216,7 +216,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F0_USART2_SERIALDRIVER) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART2_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_USART4_SERIAL_CONSOLE @@ -226,7 +226,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F0_USART3_SERIALDRIVER) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART3_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART4_SERIAL_CONSOLE @@ -236,7 +236,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F0_USART4_SERIALDRIVER) +#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART4_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -246,7 +246,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART5_SERIAL_CONSOLE) && defined(CONFIG_STM32F0_USART5_SERIALDRIVER) +#elif defined(CONFIG_USART5_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART5_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -256,7 +256,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32F0_USART6_SERIALDRIVER) +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART6_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -266,7 +266,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 6 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART7_SERIAL_CONSOLE) && defined(CONFIG_STM32F0_USART7_SERIALDRIVER) +#elif defined(CONFIG_USART7_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART7_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -277,7 +277,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 7 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART8_SERIAL_CONSOLE) && defined(CONFIG_STM32F0_USART8_SERIALDRIVER) +#elif defined(CONFIG_USART8_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART8_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -315,35 +315,35 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32F0_USART1_SERIALDRIVER +#ifndef CONFIG_STM32F0L0_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif -#ifndef CONFIG_STM32F0_USART2_SERIALDRIVER +#ifndef CONFIG_STM32F0L0_USART2_SERIALDRIVER # undef CONFIG_USART2_RXDMA #endif -#ifndef CONFIG_STM32F0_USART3_SERIALDRIVER +#ifndef CONFIG_STM32F0L0_USART3_SERIALDRIVER # undef CONFIG_USART3_RXDMA #endif -#ifndef CONFIG_STM32F0_USART4_SERIALDRIVER +#ifndef CONFIG_STM32F0L0_USART4_SERIALDRIVER # undef CONFIG_USART4_RXDMA #endif -#ifndef CONFIG_STM32F0_USART5_SERIALDRIVER +#ifndef CONFIG_STM32F0L0_USART5_SERIALDRIVER # undef CONFIG_USART5_RXDMA #endif -#ifndef CONFIG_STM32F0_USART6_SERIALDRIVER +#ifndef CONFIG_STM32F0L0_USART6_SERIALDRIVER # undef CONFIG_USART6_RXDMA #endif -#ifndef CONFIG_STM32F0_USART7_SERIALDRIVER +#ifndef CONFIG_STM32F0L0_USART7_SERIALDRIVER # undef CONFIG_USART7_RXDMA #endif -#ifndef CONFIG_STM32F0_USART8_SERIALDRIVER +#ifndef CONFIG_STM32F0L0_USART8_SERIALDRIVER # undef CONFIG_USART8_RXDMA #endif @@ -381,21 +381,21 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32F0_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#if defined(CONFIG_STM32F0L0_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32F0L0_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32F0L0_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0_USART4_SERIALDRIVER) && !defined(CONFIG_USART4_RXDMA) +#elif defined(CONFIG_STM32F0L0_USART4_SERIALDRIVER) && !defined(CONFIG_USART4_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0_USART5_SERIALDRIVER) && !defined(CONFIG_USART5_RXDMA) +#elif defined(CONFIG_STM32F0L0_USART5_SERIALDRIVER) && !defined(CONFIG_USART5_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA) +#elif defined(CONFIG_STM32F0L0_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0_USART7_SERIALDRIVER) && !defined(CONFIG_USART7_RXDMA) +#elif defined(CONFIG_STM32F0L0_USART7_SERIALDRIVER) && !defined(CONFIG_USART7_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0_USART8_SERIALDRIVER) && !defined(CONFIG_USART8_RXDMA) +#elif defined(CONFIG_STM32F0L0_USART8_SERIALDRIVER) && !defined(CONFIG_USART8_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif @@ -438,7 +438,7 @@ extern "C" ************************************************************************************/ /************************************************************************************ - * Name: stm32f0_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Must be called periodically if any STM32 USART is configured for DMA. The DMA @@ -451,7 +451,7 @@ extern "C" ************************************************************************************/ #ifdef SERIAL_HAVE_DMA -void stm32f0_serial_dma_poll(void); +void stm32_serial_dma_poll(void); #endif #undef EXTERN @@ -460,4 +460,4 @@ void stm32f0_serial_dma_poll(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_STC_STM32F0_STM32F0_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_UART_H */ diff --git a/arch/arm/src/stm32f0/stm32f0_usbdev.c b/arch/arm/src/stm32f0l0/stm32_usbdev.c similarity index 66% rename from arch/arm/src/stm32f0/stm32f0_usbdev.c rename to arch/arm/src/stm32f0l0/stm32_usbdev.c index 018405397d8..2cca8a24b55 100644 --- a/arch/arm/src/stm32f0/stm32f0_usbdev.c +++ b/arch/arm/src/stm32f0l0/stm32_usbdev.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0/stm32f0_usbdev.c + * arch/arm/src/stm32f0l0/stm32_usbdev.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -61,13 +61,13 @@ #include "up_arch.h" #include "up_internal.h" -#include "chip/stm32f0_rcc.h" -#include "chip/stm32f0_usbdev.h" -#include "stm32f0_hsi48.h" -#include "stm32f0_gpio.h" -#include "stm32f0_usbdev.h" +#include "hardware/stm32_rcc.h" +#include "hardware/stm32_usbdev.h" +#include "stm32_hsi48.h" +#include "stm32_gpio.h" +#include "stm32_usbdev.h" -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32F0_USB) +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32F0L0_USB) /**************************************************************************** * Pre-processor Definitions @@ -88,22 +88,22 @@ */ #ifndef CONFIG_DEBUG_USB_INFO -# undef CONFIG_STM32F0_USBDEV_REGDEBUG +# undef CONFIG_STM32F0L0_USBDEV_REGDEBUG #endif /* Initial interrupt mask: Reset + Suspend + Correct Transfer */ -#define STM32F0_CNTR_SETUP (USB_CNTR_RESETM|USB_CNTR_SUSPM|USB_CNTR_CTRM) +#define STM32_CNTR_SETUP (USB_CNTR_RESETM|USB_CNTR_SUSPM|USB_CNTR_CTRM) /* Endpoint identifiers. The STM32 supports up to 16 mono-directional or 8 * bidirectional endpoints. However, when you take into account PMA buffer * usage (see below) and the fact that EP0 is bidirectional, then there is * a functional limitation of EP0 + 5 mono-directional endpoints = 6. We'll - * define STM32F0_NENDPOINTS to be 8, however, because that is how many + * define STM32_NENDPOINTS to be 8, however, because that is how many * endpoint register sets there are. */ -#define STM32F0_NENDPOINTS (8) +#define STM32_NENDPOINTS (8) #define EP0 (0) #define EP1 (1) #define EP2 (2) @@ -113,41 +113,41 @@ #define EP6 (6) #define EP7 (7) -#define STM32F0_ENDP_BIT(ep) (1 << (ep)) -#define STM32F0_ENDP_ALLSET 0xff +#define STM32_ENDP_BIT(ep) (1 << (ep)) +#define STM32_ENDP_ALLSET 0xff /* Packet sizes. We us a fixed 64 max packet size for all endpoint types */ -#define STM32F0_MAXPACKET_SHIFT (6) -#define STM32F0_MAXPACKET_SIZE (1 << (STM32F0_MAXPACKET_SHIFT)) -#define STM32F0_MAXPACKET_MASK (STM32F0_MAXPACKET_SIZE-1) +#define STM32_MAXPACKET_SHIFT (6) +#define STM32_MAXPACKET_SIZE (1 << (STM32_MAXPACKET_SHIFT)) +#define STM32_MAXPACKET_MASK (STM32_MAXPACKET_SIZE-1) -#define STM32F0_EP0MAXPACKET STM32F0_MAXPACKET_SIZE +#define STM32_EP0MAXPACKET STM32_MAXPACKET_SIZE /* Buffer descriptor table. We assume that USB has exclusive use of CAN/USB * memory. The buffer table is positioned at the beginning of the 512-byte - * CAN/USB memory. We will use the first STM32F0_NENDPOINTS*4 words for the buffer + * CAN/USB memory. We will use the first STM32_NENDPOINTS*4 words for the buffer * table. That is exactly 64 bytes, leaving 7*64 bytes for endpoint buffers. */ -#define STM32F0_BTABLE_ADDRESS (0x00) /* Start at the beginning of USB/CAN RAM */ -#define STM32F0_DESC_SIZE (8) /* Each descriptor is 4*2=8 bytes in size */ -#define STM32F0_BTABLE_SIZE (STM32F0_NENDPOINTS*STM32F0_DESC_SIZE) +#define STM32_BTABLE_ADDRESS (0x00) /* Start at the beginning of USB/CAN RAM */ +#define STM32_DESC_SIZE (8) /* Each descriptor is 4*2=8 bytes in size */ +#define STM32_BTABLE_SIZE (STM32_NENDPOINTS*STM32_DESC_SIZE) /* Buffer layout. Assume that all buffers are 64-bytes (maxpacketsize), then * we have space for only 7 buffers; endpoint 0 will require two buffers, leaving * 5 for other endpoints. */ -#define STM32F0_BUFFER_START STM32F0_BTABLE_SIZE -#define STM32F0_EP0_RXADDR STM32F0_BUFFER_START -#define STM32F0_EP0_TXADDR (STM32F0_EP0_RXADDR+STM32F0_EP0MAXPACKET) +#define STM32_BUFFER_START STM32_BTABLE_SIZE +#define STM32_EP0_RXADDR STM32_BUFFER_START +#define STM32_EP0_TXADDR (STM32_EP0_RXADDR+STM32_EP0MAXPACKET) -#define STM32F0_BUFFER_EP0 0x03 -#define STM32F0_NBUFFERS 7 -#define STM32F0_BUFFER_BIT(bn) (1 << (bn)) -#define STM32F0_BUFFER_ALLSET 0x7f -#define STM32F0_BUFNO2BUF(bn) (STM32F0_BUFFER_START+((bn)<head == NULL) -#define stm32f0_rqpeek(ep) ((ep)->head) +#define stm32_rqempty(ep) ((ep)->head == NULL) +#define stm32_rqpeek(ep) ((ep)->head) /* USB trace ****************************************************************/ /* Trace error codes */ -#define STM32F0_TRACEERR_ALLOCFAIL 0x0001 -#define STM32F0_TRACEERR_BADCLEARFEATURE 0x0002 -#define STM32F0_TRACEERR_BADDEVGETSTATUS 0x0003 -#define STM32F0_TRACEERR_BADEPGETSTATUS 0x0004 -#define STM32F0_TRACEERR_BADEPNO 0x0005 -#define STM32F0_TRACEERR_BADEPTYPE 0x0006 -#define STM32F0_TRACEERR_BADGETCONFIG 0x0007 -#define STM32F0_TRACEERR_BADGETSETDESC 0x0008 -#define STM32F0_TRACEERR_BADGETSTATUS 0x0009 -#define STM32F0_TRACEERR_BADSETADDRESS 0x000a -#define STM32F0_TRACEERR_BADSETCONFIG 0x000b -#define STM32F0_TRACEERR_BADSETFEATURE 0x000c -#define STM32F0_TRACEERR_BINDFAILED 0x000d -#define STM32F0_TRACEERR_DISPATCHSTALL 0x000e -#define STM32F0_TRACEERR_DRIVER 0x000f -#define STM32F0_TRACEERR_DRIVERREGISTERED 0x0010 -#define STM32F0_TRACEERR_EP0BADCTR 0x0011 -#define STM32F0_TRACEERR_EP0SETUPSTALLED 0x0012 -#define STM32F0_TRACEERR_EPBUFFER 0x0013 -#define STM32F0_TRACEERR_EPDISABLED 0x0014 -#define STM32F0_TRACEERR_EPOUTNULLPACKET 0x0015 -#define STM32F0_TRACEERR_EPRESERVE 0x0016 -#define STM32F0_TRACEERR_INVALIDCTRLREQ 0x0017 -#define STM32F0_TRACEERR_INVALIDPARMS 0x0018 -#define STM32F0_TRACEERR_IRQREGISTRATION 0x0019 -#define STM32F0_TRACEERR_NOTCONFIGURED 0x001a -#define STM32F0_TRACEERR_REQABORTED 0x001b +#define STM32_TRACEERR_ALLOCFAIL 0x0001 +#define STM32_TRACEERR_BADCLEARFEATURE 0x0002 +#define STM32_TRACEERR_BADDEVGETSTATUS 0x0003 +#define STM32_TRACEERR_BADEPGETSTATUS 0x0004 +#define STM32_TRACEERR_BADEPNO 0x0005 +#define STM32_TRACEERR_BADEPTYPE 0x0006 +#define STM32_TRACEERR_BADGETCONFIG 0x0007 +#define STM32_TRACEERR_BADGETSETDESC 0x0008 +#define STM32_TRACEERR_BADGETSTATUS 0x0009 +#define STM32_TRACEERR_BADSETADDRESS 0x000a +#define STM32_TRACEERR_BADSETCONFIG 0x000b +#define STM32_TRACEERR_BADSETFEATURE 0x000c +#define STM32_TRACEERR_BINDFAILED 0x000d +#define STM32_TRACEERR_DISPATCHSTALL 0x000e +#define STM32_TRACEERR_DRIVER 0x000f +#define STM32_TRACEERR_DRIVERREGISTERED 0x0010 +#define STM32_TRACEERR_EP0BADCTR 0x0011 +#define STM32_TRACEERR_EP0SETUPSTALLED 0x0012 +#define STM32_TRACEERR_EPBUFFER 0x0013 +#define STM32_TRACEERR_EPDISABLED 0x0014 +#define STM32_TRACEERR_EPOUTNULLPACKET 0x0015 +#define STM32_TRACEERR_EPRESERVE 0x0016 +#define STM32_TRACEERR_INVALIDCTRLREQ 0x0017 +#define STM32_TRACEERR_INVALIDPARMS 0x0018 +#define STM32_TRACEERR_IRQREGISTRATION 0x0019 +#define STM32_TRACEERR_NOTCONFIGURED 0x001a +#define STM32_TRACEERR_REQABORTED 0x001b /* Trace interrupt codes */ -#define STM32F0_TRACEINTID_CLEARFEATURE 0x0001 -#define STM32F0_TRACEINTID_DEVGETSTATUS 0x0002 -#define STM32F0_TRACEINTID_DISPATCH 0x0003 -#define STM32F0_TRACEINTID_EP0IN 0x0004 -#define STM32F0_TRACEINTID_EP0INDONE 0x0005 -#define STM32F0_TRACEINTID_EP0OUTDONE 0x0006 -#define STM32F0_TRACEINTID_EP0SETUPDONE 0x0007 -#define STM32F0_TRACEINTID_EP0SETUPSETADDRESS 0x0008 -#define STM32F0_TRACEINTID_EPGETSTATUS 0x0009 -#define STM32F0_TRACEINTID_EPINDONE 0x000a -#define STM32F0_TRACEINTID_EPINQEMPTY 0x000b -#define STM32F0_TRACEINTID_EPOUTDONE 0x000c -#define STM32F0_TRACEINTID_EPOUTPENDING 0x000d -#define STM32F0_TRACEINTID_EPOUTQEMPTY 0x000e -#define STM32F0_TRACEINTID_ESOF 0x000f -#define STM32F0_TRACEINTID_GETCONFIG 0x0010 -#define STM32F0_TRACEINTID_GETSETDESC 0x0011 -#define STM32F0_TRACEINTID_GETSETIF 0x0012 -#define STM32F0_TRACEINTID_GETSTATUS 0x0013 -#define STM32F0_TRACEINTID_INTERRUPT 0x0014 -#define STM32F0_TRACEINTID_IFGETSTATUS 0x0015 -#define STM32F0_TRACEINTID_LPCTR 0x0016 -#define STM32F0_TRACEINTID_NOSTDREQ 0x0017 -#define STM32F0_TRACEINTID_RESET 0x0018 -#define STM32F0_TRACEINTID_SETCONFIG 0x0019 -#define STM32F0_TRACEINTID_SETFEATURE 0x001a -#define STM32F0_TRACEINTID_SUSP 0x001b -#define STM32F0_TRACEINTID_SYNCHFRAME 0x001c -#define STM32F0_TRACEINTID_WKUP 0x001d -#define STM32F0_TRACEINTID_EP0SETUPOUT 0x001e -#define STM32F0_TRACEINTID_EP0SETUPOUTDATA 0x001f +#define STM32_TRACEINTID_CLEARFEATURE 0x0001 +#define STM32_TRACEINTID_DEVGETSTATUS 0x0002 +#define STM32_TRACEINTID_DISPATCH 0x0003 +#define STM32_TRACEINTID_EP0IN 0x0004 +#define STM32_TRACEINTID_EP0INDONE 0x0005 +#define STM32_TRACEINTID_EP0OUTDONE 0x0006 +#define STM32_TRACEINTID_EP0SETUPDONE 0x0007 +#define STM32_TRACEINTID_EP0SETUPSETADDRESS 0x0008 +#define STM32_TRACEINTID_EPGETSTATUS 0x0009 +#define STM32_TRACEINTID_EPINDONE 0x000a +#define STM32_TRACEINTID_EPINQEMPTY 0x000b +#define STM32_TRACEINTID_EPOUTDONE 0x000c +#define STM32_TRACEINTID_EPOUTPENDING 0x000d +#define STM32_TRACEINTID_EPOUTQEMPTY 0x000e +#define STM32_TRACEINTID_ESOF 0x000f +#define STM32_TRACEINTID_GETCONFIG 0x0010 +#define STM32_TRACEINTID_GETSETDESC 0x0011 +#define STM32_TRACEINTID_GETSETIF 0x0012 +#define STM32_TRACEINTID_GETSTATUS 0x0013 +#define STM32_TRACEINTID_INTERRUPT 0x0014 +#define STM32_TRACEINTID_IFGETSTATUS 0x0015 +#define STM32_TRACEINTID_LPCTR 0x0016 +#define STM32_TRACEINTID_NOSTDREQ 0x0017 +#define STM32_TRACEINTID_RESET 0x0018 +#define STM32_TRACEINTID_SETCONFIG 0x0019 +#define STM32_TRACEINTID_SETFEATURE 0x001a +#define STM32_TRACEINTID_SUSP 0x001b +#define STM32_TRACEINTID_SYNCHFRAME 0x001c +#define STM32_TRACEINTID_WKUP 0x001d +#define STM32_TRACEINTID_EP0SETUPOUT 0x001e +#define STM32_TRACEINTID_EP0SETUPOUTDATA 0x001f /* Ever-present MIN and MAX macros */ @@ -256,7 +256,7 @@ /* The various states of a control pipe */ -enum stm32f0_ep0state_e +enum stm32_ep0state_e { EP0STATE_IDLE = 0, /* No request in progress */ EP0STATE_SETUP_OUT, /* Set up recived with data for device OUT in progress */ @@ -269,7 +269,7 @@ enum stm32f0_ep0state_e /* Resume states */ -enum stm32f0_rsmstate_e +enum stm32_rsmstate_e { RSMSTATE_IDLE = 0, /* Device is either fully suspended or running */ RSMSTATE_STARTED, /* Resume sequence has been started */ @@ -284,28 +284,28 @@ union wb_u /* A container for a request so that the request make be retained in a list */ -struct stm32f0_req_s +struct stm32_req_s { struct usbdev_req_s req; /* Standard USB request */ - struct stm32f0_req_s *flink; /* Supports a singly linked list */ + struct stm32_req_s *flink; /* Supports a singly linked list */ }; /* This is the internal representation of an endpoint */ -struct stm32f0_ep_s +struct stm32_ep_s { /* Common endpoint fields. This must be the first thing defined in the * structure so that it is possible to simply cast from struct usbdev_ep_s - * to struct stm32f0_ep_s. + * to struct stm32_ep_s. */ struct usbdev_ep_s ep; /* Standard endpoint structure */ /* STR71X-specific fields */ - struct stm32f0_usbdev_s *dev; /* Reference to private driver data */ - struct stm32f0_req_s *head; /* Request list for this endpoint */ - struct stm32f0_req_s *tail; + struct stm32_usbdev_s *dev; /* Reference to private driver data */ + struct stm32_req_s *head; /* Request list for this endpoint */ + struct stm32_req_s *tail; uint8_t bufno; /* Allocated buffer number */ uint8_t stalled:1; /* true: Endpoint is stalled */ uint8_t halted:1; /* true: Endpoint feature halted */ @@ -313,11 +313,11 @@ struct stm32f0_ep_s uint8_t txnullpkt:1; /* Null packet needed at end of transfer */ }; -struct stm32f0_usbdev_s +struct stm32_usbdev_s { /* Common device fields. This must be the first thing defined in the * structure so that it is possible to simply cast from struct usbdev_s - * to structstm32f0_usbdev_s. + * to structstm32_usbdev_s. */ struct usbdev_s usbdev; @@ -328,8 +328,8 @@ struct stm32f0_usbdev_s /* STM32-specific fields */ - uint8_t ep0state; /* State of EP0 (see enum stm32f0_ep0state_e) */ - uint8_t rsmstate; /* Resume state (see enum stm32f0_rsmstate_e) */ + uint8_t ep0state; /* State of EP0 (see enum stm32_ep0state_e) */ + uint8_t rsmstate; /* Resume state (see enum stm32_rsmstate_e) */ uint8_t nesofs; /* ESOF counter (for resume support) */ uint8_t rxpending:1; /* 1: OUT data in PMA, but no read requests */ uint8_t selfpowered:1; /* 1: Device is self powered */ @@ -348,7 +348,7 @@ struct stm32f0_usbdev_s * ep0data * For OUT SETUP requests, the SETUP data phase must also complete before * the SETUP command can be processed. The ep0 packet receipt logic - * stm32f0_ep0_rdrequest will save the accompanying EP0 OUT data in + * stm32_ep0_rdrequest will save the accompanying EP0 OUT data in * ep0data[] before the SETUP command is re-processed. * * ep0datlen @@ -362,7 +362,7 @@ struct stm32f0_usbdev_s /* The endpoint list */ - struct stm32f0_ep_s eplist[STM32F0_NENDPOINTS]; + struct stm32_ep_s eplist[STM32_NENDPOINTS]; }; /**************************************************************************** @@ -371,147 +371,147 @@ struct stm32f0_usbdev_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32F0_USBDEV_REGDEBUG -static uint16_t stm32f0_getreg(uint32_t addr); -static void stm32f0_putreg(uint16_t val, uint32_t addr); -static void stm32f0_dumpep(int epno); +#ifdef CONFIG_STM32F0L0_USBDEV_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint16_t val, uint32_t addr); +static void stm32_dumpep(int epno); #else -# define stm32f0_getreg(addr) getreg16(addr) -# define stm32f0_putreg(val,addr) putreg16(val,addr) -# define stm32f0_dumpep(epno) +# define stm32_getreg(addr) getreg16(addr) +# define stm32_putreg(val,addr) putreg16(val,addr) +# define stm32_dumpep(epno) #endif /* Low-Level Helpers ********************************************************/ static inline void - stm32f0_seteptxcount(uint8_t epno, uint16_t count); + stm32_seteptxcount(uint8_t epno, uint16_t count); static inline void - stm32f0_seteptxaddr(uint8_t epno, uint16_t addr); + stm32_seteptxaddr(uint8_t epno, uint16_t addr); static inline uint16_t - stm32f0_geteptxaddr(uint8_t epno); -static void stm32f0_seteprxcount(uint8_t epno, uint16_t count); + stm32_geteptxaddr(uint8_t epno); +static void stm32_seteprxcount(uint8_t epno, uint16_t count); static inline uint16_t - stm32f0_geteprxcount(uint8_t epno); + stm32_geteprxcount(uint8_t epno); static inline void - stm32f0_seteprxaddr(uint8_t epno, uint16_t addr); + stm32_seteprxaddr(uint8_t epno, uint16_t addr); static inline uint16_t - stm32f0_geteprxaddr(uint8_t epno); + stm32_geteprxaddr(uint8_t epno); static inline void - stm32f0_setepaddress(uint8_t epno, uint16_t addr); + stm32_setepaddress(uint8_t epno, uint16_t addr); static inline void - stm32f0_seteptype(uint8_t epno, uint16_t type); + stm32_seteptype(uint8_t epno, uint16_t type); static inline void - stm32f0_seteptxaddr(uint8_t epno, uint16_t addr); + stm32_seteptxaddr(uint8_t epno, uint16_t addr); static inline void - stm32f0_setstatusout(uint8_t epno); + stm32_setstatusout(uint8_t epno); static inline void - stm32f0_clrstatusout(uint8_t epno); -static void stm32f0_clrrxdtog(uint8_t epno); -static void stm32f0_clrtxdtog(uint8_t epno); -static void stm32f0_clrepctrrx(uint8_t epno); -static void stm32f0_clrepctrtx(uint8_t epno); -static void stm32f0_seteptxstatus(uint8_t epno, uint16_t state); -static void stm32f0_seteprxstatus(uint8_t epno, uint16_t state); + stm32_clrstatusout(uint8_t epno); +static void stm32_clrrxdtog(uint8_t epno); +static void stm32_clrtxdtog(uint8_t epno); +static void stm32_clrepctrrx(uint8_t epno); +static void stm32_clrepctrtx(uint8_t epno); +static void stm32_seteptxstatus(uint8_t epno, uint16_t state); +static void stm32_seteprxstatus(uint8_t epno, uint16_t state); static inline uint16_t - stm32f0_geteptxstatus(uint8_t epno); + stm32_geteptxstatus(uint8_t epno); static inline uint16_t - stm32f0_geteprxstatus(uint8_t epno); -static bool stm32f0_eptxstalled(uint8_t epno); -static bool stm32f0_eprxstalled(uint8_t epno); -static void stm32f0_setimask(struct stm32f0_usbdev_s *priv, uint16_t setbits, + stm32_geteprxstatus(uint8_t epno); +static bool stm32_eptxstalled(uint8_t epno); +static bool stm32_eprxstalled(uint8_t epno); +static void stm32_setimask(struct stm32_usbdev_s *priv, uint16_t setbits, uint16_t clrbits); /* Suspend/Resume Helpers ***************************************************/ -static void stm32f0_suspend(struct stm32f0_usbdev_s *priv); -static void stm32f0_initresume(struct stm32f0_usbdev_s *priv); -static void stm32f0_esofpoll(struct stm32f0_usbdev_s *priv) ; +static void stm32_suspend(struct stm32_usbdev_s *priv); +static void stm32_initresume(struct stm32_usbdev_s *priv); +static void stm32_esofpoll(struct stm32_usbdev_s *priv) ; /* Request Helpers **********************************************************/ -static void stm32f0_copytopma(const uint8_t *buffer, uint16_t pma, +static void stm32_copytopma(const uint8_t *buffer, uint16_t pma, uint16_t nbytes); static inline void - stm32f0_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes); -static struct stm32f0_req_s * - stm32f0_rqdequeue(struct stm32f0_ep_s *privep); -static void stm32f0_rqenqueue(struct stm32f0_ep_s *privep, - struct stm32f0_req_s *req); + stm32_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes); +static struct stm32_req_s * + stm32_rqdequeue(struct stm32_ep_s *privep); +static void stm32_rqenqueue(struct stm32_ep_s *privep, + struct stm32_req_s *req); static inline void - stm32f0_abortrequest(struct stm32f0_ep_s *privep, - struct stm32f0_req_s *privreq, int16_t result); -static void stm32f0_reqcomplete(struct stm32f0_ep_s *privep, int16_t result); -static void stm32f0_epwrite(struct stm32f0_usbdev_s *buf, - struct stm32f0_ep_s *privep, const uint8_t *data, uint32_t nbytes); -static int stm32f0_wrrequest(struct stm32f0_usbdev_s *priv, - struct stm32f0_ep_s *privep); + stm32_abortrequest(struct stm32_ep_s *privep, + struct stm32_req_s *privreq, int16_t result); +static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result); +static void stm32_epwrite(struct stm32_usbdev_s *buf, + struct stm32_ep_s *privep, const uint8_t *data, uint32_t nbytes); +static int stm32_wrrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); inline static int - stm32f0_wrrequest_ep0(struct stm32f0_usbdev_s *priv, - struct stm32f0_ep_s *privep); + stm32_wrrequest_ep0(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); static inline int - stm32f0_ep0_rdrequest(struct stm32f0_usbdev_s *priv); -static int stm32f0_rdrequest(struct stm32f0_usbdev_s *priv, - struct stm32f0_ep_s *privep); -static void stm32f0_cancelrequests(struct stm32f0_ep_s *privep); + stm32_ep0_rdrequest(struct stm32_usbdev_s *priv); +static int stm32_rdrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); +static void stm32_cancelrequests(struct stm32_ep_s *privep); /* Interrupt level processing ***********************************************/ -static void stm32f0_dispatchrequest(struct stm32f0_usbdev_s *priv); -static void stm32f0_epdone(struct stm32f0_usbdev_s *priv, uint8_t epno); -static void stm32f0_setdevaddr(struct stm32f0_usbdev_s *priv, uint8_t value); -static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv); -static void stm32f0_ep0out(struct stm32f0_usbdev_s *priv); -static void stm32f0_ep0in(struct stm32f0_usbdev_s *priv); +static void stm32_dispatchrequest(struct stm32_usbdev_s *priv); +static void stm32_epdone(struct stm32_usbdev_s *priv, uint8_t epno); +static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value); +static void stm32_ep0setup(struct stm32_usbdev_s *priv); +static void stm32_ep0out(struct stm32_usbdev_s *priv); +static void stm32_ep0in(struct stm32_usbdev_s *priv); static inline void - stm32f0_ep0done(struct stm32f0_usbdev_s *priv, uint16_t istr); -static void stm32f0_lptransfer(struct stm32f0_usbdev_s *priv); -static int stm32f0_usb_interrupt(int irq, void *context, FAR void *arg); + stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr); +static void stm32_lptransfer(struct stm32_usbdev_s *priv); +static int stm32_usb_interrupt(int irq, void *context, FAR void *arg); /* Endpoint helpers *********************************************************/ -static inline struct stm32f0_ep_s * - stm32f0_epreserve(struct stm32f0_usbdev_s *priv, uint8_t epset); +static inline struct stm32_ep_s * + stm32_epreserve(struct stm32_usbdev_s *priv, uint8_t epset); static inline void - stm32f0_epunreserve(struct stm32f0_usbdev_s *priv, - struct stm32f0_ep_s *privep); + stm32_epunreserve(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); static inline bool - stm32f0_epreserved(struct stm32f0_usbdev_s *priv, int epno); -static int stm32f0_epallocpma(struct stm32f0_usbdev_s *priv); + stm32_epreserved(struct stm32_usbdev_s *priv, int epno); +static int stm32_epallocpma(struct stm32_usbdev_s *priv); static inline void - stm32f0_epfreepma(struct stm32f0_usbdev_s *priv, - struct stm32f0_ep_s *privep); + stm32_epfreepma(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); /* Endpoint operations ******************************************************/ -static int stm32f0_epconfigure(struct usbdev_ep_s *ep, +static int stm32_epconfigure(struct usbdev_ep_s *ep, const struct usb_epdesc_s *desc, bool last); -static int stm32f0_epdisable(struct usbdev_ep_s *ep); +static int stm32_epdisable(struct usbdev_ep_s *ep); static struct usbdev_req_s * - stm32f0_epallocreq(struct usbdev_ep_s *ep); -static void stm32f0_epfreereq(struct usbdev_ep_s *ep, + stm32_epallocreq(struct usbdev_ep_s *ep); +static void stm32_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *); -static int stm32f0_epsubmit(struct usbdev_ep_s *ep, +static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req); -static int stm32f0_epcancel(struct usbdev_ep_s *ep, +static int stm32_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req); -static int stm32f0_epstall(struct usbdev_ep_s *ep, bool resume); +static int stm32_epstall(struct usbdev_ep_s *ep, bool resume); /* USB device controller operations *****************************************/ static struct usbdev_ep_s * - stm32f0_allocep(struct usbdev_s *dev, uint8_t epno, bool in, + stm32_allocep(struct usbdev_s *dev, uint8_t epno, bool in, uint8_t eptype); -static void stm32f0_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep); -static int stm32f0_getframe(struct usbdev_s *dev); -static int stm32f0_wakeup(struct usbdev_s *dev); -static int stm32f0_selfpowered(struct usbdev_s *dev, bool selfpowered); +static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep); +static int stm32_getframe(struct usbdev_s *dev); +static int stm32_wakeup(struct usbdev_s *dev); +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered); /* Initialization/Reset *****************************************************/ -static void stm32f0_reset(struct stm32f0_usbdev_s *priv); -static void stm32f0_hwreset(struct stm32f0_usbdev_s *priv); -static void stm32f0_hwsetup(struct stm32f0_usbdev_s *priv); -static void stm32f0_hwshutdown(struct stm32f0_usbdev_s *priv); +static void stm32_reset(struct stm32_usbdev_s *priv); +static void stm32_hwreset(struct stm32_usbdev_s *priv); +static void stm32_hwsetup(struct stm32_usbdev_s *priv); +static void stm32_hwshutdown(struct stm32_usbdev_s *priv); /**************************************************************************** * Private Data @@ -521,27 +521,27 @@ static void stm32f0_hwshutdown(struct stm32f0_usbdev_s *priv); * be simply retained in a single global instance. */ -static struct stm32f0_usbdev_s g_usbdev; +static struct stm32_usbdev_s g_usbdev; static const struct usbdev_epops_s g_epops = { - .configure = stm32f0_epconfigure, - .disable = stm32f0_epdisable, - .allocreq = stm32f0_epallocreq, - .freereq = stm32f0_epfreereq, - .submit = stm32f0_epsubmit, - .cancel = stm32f0_epcancel, - .stall = stm32f0_epstall, + .configure = stm32_epconfigure, + .disable = stm32_epdisable, + .allocreq = stm32_epallocreq, + .freereq = stm32_epfreereq, + .submit = stm32_epsubmit, + .cancel = stm32_epcancel, + .stall = stm32_epstall, }; static const struct usbdev_ops_s g_devops = { - .allocep = stm32f0_allocep, - .freeep = stm32f0_freeep, - .getframe = stm32f0_getframe, - .wakeup = stm32f0_wakeup, - .selfpowered = stm32f0_selfpowered, - .pullup = stm32f0_usbpullup, + .allocep = stm32_allocep, + .freeep = stm32_freeep, + .getframe = stm32_getframe, + .wakeup = stm32_wakeup, + .selfpowered = stm32_selfpowered, + .pullup = stm32_usbpullup, }; /**************************************************************************** @@ -551,37 +551,37 @@ static const struct usbdev_ops_s g_devops = #ifdef CONFIG_USBDEV_TRACE_STRINGS const struct trace_msg_t g_usb_trace_strings_intdecode[] = { - TRACE_STR(STM32F0_TRACEINTID_CLEARFEATURE ), - TRACE_STR(STM32F0_TRACEINTID_DEVGETSTATUS ), - TRACE_STR(STM32F0_TRACEINTID_DISPATCH ), - TRACE_STR(STM32F0_TRACEINTID_EP0IN ), - TRACE_STR(STM32F0_TRACEINTID_EP0INDONE ), - TRACE_STR(STM32F0_TRACEINTID_EP0OUTDONE ), - TRACE_STR(STM32F0_TRACEINTID_EP0SETUPDONE ), - TRACE_STR(STM32F0_TRACEINTID_EP0SETUPSETADDRESS ), - TRACE_STR(STM32F0_TRACEINTID_EPGETSTATUS ), - TRACE_STR(STM32F0_TRACEINTID_EPINDONE ), - TRACE_STR(STM32F0_TRACEINTID_EPINQEMPTY ), - TRACE_STR(STM32F0_TRACEINTID_EPOUTDONE ), - TRACE_STR(STM32F0_TRACEINTID_EPOUTPENDING ), - TRACE_STR(STM32F0_TRACEINTID_EPOUTQEMPTY ), - TRACE_STR(STM32F0_TRACEINTID_ESOF ), - TRACE_STR(STM32F0_TRACEINTID_GETCONFIG ), - TRACE_STR(STM32F0_TRACEINTID_GETSETDESC ), - TRACE_STR(STM32F0_TRACEINTID_GETSETIF ), - TRACE_STR(STM32F0_TRACEINTID_GETSTATUS ), - TRACE_STR(STM32F0_TRACEINTID_INTERRUPT ), - TRACE_STR(STM32F0_TRACEINTID_IFGETSTATUS ), - TRACE_STR(STM32F0_TRACEINTID_LPCTR ), - TRACE_STR(STM32F0_TRACEINTID_NOSTDREQ ), - TRACE_STR(STM32F0_TRACEINTID_RESET ), - TRACE_STR(STM32F0_TRACEINTID_SETCONFIG ), - TRACE_STR(STM32F0_TRACEINTID_SETFEATURE ), - TRACE_STR(STM32F0_TRACEINTID_SUSP ), - TRACE_STR(STM32F0_TRACEINTID_SYNCHFRAME ), - TRACE_STR(STM32F0_TRACEINTID_WKUP ), - TRACE_STR(STM32F0_TRACEINTID_EP0SETUPOUT ), - TRACE_STR(STM32F0_TRACEINTID_EP0SETUPOUTDATA ), + TRACE_STR(STM32_TRACEINTID_CLEARFEATURE ), + TRACE_STR(STM32_TRACEINTID_DEVGETSTATUS ), + TRACE_STR(STM32_TRACEINTID_DISPATCH ), + TRACE_STR(STM32_TRACEINTID_EP0IN ), + TRACE_STR(STM32_TRACEINTID_EP0INDONE ), + TRACE_STR(STM32_TRACEINTID_EP0OUTDONE ), + TRACE_STR(STM32_TRACEINTID_EP0SETUPDONE ), + TRACE_STR(STM32_TRACEINTID_EP0SETUPSETADDRESS ), + TRACE_STR(STM32_TRACEINTID_EPGETSTATUS ), + TRACE_STR(STM32_TRACEINTID_EPINDONE ), + TRACE_STR(STM32_TRACEINTID_EPINQEMPTY ), + TRACE_STR(STM32_TRACEINTID_EPOUTDONE ), + TRACE_STR(STM32_TRACEINTID_EPOUTPENDING ), + TRACE_STR(STM32_TRACEINTID_EPOUTQEMPTY ), + TRACE_STR(STM32_TRACEINTID_ESOF ), + TRACE_STR(STM32_TRACEINTID_GETCONFIG ), + TRACE_STR(STM32_TRACEINTID_GETSETDESC ), + TRACE_STR(STM32_TRACEINTID_GETSETIF ), + TRACE_STR(STM32_TRACEINTID_GETSTATUS ), + TRACE_STR(STM32_TRACEINTID_INTERRUPT ), + TRACE_STR(STM32_TRACEINTID_IFGETSTATUS ), + TRACE_STR(STM32_TRACEINTID_LPCTR ), + TRACE_STR(STM32_TRACEINTID_NOSTDREQ ), + TRACE_STR(STM32_TRACEINTID_RESET ), + TRACE_STR(STM32_TRACEINTID_SETCONFIG ), + TRACE_STR(STM32_TRACEINTID_SETFEATURE ), + TRACE_STR(STM32_TRACEINTID_SUSP ), + TRACE_STR(STM32_TRACEINTID_SYNCHFRAME ), + TRACE_STR(STM32_TRACEINTID_WKUP ), + TRACE_STR(STM32_TRACEINTID_EP0SETUPOUT ), + TRACE_STR(STM32_TRACEINTID_EP0SETUPOUTDATA ), TRACE_STR_END }; #endif @@ -589,33 +589,33 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = #ifdef CONFIG_USBDEV_TRACE_STRINGS const struct trace_msg_t g_usb_trace_strings_deverror[] = { - TRACE_STR(STM32F0_TRACEERR_ALLOCFAIL ), - TRACE_STR(STM32F0_TRACEERR_BADCLEARFEATURE ), - TRACE_STR(STM32F0_TRACEERR_BADDEVGETSTATUS ), - TRACE_STR(STM32F0_TRACEERR_BADEPGETSTATUS ), - TRACE_STR(STM32F0_TRACEERR_BADEPNO ), - TRACE_STR(STM32F0_TRACEERR_BADEPTYPE ), - TRACE_STR(STM32F0_TRACEERR_BADGETCONFIG ), - TRACE_STR(STM32F0_TRACEERR_BADGETSETDESC ), - TRACE_STR(STM32F0_TRACEERR_BADGETSTATUS ), - TRACE_STR(STM32F0_TRACEERR_BADSETADDRESS ), - TRACE_STR(STM32F0_TRACEERR_BADSETCONFIG ), - TRACE_STR(STM32F0_TRACEERR_BADSETFEATURE ), - TRACE_STR(STM32F0_TRACEERR_BINDFAILED ), - TRACE_STR(STM32F0_TRACEERR_DISPATCHSTALL ), - TRACE_STR(STM32F0_TRACEERR_DRIVER ), - TRACE_STR(STM32F0_TRACEERR_DRIVERREGISTERED ), - TRACE_STR(STM32F0_TRACEERR_EP0BADCTR ), - TRACE_STR(STM32F0_TRACEERR_EP0SETUPSTALLED ), - TRACE_STR(STM32F0_TRACEERR_EPBUFFER ), - TRACE_STR(STM32F0_TRACEERR_EPDISABLED ), - TRACE_STR(STM32F0_TRACEERR_EPOUTNULLPACKET ), - TRACE_STR(STM32F0_TRACEERR_EPRESERVE ), - TRACE_STR(STM32F0_TRACEERR_INVALIDCTRLREQ ), - TRACE_STR(STM32F0_TRACEERR_INVALIDPARMS ), - TRACE_STR(STM32F0_TRACEERR_IRQREGISTRATION ), - TRACE_STR(STM32F0_TRACEERR_NOTCONFIGURED ), - TRACE_STR(STM32F0_TRACEERR_REQABORTED ), + TRACE_STR(STM32_TRACEERR_ALLOCFAIL ), + TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE ), + TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS ), + TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS ), + TRACE_STR(STM32_TRACEERR_BADEPNO ), + TRACE_STR(STM32_TRACEERR_BADEPTYPE ), + TRACE_STR(STM32_TRACEERR_BADGETCONFIG ), + TRACE_STR(STM32_TRACEERR_BADGETSETDESC ), + TRACE_STR(STM32_TRACEERR_BADGETSTATUS ), + TRACE_STR(STM32_TRACEERR_BADSETADDRESS ), + TRACE_STR(STM32_TRACEERR_BADSETCONFIG ), + TRACE_STR(STM32_TRACEERR_BADSETFEATURE ), + TRACE_STR(STM32_TRACEERR_BINDFAILED ), + TRACE_STR(STM32_TRACEERR_DISPATCHSTALL ), + TRACE_STR(STM32_TRACEERR_DRIVER ), + TRACE_STR(STM32_TRACEERR_DRIVERREGISTERED ), + TRACE_STR(STM32_TRACEERR_EP0BADCTR ), + TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED ), + TRACE_STR(STM32_TRACEERR_EPBUFFER ), + TRACE_STR(STM32_TRACEERR_EPDISABLED ), + TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET ), + TRACE_STR(STM32_TRACEERR_EPRESERVE ), + TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ ), + TRACE_STR(STM32_TRACEERR_INVALIDPARMS ), + TRACE_STR(STM32_TRACEERR_IRQREGISTRATION ), + TRACE_STR(STM32_TRACEERR_NOTCONFIGURED ), + TRACE_STR(STM32_TRACEERR_REQABORTED ), TRACE_STR_END }; #endif @@ -629,11 +629,11 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = ****************************************************************************/ /**************************************************************************** - * Name: stm32f0_getreg + * Name: stm32_getreg ****************************************************************************/ -#ifdef CONFIG_STM32F0_USBDEV_REGDEBUG -static uint16_t stm32f0_getreg(uint32_t addr) +#ifdef CONFIG_STM32F0L0_USBDEV_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; static uint16_t preval = 0; @@ -687,11 +687,11 @@ static uint16_t stm32f0_getreg(uint32_t addr) #endif /**************************************************************************** - * Name: stm32f0_putreg + * Name: stm32_putreg ****************************************************************************/ -#ifdef CONFIG_STM32F0_USBDEV_REGDEBUG -static void stm32f0_putreg(uint16_t val, uint32_t addr) +#ifdef CONFIG_STM32F0L0_USBDEV_REGDEBUG +static void stm32_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ @@ -704,44 +704,44 @@ static void stm32f0_putreg(uint16_t val, uint32_t addr) #endif /**************************************************************************** - * Name: stm32f0_dumpep + * Name: stm32_dumpep ****************************************************************************/ -#ifdef CONFIG_STM32F0_USBDEV_REGDEBUG -static void stm32f0_dumpep(int epno) +#ifdef CONFIG_STM32F0L0_USBDEV_REGDEBUG +static void stm32_dumpep(int epno) { uint32_t addr; /* Common registers */ - uinfo("CNTR: %04x\n", getreg16(STM32F0_USB_CNTR)); - uinfo("ISTR: %04x\n", getreg16(STM32F0_USB_ISTR)); - uinfo("FNR: %04x\n", getreg16(STM32F0_USB_FNR)); - uinfo("DADDR: %04x\n", getreg16(STM32F0_USB_DADDR)); - uinfo("BTABLE: %04x\n", getreg16(STM32F0_USB_BTABLE)); + uinfo("CNTR: %04x\n", getreg16(STM32_USB_CNTR)); + uinfo("ISTR: %04x\n", getreg16(STM32_USB_ISTR)); + uinfo("FNR: %04x\n", getreg16(STM32_USB_FNR)); + uinfo("DADDR: %04x\n", getreg16(STM32_USB_DADDR)); + uinfo("BTABLE: %04x\n", getreg16(STM32_USB_BTABLE)); /* Endpoint register */ - addr = STM32F0_USB_EPR(epno); + addr = STM32_USB_EPR(epno); uinfo("EPR%d: [%08x] %04x\n", epno, addr, getreg16(addr)); /* Endpoint descriptor */ - addr = STM32F0_USB_BTABLE_ADDR(epno, 0); + addr = STM32_USB_BTABLE_ADDR(epno, 0); uinfo("DESC: %08x\n", addr); /* Endpoint buffer descriptor */ - addr = STM32F0_USB_ADDR_TX(epno); + addr = STM32_USB_ADDR_TX(epno); uinfo(" TX ADDR: [%08x] %04x\n", addr, getreg16(addr)); - addr = STM32F0_USB_COUNT_TX(epno); + addr = STM32_USB_COUNT_TX(epno); uinfo(" COUNT: [%08x] %04x\n", addr, getreg16(addr)); - addr = STM32F0_USB_ADDR_RX(epno); + addr = STM32_USB_ADDR_RX(epno); uinfo(" RX ADDR: [%08x] %04x\n", addr, getreg16(addr)); - addr = STM32F0_USB_COUNT_RX(epno); + addr = STM32_USB_COUNT_RX(epno); uinfo(" COUNT: [%08x] %04x\n", addr, getreg16(addr)); } #endif @@ -750,42 +750,42 @@ static void stm32f0_dumpep(int epno) * Low-Level Helpers ****************************************************************************/ /**************************************************************************** - * Name: stm32f0_seteptxcount + * Name: stm32_seteptxcount ****************************************************************************/ -static inline void stm32f0_seteptxcount(uint8_t epno, uint16_t count) +static inline void stm32_seteptxcount(uint8_t epno, uint16_t count) { - volatile uint32_t *epaddr = (uint32_t *)STM32F0_USB_COUNT_TX(epno); + volatile uint32_t *epaddr = (uint32_t *)STM32_USB_COUNT_TX(epno); *epaddr = count; } /**************************************************************************** - * Name: stm32f0_seteptxaddr + * Name: stm32_seteptxaddr ****************************************************************************/ -static inline void stm32f0_seteptxaddr(uint8_t epno, uint16_t addr) +static inline void stm32_seteptxaddr(uint8_t epno, uint16_t addr) { - volatile uint32_t *txaddr = (uint32_t *)STM32F0_USB_ADDR_TX(epno); + volatile uint32_t *txaddr = (uint32_t *)STM32_USB_ADDR_TX(epno); *txaddr = addr; } /**************************************************************************** - * Name: stm32f0_geteptxaddr + * Name: stm32_geteptxaddr ****************************************************************************/ -static inline uint16_t stm32f0_geteptxaddr(uint8_t epno) +static inline uint16_t stm32_geteptxaddr(uint8_t epno) { - volatile uint32_t *txaddr = (uint32_t *)STM32F0_USB_ADDR_TX(epno); + volatile uint32_t *txaddr = (uint32_t *)STM32_USB_ADDR_TX(epno); return (uint16_t)*txaddr; } /**************************************************************************** - * Name: stm32f0_seteprxcount + * Name: stm32_seteprxcount ****************************************************************************/ -static void stm32f0_seteprxcount(uint8_t epno, uint16_t count) +static void stm32_seteprxcount(uint8_t epno, uint16_t count) { - volatile uint32_t *epaddr = (uint32_t *)STM32F0_USB_COUNT_RX(epno); + volatile uint32_t *epaddr = (uint32_t *)STM32_USB_COUNT_RX(epno); uint32_t rxcount = 0; uint16_t nblocks; @@ -827,74 +827,74 @@ static void stm32f0_seteprxcount(uint8_t epno, uint16_t count) } /**************************************************************************** - * Name: stm32f0_geteprxcount + * Name: stm32_geteprxcount ****************************************************************************/ -static inline uint16_t stm32f0_geteprxcount(uint8_t epno) +static inline uint16_t stm32_geteprxcount(uint8_t epno) { - volatile uint32_t *epaddr = (uint32_t *)STM32F0_USB_COUNT_RX(epno); + volatile uint32_t *epaddr = (uint32_t *)STM32_USB_COUNT_RX(epno); return (*epaddr) & USB_COUNT_RX_MASK; } /**************************************************************************** - * Name: stm32f0_seteprxaddr + * Name: stm32_seteprxaddr ****************************************************************************/ -static inline void stm32f0_seteprxaddr(uint8_t epno, uint16_t addr) +static inline void stm32_seteprxaddr(uint8_t epno, uint16_t addr) { - volatile uint32_t *rxaddr = (uint32_t *)STM32F0_USB_ADDR_RX(epno); + volatile uint32_t *rxaddr = (uint32_t *)STM32_USB_ADDR_RX(epno); *rxaddr = addr; } /**************************************************************************** - * Name: stm32f0_seteprxaddr + * Name: stm32_seteprxaddr ****************************************************************************/ -static inline uint16_t stm32f0_geteprxaddr(uint8_t epno) +static inline uint16_t stm32_geteprxaddr(uint8_t epno) { - volatile uint32_t *rxaddr = (uint32_t *)STM32F0_USB_ADDR_RX(epno); + volatile uint32_t *rxaddr = (uint32_t *)STM32_USB_ADDR_RX(epno); return (uint16_t)*rxaddr; } /**************************************************************************** - * Name: stm32f0_setepaddress + * Name: stm32_setepaddress ****************************************************************************/ -static inline void stm32f0_setepaddress(uint8_t epno, uint16_t addr) +static inline void stm32_setepaddress(uint8_t epno, uint16_t addr) { - uint32_t epaddr = STM32F0_USB_EPR(epno); + uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32f0_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval &= ~USB_EPR_EA_MASK; regval |= (addr << USB_EPR_EA_SHIFT); - stm32f0_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32f0_seteptype + * Name: stm32_seteptype ****************************************************************************/ -static inline void stm32f0_seteptype(uint8_t epno, uint16_t type) +static inline void stm32_seteptype(uint8_t epno, uint16_t type) { - uint32_t epaddr = STM32F0_USB_EPR(epno); + uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32f0_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval &= ~USB_EPR_EPTYPE_MASK; regval |= type; - stm32f0_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32f0_setstatusout + * Name: stm32_setstatusout ****************************************************************************/ -static inline void stm32f0_setstatusout(uint8_t epno) +static inline void stm32_setstatusout(uint8_t epno) { - uint32_t epaddr = STM32F0_USB_EPR(epno); + uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; /* For a BULK endpoint the EP_KIND bit is used to enabled double buffering; @@ -902,19 +902,19 @@ static inline void stm32f0_setstatusout(uint8_t epno) * transaction is expected. The bit is not used with out endpoint types. */ - regval = stm32f0_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval |= USB_EPR_EP_KIND; - stm32f0_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32f0_clrstatusout + * Name: stm32_clrstatusout ****************************************************************************/ -static inline void stm32f0_clrstatusout(uint8_t epno) +static inline void stm32_clrstatusout(uint8_t epno) { - uint32_t epaddr = STM32F0_USB_EPR(epno); + uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; /* For a BULK endpoint the EP_KIND bit is used to enabled double buffering; @@ -922,103 +922,103 @@ static inline void stm32f0_clrstatusout(uint8_t epno) * transaction is expected. The bit is not used with out endpoint types. */ - regval = stm32f0_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval &= ~USB_EPR_EP_KIND; - stm32f0_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32f0_clrrxdtog + * Name: stm32_clrrxdtog ****************************************************************************/ -static void stm32f0_clrrxdtog(uint8_t epno) +static void stm32_clrrxdtog(uint8_t epno) { - uint32_t epaddr = STM32F0_USB_EPR(epno); + uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32f0_getreg(epaddr); + regval = stm32_getreg(epaddr); if ((regval & USB_EPR_DTOG_RX) != 0) { regval &= EPR_NOTOG_MASK; regval |= USB_EPR_DTOG_RX; - stm32f0_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } } /**************************************************************************** - * Name: stm32f0_clrtxdtog + * Name: stm32_clrtxdtog ****************************************************************************/ -static void stm32f0_clrtxdtog(uint8_t epno) +static void stm32_clrtxdtog(uint8_t epno) { - uint32_t epaddr = STM32F0_USB_EPR(epno); + uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32f0_getreg(epaddr); + regval = stm32_getreg(epaddr); if ((regval & USB_EPR_DTOG_TX) != 0) { regval &= EPR_NOTOG_MASK; regval |= USB_EPR_DTOG_TX; - stm32f0_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } } /**************************************************************************** - * Name: stm32f0_clrepctrrx + * Name: stm32_clrepctrrx ****************************************************************************/ -static void stm32f0_clrepctrrx(uint8_t epno) +static void stm32_clrepctrrx(uint8_t epno) { - uint32_t epaddr = STM32F0_USB_EPR(epno); + uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32f0_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval &= ~USB_EPR_CTR_RX; - stm32f0_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32f0_clrepctrtx + * Name: stm32_clrepctrtx ****************************************************************************/ -static void stm32f0_clrepctrtx(uint8_t epno) +static void stm32_clrepctrtx(uint8_t epno) { - uint32_t epaddr = STM32F0_USB_EPR(epno); + uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32f0_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval &= ~USB_EPR_CTR_TX; - stm32f0_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32f0_geteptxstatus + * Name: stm32_geteptxstatus ****************************************************************************/ -static inline uint16_t stm32f0_geteptxstatus(uint8_t epno) +static inline uint16_t stm32_geteptxstatus(uint8_t epno) { - return (uint16_t)(stm32f0_getreg(STM32F0_USB_EPR(epno)) & USB_EPR_STATTX_MASK); + return (uint16_t)(stm32_getreg(STM32_USB_EPR(epno)) & USB_EPR_STATTX_MASK); } /**************************************************************************** - * Name: stm32f0_geteprxstatus + * Name: stm32_geteprxstatus ****************************************************************************/ -static inline uint16_t stm32f0_geteprxstatus(uint8_t epno) +static inline uint16_t stm32_geteprxstatus(uint8_t epno) { - return (stm32f0_getreg(STM32F0_USB_EPR(epno)) & USB_EPR_STATRX_MASK); + return (stm32_getreg(STM32_USB_EPR(epno)) & USB_EPR_STATRX_MASK); } /**************************************************************************** - * Name: stm32f0_seteptxstatus + * Name: stm32_seteptxstatus ****************************************************************************/ -static void stm32f0_seteptxstatus(uint8_t epno, uint16_t state) +static void stm32_seteptxstatus(uint8_t epno, uint16_t state) { - uint32_t epaddr = STM32F0_USB_EPR(epno); + uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; /* The bits in the STAT_TX field can be toggled by software to set their @@ -1026,7 +1026,7 @@ static void stm32f0_seteptxstatus(uint8_t epno, uint16_t state) * value toggles. */ - regval = stm32f0_getreg(epaddr); + regval = stm32_getreg(epaddr); /* The exclusive OR will set STAT_TX bits to 1 if there value is different * from the bits requested in 'state' @@ -1034,16 +1034,16 @@ static void stm32f0_seteptxstatus(uint8_t epno, uint16_t state) regval ^= state; regval &= EPR_TXDTOG_MASK; - stm32f0_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32f0_seteprxstatus + * Name: stm32_seteprxstatus ****************************************************************************/ -static void stm32f0_seteprxstatus(uint8_t epno, uint16_t state) +static void stm32_seteprxstatus(uint8_t epno, uint16_t state) { - uint32_t epaddr = STM32F0_USB_EPR(epno); + uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; /* The bits in the STAT_RX field can be toggled by software to set their @@ -1051,7 +1051,7 @@ static void stm32f0_seteprxstatus(uint8_t epno, uint16_t state) * value toggles. */ - regval = stm32f0_getreg(epaddr); + regval = stm32_getreg(epaddr); /* The exclusive OR will set STAT_RX bits to 1 if there value is different * from the bits requested in 'state' @@ -1059,35 +1059,35 @@ static void stm32f0_seteprxstatus(uint8_t epno, uint16_t state) regval ^= state; regval &= EPR_RXDTOG_MASK; - stm32f0_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32f0_eptxstalled + * Name: stm32_eptxstalled ****************************************************************************/ -static inline bool stm32f0_eptxstalled(uint8_t epno) +static inline bool stm32_eptxstalled(uint8_t epno) { - return (stm32f0_geteptxstatus(epno) == USB_EPR_STATTX_STALL); + return (stm32_geteptxstatus(epno) == USB_EPR_STATTX_STALL); } /**************************************************************************** - * Name: stm32f0_eprxstalled + * Name: stm32_eprxstalled ****************************************************************************/ -static inline bool stm32f0_eprxstalled(uint8_t epno) +static inline bool stm32_eprxstalled(uint8_t epno) { - return (stm32f0_geteprxstatus(epno) == USB_EPR_STATRX_STALL); + return (stm32_geteprxstatus(epno) == USB_EPR_STATRX_STALL); } /**************************************************************************** * Request Helpers ****************************************************************************/ /**************************************************************************** - * Name: stm32f0_copytopma + * Name: stm32_copytopma ****************************************************************************/ -static void stm32f0_copytopma(const uint8_t *buffer, uint16_t pma, uint16_t nbytes) +static void stm32_copytopma(const uint8_t *buffer, uint16_t pma, uint16_t nbytes) { uint16_t *dest; uint16_t ms; @@ -1097,7 +1097,7 @@ static void stm32f0_copytopma(const uint8_t *buffer, uint16_t pma, uint16_t nbyt /* Copy loop. Source=user buffer, Dest=packet memory */ - dest = (uint16_t *)(STM32F0_USBRAM_BASE + ((uint32_t)pma << 1)); + dest = (uint16_t *)(STM32_USBRAM_BASE + ((uint32_t)pma << 1)); for (i = nwords; i != 0; i--) { /* Read two bytes and pack into on 16-bit word */ @@ -1115,11 +1115,11 @@ static void stm32f0_copytopma(const uint8_t *buffer, uint16_t pma, uint16_t nbyt } /**************************************************************************** - * Name: stm32f0_copyfrompma + * Name: stm32_copyfrompma ****************************************************************************/ static inline void -stm32f0_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes) +stm32_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes) { uint32_t *src; int nwords = (nbytes + 1) >> 1; @@ -1127,7 +1127,7 @@ stm32f0_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes) /* Copy loop. Source=packet memory, Dest=user buffer */ - src = (uint32_t *)(STM32F0_USBRAM_BASE + ((uint32_t)pma << 1)); + src = (uint32_t *)(STM32_USBRAM_BASE + ((uint32_t)pma << 1)); for (i = nwords; i != 0; i--) { /* Copy 16-bits from packet memory to user buffer. */ @@ -1143,12 +1143,12 @@ stm32f0_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes) } /**************************************************************************** - * Name: stm32f0_rqdequeue + * Name: stm32_rqdequeue ****************************************************************************/ -static struct stm32f0_req_s *stm32f0_rqdequeue(struct stm32f0_ep_s *privep) +static struct stm32_req_s *stm32_rqdequeue(struct stm32_ep_s *privep) { - struct stm32f0_req_s *ret = privep->head; + struct stm32_req_s *ret = privep->head; if (ret) { @@ -1165,10 +1165,10 @@ static struct stm32f0_req_s *stm32f0_rqdequeue(struct stm32f0_ep_s *privep) } /**************************************************************************** - * Name: stm32f0_rqenqueue + * Name: stm32_rqenqueue ****************************************************************************/ -static void stm32f0_rqenqueue(struct stm32f0_ep_s *privep, struct stm32f0_req_s *req) +static void stm32_rqenqueue(struct stm32_ep_s *privep, struct stm32_req_s *req) { req->flink = NULL; if (!privep->head) @@ -1184,13 +1184,13 @@ static void stm32f0_rqenqueue(struct stm32f0_ep_s *privep, struct stm32f0_req_s } /**************************************************************************** - * Name: stm32f0_abortrequest + * Name: stm32_abortrequest ****************************************************************************/ static inline void -stm32f0_abortrequest(struct stm32f0_ep_s *privep, struct stm32f0_req_s *privreq, int16_t result) +stm32_abortrequest(struct stm32_ep_s *privep, struct stm32_req_s *privreq, int16_t result) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_REQABORTED), (uint16_t)USB_EPNO(privep->ep.eplog)); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_REQABORTED), (uint16_t)USB_EPNO(privep->ep.eplog)); /* Save the result in the request structure */ @@ -1202,18 +1202,18 @@ stm32f0_abortrequest(struct stm32f0_ep_s *privep, struct stm32f0_req_s *privreq, } /**************************************************************************** - * Name: stm32f0_reqcomplete + * Name: stm32_reqcomplete ****************************************************************************/ -static void stm32f0_reqcomplete(struct stm32f0_ep_s *privep, int16_t result) +static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result) { - struct stm32f0_req_s *privreq; + struct stm32_req_s *privreq; irqstate_t flags; /* Remove the completed request at the head of the endpoint request list */ flags = enter_critical_section(); - privreq = stm32f0_rqdequeue(privep); + privreq = stm32_rqdequeue(privep); leave_critical_section(flags); if (privreq) @@ -1247,8 +1247,8 @@ static void stm32f0_reqcomplete(struct stm32f0_ep_s *privep, int16_t result) * Name: tm32_epwrite ****************************************************************************/ -static void stm32f0_epwrite(struct stm32f0_usbdev_s *priv, - struct stm32f0_ep_s *privep, +static void stm32_epwrite(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep, const uint8_t *buf, uint32_t nbytes) { uint8_t epno = USB_EPNO(privep->ep.eplog); @@ -1262,12 +1262,12 @@ static void stm32f0_epwrite(struct stm32f0_usbdev_s *priv, * endpoint */ - stm32f0_copytopma(buf, stm32f0_geteptxaddr(epno), nbytes); + stm32_copytopma(buf, stm32_geteptxaddr(epno), nbytes); } /* Send the packet (might be a null packet nbytes == 0) */ - stm32f0_seteptxcount(epno, nbytes); + stm32_seteptxcount(epno, nbytes); priv->txstatus = USB_EPR_STATTX_VALID; /* Indicate that there is data in the TX packet memory. This will be cleared @@ -1278,29 +1278,29 @@ static void stm32f0_epwrite(struct stm32f0_usbdev_s *priv, } /**************************************************************************** - * Name: stm32f0_wrrequest_ep0 + * Name: stm32_wrrequest_ep0 * * Description: * Handle the ep0 state on writes. * ****************************************************************************/ -inline static int stm32f0_wrrequest_ep0(struct stm32f0_usbdev_s *priv, - struct stm32f0_ep_s *privep) +inline static int stm32_wrrequest_ep0(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) { int ret; - ret = stm32f0_wrrequest(priv, privep); + ret = stm32_wrrequest(priv, privep); priv->ep0state = ((ret == OK) ? EP0STATE_WRREQUEST : EP0STATE_IDLE); return ret; } /**************************************************************************** - * Name: stm32f0_wrrequest + * Name: stm32_wrrequest ****************************************************************************/ -static int stm32f0_wrrequest(struct stm32f0_usbdev_s *priv, struct stm32f0_ep_s *privep) +static int stm32_wrrequest(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) { - struct stm32f0_req_s *privreq; + struct stm32_req_s *privreq; uint8_t *buf; uint8_t epno; int nbytes; @@ -1314,14 +1314,14 @@ static int stm32f0_wrrequest(struct stm32f0_usbdev_s *priv, struct stm32f0_ep_s /* Check the request from the head of the endpoint request queue */ - privreq = stm32f0_rqpeek(privep); + privreq = stm32_rqpeek(privep); if (!privreq) { /* There is no TX transfer in progress and no new pending TX * requests to send. */ - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_EPINQEMPTY), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINQEMPTY), 0); return -ENOENT; } @@ -1374,7 +1374,7 @@ static int stm32f0_wrrequest(struct stm32f0_usbdev_s *priv, struct stm32f0_ep_s /* Send the packet (might be a null packet nbytes == 0) */ buf = privreq->req.buf + privreq->req.xfrd; - stm32f0_epwrite(priv, privep, buf, nbytes); + stm32_epwrite(priv, privep, buf, nbytes); /* Update for the next data IN interrupt */ @@ -1391,23 +1391,23 @@ static int stm32f0_wrrequest(struct stm32f0_usbdev_s *priv, struct stm32f0_ep_s usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd); privep->txnullpkt = 0; - stm32f0_reqcomplete(privep, OK); + stm32_reqcomplete(privep, OK); } return OK; } /**************************************************************************** - * Name: stm32f0_ep0_rdrequest + * Name: stm32_ep0_rdrequest * * Description: - * This function is called from the stm32f0_ep0out handler when the ep0state + * This function is called from the stm32_ep0out handler when the ep0state * is EP0STATE_SETUP_OUT and uppon new incoming data is available in the endpoint * 0's buffer. This function will simply copy the OUT data into ep0data. * ****************************************************************************/ -static inline int stm32f0_ep0_rdrequest(struct stm32f0_usbdev_s *priv) +static inline int stm32_ep0_rdrequest(struct stm32_usbdev_s *priv) { uint32_t src; int pmalen; @@ -1415,7 +1415,7 @@ static inline int stm32f0_ep0_rdrequest(struct stm32f0_usbdev_s *priv) /* Get the number of bytes to read from packet memory */ - pmalen = stm32f0_geteprxcount(EP0); + pmalen = stm32_geteprxcount(EP0); uinfo("EP0: pmalen=%d\n", pmalen); usbtrace(TRACE_READ(EP0), pmalen); @@ -1423,31 +1423,31 @@ static inline int stm32f0_ep0_rdrequest(struct stm32f0_usbdev_s *priv) /* Read the data into our special buffer for SETUP data */ readlen = MIN(CONFIG_USBDEV_SETUP_MAXDATASIZE, pmalen); - src = stm32f0_geteprxaddr(EP0); + src = stm32_geteprxaddr(EP0); /* Receive the next packet */ - stm32f0_copyfrompma(&priv->ep0data[0], src, readlen); + stm32_copyfrompma(&priv->ep0data[0], src, readlen); /* Now we can process the setup command */ priv->ep0state = EP0STATE_SETUP_READY; priv->ep0datlen = readlen; - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_EP0SETUPOUTDATA), readlen); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUTDATA), readlen); - stm32f0_ep0setup(priv); + stm32_ep0setup(priv); priv->ep0datlen = 0; /* mark the date consumed */ return OK; } /**************************************************************************** - * Name: stm32f0_rdrequest + * Name: stm32_rdrequest ****************************************************************************/ -static int stm32f0_rdrequest(struct stm32f0_usbdev_s *priv, struct stm32f0_ep_s *privep) +static int stm32_rdrequest(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) { - struct stm32f0_req_s *privreq; + struct stm32_req_s *privreq; uint32_t src; uint8_t *dest; uint8_t epno; @@ -1457,7 +1457,7 @@ static int stm32f0_rdrequest(struct stm32f0_usbdev_s *priv, struct stm32f0_ep_s /* Check the request from the head of the endpoint request queue */ epno = USB_EPNO(privep->ep.eplog); - privreq = stm32f0_rqpeek(privep); + privreq = stm32_rqpeek(privep); if (!privreq) { /* Incoming data available in PMA, but no packet to receive the data. @@ -1465,7 +1465,7 @@ static int stm32f0_rdrequest(struct stm32f0_usbdev_s *priv, struct stm32f0_ep_s * soon. */ - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_EPOUTQEMPTY), epno); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTQEMPTY), epno); return -ENOENT; } @@ -1475,8 +1475,8 @@ static int stm32f0_rdrequest(struct stm32f0_usbdev_s *priv, struct stm32f0_ep_s if (privreq->req.len == 0) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_EPOUTNULLPACKET), 0); - stm32f0_reqcomplete(privep, OK); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); + stm32_reqcomplete(privep, OK); return OK; } @@ -1485,16 +1485,16 @@ static int stm32f0_rdrequest(struct stm32f0_usbdev_s *priv, struct stm32f0_ep_s /* Get the source and destination transfer addresses */ dest = privreq->req.buf + privreq->req.xfrd; - src = stm32f0_geteprxaddr(epno); + src = stm32_geteprxaddr(epno); /* Get the number of bytes to read from packet memory */ - pmalen = stm32f0_geteprxcount(epno); + pmalen = stm32_geteprxcount(epno); readlen = MIN(privreq->req.len, pmalen); /* Receive the next packet */ - stm32f0_copyfrompma(dest, src, readlen); + stm32_copyfrompma(dest, src, readlen); /* If the receive buffer is full or this is a partial packet, * then we are finished with the request buffer). @@ -1506,23 +1506,23 @@ static int stm32f0_rdrequest(struct stm32f0_usbdev_s *priv, struct stm32f0_ep_s /* Return the read request to the class driver. */ usbtrace(TRACE_COMPLETE(epno), privreq->req.xfrd); - stm32f0_reqcomplete(privep, OK); + stm32_reqcomplete(privep, OK); } return OK; } /**************************************************************************** - * Name: stm32f0_cancelrequests + * Name: stm32_cancelrequests ****************************************************************************/ -static void stm32f0_cancelrequests(struct stm32f0_ep_s *privep) +static void stm32_cancelrequests(struct stm32_ep_s *privep) { - while (!stm32f0_rqempty(privep)) + while (!stm32_rqempty(privep)) { usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), - (stm32f0_rqpeek(privep))->req.xfrd); - stm32f0_reqcomplete(privep, -ESHUTDOWN); + (stm32_rqpeek(privep))->req.xfrd); + stm32_reqcomplete(privep, -ESHUTDOWN); } } @@ -1530,14 +1530,14 @@ static void stm32f0_cancelrequests(struct stm32f0_ep_s *privep) * Interrupt Level Processing ****************************************************************************/ /**************************************************************************** - * Name: stm32f0_dispatchrequest + * Name: stm32_dispatchrequest ****************************************************************************/ -static void stm32f0_dispatchrequest(struct stm32f0_usbdev_s *priv) +static void stm32_dispatchrequest(struct stm32_usbdev_s *priv) { int ret; - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_DISPATCH), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DISPATCH), 0); if (priv && priv->driver) { /* Forward to the control request to the class driver implementation */ @@ -1548,24 +1548,24 @@ static void stm32f0_dispatchrequest(struct stm32f0_usbdev_s *priv) { /* Stall on failure */ - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_DISPATCHSTALL), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DISPATCHSTALL), 0); priv->ep0state = EP0STATE_STALLED; } } } /**************************************************************************** - * Name: stm32f0_epdone + * Name: stm32_epdone ****************************************************************************/ -static void stm32f0_epdone(struct stm32f0_usbdev_s *priv, uint8_t epno) +static void stm32_epdone(struct stm32_usbdev_s *priv, uint8_t epno) { - struct stm32f0_ep_s *privep; + struct stm32_ep_s *privep; uint16_t epr; /* Decode and service non control endpoints interrupt */ - epr = stm32f0_getreg(STM32F0_USB_EPR(epno)); + epr = stm32_getreg(STM32_USB_EPR(epno)); privep = &priv->eplist[epno]; /* OUT: host-to-device @@ -1575,17 +1575,17 @@ static void stm32f0_epdone(struct stm32f0_usbdev_s *priv, uint8_t epno) if ((epr & USB_EPR_CTR_RX) != 0) { - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_EPOUTDONE), epr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTDONE), epr); /* Handle read requests. First check if a read request is available to * accept the host data. */ - if (!stm32f0_rqempty(privep)) + if (!stm32_rqempty(privep)) { /* Read host data into the current read request */ - (void)stm32f0_rdrequest(priv, privep); + (void)stm32_rdrequest(priv, privep); /* "After the received data is processed, the application software * should set the STAT_RX bits to '11' (Valid) in the USB_EPnR, @@ -1597,9 +1597,9 @@ static void stm32f0_epdone(struct stm32f0_usbdev_s *priv, uint8_t epno) /* NAK further OUT packets if there there no more read requests */ - if (stm32f0_rqempty(privep)) + if (stm32_rqempty(privep)) { - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_EPOUTPENDING), (uint16_t)epno); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTPENDING), (uint16_t)epno); /* Mark the RX processing as pending and NAK any OUT actions * on this endpoint. "While the STAT_RX bits are equal to '10' @@ -1614,8 +1614,8 @@ static void stm32f0_epdone(struct stm32f0_usbdev_s *priv, uint8_t epno) /* Clear the interrupt status and set the new RX status */ - stm32f0_clrepctrrx(epno); - stm32f0_seteprxstatus(epno, priv->rxstatus); + stm32_clrepctrrx(epno); + stm32_seteprxstatus(epno, priv->rxstatus); } /* IN: device-to-host @@ -1627,59 +1627,59 @@ static void stm32f0_epdone(struct stm32f0_usbdev_s *priv, uint8_t epno) { /* Clear interrupt status */ - stm32f0_clrepctrtx(epno); - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_EPINDONE), epr); + stm32_clrepctrtx(epno); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINDONE), epr); /* Handle write requests */ priv->txstatus = USB_EPR_STATTX_NAK; if (epno == EP0) { - (void)stm32f0_wrrequest_ep0(priv, privep); + (void)stm32_wrrequest_ep0(priv, privep); } else { - (void)stm32f0_wrrequest(priv, privep); + (void)stm32_wrrequest(priv, privep); } /* Set the new TX status */ - stm32f0_seteptxstatus(epno, priv->txstatus); + stm32_seteptxstatus(epno, priv->txstatus); } } /**************************************************************************** - * Name: stm32f0_setdevaddr + * Name: stm32_setdevaddr ****************************************************************************/ -static void stm32f0_setdevaddr(struct stm32f0_usbdev_s *priv, uint8_t value) +static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value) { int epno; /* Set address in every allocated endpoint */ - for (epno = 0; epno < STM32F0_NENDPOINTS; epno++) + for (epno = 0; epno < STM32_NENDPOINTS; epno++) { - if (stm32f0_epreserved(priv, epno)) + if (stm32_epreserved(priv, epno)) { - stm32f0_setepaddress((uint8_t)epno, (uint8_t)epno); + stm32_setepaddress((uint8_t)epno, (uint8_t)epno); } } /* Set the device address and enable function */ - stm32f0_putreg(value | USB_DADDR_EF, STM32F0_USB_DADDR); + stm32_putreg(value | USB_DADDR_EF, STM32_USB_DADDR); } /**************************************************************************** - * Name: stm32f0_ep0setup + * Name: stm32_ep0setup ****************************************************************************/ -static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) +static void stm32_ep0setup(struct stm32_usbdev_s *priv) { - struct stm32f0_ep_s *ep0 = &priv->eplist[EP0]; - struct stm32f0_req_s *privreq = stm32f0_rqpeek(ep0); - struct stm32f0_ep_s *privep; + struct stm32_ep_s *ep0 = &priv->eplist[EP0]; + struct stm32_req_s *privreq = stm32_rqpeek(ep0); + struct stm32_ep_s *privep; union wb_u value; union wb_u index; union wb_u len; @@ -1692,7 +1692,7 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) * was a zero-length transfer!) */ - while (!stm32f0_rqempty(ep0)) + while (!stm32_rqempty(ep0)) { int16_t result = OK; if (privreq->req.xfrd != privreq->req.len) @@ -1701,7 +1701,7 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) } usbtrace(TRACE_COMPLETE(ep0->ep.eplog), privreq->req.xfrd); - stm32f0_reqcomplete(ep0, result); + stm32_reqcomplete(ep0, result); } /* Assume NOT stalled; no TX in progress */ @@ -1718,7 +1718,7 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) * request */ - stm32f0_copyfrompma((uint8_t *)&priv->ctrl, stm32f0_geteprxaddr(EP0), + stm32_copyfrompma((uint8_t *)&priv->ctrl, stm32_geteprxaddr(EP0), USB_SIZEOF_CTRLREQ); /* And extract the little-endian 16-bit values to host order */ @@ -1735,7 +1735,7 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) if (USB_REQ_ISOUT(priv->ctrl.type) && len.w > 0) { - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_EP0SETUPOUT), len.w); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUT), len.w); /* At this point priv->ctrl is the setup packet. */ @@ -1752,11 +1752,11 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) if ((priv->ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD) { - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_NOSTDREQ), priv->ctrl.type); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_NOSTDREQ), priv->ctrl.type); /* Let the class implementation handle all non-standar requests */ - stm32f0_dispatchrequest(priv); + stm32_dispatchrequest(priv); return; } @@ -1774,11 +1774,11 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) * len: 2; data = status */ - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_GETSTATUS), priv->ctrl.type); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), priv->ctrl.type); if (len.w != 2 || (priv->ctrl.type & USB_REQ_DIR_IN) == 0 || index.b[MSB] != 0 || value.w != 0) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_BADEPGETSTATUS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), 0); priv->ep0state = EP0STATE_STALLED; } else @@ -1788,10 +1788,10 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) case USB_REQ_RECIPIENT_ENDPOINT: { epno = USB_EPNO(index.b[LSB]); - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_EPGETSTATUS), epno); - if (epno >= STM32F0_NENDPOINTS) + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPGETSTATUS), epno); + if (epno >= STM32_NENDPOINTS) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_BADEPGETSTATUS), epno); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), epno); priv->ep0state = EP0STATE_STALLED; } else @@ -1803,7 +1803,7 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) { /* IN endpoint */ - if (stm32f0_eptxstalled(epno)) + if (stm32_eptxstalled(epno)) { /* IN Endpoint stalled */ @@ -1814,7 +1814,7 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) { /* OUT endpoint */ - if (stm32f0_eprxstalled(epno)) + if (stm32_eprxstalled(epno)) { /* OUT Endpoint stalled */ @@ -1829,7 +1829,7 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) { if (index.w == 0) { - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_DEVGETSTATUS), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVGETSTATUS), 0); /* Features: Remote Wakeup=YES; selfpowered=? */ @@ -1840,7 +1840,7 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) } else { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_BADDEVGETSTATUS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADDEVGETSTATUS), 0); priv->ep0state = EP0STATE_STALLED; } } @@ -1848,7 +1848,7 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) case USB_REQ_RECIPIENT_INTERFACE: { - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_IFGETSTATUS), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IFGETSTATUS), 0); response.w = 0; nbytes = 2; /* Response size: 2 bytes */ } @@ -1856,7 +1856,7 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) default: { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_BADGETSTATUS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSTATUS), 0); priv->ep0state = EP0STATE_STALLED; } break; @@ -1873,14 +1873,14 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) * len: zero, data = none */ - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_CLEARFEATURE), priv->ctrl.type); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), priv->ctrl.type); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT) { /* Let the class implementation handle all recipients (except for the * endpoint recipient) */ - stm32f0_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } else @@ -1888,16 +1888,16 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) /* Endpoint recipient */ epno = USB_EPNO(index.b[LSB]); - if (epno < STM32F0_NENDPOINTS && index.b[MSB] == 0 && + if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 && value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) { privep = &priv->eplist[epno]; privep->halted = 0; - (void)stm32f0_epstall(&privep->ep, true); + (void)stm32_epstall(&privep->ep, true); } else { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_BADCLEARFEATURE), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADCLEARFEATURE), 0); priv->ep0state = EP0STATE_STALLED; } } @@ -1912,7 +1912,7 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_SETFEATURE), priv->ctrl.type); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), priv->ctrl.type); if (((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) && value.w == USB_FEATURE_TESTMODE) { @@ -1924,7 +1924,7 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) { /* The class driver handles all recipients except recipient=endpoint */ - stm32f0_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } else @@ -1932,16 +1932,16 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) /* Handler recipient=endpoint */ epno = USB_EPNO(index.b[LSB]); - if (epno < STM32F0_NENDPOINTS && index.b[MSB] == 0 && + if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 && value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) { privep = &priv->eplist[epno]; privep->halted = 1; - (void)stm32f0_epstall(&privep->ep, false); + (void)stm32_epstall(&privep->ep, false); } else { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_BADSETFEATURE), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); priv->ep0state = EP0STATE_STALLED; } } @@ -1956,11 +1956,11 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_EP0SETUPSETADDRESS), value.w); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPSETADDRESS), value.w); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_DEVICE || index.w != 0 || len.w != 0 || value.w > 127) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_BADSETADDRESS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETADDRESS), 0); priv->ep0state = EP0STATE_STALLED; } @@ -1985,17 +1985,17 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_GETSETDESC), priv->ctrl.type); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), priv->ctrl.type); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) { /* The request seems valid... let the class implementation handle it */ - stm32f0_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } else { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_BADGETSETDESC), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSETDESC), 0); priv->ep0state = EP0STATE_STALLED; } } @@ -2009,18 +2009,18 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_GETCONFIG), priv->ctrl.type); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), priv->ctrl.type); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && value.w == 0 && index.w == 0 && len.w == 1) { /* The request seems valid... let the class implementation handle it */ - stm32f0_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } else { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_BADGETCONFIG), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETCONFIG), 0); priv->ep0state = EP0STATE_STALLED; } } @@ -2034,18 +2034,18 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_SETCONFIG), priv->ctrl.type); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), priv->ctrl.type); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && index.w == 0 && len.w == 0) { /* The request seems valid... let the class implementation handle it */ - stm32f0_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } else { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_BADSETCONFIG), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETCONFIG), 0); priv->ep0state = EP0STATE_STALLED; } } @@ -2067,8 +2067,8 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) { /* Let the class implementation handle the request */ - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_GETSETIF), priv->ctrl.type); - stm32f0_dispatchrequest(priv); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), priv->ctrl.type); + stm32_dispatchrequest(priv); handled = true; } break; @@ -2081,13 +2081,13 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_SYNCHFRAME), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SYNCHFRAME), 0); } break; default: { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_INVALIDCTRLREQ), priv->ctrl.req); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDCTRLREQ), priv->ctrl.req); priv->ep0state = EP0STATE_STALLED; } break; @@ -2123,16 +2123,16 @@ static void stm32f0_ep0setup(struct stm32f0_usbdev_s *priv) /* Send the response (might be a zero-length packet) */ - stm32f0_epwrite(priv, ep0, response.b, nbytes); + stm32_epwrite(priv, ep0, response.b, nbytes); priv->ep0state = EP0STATE_IDLE; } } /**************************************************************************** - * Name: stm32f0_ep0in + * Name: stm32_ep0in ****************************************************************************/ -static void stm32f0_ep0in(struct stm32f0_usbdev_s *priv) +static void stm32_ep0in(struct stm32_usbdev_s *priv) { /* There is no longer anything in the EP0 TX packet memory */ @@ -2144,7 +2144,7 @@ static void stm32f0_ep0in(struct stm32f0_usbdev_s *priv) if (priv->ep0state == EP0STATE_WRREQUEST) { - stm32f0_wrrequest_ep0(priv, &priv->eplist[EP0]); + stm32_wrrequest_ep0(priv, &priv->eplist[EP0]); } /* No.. Are we processing the completion of a status response? */ @@ -2161,7 +2161,7 @@ static void stm32f0_ep0in(struct stm32f0_usbdev_s *priv) { union wb_u value; value.w = GETUINT16(priv->ctrl.value); - stm32f0_setdevaddr(priv, value.b[LSB]); + stm32_setdevaddr(priv, value.b[LSB]); } } else @@ -2171,24 +2171,24 @@ static void stm32f0_ep0in(struct stm32f0_usbdev_s *priv) } /**************************************************************************** - * Name: stm32f0_ep0out + * Name: stm32_ep0out ****************************************************************************/ -static void stm32f0_ep0out(struct stm32f0_usbdev_s *priv) +static void stm32_ep0out(struct stm32_usbdev_s *priv) { int ret; - struct stm32f0_ep_s *privep = &priv->eplist[EP0]; + struct stm32_ep_s *privep = &priv->eplist[EP0]; switch (priv->ep0state) { case EP0STATE_RDREQUEST: /* Read request in progress */ case EP0STATE_IDLE: /* No transfer in progress */ - ret = stm32f0_rdrequest(priv, privep); + ret = stm32_rdrequest(priv, privep); priv->ep0state = ((ret == OK) ? EP0STATE_RDREQUEST : EP0STATE_IDLE); break; case EP0STATE_SETUP_OUT: /* SETUP was waiting for data */ - ret = stm32f0_ep0_rdrequest(priv); /* Off load the data and run the + ret = stm32_ep0_rdrequest(priv); /* Off load the data and run the * last set up command with the OUT * data */ @@ -2210,10 +2210,10 @@ static void stm32f0_ep0out(struct stm32f0_usbdev_s *priv) } /**************************************************************************** - * Name: stm32f0_ep0done + * Name: stm32_ep0done ****************************************************************************/ -static inline void stm32f0_ep0done(struct stm32f0_usbdev_s *priv, uint16_t istr) +static inline void stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr) { uint16_t epr; @@ -2227,8 +2227,8 @@ static inline void stm32f0_ep0done(struct stm32f0_usbdev_s *priv, uint16_t istr) /* Set both RX and TX status to NAK */ - stm32f0_seteprxstatus(EP0, USB_EPR_STATRX_NAK); - stm32f0_seteptxstatus(EP0, USB_EPR_STATTX_NAK); + stm32_seteprxstatus(EP0, USB_EPR_STATRX_NAK); + stm32_seteptxstatus(EP0, USB_EPR_STATTX_NAK); /* Check the direction bit to determine if this the completion of an EP0 * packet sent to or received from the host PC. @@ -2238,15 +2238,15 @@ static inline void stm32f0_ep0done(struct stm32f0_usbdev_s *priv, uint16_t istr) { /* EP0 IN: device-to-host (DIR=0) */ - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_EP0IN), istr); - stm32f0_clrepctrtx(EP0); - stm32f0_ep0in(priv); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0IN), istr); + stm32_clrepctrtx(EP0); + stm32_ep0in(priv); } else { /* EP0 OUT: host-to-device (DIR=1) */ - epr = stm32f0_getreg(STM32F0_USB_EPR(EP0)); + epr = stm32_getreg(STM32_USB_EPR(EP0)); /* CTR_TX is set when an IN transaction successfully * completes on an endpoint @@ -2254,9 +2254,9 @@ static inline void stm32f0_ep0done(struct stm32f0_usbdev_s *priv, uint16_t istr) if ((epr & USB_EPR_CTR_TX) != 0) { - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_EP0INDONE), epr); - stm32f0_clrepctrtx(EP0); - stm32f0_ep0in(priv); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0INDONE), epr); + stm32_clrepctrtx(EP0); + stm32_ep0in(priv); } /* SETUP is set by the hardware when the last completed @@ -2265,9 +2265,9 @@ static inline void stm32f0_ep0done(struct stm32f0_usbdev_s *priv, uint16_t istr) else if ((epr & USB_EPR_SETUP) != 0) { - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_EP0SETUPDONE), epr); - stm32f0_clrepctrrx(EP0); - stm32f0_ep0setup(priv); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPDONE), epr); + stm32_clrepctrrx(EP0); + stm32_ep0setup(priv); } /* Set by the hardware when an OUT/SETUP transaction successfully @@ -2276,23 +2276,23 @@ static inline void stm32f0_ep0done(struct stm32f0_usbdev_s *priv, uint16_t istr) else if ((epr & USB_EPR_CTR_RX) != 0) { - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_EP0OUTDONE), epr); - stm32f0_clrepctrrx(EP0); - stm32f0_ep0out(priv); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0OUTDONE), epr); + stm32_clrepctrrx(EP0); + stm32_ep0out(priv); } /* None of the above */ else { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_EP0BADCTR), epr); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0BADCTR), epr); return; /* Does this ever happen? */ } } /* Make sure that the EP0 packet size is still OK (superstitious?) */ - stm32f0_seteprxcount(EP0, STM32F0_EP0MAXPACKET); + stm32_seteprxcount(EP0, STM32_EP0MAXPACKET); /* Now figure out the new RX/TX status. Here are all possible * consequences of the above EP0 operations: @@ -2309,7 +2309,7 @@ static inline void stm32f0_ep0done(struct stm32f0_usbdev_s *priv, uint16_t istr) if (priv->ep0state == EP0STATE_STALLED) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_EP0SETUPSTALLED), priv->ep0state); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), priv->ep0state); priv->rxstatus = USB_EPR_STATRX_STALL; priv->txstatus = USB_EPR_STATTX_STALL; } @@ -2328,24 +2328,24 @@ static inline void stm32f0_ep0done(struct stm32f0_usbdev_s *priv, uint16_t istr) /* Now set the new TX and RX status */ - stm32f0_seteprxstatus(EP0, priv->rxstatus); - stm32f0_seteptxstatus(EP0, priv->txstatus); + stm32_seteprxstatus(EP0, priv->rxstatus); + stm32_seteptxstatus(EP0, priv->txstatus); } /**************************************************************************** - * Name: stm32f0_lptransfer + * Name: stm32_lptransfer ****************************************************************************/ -static void stm32f0_lptransfer(struct stm32f0_usbdev_s *priv) +static void stm32_lptransfer(struct stm32_usbdev_s *priv) { uint8_t epno; uint16_t istr; /* Stay in loop while LP interrupts are pending */ - while (((istr = stm32f0_getreg(STM32F0_USB_ISTR)) & USB_ISTR_CTR) != 0) + while (((istr = stm32_getreg(STM32_USB_ISTR)) & USB_ISTR_CTR) != 0) { - stm32f0_putreg((uint16_t)~USB_ISTR_CTR, STM32F0_USB_ISTR); + stm32_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); /* Extract highest priority endpoint number */ @@ -2355,25 +2355,25 @@ static void stm32f0_lptransfer(struct stm32f0_usbdev_s *priv) if (epno == 0) { - stm32f0_ep0done(priv, istr); + stm32_ep0done(priv, istr); } /* Handle other endpoint completion events */ else { - stm32f0_epdone(priv, epno); + stm32_epdone(priv, epno); } } } /**************************************************************************** - * Name: stm32f0_usb_interrupt + * Name: stm32_usb_interrupt ****************************************************************************/ -static int stm32f0_usb_interrupt(int irq, void *context, FAR void *arg) +static int stm32_usb_interrupt(int irq, void *context, FAR void *arg) { - struct stm32f0_usbdev_s *priv = (struct stm32f0_usbdev_s *)arg; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)arg; uint16_t istr; uint8_t epno; @@ -2383,11 +2383,11 @@ static int stm32f0_usb_interrupt(int irq, void *context, FAR void *arg) * for isochronous and double-buffer bulk transfers. */ - istr = stm32f0_getreg(STM32F0_USB_ISTR); - usbtrace(TRACE_INTENTRY(STM32F0_TRACEINTID_INTERRUPT), istr); + istr = stm32_getreg(STM32_USB_ISTR); + usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_INTERRUPT), istr); while ((istr & USB_ISTR_CTR) != 0) { - stm32f0_putreg((uint16_t)~USB_ISTR_CTR, STM32F0_USB_ISTR); + stm32_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); /* Extract highest priority endpoint number */ @@ -2395,11 +2395,11 @@ static int stm32f0_usb_interrupt(int irq, void *context, FAR void *arg) /* And handle the completion event */ - stm32f0_epdone(priv, epno); + stm32_epdone(priv, epno); /* Fetch the status again for the next time through the loop */ - istr = stm32f0_getreg(STM32F0_USB_ISTR); + istr = stm32_getreg(STM32_USB_ISTR); } /* Handle Reset interrupts. When this event occurs, the peripheral is left @@ -2411,14 +2411,14 @@ static int stm32f0_usb_interrupt(int irq, void *context, FAR void *arg) { /* Reset interrupt received. Clear the RESET interrupt status. */ - stm32f0_putreg(~USB_ISTR_RESET, STM32F0_USB_ISTR); - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_RESET), istr); + stm32_putreg(~USB_ISTR_RESET, STM32_USB_ISTR); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RESET), istr); /* Restore our power-up state and exit now because istr is no longer * valid. */ - stm32f0_reset(priv); + stm32_reset(priv); goto exit_interrupt; } @@ -2432,12 +2432,12 @@ static int stm32f0_usb_interrupt(int irq, void *context, FAR void *arg) * cause of the resume is indicated in the FNR register */ - stm32f0_putreg(~USB_ISTR_WKUP, STM32F0_USB_ISTR); - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_WKUP), stm32f0_getreg(STM32F0_USB_FNR)); + stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WKUP), stm32_getreg(STM32_USB_FNR)); /* Perform the wakeup action */ - stm32f0_initresume(priv); + stm32_initresume(priv); priv->rsmstate = RSMSTATE_IDLE; /* Disable ESOF polling, disable the wakeup interrupt, and @@ -2445,49 +2445,49 @@ static int stm32f0_usb_interrupt(int irq, void *context, FAR void *arg) * interrupts. */ - stm32f0_setimask(priv, USB_CNTR_SUSPM, USB_CNTR_ESOFM | USB_CNTR_WKUPM); - stm32f0_putreg(~USB_CNTR_SUSPM, STM32F0_USB_ISTR); + stm32_setimask(priv, USB_CNTR_SUSPM, USB_CNTR_ESOFM | USB_CNTR_WKUPM); + stm32_putreg(~USB_CNTR_SUSPM, STM32_USB_ISTR); } if ((istr & USB_ISTR_SUSP & priv->imask) != 0) { - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_SUSP), 0); - stm32f0_suspend(priv); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSP), 0); + stm32_suspend(priv); /* Clear of the ISTR bit must be done after setting of USB_CNTR_FSUSP */ - stm32f0_putreg(~USB_ISTR_SUSP, STM32F0_USB_ISTR); + stm32_putreg(~USB_ISTR_SUSP, STM32_USB_ISTR); } if ((istr & USB_ISTR_ESOF & priv->imask) != 0) { - stm32f0_putreg(~USB_ISTR_ESOF, STM32F0_USB_ISTR); + stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); /* Resume handling timing is made with ESOFs */ - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_ESOF), 0); - stm32f0_esofpoll(priv); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ESOF), 0); + stm32_esofpoll(priv); } if ((istr & USB_ISTR_CTR & priv->imask) != 0) { /* Low priority endpoint correct transfer interrupt */ - usbtrace(TRACE_INTDECODE(STM32F0_TRACEINTID_LPCTR), istr); - stm32f0_lptransfer(priv); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_LPCTR), istr); + stm32_lptransfer(priv); } exit_interrupt: - usbtrace(TRACE_INTEXIT(STM32F0_TRACEINTID_INTERRUPT), 0); + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_INTERRUPT), 0); return OK; } /**************************************************************************** - * Name: stm32f0_setimask + * Name: stm32_setimask ****************************************************************************/ static void -stm32f0_setimask(struct stm32f0_usbdev_s *priv, uint16_t setbits, uint16_t clrbits) +stm32_setimask(struct stm32_usbdev_s *priv, uint16_t setbits, uint16_t clrbits) { uint16_t regval; @@ -2500,20 +2500,20 @@ stm32f0_setimask(struct stm32f0_usbdev_s *priv, uint16_t setbits, uint16_t clrbi * register (Hmmm... who is shadowing whom?) */ - regval = stm32f0_getreg(STM32F0_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval &= ~USB_CNTR_ALLINTS; regval |= priv->imask; - stm32f0_putreg(regval, STM32F0_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); } /**************************************************************************** * Suspend/Resume Helpers ****************************************************************************/ /**************************************************************************** - * Name: stm32f0_suspend + * Name: stm32_suspend ****************************************************************************/ -static void stm32f0_suspend(struct stm32f0_usbdev_s *priv) +static void stm32_suspend(struct stm32_usbdev_s *priv) { uint16_t regval; @@ -2528,16 +2528,16 @@ static void stm32f0_suspend(struct stm32f0_usbdev_s *priv) * interrupt. Clear any pending WKUP interrupt. */ - stm32f0_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); - stm32f0_putreg(~USB_ISTR_WKUP, STM32F0_USB_ISTR); + stm32_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); + stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); /* Set the FSUSP bit in the CNTR register. This activates suspend mode * within the USB peripheral and disables further SUSP interrupts. */ - regval = stm32f0_getreg(STM32F0_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval |= USB_CNTR_FSUSP; - stm32f0_putreg(regval, STM32F0_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); /* If we are not a self-powered device, the got to low-power mode */ @@ -2548,23 +2548,23 @@ static void stm32f0_suspend(struct stm32f0_usbdev_s *priv) * able to detect resume activity */ - regval = stm32f0_getreg(STM32F0_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval |= USB_CNTR_LPMODE; - stm32f0_putreg(regval, STM32F0_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); } /* Let the board-specific logic know that we have entered the suspend * state */ - stm32f0_usbsuspend((struct usbdev_s *)priv, false); + stm32_usbsuspend((struct usbdev_s *)priv, false); } /**************************************************************************** - * Name: stm32f0_initresume + * Name: stm32_initresume ****************************************************************************/ -static void stm32f0_initresume(struct stm32f0_usbdev_s *priv) +static void stm32_initresume(struct stm32_usbdev_s *priv) { uint16_t regval; @@ -2578,17 +2578,17 @@ static void stm32f0_initresume(struct stm32f0_usbdev_s *priv) * hardware when a WKUP interrupt event occurs). */ - regval = stm32f0_getreg(STM32F0_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval &= (~USB_CNTR_LPMODE); - stm32f0_putreg(regval, STM32F0_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); /* Restore full power -- whatever that means for this particular board */ - stm32f0_usbsuspend((struct usbdev_s *)priv, true); + stm32_usbsuspend((struct usbdev_s *)priv, true); /* Reset FSUSP bit and enable normal interrupt handling */ - stm32f0_putreg(STM32F0_CNTR_SETUP, STM32F0_USB_CNTR); + stm32_putreg(STM32_CNTR_SETUP, STM32_USB_CNTR); /* Notify the class driver of the resume event */ @@ -2599,10 +2599,10 @@ static void stm32f0_initresume(struct stm32f0_usbdev_s *priv) } /**************************************************************************** - * Name: stm32f0_esofpoll + * Name: stm32_esofpoll ****************************************************************************/ -static void stm32f0_esofpoll(struct stm32f0_usbdev_s *priv) +static void stm32_esofpoll(struct stm32_usbdev_s *priv) { uint16_t regval; @@ -2613,9 +2613,9 @@ static void stm32f0_esofpoll(struct stm32f0_usbdev_s *priv) /* One ESOF after internal resume requested */ case RSMSTATE_STARTED: - regval = stm32f0_getreg(STM32F0_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval |= USB_CNTR_RESUME; - stm32f0_putreg(regval, STM32F0_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); priv->rsmstate = RSMSTATE_WAITING; priv->nesofs = 10; break; @@ -2628,17 +2628,17 @@ static void stm32f0_esofpoll(struct stm32f0_usbdev_s *priv) { /* Okay.. we are ready to resume normal operation */ - regval = stm32f0_getreg(STM32F0_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval &= (~USB_CNTR_RESUME); - stm32f0_putreg(regval, STM32F0_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); priv->rsmstate = RSMSTATE_IDLE; /* Disable ESOF polling, disable the SUSP interrupt, and enable * the WKUP interrupt. Clear any pending WKUP interrupt. */ - stm32f0_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); - stm32f0_putreg(~USB_ISTR_WKUP, STM32F0_USB_ISTR); + stm32_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); + stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); } break; @@ -2653,13 +2653,13 @@ static void stm32f0_esofpoll(struct stm32f0_usbdev_s *priv) * Endpoint Helpers ****************************************************************************/ /**************************************************************************** - * Name: stm32f0_epreserve + * Name: stm32_epreserve ****************************************************************************/ -static inline struct stm32f0_ep_s * -stm32f0_epreserve(struct stm32f0_usbdev_s *priv, uint8_t epset) +static inline struct stm32_ep_s * +stm32_epreserve(struct stm32_usbdev_s *priv, uint8_t epset) { - struct stm32f0_ep_s *privep = NULL; + struct stm32_ep_s *privep = NULL; irqstate_t flags; int epndx = 0; @@ -2671,9 +2671,9 @@ stm32f0_epreserve(struct stm32f0_usbdev_s *priv, uint8_t epset) * (skipping EP0) */ - for (epndx = 1; epndx < STM32F0_NENDPOINTS; epndx++) + for (epndx = 1; epndx < STM32_NENDPOINTS; epndx++) { - uint8_t bit = STM32F0_ENDP_BIT(epndx); + uint8_t bit = STM32_ENDP_BIT(epndx); if ((epset & bit) != 0) { /* Mark the endpoint no longer available */ @@ -2693,43 +2693,43 @@ stm32f0_epreserve(struct stm32f0_usbdev_s *priv, uint8_t epset) } /**************************************************************************** - * Name: stm32f0_epunreserve + * Name: stm32_epunreserve ****************************************************************************/ static inline void -stm32f0_epunreserve(struct stm32f0_usbdev_s *priv, struct stm32f0_ep_s *privep) +stm32_epunreserve(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) { irqstate_t flags = enter_critical_section(); - priv->epavail |= STM32F0_ENDP_BIT(USB_EPNO(privep->ep.eplog)); + priv->epavail |= STM32_ENDP_BIT(USB_EPNO(privep->ep.eplog)); leave_critical_section(flags); } /**************************************************************************** - * Name: stm32f0_epreserved + * Name: stm32_epreserved ****************************************************************************/ static inline bool -stm32f0_epreserved(struct stm32f0_usbdev_s *priv, int epno) +stm32_epreserved(struct stm32_usbdev_s *priv, int epno) { - return ((priv->epavail & STM32F0_ENDP_BIT(epno)) == 0); + return ((priv->epavail & STM32_ENDP_BIT(epno)) == 0); } /**************************************************************************** - * Name: stm32f0_epallocpma + * Name: stm32_epallocpma ****************************************************************************/ -static int stm32f0_epallocpma(struct stm32f0_usbdev_s *priv) +static int stm32_epallocpma(struct stm32_usbdev_s *priv) { irqstate_t flags; int bufno = ERROR; int bufndx; flags = enter_critical_section(); - for (bufndx = 2; bufndx < STM32F0_NBUFFERS; bufndx++) + for (bufndx = 2; bufndx < STM32_NBUFFERS; bufndx++) { /* Check if this buffer is available */ - uint8_t bit = STM32F0_BUFFER_BIT(bufndx); + uint8_t bit = STM32_BUFFER_BIT(bufndx); if ((priv->bufavail & bit) != 0) { /* Yes.. Mark the endpoint no longer available */ @@ -2748,14 +2748,14 @@ static int stm32f0_epallocpma(struct stm32f0_usbdev_s *priv) } /**************************************************************************** - * Name: stm32f0_epfreepma + * Name: stm32_epfreepma ****************************************************************************/ static inline void -stm32f0_epfreepma(struct stm32f0_usbdev_s *priv, struct stm32f0_ep_s *privep) +stm32_epfreepma(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) { irqstate_t flags = enter_critical_section(); - priv->epavail |= STM32F0_ENDP_BIT(privep->bufno); + priv->epavail |= STM32_ENDP_BIT(privep->bufno); leave_critical_section(flags); } @@ -2763,14 +2763,14 @@ stm32f0_epfreepma(struct stm32f0_usbdev_s *priv, struct stm32f0_ep_s *privep) * Endpoint operations ****************************************************************************/ /**************************************************************************** - * Name: stm32f0_epconfigure + * Name: stm32_epconfigure ****************************************************************************/ -static int stm32f0_epconfigure(struct usbdev_ep_s *ep, +static int stm32_epconfigure(struct usbdev_ep_s *ep, const struct usb_epdesc_s *desc, bool last) { - struct stm32f0_ep_s *privep = (struct stm32f0_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; uint16_t pma; uint16_t setting; uint16_t maxpacket; @@ -2779,7 +2779,7 @@ static int stm32f0_epconfigure(struct usbdev_ep_s *ep, #ifdef CONFIG_DEBUG_FEATURES if (!ep || !desc) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); uerr("ERROR: ep=%p desc=%p\n"); return -EINVAL; } @@ -2813,21 +2813,21 @@ static int stm32f0_epconfigure(struct usbdev_ep_s *ep, break; default: - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_BADEPTYPE), (uint16_t)desc->type); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPTYPE), (uint16_t)desc->type); return -EINVAL; } - stm32f0_seteptype(epno, setting); + stm32_seteptype(epno, setting); /* Get the address of the PMA buffer allocated for this endpoint */ #warning "REVISIT: Should configure BULK EPs using double buffer feature" - pma = STM32F0_BUFNO2BUF(privep->bufno); + pma = STM32_BUFNO2BUF(privep->bufno); /* Get the maxpacket size of the endpoint. */ maxpacket = GETUINT16(desc->mxpacketsize); - DEBUGASSERT(maxpacket <= STM32F0_MAXPACKET_SIZE); + DEBUGASSERT(maxpacket <= STM32_MAXPACKET_SIZE); ep->maxpacket = maxpacket; /* Get the subset matching the requested direction */ @@ -2840,9 +2840,9 @@ static int stm32f0_epconfigure(struct usbdev_ep_s *ep, /* Set up TX; disable RX */ - stm32f0_seteptxaddr(epno, pma); - stm32f0_seteptxstatus(epno, USB_EPR_STATTX_NAK); - stm32f0_seteprxstatus(epno, USB_EPR_STATRX_DIS); + stm32_seteptxaddr(epno, pma); + stm32_seteptxstatus(epno, USB_EPR_STATTX_NAK); + stm32_seteprxstatus(epno, USB_EPR_STATRX_DIS); } else { @@ -2852,30 +2852,30 @@ static int stm32f0_epconfigure(struct usbdev_ep_s *ep, /* Set up RX; disable TX */ - stm32f0_seteprxaddr(epno, pma); - stm32f0_seteprxcount(epno, maxpacket); - stm32f0_seteprxstatus(epno, USB_EPR_STATRX_VALID); - stm32f0_seteptxstatus(epno, USB_EPR_STATTX_DIS); + stm32_seteprxaddr(epno, pma); + stm32_seteprxcount(epno, maxpacket); + stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID); + stm32_seteptxstatus(epno, USB_EPR_STATTX_DIS); } - stm32f0_dumpep(epno); + stm32_dumpep(epno); return OK; } /**************************************************************************** - * Name: stm32f0_epdisable + * Name: stm32_epdisable ****************************************************************************/ -static int stm32f0_epdisable(struct usbdev_ep_s *ep) +static int stm32_epdisable(struct usbdev_ep_s *ep) { - struct stm32f0_ep_s *privep = (struct stm32f0_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; irqstate_t flags; uint8_t epno; #ifdef CONFIG_DEBUG_FEATURES if (!ep) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); uerr("ERROR: ep=%p\n", ep); return -EINVAL; } @@ -2887,58 +2887,58 @@ static int stm32f0_epdisable(struct usbdev_ep_s *ep) /* Cancel any ongoing activity */ flags = enter_critical_section(); - stm32f0_cancelrequests(privep); + stm32_cancelrequests(privep); /* Disable TX; disable RX */ - stm32f0_seteprxcount(epno, 0); - stm32f0_seteprxstatus(epno, USB_EPR_STATRX_DIS); - stm32f0_seteptxstatus(epno, USB_EPR_STATTX_DIS); + stm32_seteprxcount(epno, 0); + stm32_seteprxstatus(epno, USB_EPR_STATRX_DIS); + stm32_seteptxstatus(epno, USB_EPR_STATTX_DIS); leave_critical_section(flags); return OK; } /**************************************************************************** - * Name: stm32f0_epallocreq + * Name: stm32_epallocreq ****************************************************************************/ -static struct usbdev_req_s *stm32f0_epallocreq(struct usbdev_ep_s *ep) +static struct usbdev_req_s *stm32_epallocreq(struct usbdev_ep_s *ep) { - struct stm32f0_req_s *privreq; + struct stm32_req_s *privreq; #ifdef CONFIG_DEBUG_FEATURES if (!ep) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return NULL; } #endif usbtrace(TRACE_EPALLOCREQ, USB_EPNO(ep->eplog)); - privreq = (struct stm32f0_req_s *)kmm_malloc(sizeof(struct stm32f0_req_s)); + privreq = (struct stm32_req_s *)kmm_malloc(sizeof(struct stm32_req_s)); if (!privreq) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_ALLOCFAIL), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); return NULL; } - memset(privreq, 0, sizeof(struct stm32f0_req_s)); + memset(privreq, 0, sizeof(struct stm32_req_s)); return &privreq->req; } /**************************************************************************** - * Name: stm32f0_epfreereq + * Name: stm32_epfreereq ****************************************************************************/ -static void stm32f0_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) +static void stm32_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct stm32f0_req_s *privreq = (struct stm32f0_req_s *)req; + struct stm32_req_s *privreq = (struct stm32_req_s *)req; #ifdef CONFIG_DEBUG_FEATURES if (!ep || !req) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return; } #endif @@ -2948,14 +2948,14 @@ static void stm32f0_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) } /**************************************************************************** - * Name: stm32f0_epsubmit + * Name: stm32_epsubmit ****************************************************************************/ -static int stm32f0_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) +static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct stm32f0_req_s *privreq = (struct stm32f0_req_s *)req; - struct stm32f0_ep_s *privep = (struct stm32f0_ep_s *)ep; - struct stm32f0_usbdev_s *priv; + struct stm32_req_s *privreq = (struct stm32_req_s *)req; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + struct stm32_usbdev_s *priv; irqstate_t flags; uint8_t epno; int ret = OK; @@ -2963,7 +2963,7 @@ static int stm32f0_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) #ifdef CONFIG_DEBUG_FEATURES if (!req || !req->callback || !req->buf || !ep) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); return -EINVAL; @@ -2976,7 +2976,7 @@ static int stm32f0_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) #ifdef CONFIG_DEBUG_FEATURES if (!priv->driver) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); uerr("ERROR: driver=%p\n", priv->driver); return -ESHUTDOWN; } @@ -2993,7 +2993,7 @@ static int stm32f0_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) if (privep->stalled) { - stm32f0_abortrequest(privep, privreq, -EBUSY); + stm32_abortrequest(privep, privreq, -EBUSY); uerr("ERROR: stalled\n"); ret = -EBUSY; } @@ -3007,7 +3007,7 @@ static int stm32f0_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { /* Add the new request to the request queue for the IN endpoint */ - stm32f0_rqenqueue(privep, privreq); + stm32_rqenqueue(privep, privreq); usbtrace(TRACE_INREQQUEUED(epno), req->len); /* If the IN endpoint FIFO is available, then transfer the data now */ @@ -3017,16 +3017,16 @@ static int stm32f0_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) priv->txstatus = USB_EPR_STATTX_NAK; if (epno == EP0) { - ret = stm32f0_wrrequest_ep0(priv, privep); + ret = stm32_wrrequest_ep0(priv, privep); } else { - ret = stm32f0_wrrequest(priv, privep); + ret = stm32_wrrequest(priv, privep); } /* Set the new TX status */ - stm32f0_seteptxstatus(epno, priv->txstatus); + stm32_seteptxstatus(epno, priv->txstatus); } } @@ -3037,7 +3037,7 @@ static int stm32f0_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) /* Add the new request to the request queue for the OUT endpoint */ privep->txnullpkt = 0; - stm32f0_rqenqueue(privep, privreq); + stm32_rqenqueue(privep, privreq); usbtrace(TRACE_OUTREQQUEUED(epno), req->len); /* This there a incoming data pending the availability of a request? */ @@ -3052,7 +3052,7 @@ static int stm32f0_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) */ priv->rxstatus = USB_EPR_STATRX_VALID; - stm32f0_seteprxstatus(epno, priv->rxstatus); + stm32_seteprxstatus(epno, priv->rxstatus); /* Data is no longer pending */ @@ -3065,37 +3065,37 @@ static int stm32f0_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) } /**************************************************************************** - * Name: stm32f0_epcancel + * Name: stm32_epcancel ****************************************************************************/ -static int stm32f0_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) +static int stm32_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct stm32f0_ep_s *privep = (struct stm32f0_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; irqstate_t flags; #ifdef CONFIG_DEBUG_USB if (!ep || !req) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif usbtrace(TRACE_EPCANCEL, USB_EPNO(ep->eplog)); flags = enter_critical_section(); - stm32f0_cancelrequests(privep); + stm32_cancelrequests(privep); leave_critical_section(flags); return OK; } /**************************************************************************** - * Name: stm32f0_epstall + * Name: stm32_epstall ****************************************************************************/ -static int stm32f0_epstall(struct usbdev_ep_s *ep, bool resume) +static int stm32_epstall(struct usbdev_ep_s *ep, bool resume) { - struct stm32f0_ep_s *privep; - struct stm32f0_usbdev_s *priv; + struct stm32_ep_s *privep; + struct stm32_usbdev_s *priv; uint8_t epno; uint16_t status; irqstate_t flags; @@ -3103,13 +3103,13 @@ static int stm32f0_epstall(struct usbdev_ep_s *ep, bool resume) #ifdef CONFIG_DEBUG_USB if (!ep) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif - privep = (struct stm32f0_ep_s *)ep; - priv = (struct stm32f0_usbdev_s *)privep->dev; + privep = (struct stm32_ep_s *)ep; + priv = (struct stm32_usbdev_s *)privep->dev; epno = USB_EPNO(ep->eplog); /* STALL or RESUME the endpoint */ @@ -3123,16 +3123,16 @@ static int stm32f0_epstall(struct usbdev_ep_s *ep, bool resume) if (USB_ISEPIN(ep->eplog)) { - status = stm32f0_geteptxstatus(epno); + status = stm32_geteptxstatus(epno); } else { - status = stm32f0_geteprxstatus(epno); + status = stm32_geteprxstatus(epno); } if (status == 0) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_EPDISABLED), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPDISABLED), 0); if (epno == 0) { @@ -3155,46 +3155,46 @@ static int stm32f0_epstall(struct usbdev_ep_s *ep, bool resume) { /* IN endpoint */ - if (stm32f0_eptxstalled(epno)) + if (stm32_eptxstalled(epno)) { - stm32f0_clrtxdtog(epno); + stm32_clrtxdtog(epno); /* Restart any queued write requests */ priv->txstatus = USB_EPR_STATTX_NAK; if (epno == EP0) { - (void)stm32f0_wrrequest_ep0(priv, privep); + (void)stm32_wrrequest_ep0(priv, privep); } else { - (void)stm32f0_wrrequest(priv, privep); + (void)stm32_wrrequest(priv, privep); } /* Set the new TX status */ - stm32f0_seteptxstatus(epno, priv->txstatus); + stm32_seteptxstatus(epno, priv->txstatus); } } else { /* OUT endpoint */ - if (stm32f0_eprxstalled(epno)) + if (stm32_eprxstalled(epno)) { if (epno == EP0) { /* After clear the STALL, enable the default endpoint receiver */ - stm32f0_seteprxcount(epno, ep->maxpacket); + stm32_seteprxcount(epno, ep->maxpacket); } else { - stm32f0_clrrxdtog(epno); + stm32_clrrxdtog(epno); } priv->rxstatus = USB_EPR_STATRX_VALID; - stm32f0_seteprxstatus(epno, USB_EPR_STATRX_VALID); + stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID); } } } @@ -3211,14 +3211,14 @@ static int stm32f0_epstall(struct usbdev_ep_s *ep, bool resume) /* IN endpoint */ priv->txstatus = USB_EPR_STATTX_STALL; - stm32f0_seteptxstatus(epno, USB_EPR_STATTX_STALL); + stm32_seteptxstatus(epno, USB_EPR_STATTX_STALL); } else { /* OUT endpoint */ priv->rxstatus = USB_EPR_STATRX_STALL; - stm32f0_seteprxstatus(epno, USB_EPR_STATRX_STALL); + stm32_seteprxstatus(epno, USB_EPR_STATRX_STALL); } } @@ -3230,22 +3230,22 @@ static int stm32f0_epstall(struct usbdev_ep_s *ep, bool resume) * Device Controller Operations ****************************************************************************/ /**************************************************************************** - * Name: stm32f0_allocep + * Name: stm32_allocep ****************************************************************************/ -static struct usbdev_ep_s *stm32f0_allocep(struct usbdev_s *dev, uint8_t epno, +static struct usbdev_ep_s *stm32_allocep(struct usbdev_s *dev, uint8_t epno, bool in, uint8_t eptype) { - struct stm32f0_usbdev_s *priv = (struct stm32f0_usbdev_s *)dev; - struct stm32f0_ep_s *privep = NULL; - uint8_t epset = STM32F0_ENDP_ALLSET; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + struct stm32_ep_s *privep = NULL; + uint8_t epset = STM32_ENDP_ALLSET; int bufno; usbtrace(TRACE_DEVALLOCEP, (uint16_t)epno); #ifdef CONFIG_DEBUG_USB if (!dev) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return NULL; } #endif @@ -3265,9 +3265,9 @@ static struct usbdev_ep_s *stm32f0_allocep(struct usbdev_s *dev, uint8_t epno, * by the hardware. */ - if (epno >= STM32F0_NENDPOINTS) + if (epno >= STM32_NENDPOINTS) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_BADEPNO), (uint16_t)epno); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epno); return NULL; } @@ -3276,25 +3276,25 @@ static struct usbdev_ep_s *stm32f0_allocep(struct usbdev_s *dev, uint8_t epno, * the IN/OUT pair for this logical address. */ - epset = STM32F0_ENDP_BIT(epno); + epset = STM32_ENDP_BIT(epno); } /* Check if the selected endpoint number is available */ - privep = stm32f0_epreserve(priv, epset); + privep = stm32_epreserve(priv, epset); if (!privep) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_EPRESERVE), (uint16_t)epset); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPRESERVE), (uint16_t)epset); goto errout; } /* Allocate a PMA buffer for this endpoint */ #warning "REVISIT: Should configure BULK EPs using double buffer feature" - bufno = stm32f0_epallocpma(priv); + bufno = stm32_epallocpma(priv); if (bufno < 0) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_EPBUFFER), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPBUFFER), 0); goto errout_with_ep; } @@ -3302,80 +3302,80 @@ static struct usbdev_ep_s *stm32f0_allocep(struct usbdev_s *dev, uint8_t epno, return &privep->ep; errout_with_ep: - stm32f0_epunreserve(priv, privep); + stm32_epunreserve(priv, privep); errout: return NULL; } /**************************************************************************** - * Name: stm32f0_freeep + * Name: stm32_freeep ****************************************************************************/ -static void stm32f0_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) +static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) { - struct stm32f0_usbdev_s *priv; - struct stm32f0_ep_s *privep; + struct stm32_usbdev_s *priv; + struct stm32_ep_s *privep; #ifdef CONFIG_DEBUG_USB if (!dev || !ep) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return; } #endif - priv = (struct stm32f0_usbdev_s *)dev; - privep = (struct stm32f0_ep_s *)ep; + priv = (struct stm32_usbdev_s *)dev; + privep = (struct stm32_ep_s *)ep; usbtrace(TRACE_DEVFREEEP, (uint16_t)USB_EPNO(ep->eplog)); if (priv && privep) { /* Free the PMA buffer assigned to this endpoint */ - stm32f0_epfreepma(priv, privep); + stm32_epfreepma(priv, privep); /* Mark the endpoint as available */ - stm32f0_epunreserve(priv, privep); + stm32_epunreserve(priv, privep); } } /**************************************************************************** - * Name: stm32f0_getframe + * Name: stm32_getframe ****************************************************************************/ -static int stm32f0_getframe(struct usbdev_s *dev) +static int stm32_getframe(struct usbdev_s *dev) { uint16_t fnr; #ifdef CONFIG_DEBUG_USB if (!dev) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif /* Return the last frame number detected by the hardware */ - fnr = stm32f0_getreg(STM32F0_USB_FNR); + fnr = stm32_getreg(STM32_USB_FNR); usbtrace(TRACE_DEVGETFRAME, fnr); return (fnr & USB_FNR_FN_MASK); } /**************************************************************************** - * Name: stm32f0_wakeup + * Name: stm32_wakeup ****************************************************************************/ -static int stm32f0_wakeup(struct usbdev_s *dev) +static int stm32_wakeup(struct usbdev_s *dev) { - struct stm32f0_usbdev_s *priv = (struct stm32f0_usbdev_s *)dev; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; irqstate_t flags; usbtrace(TRACE_DEVWAKEUP, 0); #ifdef CONFIG_DEBUG_USB if (!dev) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -3385,7 +3385,7 @@ static int stm32f0_wakeup(struct usbdev_s *dev) */ flags = enter_critical_section(); - stm32f0_initresume(priv); + stm32_initresume(priv); priv->rsmstate = RSMSTATE_STARTED; /* Disable the SUSP interrupt (until we are fully resumed), disable @@ -3394,26 +3394,26 @@ static int stm32f0_wakeup(struct usbdev_s *dev) * pending ESOF interrupt. */ - stm32f0_setimask(priv, USB_CNTR_ESOFM, USB_CNTR_WKUPM | USB_CNTR_SUSPM); - stm32f0_putreg(~USB_ISTR_ESOF, STM32F0_USB_ISTR); + stm32_setimask(priv, USB_CNTR_ESOFM, USB_CNTR_WKUPM | USB_CNTR_SUSPM); + stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); leave_critical_section(flags); return OK; } /**************************************************************************** - * Name: stm32f0_selfpowered + * Name: stm32_selfpowered ****************************************************************************/ -static int stm32f0_selfpowered(struct usbdev_s *dev, bool selfpowered) +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered) { - struct stm32f0_usbdev_s *priv = (struct stm32f0_usbdev_s *)dev; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); #ifdef CONFIG_DEBUG_USB if (!dev) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -ENODEV; } #endif @@ -3427,16 +3427,16 @@ static int stm32f0_selfpowered(struct usbdev_s *dev, bool selfpowered) ****************************************************************************/ /**************************************************************************** - * Name: stm32f0_reset + * Name: stm32_reset ****************************************************************************/ -static void stm32f0_reset(struct stm32f0_usbdev_s *priv) +static void stm32_reset(struct stm32_usbdev_s *priv) { int epno; /* Put the USB controller in reset, disable all interrupts */ - stm32f0_putreg(USB_CNTR_FRES, STM32F0_USB_CNTR); + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); /* Tell the class driver that we are disconnected. The class driver * should then accept any new configurations. @@ -3452,19 +3452,19 @@ static void stm32f0_reset(struct stm32f0_usbdev_s *priv) /* Reset endpoints */ - for (epno = 0; epno < STM32F0_NENDPOINTS; epno++) + for (epno = 0; epno < STM32_NENDPOINTS; epno++) { - struct stm32f0_ep_s *privep = &priv->eplist[epno]; + struct stm32_ep_s *privep = &priv->eplist[epno]; /* Cancel any queued requests. Since they are canceled * with status -ESHUTDOWN, then will not be requeued * until the configuration is reset. NOTE: This should * not be necessary... the CLASS_DISCONNECT above should - * result in the class implementation calling stm32f0_epdisable + * result in the class implementation calling stm32_epdisable * for each of its configured endpoints. */ - stm32f0_cancelrequests(privep); + stm32_cancelrequests(privep); /* Reset endpoint status */ @@ -3476,58 +3476,58 @@ static void stm32f0_reset(struct stm32f0_usbdev_s *priv) /* Re-configure the USB controller in its initial, unconnected state */ - stm32f0_hwreset(priv); + stm32_hwreset(priv); priv->usbdev.speed = USB_SPEED_FULL; } /**************************************************************************** - * Name: stm32f0_hwreset + * Name: stm32_hwreset ****************************************************************************/ -static void stm32f0_hwreset(struct stm32f0_usbdev_s *priv) +static void stm32_hwreset(struct stm32_usbdev_s *priv) { /* Put the USB controller into reset, clear all interrupt enables */ - stm32f0_putreg(USB_CNTR_FRES, STM32F0_USB_CNTR); + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); /* Disable interrupts (and perhaps take the USB controller out of reset) */ priv->imask = 0; - stm32f0_putreg(priv->imask, STM32F0_USB_CNTR); + stm32_putreg(priv->imask, STM32_USB_CNTR); /* Set the STM32 BTABLE address */ - stm32f0_putreg(STM32F0_BTABLE_ADDRESS & 0xfff8, STM32F0_USB_BTABLE); + stm32_putreg(STM32_BTABLE_ADDRESS & 0xfff8, STM32_USB_BTABLE); /* Initialize EP0 */ - stm32f0_seteptype(EP0, USB_EPR_EPTYPE_CONTROL); - stm32f0_seteptxstatus(EP0, USB_EPR_STATTX_NAK); - stm32f0_seteprxaddr(EP0, STM32F0_EP0_RXADDR); - stm32f0_seteprxcount(EP0, STM32F0_EP0MAXPACKET); - stm32f0_seteptxaddr(EP0, STM32F0_EP0_TXADDR); - stm32f0_clrstatusout(EP0); - stm32f0_seteprxstatus(EP0, USB_EPR_STATRX_VALID); + stm32_seteptype(EP0, USB_EPR_EPTYPE_CONTROL); + stm32_seteptxstatus(EP0, USB_EPR_STATTX_NAK); + stm32_seteprxaddr(EP0, STM32_EP0_RXADDR); + stm32_seteprxcount(EP0, STM32_EP0MAXPACKET); + stm32_seteptxaddr(EP0, STM32_EP0_TXADDR); + stm32_clrstatusout(EP0); + stm32_seteprxstatus(EP0, USB_EPR_STATRX_VALID); /* Set the device to respond on default address */ - stm32f0_setdevaddr(priv, 0); + stm32_setdevaddr(priv, 0); /* Clear any pending interrupts */ - stm32f0_putreg(0, STM32F0_USB_ISTR); + stm32_putreg(0, STM32_USB_ISTR); /* Enable interrupts at the USB controller */ - stm32f0_setimask(priv, STM32F0_CNTR_SETUP, (USB_CNTR_ALLINTS & ~STM32F0_CNTR_SETUP)); - stm32f0_dumpep(EP0); + stm32_setimask(priv, STM32_CNTR_SETUP, (USB_CNTR_ALLINTS & ~STM32_CNTR_SETUP)); + stm32_dumpep(EP0); } /**************************************************************************** - * Name: stm32f0_hwsetup + * Name: stm32_hwsetup ****************************************************************************/ -static void stm32f0_hwsetup(struct stm32f0_usbdev_s *priv) +static void stm32_hwsetup(struct stm32_usbdev_s *priv) { int epno; @@ -3535,28 +3535,28 @@ static void stm32f0_hwsetup(struct stm32f0_usbdev_s *priv) * all USB interrupts */ - stm32f0_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32F0_USB_CNTR); + stm32_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); /* Disconnect the device / disable the pull-up. We don't want the * host to enumerate us until the class driver is registered. */ - stm32f0_usbpullup(&priv->usbdev, false); + stm32_usbpullup(&priv->usbdev, false); /* Initialize the device state structure. NOTE: many fields * have the initial value of zero and, hence, are not explicitly * initialized here. */ - memset(priv, 0, sizeof(struct stm32f0_usbdev_s)); + memset(priv, 0, sizeof(struct stm32_usbdev_s)); priv->usbdev.ops = &g_devops; priv->usbdev.ep0 = &priv->eplist[EP0].ep; - priv->epavail = STM32F0_ENDP_ALLSET & ~STM32F0_ENDP_BIT(EP0); - priv->bufavail = STM32F0_BUFFER_ALLSET & ~STM32F0_BUFFER_EP0; + priv->epavail = STM32_ENDP_ALLSET & ~STM32_ENDP_BIT(EP0); + priv->bufavail = STM32_BUFFER_ALLSET & ~STM32_BUFFER_EP0; /* Initialize the endpoint list */ - for (epno = 0; epno < STM32F0_NENDPOINTS; epno++) + for (epno = 0; epno < STM32_NENDPOINTS; epno++) { /* Set endpoint operations, reference to driver structure (not * really necessary because there is only one controller), and @@ -3573,13 +3573,13 @@ static void stm32f0_hwsetup(struct stm32f0_usbdev_s *priv) * packet size can be selected when the endpoint is configured. */ - priv->eplist[epno].ep.maxpacket = STM32F0_MAXPACKET_SIZE; + priv->eplist[epno].ep.maxpacket = STM32_MAXPACKET_SIZE; } /* Select a smaller endpoint size for EP0 */ -#if STM32F0_EP0MAXPACKET < STM32F0_MAXPACKET_SIZE - priv->eplist[EP0].ep.maxpacket = STM32F0_EP0MAXPACKET; +#if STM32_EP0MAXPACKET < STM32_MAXPACKET_SIZE + priv->eplist[EP0].ep.maxpacket = STM32_EP0MAXPACKET; #endif /* Configure the USB controller. USB uses the following GPIO pins: @@ -3600,33 +3600,33 @@ static void stm32f0_hwsetup(struct stm32f0_usbdev_s *priv) * class driver has been bound. */ - stm32f0_putreg(USB_CNTR_FRES, STM32F0_USB_CNTR); + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); up_mdelay(5); } /**************************************************************************** - * Name: stm32f0_hwshutdown + * Name: stm32_hwshutdown ****************************************************************************/ -static void stm32f0_hwshutdown(struct stm32f0_usbdev_s *priv) +static void stm32_hwshutdown(struct stm32_usbdev_s *priv) { priv->usbdev.speed = USB_SPEED_UNKNOWN; /* Disable all interrupts and force the USB controller into reset */ - stm32f0_putreg(USB_CNTR_FRES, STM32F0_USB_CNTR); + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); /* Clear any pending interrupts */ - stm32f0_putreg(0, STM32F0_USB_ISTR); + stm32_putreg(0, STM32_USB_ISTR); /* Disconnect the device / disable the pull-up */ - stm32f0_usbpullup(&priv->usbdev, false); + stm32_usbpullup(&priv->usbdev, false); /* Power down the USB controller */ - stm32f0_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32F0_USB_CNTR); + stm32_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); } /**************************************************************************** @@ -3652,31 +3652,31 @@ void up_usbinitialize(void) * easier. */ - struct stm32f0_usbdev_s *priv = &g_usbdev; + struct stm32_usbdev_s *priv = &g_usbdev; uint32_t regval; usbtrace(TRACE_DEVINIT, 0); /* Configure USB GPIO alternate function pins */ -#ifdef CONFIG_STM32F0_STM32F30XX - (void)stm32f0_configgpio(GPIO_USB_DM); - (void)stm32f0_configgpio(GPIO_USB_DP); +#ifdef CONFIG_STM32F0L0_STM32F30XX + (void)stm32_configgpio(GPIO_USB_DM); + (void)stm32_configgpio(GPIO_USB_DP); #endif /* Enable clocking to the USB peripheral */ - regval = getreg32(STM32F0_RCC_APB1RSTR); + regval = getreg32(STM32_RCC_APB1RSTR); regval &= ~RCC_APB1ENR_USBEN; - putreg32(regval, STM32F0_RCC_APB1RSTR); + putreg32(regval, STM32_RCC_APB1RSTR); /* Enable HSI48 clocking to to support USB transfers */ - stm32f0_enable_hsi48(SYNCSRC_USB); + stm32_enable_hsi48(SYNCSRC_USB); /* Power up the USB controller, but leave it in the reset state */ - stm32f0_hwsetup(priv); + stm32_hwsetup(priv); /* Attach USB controller interrupt handlers. The hardware will not be * initialized and interrupts will not be enabled until the class device @@ -3684,10 +3684,10 @@ void up_usbinitialize(void) * them when we need them later. */ - if (irq_attach(STM32F0_IRQ_USB, stm32f0_usb_interrupt, priv) != 0) + if (irq_attach(STM32_IRQ_USB, stm32_usb_interrupt, priv) != 0) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_IRQREGISTRATION), - (uint16_t)STM32F0_IRQ_USB); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION), + (uint16_t)STM32_IRQ_USB); goto errout; } @@ -3716,7 +3716,7 @@ void up_usbuninitialize(void) * easier. */ - struct stm32f0_usbdev_s *priv = &g_usbdev; + struct stm32_usbdev_s *priv = &g_usbdev; irqstate_t flags; flags = enter_critical_section(); @@ -3724,18 +3724,18 @@ void up_usbuninitialize(void) /* Disable and detach the USB IRQs */ - up_disable_irq(STM32F0_IRQ_USB); - irq_detach(STM32F0_IRQ_USB); + up_disable_irq(STM32_IRQ_USB); + irq_detach(STM32_IRQ_USB); if (priv->driver) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_DRIVERREGISTERED), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVERREGISTERED), 0); usbdev_unregister(priv->driver); } /* Put the hardware in an inactive state */ - stm32f0_hwshutdown(priv); + stm32_hwshutdown(priv); leave_critical_section(flags); } @@ -3755,7 +3755,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) * easier. */ - struct stm32f0_usbdev_s *priv = &g_usbdev; + struct stm32_usbdev_s *priv = &g_usbdev; int ret; usbtrace(TRACE_DEVREGISTER, 0); @@ -3764,13 +3764,13 @@ int usbdev_register(struct usbdevclass_driver_s *driver) if (!driver || !driver->ops->bind || !driver->ops->unbind || !driver->ops->disconnect || !driver->ops->setup) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } if (priv->driver) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_DRIVER), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0); return -EBUSY; } #endif @@ -3784,23 +3784,23 @@ int usbdev_register(struct usbdevclass_driver_s *driver) ret = CLASS_BIND(driver, &priv->usbdev); if (ret) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_BINDFAILED), (uint16_t)-ret); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t)-ret); } else { /* Setup the USB controller -- enabling interrupts at the USB controller */ - stm32f0_hwreset(priv); + stm32_hwreset(priv); /* Enable USB controller interrupts at the NVIC */ - up_enable_irq(STM32F0_IRQ_USB); + up_enable_irq(STM32_IRQ_USB); /* Enable pull-up to connect the device. The host should enumerate us * some time after this */ - stm32f0_usbpullup(&priv->usbdev, true); + stm32_usbpullup(&priv->usbdev, true); priv->usbdev.speed = USB_SPEED_FULL; } @@ -3825,7 +3825,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) * easier. */ - struct stm32f0_usbdev_s *priv = &g_usbdev; + struct stm32_usbdev_s *priv = &g_usbdev; irqstate_t flags; usbtrace(TRACE_DEVUNREGISTER, 0); @@ -3833,7 +3833,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) #ifdef CONFIG_DEBUG_USB if (driver != priv->driver) { - usbtrace(TRACE_DEVERROR(STM32F0_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -3843,7 +3843,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) */ flags = enter_critical_section(); - stm32f0_reset(priv); + stm32_reset(priv); /* Unbind the class driver */ @@ -3851,15 +3851,15 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) /* Disable USB controller interrupts (but keep them attached) */ - up_disable_irq(STM32F0_IRQ_USB); + up_disable_irq(STM32_IRQ_USB); /* Put the hardware in an inactive state. Then bring the hardware back up - * in the reset state (this is probably not necessary, the stm32f0_reset() + * in the reset state (this is probably not necessary, the stm32_reset() * call above was probably sufficient). */ - stm32f0_hwshutdown(priv); - stm32f0_hwsetup(priv); + stm32_hwshutdown(priv); + stm32_hwsetup(priv); /* Unhook the driver */ @@ -3868,4 +3868,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) return OK; } -#endif /* CONFIG_USBDEV && CONFIG_STM32F0_USB */ +#endif /* CONFIG_USBDEV && CONFIG_STM32F0L0_USB */ diff --git a/arch/arm/src/stm32f0/stm32f0_usbdev.h b/arch/arm/src/stm32f0l0/stm32_usbdev.h similarity index 86% rename from arch/arm/src/stm32f0/stm32f0_usbdev.h rename to arch/arm/src/stm32f0l0/stm32_usbdev.h index fb0398158c8..fb3a48f44fc 100644 --- a/arch/arm/src/stm32f0/stm32f0_usbdev.h +++ b/arch/arm/src/stm32f0l0/stm32_usbdev.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32f0/stm32f0_usbdev.h + * arch/arm/src/stm32f0l0/stm32_usbdev.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_USBDEV_H -#define __ARCH_ARM_SRC_STM32F0_STM32F0_USBDEV_H +#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_USBDEV_H +#define __ARCH_ARM_SRC_STM32F0L0_STM32_USBDEV_H /************************************************************************************ * Included Files @@ -45,7 +45,7 @@ #include #include "chip.h" -#include "chip/stm32f0_usbdev.h" +#include "hardware/stm32_usbdev.h" /************************************************************************************ * Public Functions @@ -63,29 +63,29 @@ extern "C" #endif /************************************************************************************ - * Name: stm32f0_usbpullup + * Name: stm32_usbpullup * * Description: * If USB is supported and the board supports a pullup via GPIO (for USB software - * connect and disconnect), then the board software must provide stm32f0_pullup. + * connect and disconnect), then the board software must provide stm32_pullup. * See include/nuttx/usb/usbdev.h for additional description of this method. * ************************************************************************************/ -int stm32f0_usbpullup(FAR struct usbdev_s *dev, bool enable); +int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable); /************************************************************************************ - * Name: stm32f0_usbsuspend + * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32f0_usbsuspend logic if the USBDEV driver is + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is * used. This function is called whenever the USB enters or leaves suspend mode. * This is an opportunity for the board logic to shutdown clocks, power, etc. * while the USB is suspended. * ************************************************************************************/ -void stm32f0_usbsuspend(FAR struct usbdev_s *dev, bool resume); +void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume); #undef EXTERN #if defined(__cplusplus) @@ -93,4 +93,4 @@ void stm32f0_usbsuspend(FAR struct usbdev_s *dev, bool resume); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_USBDEV_H */ +#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_USBDEV_H */ diff --git a/configs/nucleo-f072rb/include/board.h b/configs/nucleo-f072rb/include/board.h index fa1b29dad36..873e0cce0b0 100644 --- a/configs/nucleo-f072rb/include/board.h +++ b/configs/nucleo-f072rb/include/board.h @@ -72,14 +72,14 @@ * Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins. */ -#define STM32F0_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ +#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ -#define STM32F0_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */ -#define STM32F0_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */ -#define STM32F0_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */ -#define STM32F0_HSE_FREQUENCY STM32F0_BOARD_XTAL -#define STM32F0_LSI_FREQUENCY 40000 /* Approximately 40KHz */ -#define STM32F0_LSE_FREQUENCY 32768 /* X2 on board */ +#define STM32_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */ +#define STM32_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */ +#define STM32_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSI_FREQUENCY 40000 /* Approximately 40KHz */ +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ /* PLL Configuration * @@ -93,7 +93,7 @@ * If the USB interface is used in the application, it requires a precise * 48MHz clock which can be generated from either the (1) the internal * main PLL with the HSE clock source using an HSE crystal oscillator. In - * this case, the PLL VCO clock (defined by STM32F0_CFGR_PLLMUL) must be + * this case, the PLL VCO clock (defined by STM32_CFGR_PLLMUL) must be * programmed to output a 96 MHz frequency. This is required to provide a * 48MHz clock to the (USBCLK = PLLVCO/2). Or (2) by using the internal * 48MHz oscillator in automatic trimming mode. The synchronization for @@ -111,63 +111,63 @@ * PLL source). */ -#define STM32F0_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ -#define STM32F0_PLLSRC_FREQUENCY (STM32F0_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ -#ifdef CONFIG_STM32F0_USB -# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */ -# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ -# define STM32F0_PLL_FREQUENCY (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ +#define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ +#ifdef CONFIG_STM32F0L0_USB +# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ +# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ +# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ #else -# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */ -# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ -# define STM32F0_PLL_FREQUENCY (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ +# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ +# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ +# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ #endif /* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output - * frequency (STM32F0_PLL_FREQUENCY divided by the PLLDIV value). + * frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). */ -#define STM32F0_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ -#define STM32F0_SYSCLK_SWS RCC_CFGR_SWS_PLL -#ifdef CONFIG_STM32F0_USB -# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#ifdef CONFIG_STM32F0L0_USB +# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #else -# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ +# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #endif -#define STM32F0_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32F0_HCLK_FREQUENCY STM32F0_SYSCLK_FREQUENCY -#define STM32F0_BOARD_HCLK STM32F0_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY +#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* APB1 clock (PCLK1) is HCLK (48MHz) */ -#define STM32F0_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32F0_PCLK1_FREQUENCY (STM32F0_HCLK_FREQUENCY) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (48MHz) */ -#define STM32F0_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32F0_PCLK2_FREQUENCY STM32F0_HCLK_FREQUENCY -#define STM32F0_APB2_CLKIN (STM32F0_PCLK2_FREQUENCY) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */ -#define STM32F0_APB1_TIM1_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM2_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM3_CLKIN (STM32F0_PCLK1_FREQUENCY) +#define STM32_APB1_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM6_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM7_CLKIN (STM32F0_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM14_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM15_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM16_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM17_CLKIN (STM32F0_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) /* LED definitions ******************************************************************/ /* LEDs * - * The Nucleo-64 board has one user controlable LED, User LD2. This green + * The Nucleo-64 board has one user controllable LED, User LD2. This green * LED is a user LED connected to Arduino signal D13 corresponding to STM32 * I/O PA5 (PB13 on other some other Nucleo-64 boards). * diff --git a/configs/nucleo-f072rb/nsh/defconfig b/configs/nucleo-f072rb/nsh/defconfig index 12d254db9a5..8dd858d56f7 100644 --- a/configs/nucleo-f072rb/nsh/defconfig +++ b/configs/nucleo-f072rb/nsh/defconfig @@ -48,8 +48,8 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0_PWR=y -CONFIG_STM32F0_USART2=y +CONFIG_STM32F0L0_PWR=y +CONFIG_STM32F0L0_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 diff --git a/configs/nucleo-f072rb/src/nucleo-f072rb.h b/configs/nucleo-f072rb/src/nucleo-f072rb.h index 04d7bc6ffcd..d02bc78767e 100644 --- a/configs/nucleo-f072rb/src/nucleo-f072rb.h +++ b/configs/nucleo-f072rb/src/nucleo-f072rb.h @@ -45,7 +45,7 @@ #include #include -#include "stm32f0_gpio.h" +#include "stm32_gpio.h" /**************************************************************************** * Pre-processor Definitions @@ -54,15 +54,15 @@ /* Configuration ************************************************************/ /* How many SPI modules does this chip support? */ -#if STM32F0_NSPI < 1 -# undef CONFIG_STM32F0_SPI1 -# undef CONFIG_STM32F0_SPI2 -# undef CONFIG_STM32F0_SPI3 -#elif STM32F0_NSPI < 2 -# undef CONFIG_STM32F0_SPI2 -# undef CONFIG_STM32F0_SPI3 -#elif STM32F0_NSPI < 3 -# undef CONFIG_STM32F0_SPI3 +#if STM32_NSPI < 1 +# undef CONFIG_STM32F0L0_SPI1 +# undef CONFIG_STM32F0L0_SPI2 +# undef CONFIG_STM32F0L0_SPI3 +#elif STM32_NSPI < 2 +# undef CONFIG_STM32F0L0_SPI2 +# undef CONFIG_STM32F0L0_SPI3 +#elif STM32_NSPI < 3 +# undef CONFIG_STM32F0L0_SPI3 #endif /* Nucleo-F072RB GPIOs ******************************************************/ diff --git a/configs/nucleo-f072rb/src/stm32_autoleds.c b/configs/nucleo-f072rb/src/stm32_autoleds.c index ee3779dec57..4c634714127 100644 --- a/configs/nucleo-f072rb/src/stm32_autoleds.c +++ b/configs/nucleo-f072rb/src/stm32_autoleds.c @@ -49,7 +49,7 @@ #include "chip.h" #include "up_arch.h" #include "up_internal.h" -#include "stm32f0_gpio.h" +#include "stm32_gpio.h" #include "nucleo-f072rb.h" #ifdef CONFIG_ARCH_LEDS @@ -66,7 +66,7 @@ void board_autoled_initialize(void) { /* Configure LD2 GPIO for output */ - stm32f0_configgpio(GPIO_LD2); + stm32_configgpio(GPIO_LD2); } /**************************************************************************** @@ -77,7 +77,7 @@ void board_autoled_on(int led) { if (led == 1) { - stm32f0_gpiowrite(GPIO_LD2, true); + stm32_gpiowrite(GPIO_LD2, true); } } @@ -89,7 +89,7 @@ void board_autoled_off(int led) { if (led == 1) { - stm32f0_gpiowrite(GPIO_LD2, false); + stm32_gpiowrite(GPIO_LD2, false); } } diff --git a/configs/nucleo-f072rb/src/stm32_boot.c b/configs/nucleo-f072rb/src/stm32_boot.c index 0655e5b0b63..8a4cab045b8 100644 --- a/configs/nucleo-f072rb/src/stm32_boot.c +++ b/configs/nucleo-f072rb/src/stm32_boot.c @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/nucleo-f072rb/src/stm32f0_boot.c + * configs/nucleo-f072rb/src/stm32f072rb_boot.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -53,16 +53,16 @@ ************************************************************************************/ /************************************************************************************ - * Name: stm32f0_boardinitialize + * Name: stm32_boardinitialize * * Description: * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured + * is called early in the initialization -- after all memory has been configured * and mapped but before any devices have been initialized. * ************************************************************************************/ -void stm32f0_boardinitialize(void) +void stm32_boardinitialize(void) { #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ diff --git a/configs/nucleo-f072rb/src/stm32_bringup.c b/configs/nucleo-f072rb/src/stm32_bringup.c index 255e65f9b97..430176b07cf 100644 --- a/configs/nucleo-f072rb/src/stm32_bringup.c +++ b/configs/nucleo-f072rb/src/stm32_bringup.c @@ -45,7 +45,7 @@ #include -#include "stm32f0_i2c.h" +#include "stm32_i2c.h" #include "nucleo-f072rb.h" /**************************************************************************** @@ -53,7 +53,7 @@ ****************************************************************************/ #undef HAVE_I2C_DRIVER -#if defined(CONFIG_STM32F0_I2C1) && defined(CONFIG_I2C_DRIVER) +#if defined(CONFIG_STM32F0L0_I2C1) && defined(CONFIG_I2C_DRIVER) # define HAVE_I2C_DRIVER 1 #endif @@ -95,7 +95,7 @@ int stm32_bringup(void) #ifdef HAVE_I2C_DRIVER /* Get the I2C lower half instance */ - i2c = stm32f0_i2cbus_initialize(1); + i2c = stm32_i2cbus_initialize(1); if (i2c == NULL) { i2cerr("ERROR: Inialize I2C1: %d\n", ret); diff --git a/configs/nucleo-f072rb/src/stm32_buttons.c b/configs/nucleo-f072rb/src/stm32_buttons.c index f8574e47b3d..f263beb2a39 100644 --- a/configs/nucleo-f072rb/src/stm32_buttons.c +++ b/configs/nucleo-f072rb/src/stm32_buttons.c @@ -47,7 +47,7 @@ #include #include -#include "stm32f0_gpio.h" +#include "stm32_gpio.h" #include "nucleo-f072rb.h" #ifdef CONFIG_ARCH_BUTTONS @@ -73,7 +73,7 @@ void board_button_initialize(void) * also configured for the pin. */ - stm32f0_configgpio(GPIO_BTN_USER); + stm32_configgpio(GPIO_BTN_USER); } /**************************************************************************** @@ -86,7 +86,7 @@ uint32_t board_buttons(void) * pressed. */ - bool released = stm32f0_gpioread(GPIO_BTN_USER); + bool released = stm32_gpioread(GPIO_BTN_USER); return !released; } @@ -119,7 +119,7 @@ int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) if (id == BUTTON_USER) { - ret = stm32f0_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg); + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg); } return ret; diff --git a/configs/nucleo-f072rb/src/stm32_userleds.c b/configs/nucleo-f072rb/src/stm32_userleds.c index 8febc96b467..8dc151c67d5 100644 --- a/configs/nucleo-f072rb/src/stm32_userleds.c +++ b/configs/nucleo-f072rb/src/stm32_userleds.c @@ -49,7 +49,7 @@ #include "chip.h" #include "up_arch.h" #include "up_internal.h" -#include "stm32f0_gpio.h" +#include "stm32_gpio.h" #include "nucleo-f072rb.h" #ifndef CONFIG_ARCH_LEDS @@ -172,7 +172,7 @@ void board_userled_initialize(void) { /* Configure LD2 GPIO for output */ - stm32f0_configgpio(GPIO_LD2); + stm32_configgpio(GPIO_LD2); } /**************************************************************************** @@ -183,7 +183,7 @@ void board_userled(int led, bool ledon) { if (led == BOARD_LD2) { - stm32f0_gpiowrite(GPIO_LD2, ledon); + stm32_gpiowrite(GPIO_LD2, ledon); } } @@ -193,15 +193,15 @@ void board_userled(int led, bool ledon) void board_userled_all(uint8_t ledset) { - stm32f0_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); + stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); } /**************************************************************************** - * Name: stm32f0_led_pminitialize + * Name: stm32_led_pminitialize ****************************************************************************/ #ifdef CONFIG_PM -void stm32f0_led_pminitialize(void) +void stm32_led_pminitialize(void) { /* Register to receive power management callbacks */ diff --git a/configs/nucleo-f091rc/include/board.h b/configs/nucleo-f091rc/include/board.h index be7e3f5a9e6..a3e796aca1c 100644 --- a/configs/nucleo-f091rc/include/board.h +++ b/configs/nucleo-f091rc/include/board.h @@ -72,14 +72,14 @@ * Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins. */ -#define STM32F0_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ +#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ -#define STM32F0_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */ -#define STM32F0_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */ -#define STM32F0_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */ -#define STM32F0_HSE_FREQUENCY STM32F0_BOARD_XTAL -#define STM32F0_LSI_FREQUENCY 40000 /* Approximately 40KHz */ -#define STM32F0_LSE_FREQUENCY 32768 /* X2 on board */ +#define STM32_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */ +#define STM32_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */ +#define STM32_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSI_FREQUENCY 40000 /* Approximately 40KHz */ +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ /* PLL Configuration * @@ -93,7 +93,7 @@ * If the USB interface is used in the application, it requires a precise * 48MHz clock which can be generated from either the (1) the internal * main PLL with the HSE clock source using an HSE crystal oscillator. In - * this case, the PLL VCO clock (defined by STM32F0_CFGR_PLLMUL) must be + * this case, the PLL VCO clock (defined by STM32_CFGR_PLLMUL) must be * programmed to output a 96 MHz frequency. This is required to provide a * 48MHz clock to the (USBCLK = PLLVCO/2). Or (2) by using the internal * 48MHz oscillator in automatic trimming mode. The synchronization for @@ -111,58 +111,58 @@ * PLL source). */ -#define STM32F0_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ -#define STM32F0_PLLSRC_FREQUENCY (STM32F0_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ -#ifdef CONFIG_STM32F0_USB -# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */ -# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ -# define STM32F0_PLL_FREQUENCY (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ +#define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ +#ifdef CONFIG_STM32F0L0_USB +# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ +# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ +# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ #else -# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */ -# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ -# define STM32F0_PLL_FREQUENCY (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ +# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ +# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ +# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ #endif /* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output - * frequency (STM32F0_PLL_FREQUENCY divided by the PLLDIV value). + * frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). */ -#define STM32F0_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ -#define STM32F0_SYSCLK_SWS RCC_CFGR_SWS_PLL -#ifdef CONFIG_STM32F0_USB -# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#ifdef CONFIG_STM32F0L0_USB +# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #else -# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ +# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #endif -#define STM32F0_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32F0_HCLK_FREQUENCY STM32F0_SYSCLK_FREQUENCY -#define STM32F0_BOARD_HCLK STM32F0_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY +#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* APB1 clock (PCLK1) is HCLK (48MHz) */ -#define STM32F0_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32F0_PCLK1_FREQUENCY (STM32F0_HCLK_FREQUENCY) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (48MHz) */ -#define STM32F0_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32F0_PCLK2_FREQUENCY STM32F0_HCLK_FREQUENCY -#define STM32F0_APB2_CLKIN (STM32F0_PCLK2_FREQUENCY) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */ -#define STM32F0_APB1_TIM1_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM2_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM3_CLKIN (STM32F0_PCLK1_FREQUENCY) +#define STM32_APB1_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM6_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM7_CLKIN (STM32F0_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM14_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM15_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM16_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM17_CLKIN (STM32F0_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) /* LED definitions ******************************************************************/ /* LEDs diff --git a/configs/nucleo-f091rc/nsh/defconfig b/configs/nucleo-f091rc/nsh/defconfig index d6658beecf0..883aedf86e1 100644 --- a/configs/nucleo-f091rc/nsh/defconfig +++ b/configs/nucleo-f091rc/nsh/defconfig @@ -51,8 +51,8 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0_PWR=y -CONFIG_STM32F0_USART2=y +CONFIG_STM32F0L0_PWR=y +CONFIG_STM32F0L0_USART2=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/configs/nucleo-f091rc/src/nucleo-f091rc.h b/configs/nucleo-f091rc/src/nucleo-f091rc.h index 4cd683af249..e59023f9e22 100644 --- a/configs/nucleo-f091rc/src/nucleo-f091rc.h +++ b/configs/nucleo-f091rc/src/nucleo-f091rc.h @@ -45,7 +45,7 @@ #include #include -#include "stm32f0_gpio.h" +#include "stm32_gpio.h" /**************************************************************************** * Pre-processor Definitions @@ -54,15 +54,15 @@ /* Configuration ************************************************************/ /* How many SPI modules does this chip support? */ -#if STM32F0_NSPI < 1 -# undef CONFIG_STM32F0_SPI1 -# undef CONFIG_STM32F0_SPI2 -# undef CONFIG_STM32F0_SPI3 -#elif STM32F0_NSPI < 2 -# undef CONFIG_STM32F0_SPI2 -# undef CONFIG_STM32F0_SPI3 -#elif STM32F0_NSPI < 3 -# undef CONFIG_STM32F0_SPI3 +#if STM32_NSPI < 1 +# undef CONFIG_STM32F0L0_SPI1 +# undef CONFIG_STM32F0L0_SPI2 +# undef CONFIG_STM32F0L0_SPI3 +#elif STM32_NSPI < 2 +# undef CONFIG_STM32F0L0_SPI2 +# undef CONFIG_STM32F0L0_SPI3 +#elif STM32_NSPI < 3 +# undef CONFIG_STM32F0L0_SPI3 #endif /* Nucleo-F091RC GPIOs ******************************************************/ diff --git a/configs/nucleo-f091rc/src/stm32_autoleds.c b/configs/nucleo-f091rc/src/stm32_autoleds.c index 1f093e4c8ef..3991bb9b088 100644 --- a/configs/nucleo-f091rc/src/stm32_autoleds.c +++ b/configs/nucleo-f091rc/src/stm32_autoleds.c @@ -49,7 +49,7 @@ #include "chip.h" #include "up_arch.h" #include "up_internal.h" -#include "stm32f0_gpio.h" +#include "stm32_gpio.h" #include "nucleo-f091rc.h" #ifdef CONFIG_ARCH_LEDS @@ -66,7 +66,7 @@ void board_autoled_initialize(void) { /* Configure LD2 GPIO for output */ - stm32f0_configgpio(GPIO_LD2); + stm32_configgpio(GPIO_LD2); } /**************************************************************************** @@ -77,7 +77,7 @@ void board_autoled_on(int led) { if (led == 1) { - stm32f0_gpiowrite(GPIO_LD2, true); + stm32_gpiowrite(GPIO_LD2, true); } } @@ -89,7 +89,7 @@ void board_autoled_off(int led) { if (led == 1) { - stm32f0_gpiowrite(GPIO_LD2, false); + stm32_gpiowrite(GPIO_LD2, false); } } diff --git a/configs/nucleo-f091rc/src/stm32_boot.c b/configs/nucleo-f091rc/src/stm32_boot.c index 5e50fcabba7..b1f7cb91519 100644 --- a/configs/nucleo-f091rc/src/stm32_boot.c +++ b/configs/nucleo-f091rc/src/stm32_boot.c @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/nucleo-f091rc/src/stm32f0_boot.c + * configs/nucleo-f091rc/src/stm32_boot.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -53,7 +53,7 @@ ************************************************************************************/ /************************************************************************************ - * Name: stm32f0_boardinitialize + * Name: stm32_boardinitialize * * Description: * All STM32 architectures must provide the following entry point. This entry point @@ -62,7 +62,7 @@ * ************************************************************************************/ -void stm32f0_boardinitialize(void) +void stm32_boardinitialize(void) { #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ diff --git a/configs/nucleo-f091rc/src/stm32_buttons.c b/configs/nucleo-f091rc/src/stm32_buttons.c index 53ada3736b0..872e7935565 100644 --- a/configs/nucleo-f091rc/src/stm32_buttons.c +++ b/configs/nucleo-f091rc/src/stm32_buttons.c @@ -47,7 +47,7 @@ #include #include -#include "stm32f0_gpio.h" +#include "stm32_gpio.h" #include "nucleo-f091rc.h" #ifdef CONFIG_ARCH_BUTTONS @@ -73,7 +73,7 @@ void board_button_initialize(void) * also configured for the pin. */ - stm32f0_configgpio(GPIO_BTN_USER); + stm32_configgpio(GPIO_BTN_USER); } /**************************************************************************** @@ -86,7 +86,7 @@ uint32_t board_buttons(void) * pressed. */ - bool released = stm32f0_gpioread(GPIO_BTN_USER); + bool released = stm32_gpioread(GPIO_BTN_USER); return !released; } @@ -119,7 +119,7 @@ int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) if (id == BUTTON_USER) { - ret = stm32f0_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg); + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg); } return ret; diff --git a/configs/nucleo-f091rc/src/stm32_userleds.c b/configs/nucleo-f091rc/src/stm32_userleds.c index f62e84a30e4..7e581fd962d 100644 --- a/configs/nucleo-f091rc/src/stm32_userleds.c +++ b/configs/nucleo-f091rc/src/stm32_userleds.c @@ -49,7 +49,7 @@ #include "chip.h" #include "up_arch.h" #include "up_internal.h" -#include "stm32f0_gpio.h" +#include "stm32_gpio.h" #include "nucleo-f091rc.h" #ifndef CONFIG_ARCH_LEDS @@ -172,7 +172,7 @@ void board_userled_initialize(void) { /* Configure LD2 GPIO for output */ - stm32f0_configgpio(GPIO_LD2); + stm32_configgpio(GPIO_LD2); } /**************************************************************************** @@ -183,7 +183,7 @@ void board_userled(int led, bool ledon) { if (led == BOARD_LD2) { - stm32f0_gpiowrite(GPIO_LD2, ledon); + stm32_gpiowrite(GPIO_LD2, ledon); } } @@ -193,15 +193,15 @@ void board_userled(int led, bool ledon) void board_userled_all(uint8_t ledset) { - stm32f0_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); + stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); } /**************************************************************************** - * Name: stm32f0_led_pminitialize + * Name: stm32_led_pminitialize ****************************************************************************/ #ifdef CONFIG_PM -void stm32f0_led_pminitialize(void) +void stm32_led_pminitialize(void) { /* Register to receive power management callbacks */ diff --git a/configs/stm32f051-discovery/include/board.h b/configs/stm32f051-discovery/include/board.h index 412a3e72993..7db6f4b8a0a 100644 --- a/configs/stm32f051-discovery/include/board.h +++ b/configs/stm32f051-discovery/include/board.h @@ -72,14 +72,14 @@ * Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins. */ -#define STM32F0_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ +#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ -#define STM32F0_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */ -#define STM32F0_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */ -#define STM32F0_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */ -#define STM32F0_HSE_FREQUENCY STM32F0_BOARD_XTAL -#define STM32F0_LSI_FREQUENCY 40000 /* Approximately 40KHz */ -#define STM32F0_LSE_FREQUENCY 32768 /* X2 on board */ +#define STM32_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */ +#define STM32_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */ +#define STM32_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSI_FREQUENCY 40000 /* Approximately 40KHz */ +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ /* PLL Configuration * @@ -93,7 +93,7 @@ * If the USB interface is used in the application, it requires a precise * 48MHz clock which can be generated from either the (1) the internal * main PLL with the HSE clock source using an HSE crystal oscillator. In - * this case, the PLL VCO clock (defined by STM32F0_CFGR_PLLMUL) must be + * this case, the PLL VCO clock (defined by STM32_CFGR_PLLMUL) must be * programmed to output a 96 MHz frequency. This is required to provide a * 48MHz clock to the (USBCLK = PLLVCO/2). Or (2) by using the internal * 48MHz oscillator in automatic trimming mode. The synchronization for @@ -111,58 +111,58 @@ * PLL source). */ -#define STM32F0_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ -#define STM32F0_PLLSRC_FREQUENCY (STM32F0_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ -#ifdef CONFIG_STM32F0_USB -# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */ -# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ -# define STM32F0_PLL_FREQUENCY (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ +#define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ +#ifdef CONFIG_STM32F0L0_USB +# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ +# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ +# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ #else -# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */ -# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ -# define STM32F0_PLL_FREQUENCY (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ +# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ +# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ +# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ #endif /* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output - * frequency (STM32F0_PLL_FREQUENCY divided by the PLLDIV value). + * frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). */ -#define STM32F0_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ -#define STM32F0_SYSCLK_SWS RCC_CFGR_SWS_PLL -#ifdef CONFIG_STM32F0_USB -# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#ifdef CONFIG_STM32F0L0_USB +# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #else -# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ +# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #endif -#define STM32F0_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32F0_HCLK_FREQUENCY STM32F0_SYSCLK_FREQUENCY -#define STM32F0_BOARD_HCLK STM32F0_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY +#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* APB1 clock (PCLK1) is HCLK (48MHz) */ -#define STM32F0_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32F0_PCLK1_FREQUENCY (STM32F0_HCLK_FREQUENCY) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (48MHz) */ -#define STM32F0_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32F0_PCLK2_FREQUENCY STM32F0_HCLK_FREQUENCY -#define STM32F0_APB2_CLKIN (STM32F0_PCLK2_FREQUENCY) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */ -#define STM32F0_APB1_TIM1_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM2_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM3_CLKIN (STM32F0_PCLK1_FREQUENCY) +#define STM32_APB1_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM6_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM7_CLKIN (STM32F0_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM14_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM15_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM16_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM17_CLKIN (STM32F0_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) /* LED definitions ******************************************************************/ /* The STM32F0-Discovery board has four LEDs. Two of these are controlled by diff --git a/configs/stm32f051-discovery/nsh/defconfig b/configs/stm32f051-discovery/nsh/defconfig index f22ddc03ed9..106e404442f 100644 --- a/configs/stm32f051-discovery/nsh/defconfig +++ b/configs/stm32f051-discovery/nsh/defconfig @@ -44,8 +44,8 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0_PWR=y -CONFIG_STM32F0_USART1=y +CONFIG_STM32F0L0_PWR=y +CONFIG_STM32F0L0_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 diff --git a/configs/stm32f051-discovery/src/Makefile b/configs/stm32f051-discovery/src/Makefile index 24959f597f8..564a6e714fc 100644 --- a/configs/stm32f051-discovery/src/Makefile +++ b/configs/stm32f051-discovery/src/Makefile @@ -49,7 +49,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32F0_SPI),y) +ifeq ($(CONFIG_STM32F0L0_SPI),y) CSRCS += stm32_spi.c endif diff --git a/configs/stm32f051-discovery/src/stm32_autoleds.c b/configs/stm32f051-discovery/src/stm32_autoleds.c index 529dee5978a..c5ff698305b 100644 --- a/configs/stm32f051-discovery/src/stm32_autoleds.c +++ b/configs/stm32f051-discovery/src/stm32_autoleds.c @@ -86,8 +86,8 @@ void board_autoled_initialize(void) { /* Configure LED1-2 GPIOs for output */ - stm32f0_configgpio(GPIO_LED1); - stm32f0_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); } /**************************************************************************** @@ -117,8 +117,8 @@ void board_autoled_on(int led) break; } - stm32f0_gpiowrite(GPIO_LED1, led1on); - stm32f0_gpiowrite(GPIO_LED2, led2on); + stm32_gpiowrite(GPIO_LED1, led1on); + stm32_gpiowrite(GPIO_LED2, led2on); } /**************************************************************************** @@ -129,8 +129,8 @@ void board_autoled_off(int led) { if (led != 2) { - stm32f0_gpiowrite(GPIO_LED1, false); - stm32f0_gpiowrite(GPIO_LED2, false); + stm32_gpiowrite(GPIO_LED1, false); + stm32_gpiowrite(GPIO_LED2, false); } } diff --git a/configs/stm32f051-discovery/src/stm32_boot.c b/configs/stm32f051-discovery/src/stm32_boot.c index 8fac2ab07c3..04e2595624b 100644 --- a/configs/stm32f051-discovery/src/stm32_boot.c +++ b/configs/stm32f051-discovery/src/stm32_boot.c @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/stm32f051-discovery/src/stm32f0_boot.c + * configs/stm32f051-discovery/src/stm32_boot.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -53,7 +53,7 @@ ************************************************************************************/ /************************************************************************************ - * Name: stm32f0_boardinitialize + * Name: stm32_boardinitialize * * Description: * All STM32 architectures must provide the following entry point. This entry point @@ -62,7 +62,7 @@ * ************************************************************************************/ -void stm32f0_boardinitialize(void) +void stm32_boardinitialize(void) { #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ diff --git a/configs/stm32f051-discovery/src/stm32f051-discovery.h b/configs/stm32f051-discovery/src/stm32f051-discovery.h index ab5de942532..3c873d8e9d6 100644 --- a/configs/stm32f051-discovery/src/stm32f051-discovery.h +++ b/configs/stm32f051-discovery/src/stm32f051-discovery.h @@ -45,7 +45,7 @@ #include #include -#include "stm32f0_gpio.h" +#include "stm32_gpio.h" /**************************************************************************************************** * Pre-processor Definitions @@ -54,15 +54,15 @@ /* Configuration ************************************************************************************/ /* How many SPI modules does this chip support? */ -#if STM32F0_NSPI < 1 -# undef CONFIG_STM32F0_SPI1 -# undef CONFIG_STM32F0_SPI2 -# undef CONFIG_STM32F0_SPI3 -#elif STM32F0_NSPI < 2 -# undef CONFIG_STM32F0_SPI2 -# undef CONFIG_STM32F0_SPI3 -#elif STM32F0_NSPI < 3 -# undef CONFIG_STM32F0_SPI3 +#if STM32_NSPI < 1 +# undef CONFIG_STM32F0L0_SPI1 +# undef CONFIG_STM32F0L0_SPI2 +# undef CONFIG_STM32F0L0_SPI3 +#elif STM32_NSPI < 2 +# undef CONFIG_STM32F0L0_SPI2 +# undef CONFIG_STM32F0L0_SPI3 +#elif STM32_NSPI < 3 +# undef CONFIG_STM32F0L0_SPI3 #endif /* STM32F0Discovery GPIOs ***************************************************************************/ diff --git a/configs/stm32f072-discovery/include/board.h b/configs/stm32f072-discovery/include/board.h index 93c266dcf60..ad5032af40d 100644 --- a/configs/stm32f072-discovery/include/board.h +++ b/configs/stm32f072-discovery/include/board.h @@ -72,14 +72,14 @@ * Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins. */ -#define STM32F0_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ +#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ -#define STM32F0_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */ -#define STM32F0_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */ -#define STM32F0_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */ -#define STM32F0_HSE_FREQUENCY STM32F0_BOARD_XTAL -#define STM32F0_LSI_FREQUENCY 40000 /* Approximately 40KHz */ -#define STM32F0_LSE_FREQUENCY 32768 /* X2 on board */ +#define STM32_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */ +#define STM32_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */ +#define STM32_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSI_FREQUENCY 40000 /* Approximately 40KHz */ +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ /* PLL Configuration * @@ -93,7 +93,7 @@ * If the USB interface is used in the application, it requires a precise * 48MHz clock which can be generated from either the (1) the internal * main PLL with the HSE clock source using an HSE crystal oscillator. In - * this case, the PLL VCO clock (defined by STM32F0_CFGR_PLLMUL) must be + * this case, the PLL VCO clock (defined by STM32_CFGR_PLLMUL) must be * programmed to output a 96 MHz frequency. This is required to provide a * 48MHz clock to the (USBCLK = PLLVCO/2). Or (2) by using the internal * 48MHz oscillator in automatic trimming mode. The synchronization for @@ -111,58 +111,58 @@ * PLL source). */ -#define STM32F0_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ -#define STM32F0_PLLSRC_FREQUENCY (STM32F0_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ -#ifdef CONFIG_STM32F0_USB -# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */ -# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ -# define STM32F0_PLL_FREQUENCY (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ +#define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ +#ifdef CONFIG_STM32F0L0_USB +# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ +# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ +# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ #else -# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */ -# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ -# define STM32F0_PLL_FREQUENCY (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ +# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ +# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ +# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ #endif /* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output - * frequency (STM32F0_PLL_FREQUENCY divided by the PLLDIV value). + * frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). */ -#define STM32F0_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ -#define STM32F0_SYSCLK_SWS RCC_CFGR_SWS_PLL -#ifdef CONFIG_STM32F0_USB -# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#ifdef CONFIG_STM32F0L0_USB +# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #else -# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ +# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #endif -#define STM32F0_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32F0_HCLK_FREQUENCY STM32F0_SYSCLK_FREQUENCY -#define STM32F0_BOARD_HCLK STM32F0_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY +#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* APB1 clock (PCLK1) is HCLK (48MHz) */ -#define STM32F0_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32F0_PCLK1_FREQUENCY (STM32F0_HCLK_FREQUENCY) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (48MHz) */ -#define STM32F0_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32F0_PCLK2_FREQUENCY STM32F0_HCLK_FREQUENCY -#define STM32F0_APB2_CLKIN (STM32F0_PCLK2_FREQUENCY) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */ -#define STM32F0_APB1_TIM1_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM2_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM3_CLKIN (STM32F0_PCLK1_FREQUENCY) +#define STM32_APB1_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM6_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM7_CLKIN (STM32F0_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM14_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM15_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM16_CLKIN (STM32F0_PCLK1_FREQUENCY) -#define STM32F0_APB1_TIM17_CLKIN (STM32F0_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) /* LED definitions ******************************************************************/ /* The STM32F0-Discovery board has four LEDs. Two of these are controlled by diff --git a/configs/stm32f072-discovery/nsh/defconfig b/configs/stm32f072-discovery/nsh/defconfig index 5f5991a0ac6..d797f2690e6 100644 --- a/configs/stm32f072-discovery/nsh/defconfig +++ b/configs/stm32f072-discovery/nsh/defconfig @@ -44,8 +44,8 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0_PWR=y -CONFIG_STM32F0_USART1=y +CONFIG_STM32F0L0_PWR=y +CONFIG_STM32F0L0_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 diff --git a/configs/stm32f072-discovery/src/Makefile b/configs/stm32f072-discovery/src/Makefile index b40311548d3..e6bb4efaf24 100644 --- a/configs/stm32f072-discovery/src/Makefile +++ b/configs/stm32f072-discovery/src/Makefile @@ -49,7 +49,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32F0_SPI),y) +ifeq ($(CONFIG_STM32F0L0_SPI),y) CSRCS += stm32_spi.c endif diff --git a/configs/stm32f072-discovery/src/stm32_autoleds.c b/configs/stm32f072-discovery/src/stm32_autoleds.c index 528d0d5f796..ed938400d82 100644 --- a/configs/stm32f072-discovery/src/stm32_autoleds.c +++ b/configs/stm32f072-discovery/src/stm32_autoleds.c @@ -86,8 +86,8 @@ void board_autoled_initialize(void) { /* Configure LED1-2 GPIOs for output */ - stm32f0_configgpio(GPIO_LED1); - stm32f0_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); } /**************************************************************************** @@ -117,8 +117,8 @@ void board_autoled_on(int led) break; } - stm32f0_gpiowrite(GPIO_LED1, led1on); - stm32f0_gpiowrite(GPIO_LED2, led2on); + stm32_gpiowrite(GPIO_LED1, led1on); + stm32_gpiowrite(GPIO_LED2, led2on); } /**************************************************************************** @@ -129,8 +129,8 @@ void board_autoled_off(int led) { if (led != 2) { - stm32f0_gpiowrite(GPIO_LED1, false); - stm32f0_gpiowrite(GPIO_LED2, false); + stm32_gpiowrite(GPIO_LED1, false); + stm32_gpiowrite(GPIO_LED2, false); } } diff --git a/configs/stm32f072-discovery/src/stm32_boot.c b/configs/stm32f072-discovery/src/stm32_boot.c index 4d789466fb7..7f981b56dac 100644 --- a/configs/stm32f072-discovery/src/stm32_boot.c +++ b/configs/stm32f072-discovery/src/stm32_boot.c @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/stm32f072-discovery/src/stm32f0_boot.c + * configs/stm32f072-discovery/src/stm32f072_boot.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -53,7 +53,7 @@ ************************************************************************************/ /************************************************************************************ - * Name: stm32f0_boardinitialize + * Name: stm32_boardinitialize * * Description: * All STM32 architectures must provide the following entry point. This entry point @@ -62,7 +62,7 @@ * ************************************************************************************/ -void stm32f0_boardinitialize(void) +void stm32_boardinitialize(void) { #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ diff --git a/configs/stm32f072-discovery/src/stm32f072-discovery.h b/configs/stm32f072-discovery/src/stm32f072-discovery.h index 22893559b73..8f496094e73 100644 --- a/configs/stm32f072-discovery/src/stm32f072-discovery.h +++ b/configs/stm32f072-discovery/src/stm32f072-discovery.h @@ -45,7 +45,7 @@ #include #include -#include "stm32f0_gpio.h" +#include "stm32_gpio.h" /**************************************************************************************************** * Pre-processor Definitions @@ -54,15 +54,15 @@ /* Configuration ************************************************************************************/ /* How many SPI modules does this chip support? */ -#if STM32F0_NSPI < 1 -# undef CONFIG_STM32F0_SPI1 -# undef CONFIG_STM32F0_SPI2 -# undef CONFIG_STM32F0_SPI3 -#elif STM32F0_NSPI < 2 -# undef CONFIG_STM32F0_SPI2 -# undef CONFIG_STM32F0_SPI3 -#elif STM32F0_NSPI < 3 -# undef CONFIG_STM32F0_SPI3 +#if STM32_NSPI < 1 +# undef CONFIG_STM32F0L0_SPI1 +# undef CONFIG_STM32F0L0_SPI2 +# undef CONFIG_STM32F0L0_SPI3 +#elif STM32_NSPI < 2 +# undef CONFIG_STM32F0L0_SPI2 +# undef CONFIG_STM32F0L0_SPI3 +#elif STM32_NSPI < 3 +# undef CONFIG_STM32F0L0_SPI3 #endif /* STM32F0Discovery GPIOs ***************************************************************************/