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arch/arm/rtl8721f: bring up minimal NSH (P1)
Wire the RTL8721F km4tz core up to a working NuttShell: - irq.h: renumber the KM4TZ external vector table to the RTL8721F APIRQn map (UART_LOG=24, IPC=5, +GPIOB/C, TIMER7/8, ...). - ameba_loguart.c: fix the LOG-UART base to 0x40810000. The former 0x401C6000 belongs to a different Ameba part; the wrong base bus- faulted on the RX interrupt-enable write while TX still worked (LOGUART_PutChar uses its own ROM-internal base). - ameba_app_start.c: adjust the MPU read-only / RAM regions for the RTL8721F memory map and seed the RTC on first power-on so the SDM32K-clocked SYSTIMER comes up (mirrors the SDK app_rtc_init). - ameba_ipc.c: move the km4tz<->km4ns IPC to APIRQn 5 (IPC_CPU0). - ameba_board.mk: pull in fwlib ameba_rtc.c for the RTC_* symbols. - defconfig: RTL8721F RAM map, enable TIMER/TIMER_ARCH/ARMV8M_SYSTICK for a live system tick, and drop the WiFi/NET stack for now. - scripts/Make.defs: use the RTL8721F_NOR flash profile. Boots cleanly to nsh> on hardware; tick, RX and builtin apps verified. Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
This commit is contained in:
dechao_gong
Xiang Xiao
parent
d584142cf4
commit
a85db6d28f
8 changed files with 155 additions and 121 deletions
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@ -55,73 +55,96 @@
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#define RTL8721F_IRQ_FIRST (16) /* Vector number of the first external
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* interrupt */
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/* External interrupts (vectors >= 16). These map to the RTL8721F km4tz
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* (AP / host) peripheral interrupt vector numbers (APIRQn, 0..57) as defined
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* by the SDK's component/soc/RTL8721F/fwlib/include/ameba_vector_table.h
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* (CONFIG_ARM_CORE_CM4_KM4TZ branch).
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/* External interrupts (vectors >= 16). These map to the amebagreen2 km4tz
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* (AP / host) peripheral interrupt vector numbers (APIRQn, 0..78) as defined
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* by the SDK's
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* component/soc/amebagreen2/fwlib/include/ameba_vector_table.h
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* (CONFIG_ARM_CORE_CM4_KM4TZ branch). NOTE: this numbering differs from the
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* RTL8721Dx / RTL8720F -- e.g. UART_LOG is 24 (not 17) and IPC is 5 (not 3).
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*/
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#define RTL8721F_IRQ_WIFI_FISR_FESR (RTL8721F_IRQ_FIRST + 0)
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#define RTL8721F_IRQ_WL_PROTOCOL (RTL8721F_IRQ_FIRST + 1)
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#define RTL8721F_IRQ_AP_WAKE (RTL8721F_IRQ_FIRST + 2)
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#define RTL8721F_IRQ_IPC_KM4 (RTL8721F_IRQ_FIRST + 3) /* IPC_KM4TZ */
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#define RTL8721F_IRQ_IWDG (RTL8721F_IRQ_FIRST + 4)
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#define RTL8721F_IRQ_TIMER0 (RTL8721F_IRQ_FIRST + 5)
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#define RTL8721F_IRQ_TIMER1 (RTL8721F_IRQ_FIRST + 6)
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#define RTL8721F_IRQ_TIMER2 (RTL8721F_IRQ_FIRST + 7)
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#define RTL8721F_IRQ_TIMER3 (RTL8721F_IRQ_FIRST + 8)
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#define RTL8721F_IRQ_TIMER4 (RTL8721F_IRQ_FIRST + 9)
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#define RTL8721F_IRQ_TIMER5 (RTL8721F_IRQ_FIRST + 10)
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#define RTL8721F_IRQ_TIMER6 (RTL8721F_IRQ_FIRST + 11)
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#define RTL8721F_IRQ_PMC_TIMER0 (RTL8721F_IRQ_FIRST + 12)
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#define RTL8721F_IRQ_PMC_TIMER1 (RTL8721F_IRQ_FIRST + 13)
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#define RTL8721F_IRQ_UART0 (RTL8721F_IRQ_FIRST + 14)
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#define RTL8721F_IRQ_UART1 (RTL8721F_IRQ_FIRST + 15)
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#define RTL8721F_IRQ_UART2 (RTL8721F_IRQ_FIRST + 16)
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#define RTL8721F_IRQ_UART_LOG (RTL8721F_IRQ_FIRST + 17)
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#define RTL8721F_IRQ_GPIOA (RTL8721F_IRQ_FIRST + 18)
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#define RTL8721F_IRQ_RSVD (RTL8721F_IRQ_FIRST + 19)
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#define RTL8721F_IRQ_I2C0 (RTL8721F_IRQ_FIRST + 20)
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#define RTL8721F_IRQ_I2C1 (RTL8721F_IRQ_FIRST + 21)
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#define RTL8721F_IRQ_GDMA0_CH0 (RTL8721F_IRQ_FIRST + 22)
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#define RTL8721F_IRQ_GDMA0_CH1 (RTL8721F_IRQ_FIRST + 23)
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#define RTL8721F_IRQ_GDMA0_CH2 (RTL8721F_IRQ_FIRST + 24)
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#define RTL8721F_IRQ_GDMA0_CH3 (RTL8721F_IRQ_FIRST + 25)
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#define RTL8721F_IRQ_GDMA0_CH4 (RTL8721F_IRQ_FIRST + 26)
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#define RTL8721F_IRQ_GDMA0_CH5 (RTL8721F_IRQ_FIRST + 27)
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#define RTL8721F_IRQ_GDMA0_CH6 (RTL8721F_IRQ_FIRST + 28)
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#define RTL8721F_IRQ_GDMA0_CH7 (RTL8721F_IRQ_FIRST + 29)
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#define RTL8721F_IRQ_SPI0 (RTL8721F_IRQ_FIRST + 30)
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#define RTL8721F_IRQ_SPI1 (RTL8721F_IRQ_FIRST + 31)
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#define RTL8721F_IRQ_SPORT (RTL8721F_IRQ_FIRST + 32)
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#define RTL8721F_IRQ_RTC (RTL8721F_IRQ_FIRST + 33)
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#define RTL8721F_IRQ_ADC (RTL8721F_IRQ_FIRST + 34)
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#define RTL8721F_IRQ_BOR (RTL8721F_IRQ_FIRST + 35)
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#define RTL8721F_IRQ_PWR_DOWN (RTL8721F_IRQ_FIRST + 36)
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#define RTL8721F_IRQ_PKE (RTL8721F_IRQ_FIRST + 37)
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#define RTL8721F_IRQ_TRNG (RTL8721F_IRQ_FIRST + 38)
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#define RTL8721F_IRQ_AON_TIM (RTL8721F_IRQ_FIRST + 39)
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#define RTL8721F_IRQ_AON_WAKEPIN (RTL8721F_IRQ_FIRST + 40)
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#define RTL8721F_IRQ_SDIO_WIFI (RTL8721F_IRQ_FIRST + 41)
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#define RTL8721F_IRQ_SDIO_BT (RTL8721F_IRQ_FIRST + 42)
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#define RTL8721F_IRQ_RXI300 (RTL8721F_IRQ_FIRST + 43)
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#define RTL8721F_IRQ_PSRAMC (RTL8721F_IRQ_FIRST + 44)
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#define RTL8721F_IRQ_SPI_FLASH (RTL8721F_IRQ_FIRST + 45)
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#define RTL8721F_IRQ_RSIP (RTL8721F_IRQ_FIRST + 46)
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#define RTL8721F_IRQ_AES (RTL8721F_IRQ_FIRST + 47)
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#define RTL8721F_IRQ_SHA (RTL8721F_IRQ_FIRST + 48)
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#define RTL8721F_IRQ_AES_S (RTL8721F_IRQ_FIRST + 49)
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#define RTL8721F_IRQ_SHA_S (RTL8721F_IRQ_FIRST + 50)
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#define RTL8721F_IRQ_KM4NS_WDG_RST (RTL8721F_IRQ_FIRST + 51)
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#define RTL8721F_IRQ_KM4TZ_NS_WDG (RTL8721F_IRQ_FIRST + 52)
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#define RTL8721F_IRQ_KM4TZ_S_WDG (RTL8721F_IRQ_FIRST + 53)
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#define RTL8721F_IRQ_OCP (RTL8721F_IRQ_FIRST + 54)
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#define RTL8721F_IRQ_BT_CTRL_HIGH (RTL8721F_IRQ_FIRST + 55)
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#define RTL8721F_IRQ_BT_CTRL_LOW (RTL8721F_IRQ_FIRST + 56)
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#define RTL8721F_IRQ_IR (RTL8721F_IRQ_FIRST + 57)
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#define RTL8721F_IRQ_WIFI_FTSR_MBOX (RTL8721F_IRQ_FIRST + 1)
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#define RTL8721F_IRQ_WL_DMA (RTL8721F_IRQ_FIRST + 2)
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#define RTL8721F_IRQ_WL_PROTOCOL (RTL8721F_IRQ_FIRST + 3)
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#define RTL8721F_IRQ_AP_WAKE (RTL8721F_IRQ_FIRST + 4)
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#define RTL8721F_IRQ_IPC_KM4 (RTL8721F_IRQ_FIRST + 5) /* IPC_CPU0 */
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#define RTL8721F_IRQ_IWDG (RTL8721F_IRQ_FIRST + 6)
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#define RTL8721F_IRQ_TIMER0 (RTL8721F_IRQ_FIRST + 7)
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#define RTL8721F_IRQ_TIMER1 (RTL8721F_IRQ_FIRST + 8)
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#define RTL8721F_IRQ_TIMER2 (RTL8721F_IRQ_FIRST + 9)
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#define RTL8721F_IRQ_TIMER3 (RTL8721F_IRQ_FIRST + 10)
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#define RTL8721F_IRQ_TIMER4 (RTL8721F_IRQ_FIRST + 11)
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#define RTL8721F_IRQ_TIMER5 (RTL8721F_IRQ_FIRST + 12)
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#define RTL8721F_IRQ_TIMER6 (RTL8721F_IRQ_FIRST + 13)
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#define RTL8721F_IRQ_TIMER7 (RTL8721F_IRQ_FIRST + 14)
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#define RTL8721F_IRQ_TIMER8 (RTL8721F_IRQ_FIRST + 15)
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#define RTL8721F_IRQ_COEX_MAILBOX (RTL8721F_IRQ_FIRST + 16)
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#define RTL8721F_IRQ_RSVD (RTL8721F_IRQ_FIRST + 17)
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#define RTL8721F_IRQ_PMC_TIMER0 (RTL8721F_IRQ_FIRST + 18)
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#define RTL8721F_IRQ_PMC_TIMER1 (RTL8721F_IRQ_FIRST + 19)
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#define RTL8721F_IRQ_UART0 (RTL8721F_IRQ_FIRST + 20)
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#define RTL8721F_IRQ_UART1 (RTL8721F_IRQ_FIRST + 21)
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#define RTL8721F_IRQ_UART2 (RTL8721F_IRQ_FIRST + 22)
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#define RTL8721F_IRQ_UART3 (RTL8721F_IRQ_FIRST + 23)
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#define RTL8721F_IRQ_UART_LOG (RTL8721F_IRQ_FIRST + 24)
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#define RTL8721F_IRQ_GPIOA (RTL8721F_IRQ_FIRST + 25)
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#define RTL8721F_IRQ_GPIOB (RTL8721F_IRQ_FIRST + 26)
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#define RTL8721F_IRQ_GPIOC (RTL8721F_IRQ_FIRST + 27)
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#define RTL8721F_IRQ_I2C0 (RTL8721F_IRQ_FIRST + 28)
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#define RTL8721F_IRQ_I2C1 (RTL8721F_IRQ_FIRST + 29)
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#define RTL8721F_IRQ_GDMA0_CH0 (RTL8721F_IRQ_FIRST + 30)
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#define RTL8721F_IRQ_GDMA0_CH1 (RTL8721F_IRQ_FIRST + 31)
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#define RTL8721F_IRQ_GDMA0_CH2 (RTL8721F_IRQ_FIRST + 32)
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#define RTL8721F_IRQ_GDMA0_CH3 (RTL8721F_IRQ_FIRST + 33)
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#define RTL8721F_IRQ_GDMA0_CH4 (RTL8721F_IRQ_FIRST + 34)
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#define RTL8721F_IRQ_GDMA0_CH5 (RTL8721F_IRQ_FIRST + 35)
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#define RTL8721F_IRQ_GDMA0_CH6 (RTL8721F_IRQ_FIRST + 36)
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#define RTL8721F_IRQ_GDMA0_CH7 (RTL8721F_IRQ_FIRST + 37)
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#define RTL8721F_IRQ_SPI0 (RTL8721F_IRQ_FIRST + 38)
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#define RTL8721F_IRQ_SPI1 (RTL8721F_IRQ_FIRST + 39)
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#define RTL8721F_IRQ_SPORT0 (RTL8721F_IRQ_FIRST + 40)
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#define RTL8721F_IRQ_RTC (RTL8721F_IRQ_FIRST + 41)
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#define RTL8721F_IRQ_ADC (RTL8721F_IRQ_FIRST + 42)
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#define RTL8721F_IRQ_ADC_COMP (RTL8721F_IRQ_FIRST + 43)
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#define RTL8721F_IRQ_CAPTOUCH (RTL8721F_IRQ_FIRST + 44)
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#define RTL8721F_IRQ_THERMAL (RTL8721F_IRQ_FIRST + 45)
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#define RTL8721F_IRQ_BOR (RTL8721F_IRQ_FIRST + 46)
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#define RTL8721F_IRQ_PWR_DOWN (RTL8721F_IRQ_FIRST + 47)
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#define RTL8721F_IRQ_RMII (RTL8721F_IRQ_FIRST + 48)
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#define RTL8721F_IRQ_LCDC (RTL8721F_IRQ_FIRST + 49)
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#define RTL8721F_IRQ_MJPEG (RTL8721F_IRQ_FIRST + 50)
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#define RTL8721F_IRQ_PPE (RTL8721F_IRQ_FIRST + 51)
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#define RTL8721F_IRQ_PKE (RTL8721F_IRQ_FIRST + 52)
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#define RTL8721F_IRQ_TRNG (RTL8721F_IRQ_FIRST + 53)
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#define RTL8721F_IRQ_AON_TIM (RTL8721F_IRQ_FIRST + 54)
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#define RTL8721F_IRQ_AON_WAKEPIN (RTL8721F_IRQ_FIRST + 55)
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#define RTL8721F_IRQ_SDIO_WIFI (RTL8721F_IRQ_FIRST + 56)
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#define RTL8721F_IRQ_SDIO_BT (RTL8721F_IRQ_FIRST + 57)
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#define RTL8721F_IRQ_SDIO_HOST (RTL8721F_IRQ_FIRST + 58)
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#define RTL8721F_IRQ_USB (RTL8721F_IRQ_FIRST + 59)
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#define RTL8721F_IRQ_CAN0 (RTL8721F_IRQ_FIRST + 60)
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#define RTL8721F_IRQ_CAN1 (RTL8721F_IRQ_FIRST + 61)
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#define RTL8721F_IRQ_IR (RTL8721F_IRQ_FIRST + 62)
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#define RTL8721F_IRQ_RXI300 (RTL8721F_IRQ_FIRST + 63)
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#define RTL8721F_IRQ_PSRAMC (RTL8721F_IRQ_FIRST + 64)
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#define RTL8721F_IRQ_SPI_FLASH (RTL8721F_IRQ_FIRST + 65)
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#define RTL8721F_IRQ_RSIP (RTL8721F_IRQ_FIRST + 66)
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#define RTL8721F_IRQ_AES (RTL8721F_IRQ_FIRST + 67)
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#define RTL8721F_IRQ_SHA (RTL8721F_IRQ_FIRST + 68)
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#define RTL8721F_IRQ_CPU0_NS_WDG (RTL8721F_IRQ_FIRST + 69)
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#define RTL8721F_IRQ_CPU0_S_WDG (RTL8721F_IRQ_FIRST + 70)
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#define RTL8721F_IRQ_OCP (RTL8721F_IRQ_FIRST + 71)
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#define RTL8721F_IRQ_SPIC_ECC (RTL8721F_IRQ_FIRST + 72)
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#define RTL8721F_IRQ_UVC_DEC (RTL8721F_IRQ_FIRST + 73)
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#define RTL8721F_IRQ_RTC_DET (RTL8721F_IRQ_FIRST + 74)
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#define RTL8721F_IRQ_BT_MAILBOX (RTL8721F_IRQ_FIRST + 75)
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#define RTL8721F_IRQ_BT_SCB (RTL8721F_IRQ_FIRST + 76)
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#define RTL8721F_IRQ_BT_WAKE_HOST (RTL8721F_IRQ_FIRST + 77)
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#define RTL8721F_IRQ_CPU1_WDG_RST (RTL8721F_IRQ_FIRST + 78)
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#define RTL8721F_IRQ_NEXTINT (58) /* Number of external interrupts
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* (APIRQn PERI_IRQ_MAX) */
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#define RTL8721F_IRQ_NEXTINT (79) /* Number of external interrupts
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* (APIRQn count, 0..78) */
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#define NR_IRQS (RTL8721F_IRQ_FIRST + RTL8721F_IRQ_NEXTINT)
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@ -95,7 +95,7 @@ u32 app_mpu_nocache_init(void)
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mpu_entry = mpu_entry_alloc();
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mpu_cfg.region_base = 0;
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mpu_cfg.region_size = 0x000F0000;
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mpu_cfg.region_size = 0x000f0000;
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mpu_cfg.xn = MPU_EXEC_ALLOW;
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mpu_cfg.ap = MPU_UN_PRIV_RO;
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mpu_cfg.sh = MPU_NON_SHAREABLE;
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@ -177,6 +177,25 @@ void os_init(void)
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rtos_mem_init();
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}
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/* Seed the RTC on first power-on (mirrors the SDK app_rtc_init). */
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void app_rtc_init(void)
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{
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RTC_InitTypeDef rtc_initstruct;
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RTC_TimeTypeDef rtc_timestruct;
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RTC_TimeStructInit(&rtc_timestruct);
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rtc_timestruct.RTC_Year = 2021;
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rtc_timestruct.RTC_Hours = 10;
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rtc_timestruct.RTC_Minutes = 20;
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rtc_timestruct.RTC_Seconds = 30;
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RTC_StructInit(&rtc_initstruct);
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RTC_Enable(ENABLE);
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RTC_Init(&rtc_initstruct);
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RTC_SetTime(RTC_Format_BIN, &rtc_timestruct);
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}
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/* The image2 application entry point. */
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void app_start(void)
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@ -226,8 +245,6 @@ void app_start(void)
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}
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}
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SYSTIMER_Init();
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/* Low-power pins do not need pinmap init again after wake from dslp. */
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pinmap_init();
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@ -235,6 +252,36 @@ void app_start(void)
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mpu_init();
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app_mpu_nocache_init();
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/* Green2's system timer is clocked from SDM32K and needs the RTC
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* brought up first. The SDK does the first-power-on half of this
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* asynchronously from
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* the RTC_DET_IRQ handler (rtc_irq_init), but NuttX replaces the vector
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* table immediately after app_start so that deferred handler would never
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* run -- do the whole sequence synchronously here instead.
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*/
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RTC_ClearDetINT();
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SDM32K_Enable();
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SYSTIMER_Init();
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RCC_PeriphClockCmd(NULL, APBPeriph_RTC_CLOCK, ENABLE);
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if ((Get_OSC131_STATE() & RTC_BIT_FIRST_PON) == 0)
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{
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app_rtc_init();
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Set_OSC131_STATE(Get_OSC131_STATE() | RTC_BIT_FIRST_PON);
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/* Only ASIC needs OSC131K calibration (cke_rtc enabled just above). */
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if (SYSCFG_CHIPType_Get() == CHIP_TYPE_ASIC_POSTSIM)
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{
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OSC131K_Calibration(30000);
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}
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}
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/* SDM32K clock-source switch must be done after rtc_fen is enabled. */
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RTC_ClkSource_Select(SDM32K);
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main();
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}
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@ -114,6 +114,7 @@ AMEBA_FWLIB_SRCS = $(AMEBA_SOC)/fwlib/ram_common/ameba_arch.c \
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# so the fwlib sources it pulls in are listed alongside it.
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AMEBA_FWLIB_SRCS += $(TOPDIR)/arch/arm/src/rtl8721f/ameba_app_start.c \
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$(AMEBA_SOC)/fwlib/ram_common/ameba_mpu_ram.c \
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$(AMEBA_SOC)/fwlib/ram_common/ameba_rtc.c \
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$(AMEBA_SOC)/fwlib/ram_km4tz/ameba_data_flashclk.c \
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$(AMEBA_SOC)/fwlib/ram_km4tz/ameba_flashclk.c \
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$(AMEBA_SOC)/fwlib/ram_km4tz/ameba_pinmap.c \
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@ -70,7 +70,7 @@
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* SDK RTL8721F hal_platform.h. This matches the SDK km4tz main(), which
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* calls ipc_table_init(IPCAP_DEV) with the NON-secure alias 0x40804000
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* (the secure alias 0x50804000 is NOT what the AP uses).
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* RTL8721F_IRQ_IPC_KM4 maps to APIRQn IPC_KM4TZ_IRQ (external vector 3) --
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* RTL8721F_IRQ_IPC_KM4 maps to APIRQn IPC_CPU0_IRQ (external vector 5) --
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* see arch/.../irq.h.
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*/
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@ -77,16 +77,16 @@
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#define AMEBA_ENABLE 1
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#define AMEBA_DISABLE 0
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/* LOG-UART device base (UARTLOG_REG_BASE, from SDK RTL8721F
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* hal_platform.h). NOTE: this is the RTL8721F address (0x401C6000) -- it
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* differs from the RTL8721Dx LOG-UART (0x4100F000). Only
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* LOGUART_INTConfig()/INTCoreConfig() take this base explicitly; the TX
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* path (DiagPrintf/LOGUART_PutChar) is a ROM call with its own internal
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* base, which is why TX worked even when this was wrong but configuring
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* the RX interrupt bus-faulted.
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/* LOG-UART device base (UARTLOG_REG_BASE, from SDK amebagreen2
|
||||
* hal_platform.h). Only LOGUART_INTConfig()/INTCoreConfig()/RxCmd() take
|
||||
* this base explicitly; the TX path (DiagPrintf/LOGUART_PutChar) is a ROM
|
||||
* call with its own internal base. Using the wrong base (e.g. the
|
||||
* RTL8721Dx 0x401C6000) leaves TX working -- because PutChar ignores it --
|
||||
* while writing the RX interrupt-enable register bus-faults, since the
|
||||
* bogus IER address decodes to no bus slave on green2.
|
||||
*/
|
||||
|
||||
#define LOGUART_DEV ((void *)0x401C6000)
|
||||
#define LOGUART_DEV ((void *)0x40810000)
|
||||
|
||||
/***************************************************************************
|
||||
* External ROM/SDK Function Prototypes
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue