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boards/arm/rtl8730e: fix SMP cache-line false sharing on Cortex-A32

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Under sustained dual-core critical-section traffic (e.g. several UART
ISRs) the two Cortex-A32 cores live-lock trading failed STREX.  The
generic critical-section lock g_cpu_irqlock (an LDREX/STREX spinlock)
and the plain non-atomic bitmap g_cpu_irqset are defined back-to-back
in sched/irq/irq_csection.c and land in the same 64-byte cache line.
The A32 exclusive monitor reserves a full cache line, so one core's
ordinary store to g_cpu_irqset clears the other core's LDREX
reservation on g_cpu_irqlock.

Separate the two symbols onto their own cache lines in the board link
script, leaving the generic scheduler source untouched (relies on the
toolchain emitting per-object -fdata-sections).

Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
This commit is contained in:
dechao_gong 2026-09-24 16:38:31 +08:00 • committed by Xiang Xiao
parent f021af714d
commit a28daa454b
1 changed files with 23 additions and 0 deletions
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23
boards/arm/rtl8730e/rtl8730e_evb/scripts/dramboot.ld
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@ -129,6 +129,29 @@ SECTIONS
.bss : { /* BSS */
_sbss = .;
/* Cortex-A32 exclusive-monitor false-sharing workaround.
*
* The generic SMP critical-section spinlock g_cpu_irqlock and the
* plain (non-atomic) bitmap g_cpu_irqset are defined back-to-back in
* sched/irq/irq_csection.c and land in the same 64-byte cache line.
* The A32 exclusive monitor reserves a full cache line, so one core's
* ordinary store to g_cpu_irqset clears the other core's LDREX
* reservation on g_cpu_irqlock; under heavy dual-core critical-section
* traffic (e.g. several UART ISRs) the two cores live-lock trading
* failed STREX. Place the lock on its own cache line and push
* g_cpu_irqset onto the next one so they occupy separate reservation
* granules. Done here in the (chip-specific) link script so the
* generic scheduler source is left untouched; relies on the toolchain
* emitting per-object -fdata-sections.
*/
. = ALIGN(64);
*(.bss.g_cpu_irqlock)
. = ALIGN(64);
*(.bss.g_cpu_irqset)
. = ALIGN(64);
*(.bss*)
. = ALIGN(4096);
_ebss = .;