From a28daa454b2189c4a5d2e254c57a5eacdd898e1a Mon Sep 17 00:00:00 2001 From: dechao_gong Date: Thu, 24 Sep 2026 16:38:31 +0800 Subject: [PATCH] boards/arm/rtl8730e: fix SMP cache-line false sharing on Cortex-A32 Under sustained dual-core critical-section traffic (e.g. several UART ISRs) the two Cortex-A32 cores live-lock trading failed STREX. The generic critical-section lock g_cpu_irqlock (an LDREX/STREX spinlock) and the plain non-atomic bitmap g_cpu_irqset are defined back-to-back in sched/irq/irq_csection.c and land in the same 64-byte cache line. The A32 exclusive monitor reserves a full cache line, so one core's ordinary store to g_cpu_irqset clears the other core's LDREX reservation on g_cpu_irqlock. Separate the two symbols onto their own cache lines in the board link script, leaving the generic scheduler source untouched (relies on the toolchain emitting per-object -fdata-sections). Signed-off-by: dechao_gong Assisted-by: Claude --- .../rtl8730e/rtl8730e_evb/scripts/dramboot.ld | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/boards/arm/rtl8730e/rtl8730e_evb/scripts/dramboot.ld b/boards/arm/rtl8730e/rtl8730e_evb/scripts/dramboot.ld index 5aabce46aa0..6e103ffbf54 100644 --- a/boards/arm/rtl8730e/rtl8730e_evb/scripts/dramboot.ld +++ b/boards/arm/rtl8730e/rtl8730e_evb/scripts/dramboot.ld @@ -129,6 +129,29 @@ SECTIONS .bss : { /* BSS */ _sbss = .; + + /* Cortex-A32 exclusive-monitor false-sharing workaround. + * + * The generic SMP critical-section spinlock g_cpu_irqlock and the + * plain (non-atomic) bitmap g_cpu_irqset are defined back-to-back in + * sched/irq/irq_csection.c and land in the same 64-byte cache line. + * The A32 exclusive monitor reserves a full cache line, so one core's + * ordinary store to g_cpu_irqset clears the other core's LDREX + * reservation on g_cpu_irqlock; under heavy dual-core critical-section + * traffic (e.g. several UART ISRs) the two cores live-lock trading + * failed STREX. Place the lock on its own cache line and push + * g_cpu_irqset onto the next one so they occupy separate reservation + * granules. Done here in the (chip-specific) link script so the + * generic scheduler source is left untouched; relies on the toolchain + * emitting per-object -fdata-sections. + */ + + . = ALIGN(64); + *(.bss.g_cpu_irqlock) + . = ALIGN(64); + *(.bss.g_cpu_irqset) + . = ALIGN(64); + *(.bss*) . = ALIGN(4096); _ebss = .;