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arch/intel64: Fix updating MSR_IA32_TSC_ADJUST.

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If the initial value of the MSR_IA32_TSC_ADJUST register is not 0 (may be modified by BIOS or bootloader), it may cause timing errors. This commit addressed the issue.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
This commit is contained in:
ouyangxiangzhen 2025-02-12 21:14:38 +08:00 • committed by GUIDINGLI
parent 7185f41356
commit 946ac39c7a
1 changed files with 2 additions and 1 deletions
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arch/x86_64/src/intel64/intel64_tsc_tickless.c
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@ -147,7 +147,8 @@ void up_timer_initialize(void)
{
uint64_t tsc = rdtscp();
#ifdef CONFIG_ARCH_INTEL64_HAVE_TSC_ADJUST
write_msr(MSR_IA32_TSC_ADJUST, 0 - tsc);
uint64_t offset = read_msr(MSR_IA32_TSC_ADJUST) - tsc;
write_msr(MSR_IA32_TSC_ADJUST, offset);
#else
g_start_tsc = tsc;
#endif