From 946ac39c7a1bea59ca69ed4ddd6ddae2fa028256 Mon Sep 17 00:00:00 2001 From: ouyangxiangzhen Date: Wed, 12 Feb 2025 21:14:38 +0800 Subject: [PATCH] arch/intel64: Fix updating MSR_IA32_TSC_ADJUST. If the initial value of the MSR_IA32_TSC_ADJUST register is not 0 (may be modified by BIOS or bootloader), it may cause timing errors. This commit addressed the issue. Signed-off-by: ouyangxiangzhen --- arch/x86_64/src/intel64/intel64_tsc_tickless.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86_64/src/intel64/intel64_tsc_tickless.c b/arch/x86_64/src/intel64/intel64_tsc_tickless.c index 681820eb3a6..906346b8531 100644 --- a/arch/x86_64/src/intel64/intel64_tsc_tickless.c +++ b/arch/x86_64/src/intel64/intel64_tsc_tickless.c @@ -147,7 +147,8 @@ void up_timer_initialize(void) { uint64_t tsc = rdtscp(); #ifdef CONFIG_ARCH_INTEL64_HAVE_TSC_ADJUST - write_msr(MSR_IA32_TSC_ADJUST, 0 - tsc); + uint64_t offset = read_msr(MSR_IA32_TSC_ADJUST) - tsc; + write_msr(MSR_IA32_TSC_ADJUST, offset); #else g_start_tsc = tsc; #endif