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Add SAML21 RSTC register definitions
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Gregory Nutt
parent
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commit
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2 changed files with 146 additions and 1 deletions
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#define SAM_PM_BASE 0x40000000 /* Power Management */
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#define SAM_MCLK_BASE 0x40000400 /* Main Clock */
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#define SAM_RSTC_BASE 0x40000800 /* Reset controller */
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#define SAM_OSCCTRL_BASE 0x40000c00 /* Oscillators Controller */
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#define SAM_OSC32KCTRL_BASE 0x40001000 /* 32KHz Oscillators Controller */
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#define SAM_SUPC_BASE 0x40001400 /* Supply Controller */
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#define SAM_USB_BASE 0x41000000 /* Universal Serial Bus */
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#define SAM_DSU_BASE 0x41002000 /* Device Service Unit */
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#define SAM_NVMCTRL_BASE 0x41004000 /* Non-Volatile Memory Controller */
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#define SAM_MTD_BASE 0x41006000 /* ??? */
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#define SAM_MTB_BASE 0x41006000 /* Micro trace buffer */
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/* AHB-APB Bridge C */
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/* AHB-APB Bridge D */
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#define SAM_EVSYS_BASE 0x43000000 /* Event system */
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#define SAM_SERCOM5_BASE 0x43000400 /* Serial Communication Interface 5 */
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#define SAM_TC4_BASE 0x43000800 /* Timer/Counter 4 */
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#define SAM_ADC_BASE 0x43000c00 /* Analog-to-Digital Converter */
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143
arch/arm/src/samdl/chip/saml_rstc.h
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143
arch/arm/src/samdl/chip/saml_rstc.h
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/********************************************************************************************
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* arch/arm/src/samdl/chip/saml_rstc.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
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* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAM_RSTC_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAM_RSTC_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/sam_sercom.h"
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* RSTC register offsets *********************************************************************/
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#define SAM_RSTC_RCAUSE_OFFSET 0x0000 /* Reset cause */
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#define SAM_RSTC_BKUPEXIT_OFFSET 0x0002 /* Backup exit source */
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#define SAM_RSTC_WKDBCONF_OFFSET 0x0004 /* Wakeup debounce count */
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#define SAM_RSTC_WKPOL_OFFSET 0x0008 /* Wakeup polarity */
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#define SAM_RSTC_WKEN_OFFSET 0x000c /* Wakeup enable */
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#define SAM_RSTC_WKCAUSE_OFFSET 0x0010 /* Wakeup cause */
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/* RSTC register addresses *******************************************************************/
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#define SAM_RSTC_RCAUSE (SAM_RSTC_BASE+SAM_RSTC_RCAUSE_OFFSET)
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#define SAM_RSTC_BKUPEXIT (SAM_RSTC_BASE+SAM_RSTC_BKUPEXIT_OFFSET)
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#define SAM_RSTC_WKDBCONF (SAM_RSTC_BASE+SAM_RSTC_WKDBCONF_OFFSET)
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#define SAM_RSTC_WKPOL (SAM_RSTC_BASE+SAM_RSTC_WKPOL_OFFSET)
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#define SAM_RSTC_WKEN (SAM_RSTC_BASE+SAM_RSTC_WKEN_OFFSET)
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#define SAM_RSTC_WKCAUSE (SAM_RSTC_BASE+SAM_RSTC_WKCAUSE_OFFSET)
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/* RSTC register bit definitions *************************************************************/
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/* Reset cause */
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#define RSTC_RCAUSE_POR (1 << 0) /* Bit 0: Power on reset */
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#define RSTC_RCAUSE_BOD12 (1 << 1) /* Bit 1: Brown out 12 detector reset */
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#define RSTC_RCAUSE_BOD33 (1 << 2) /* Bit 2: Brown out 33 detector reset */
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#define RSTC_RCAUSE_EXT (1 << 4) /* Bit 4: External reset */
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#define RSTC_RCAUSE_WDT (1 << 5) /* Bit 5: Watchdog reset */
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#define RSTC_RCAUSE_SYST (1 << 6) /* Bit 6: System reset request */
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#define RSTC_RCAUSE_BACKUP (1 << 7) /* Bit 7: Backup reset*/
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/* Backup exit source */
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#define RSTC_BKUPEXIT_EXTWAKE (1 << 0) /* Bit 0: External wakeup */
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#define RSTC_BKUPEXIT_RTC (1 << 1) /* Bit 1: Real time counter interrupt */
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#define RSTC_BKUPEXIT_BBPS (1 << 2) /* Bit 2: Battery backup power switch */
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/* Wakeup debounce count */
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#define RSTC_WKDBCONF_MASK (0x1f)
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/* Wakeup polarity */
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#define RSTC_WKPOL_PIN(n) (1 << (n)) /* Bit n:Input pin n active high */
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# define RSTC_WKPOL_PIN0 (1 << 0) /* Bit 0: Input pin 0 active high */
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# define RSTC_WKPOL_PIN1 (1 << 1) /* Bit 1: Input pin 1 active high */
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# define RSTC_WKPOL_PIN2 (1 << 2) /* Bit 2: Input pin 2 active high */
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# define RSTC_WKPOL_PIN3 (1 << 3) /* Bit 3: Input pin 3 active high */
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# define RSTC_WKPOL_PIN4 (1 << 4) /* Bit 4: Input pin 4 active high */
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# define RSTC_WKPOL_PIN5 (1 << 5) /* Bit 5: Input pin 5 active high */
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# define RSTC_WKPOL_PIN6 (1 << 6) /* Bit 6: Input pin 6 active high */
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# define RSTC_WKPOL_PIN7 (1 << 7) /* Bit 7: Input pin 7 active high */
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/* Wakeup enable */
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#define RSTC_WKEN_PIN(n) (1 << (n)) /* Bit n: Wakeup input pin n enabled */
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# define RSTC_WKEN_PIN0 (1 << 0) /* Bit 0: Wakeup input pin 0 enabled */
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# define RSTC_WKEN_PIN1 (1 << 1) /* Bit 1: Wakeup input pin 1 enabled */
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# define RSTC_WKEN_PIN2 (1 << 2) /* Bit 2: Wakeup input pin 2 enabled */
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# define RSTC_WKEN_PIN3 (1 << 3) /* Bit 3: Wakeup input pin 3 enabled */
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# define RSTC_WKEN_PIN4 (1 << 4) /* Bit 4: Wakeup input pin 4 enabled */
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# define RSTC_WKEN_PIN5 (1 << 5) /* Bit 5: Wakeup input pin 5 enabled */
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# define RSTC_WKEN_PIN6 (1 << 6) /* Bit 6: Wakeup input pin 6 enabled */
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# define RSTC_WKEN_PIN7 (1 << 7) /* Bit 7: Wakeup input pin 7 enabled */
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/* Wakeup cause */
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#define RSTC_WKCAUSE_PIN(n) (1 << (n)) /* Bit n: WKCAUSE n active and enabled */
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# define RSTC_WKCAUSE_PIN0 (1 << 0) /* Bit 0: WKCAUSE 0 active and enabled */
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# define RSTC_WKCAUSE_PIN1 (1 << 1) /* Bit 1: WKCAUSE 1 active and enabled */
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# define RSTC_WKCAUSE_PIN2 (1 << 2) /* Bit 2: WKCAUSE 2 active and enabled */
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# define RSTC_WKCAUSE_PIN3 (1 << 3) /* Bit 3: WKCAUSE 3 active and enabled */
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# define RSTC_WKCAUSE_PIN4 (1 << 4) /* Bit 4: WKCAUSE 4 active and enabled */
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# define RSTC_WKCAUSE_PIN5 (1 << 5) /* Bit 5: WKCAUSE 5 active and enabled */
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# define RSTC_WKCAUSE_PIN6 (1 << 6) /* Bit 6: WKCAUSE 6 active and enabled */
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# define RSTC_WKCAUSE_PIN7 (1 << 7) /* Bit 7: WKCAUSE 7 active and enabled */
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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/********************************************************************************************
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* Public Data
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********************************************************************************************/
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/********************************************************************************************
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* Public Functions
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********************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAM_RSTC_H */
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