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SAML21: Add PM header file
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Gregory Nutt
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arch/arm/src/samdl/chip/saml_pm.h
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arch/arm/src/samdl/chip/saml_pm.h
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/****************************************************************************************************
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* arch/arm/src/samdl/chip/saml_pm.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
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* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAML_PM_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAML_PM_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#ifdef CONFIG_ARCH_FAMILY_SAML21
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* PM register offsets ******************************************************************************/
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#define SAM_PM_CTRLA_OFFSET 0x0000 /* Control A */
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#define SAM_PM_SLEEPCFG_OFFSET 0x0001 /* Sleep configuration */
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#define SAM_PM_PLCFG_OFFSET 0x0002 /* Performance level configuration */
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#define SAM_PM_INTENCLR_OFFSET 0x0004 /* Interrupt enable clear register */
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#define SAM_PM_INTENSET_OFFSET 0x0005 /* Interrupt enable set register */
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#define SAM_PM_INTFLAG_OFFSET 0x0006 /* Interrupt flag status and clear register */
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#define SAM_PM_STDBYCFG_OFFSET 0x0008 /* Standy configuration */
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/* PM register addresses ****************************************************************************/
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#define SAM_PM_CTRLA (SAM_PM_BASE+SAM_PM_CTRLA_OFFSET)
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#define SAM_PM_SLEEPCFG (SAM_PM_BASE+SAM_PM_SLEEPCFG_OFFSET)
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#define SAM_PM_PLCFG (SAM_PM_BASE+SAM_PM_PLCFG_OFFSET)
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#define SAM_PM_INTENCLR (SAM_PM_BASE+SAM_PM_INTENCLR_OFFSET)
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#define SAM_PM_INTENSET (SAM_PM_BASE+SAM_PM_INTENSET_OFFSET)
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#define SAM_PM_INTFLAG (SAM_PM_BASE+SAM_PM_INTFLAG_OFFSET)
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#define SAM_PM_STDBYCFG (SAM_PM_BASE+SAM_PM_STDBYCFG_OFFSET)
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/* PM register bit definitions **********************************************************************/
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/* Control A register */
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#define PM_CTRLA_IORET (1 << 2) /* Bit 2: I/O retention */
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/* Sleep configuration register */
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#define PM_SLEEPCFG_MODE_SHIFT (0) /* Bits 0-2: Idle Mode Configuration */
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#define PM_SLEEPCFG_MODE_MASK (7 << PM_SLEEPCFG_MODE_SHIFT)
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# define PM_SLEEPCFG_MODE_IDLE (2 << PM_SLEEPCFG_MODE_SHIFT) /* CPU, AHBx, APBx clocks OFF */
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# define PM_SLEEPCFG_MODE_STANDBY (4 << PM_SLEEPCFG_MODE_SHIFT) /* All clocks OFF, except sleepwalking peripherals */
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# define PM_SLEEPCFG_MODE_BACKUP (5 << PM_SLEEPCFG_MODE_SHIFT) /* Only backup domain is powered ON */
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# define PM_SLEEPCFG_MODE_OFF (6 << PM_SLEEPCFG_MODE_SHIFT) /* All power domains are powered OFF */
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/* Performance level configuration */
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#define PM_PLCFG_PLSEL_SHIFT (0) /* Bits 0-1: Performance level select */
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#define PM_PLCFG_PLSEL_MASK (3 << PM_PLCFG_PLSEL_SHIFT)
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# define PM_PLCFG_PLSEL_PL0 (0 << PM_PLCFG_PLSEL_SHIFT) /* Performance level 0 */
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# define PM_PLCFG_PLSEL_PL2 (2 << PM_PLCFG_PLSEL_SHIFT) /* Performance level 2 */
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#define PM_PLCFG_PLDIS (1 << 7) /* Bit 7: Performance level disable */
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/* Interrupt enable clear, Interrupt enable set, and Interrupt flag status and clear registers */
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#define PM_INT_PLRDY (1 << 0) /* Bit 0: Performanc level ready */
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/* Standy configuration */
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#define PM_STDBYCFG_PDCFG_SHIFT (0) /* Bits 0-1: Power domain configuration */
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#define PM_STDBYCFG_PDCFG_MASK (3 << PM_STDBYCFG_PDCFG_SHIFT)
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# define PM_STDBYCFG_PDCFG_DEFAULT (0 << PM_STDBYCFG_PDCFG_SHIFT) /* All power domains handled by HW */
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# define PM_STDBYCFG_PDCFG_PD01 (1 << PM_STDBYCFG_PDCFG_SHIFT) /* PD0 ACTIVE; PD1/2 handled by HW */
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# define PM_STDBYCFG_PDCFG_PD12 (2 << PM_STDBYCFG_PDCFG_SHIFT) /* PD0/1 ACTIVE; PD2 handled by HW */
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# define PM_STDBYCFG_PDCFG_PD012 (3 << PM_STDBYCFG_PDCFG_SHIFT) /* All power domains ACTIVE */
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#define PM_STDBYCFG_DPGPD0 (1 << 4) /* Bit 4: Dynamic power gating for power domain 0 */
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#define PM_STDBYCFG_DPGPD1 (1 << 5) /* Bit 5: Dynamic power gating for power domain 1 */
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#define PM_STDBYCFG_VREGSMOD_SHIFT (6) /* Bits 6-7: Linked power domain */
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#define PM_STDBYCFG_VREGSMOD_MASK (3 << PM_STDBYCFG_VREGSMOD_SHIFT)
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# define PM_STDBYCFG_VREGSMOD_AUTO (0 << PM_STDBYCFG_VREGSMOD_SHIFT) /* Automatic mode */
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# define PM_STDBYCFG_VREGSMOD_PERFORMANCE (1 << PM_STDBYCFG_VREGSMOD_SHIFT) /* Performance oriented */
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# define PM_STDBYCFG_VREGSMOD_LP (2 << PM_STDBYCFG_VREGSMOD_SHIFT) /* Low power consumption oriented */
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#define PM_STDBYCFG_LINKPD_SHIFT (8) /* Bits 8-9: */
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#define PM_STDBYCFG_LINKPD_MASK (3 << PM_STDBYCFG_LINKPD_SHIFT)
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# define PM_STDBYCFG_LINKPD_DEFAULT (0 << PM_STDBYCFG_LINKPD_SHIFT) /* Power domains not linked */
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# define PM_STDBYCFG_LINKPD_PD01 (1 << PM_STDBYCFG_LINKPD_SHIFT) /* Power domains P0/1 linked */
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# define PM_STDBYCFG_LINKPD_PD12 (2 << PM_STDBYCFG_LINKPD_SHIFT) /* Power domains P1/P2 linked */
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# define PM_STDBYCFG_LINKPD_PD012 (3 << PM_STDBYCFG_LINKPD_SHIFT) /* All power domains linked */
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#define PM_STDBYCFG_BBIASHS_SHIFT (10) /* Bits 10-11: Back bias for HMCRAMCHS */
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#define PM_STDBYCFG_BBIASHS_MASK (3 << PM_STDBYCFG_BBIASHS_SHIFT)
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# define PM_STDBYCFG_BBIASHS_RETBACK (0 << PM_STDBYCFG_BBIASHS_SHIFT) /* Retention back biasing mode */
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# define PM_STDBYCFG_BBIASHS_STDBYBACK (1 << PM_STDBYCFG_BBIASHS_SHIFT) /* Standby back biasing mode */
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# define PM_STDBYCFG_BBIASHS_STDBYOFF (2 << PM_STDBYCFG_BBIASHS_SHIFT) /* Standby OFF mode */
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# define PM_STDBYCFG_BBIASHS_OFF (3 << PM_STDBYCFG_BBIASHS_SHIFT) /* Always OFF mode */
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#define PM_STDBYCFG_BBIASLP_SHIFT (12) /* Bits 12-13: Back bias for HMCRAMCLP */
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#define PM_STDBYCFG_BBIASLP_MASK (3 << PM_STDBYCFG_BBIASLP_SHIFT)
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# define PM_STDBYCFG_BBIASLP_RETBACK (0 << PM_STDBYCFG_BBIASLP_SHIFT) /* Retention back biasing mode */
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# define PM_STDBYCFG_BBIASLP_STDBYBACK (1 << PM_STDBYCFG_BBIASLP_SHIFT) /* Standby back biasing mode */
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# define PM_STDBYCFG_BBIASLP_STDBYOFF (2 << PM_STDBYCFG_BBIASLP_SHIFT) /* Standby OFF mode */
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# define PM_STDBYCFG_BBIASLP_OFF (3 << PM_STDBYCFG_BBIASLP_SHIFT) /* Always OFF mode */
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/****************************************************************************************************
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* Public Types
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****************************************************************************************************/
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/****************************************************************************************************
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* Public Data
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****************************************************************************************************/
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/****************************************************************************************************
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* Public Functions
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****************************************************************************************************/
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#endif /* CONFIG_ARCH_FAMILY_SAMD20 */
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAML_PM_H */
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