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arch/arm/imxrt: Fix LPSPI frequency setting for imxrt1180

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The LPSPI_CCR register is write only in imxrt1180. Therefore, the existing
modifyreg32 calls can't be used to set the fields. Use direct putreg8
writes to update the PCSSCK, SCKPCS, DBT and SCKDIV.

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This commit is contained in:
Jukka Laitinen 2026-09-28 16:08:04 +03:00 • committed by Xiang Xiao
parent 5b8df0f65b
commit 62cc75c691
2 changed files with 24 additions and 0 deletions
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4
arch/arm/src/imxrt/hardware/imxrt_lpspi.h
View file

@ -47,6 +47,10 @@
#define IMXRT_LPSPI_DMR0_OFFSET 0x0030 /* Data Match Register 0 offset */
#define IMXRT_LPSPI_DMR1_OFFSET 0x0034 /* Data Match Register 1 offset */
#define IMXRT_LPSPI_CCR_OFFSET 0x0040 /* Clock Configuration Register offset */
#define IMXRT_LPSPI_CCR_SCKDIV_OFFSET 0x0040 /* SCK divider byte offset */
#define IMXRT_LPSPI_CCR_DBT_OFFSET 0x0041 /* Delay between transfers byte offset */
#define IMXRT_LPSPI_CCR_PCSSCK_OFFSET 0x0042 /* PCS-to-SCK delay byte offset */
#define IMXRT_LPSPI_CCR_SCKPCS_OFFSET 0x0043 /* SCK-to-PCS delay byte offset */
#define IMXRT_LPSPI_FCR_OFFSET 0x0058 /* FIFO Control Register offset */
#define IMXRT_LPSPI_FSR_OFFSET 0x005C /* FIFO Status Register offset */
#define IMXRT_LPSPI_TCR_OFFSET 0x0060 /* Transmit Command Register offset */

20
arch/arm/src/imxrt/imxrt_lpspi.c
View file

@ -684,28 +684,43 @@ static inline void imxrt_lpspi_master_set_delay_scaler(
{
case LPSPI_PCS_TO_SCK:
{
#ifdef CONFIG_ARCH_FAMILY_IMXRT118x
putreg8((uint8_t)scaler,
priv->spibase + IMXRT_LPSPI_CCR_PCSSCK_OFFSET);
#else
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET,
LPSPI_CCR_PCSSCK_MASK, 0);
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, 0,
LPSPI_CCR_PCSSCK(scaler));
#endif
break;
}
case LPSPI_LAST_SCK_TO_PCS:
{
#ifdef CONFIG_ARCH_FAMILY_IMXRT118x
putreg8((uint8_t)scaler,
priv->spibase + IMXRT_LPSPI_CCR_SCKPCS_OFFSET);
#else
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET,
LPSPI_CCR_SCKPCS_MASK, 0);
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, 0,
LPSPI_CCR_SCKPCS(scaler));
#endif
break;
}
case LPSPI_BETWEEN_TRANSFER:
{
#ifdef CONFIG_ARCH_FAMILY_IMXRT118x
putreg8((uint8_t)scaler,
priv->spibase + IMXRT_LPSPI_CCR_DBT_OFFSET);
#else
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET,
LPSPI_CCR_DBT_MASK, 0);
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, 0,
LPSPI_CCR_DBT(scaler));
#endif
break;
}
}
@ -1064,9 +1079,14 @@ static uint32_t imxrt_lpspi_setfrequency(struct spi_dev_s *dev,
/* Write the best values in the CCR register */
#ifdef CONFIG_ARCH_FAMILY_IMXRT118x
putreg8((uint8_t)best_scaler,
priv->spibase + IMXRT_LPSPI_CCR_SCKDIV_OFFSET);
#else
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET,
LPSPI_CCR_SCKDIV_MASK,
LPSPI_CCR_SCKDIV(best_scaler));
#endif
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_TCR_OFFSET,
LPSPI_TCR_PRESCALE_MASK,